WO2024000653A1 - 显示面板 - Google Patents

显示面板 Download PDF

Info

Publication number
WO2024000653A1
WO2024000653A1 PCT/CN2022/105323 CN2022105323W WO2024000653A1 WO 2024000653 A1 WO2024000653 A1 WO 2024000653A1 CN 2022105323 W CN2022105323 W CN 2022105323W WO 2024000653 A1 WO2024000653 A1 WO 2024000653A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
light
emitting unit
flexible substrate
away
Prior art date
Application number
PCT/CN2022/105323
Other languages
English (en)
French (fr)
Inventor
孙垒涛
黄灿
张春鹏
鲜于文旭
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/759,374 priority Critical patent/US20240215429A1/en
Publication of WO2024000653A1 publication Critical patent/WO2024000653A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/128—Active-matrix OLED [AMOLED] displays comprising two independent displays, e.g. for emitting information from two major sides of the display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel.
  • display panels are mainly single-sided, but in some special occasions and fields, double-sided display panels are used.
  • broadcast facilities such as digital signage, window information facilities, large-scale event venues, and outdoor advertising
  • Existing display panels usually integrate two display screens through modules to achieve double-sided display, which is costly and is not conducive to making the display panel thinner and lighter.
  • the present application provides a display panel to solve the technical problem in the prior art that double-sided display panels are relatively expensive and are not conducive to thinning and lightness.
  • This application provides a display panel, which includes:
  • a driving circuit layer provided on the flexible substrate, the driving circuit layer includes a first transistor and a second transistor;
  • a first light-emitting unit is provided on a side of the driving circuit layer away from the flexible substrate.
  • the first light-emitting unit is connected to the first source or the first drain of the first transistor.
  • the first The side of the light-emitting unit that is away from the flexible substrate emits light;
  • a second light-emitting unit is disposed on a side of the flexible substrate away from the driving circuit layer.
  • the second light-emitting unit is connected to the second source of the second transistor or the second source of the second transistor through a connection hole penetrating the flexible substrate.
  • the second drain electrode is connected, and the side of the second light-emitting unit that is away from the flexible substrate emits light.
  • the driving circuit layer includes a stacked active layer, a gate insulating layer, a first metal layer, interlayer insulation layer and second metal layer;
  • the active layer includes a first active layer and a second active layer that are spaced apart
  • the first metal layer includes a first gate electrode and a second gate electrode that are spaced apart
  • the first gate electrode corresponds to The first active layer is provided
  • the second gate is provided corresponding to the second active layer
  • the second metal layer includes the first source electrode, the first drain electrode, the second The source electrode and the second drain electrode, the first source electrode and the first drain electrode are respectively connected to the first active layer, the second source electrode and the second drain electrode are respectively connected to the The second active layer connection.
  • the interlayer insulating layer has a plurality of contact holes and connection holes, and each contact hole penetrates the interlayer insulating layer and extends to the active layer away from the On one side of the flexible substrate, the contact hole exposes a surface of the active layer away from the flexible substrate, and the connection hole penetrates the interlayer insulating layer and extends to the flexible substrate away from the flexible substrate.
  • first source electrode and the first drain electrode are respectively connected to the first active layer through corresponding contact holes, and the second source electrode and the second drain electrode are respectively connected through corresponding contact holes.
  • the contact hole is connected to the second active layer, and the second source electrode or the second drain electrode is connected to the second light-emitting unit through the connection hole.
  • the first light-emitting unit is an LED chip or an OLED light-emitting unit
  • the second light-emitting unit is the LED chip or the OLED light-emitting unit
  • both the first light-emitting unit and the second light-emitting unit are LED chips
  • the display panel further includes a flat layer, a third metal layer, a buffer layer and a fourth metal layer.
  • the flat layer is provided on a side of the second metal layer away from the flexible substrate.
  • the flat layer is provided with a via hole, and the via hole exposes the first source electrode or the first drain electrode.
  • the third metal layer is disposed on the flat layer.
  • the third metal layer includes a first bonding pad and a second bonding pad.
  • the first bonding pad passes through the The via hole is connected to the first source or the first drain, the first light-emitting unit is connected to the first pad and the second pad; the buffer layer is provided on the flexible
  • the fourth metal layer is disposed on a side of the buffer layer away from the flexible substrate, and the fourth metal layer includes a third bonding pad and a fourth bonding pad.
  • the third soldering pad is connected to the second source or the second drain
  • the second light-emitting unit is connected to the third soldering pad and the fourth soldering pad.
  • the LED chip includes connection electrodes, and the first bonding pad, the second bonding pad, the third bonding pad and the fourth bonding pad are respectively connected to the corresponding The connecting electrodes are connected through conductive glue or metal bonding.
  • the first light-emitting unit is an OLED light-emitting unit
  • the second light-emitting unit is an LED chip
  • the display panel further includes a flat layer and a pixel definition layer
  • the first light-emitting unit is an OLED light-emitting unit.
  • the unit includes an anode, a luminescent layer and a cathode;
  • the flat layer is provided on a side of the second metal layer away from the flexible substrate, the flat layer is provided with a via hole, and the via hole exposes the first source electrode or the first The drain electrode is away from a side surface of the flexible substrate, the anode is disposed on the flat layer, the anode is connected to the first source electrode or the first drain electrode through the via hole, the The pixel definition layer is disposed on a side of the anode away from the flexible substrate, the pixel definition layer has an opening, and the opening exposes a surface of a side of the anode away from the flexible substrate, and the light-emitting layer is disposed In the opening, the cathode is disposed on a side of the light-emitting layer away from the flexible substrate.
  • the first light-emitting unit is an LED chip
  • the second light-emitting unit is an OLED light-emitting unit
  • the display panel further includes a buffer layer and a first pixel definition layer
  • the third light-emitting unit is an OLED light-emitting unit.
  • the two light-emitting units include an anode, a light-emitting layer and a cathode;
  • the buffer layer is disposed on a side of the flexible substrate away from the driving circuit layer
  • the anode is disposed on the buffer layer
  • the anode is connected to the second source electrode or the second source electrode through the connection hole.
  • the second drain is connected
  • the pixel definition layer is disposed on a side of the anode away from the flexible substrate
  • the pixel definition layer has an opening, the opening exposes the anode away from the flexible substrate
  • the luminescent layer is disposed in the opening
  • the cathode is disposed on a side of the luminescent layer away from the flexible substrate.
  • the driving circuit layer further includes an insulating layer and a fifth metal layer;
  • the insulating layer is disposed on a side of the first metal layer away from the flexible substrate
  • the fifth metal layer is disposed between the insulating layer and the interlayer insulating layer
  • the fifth metal layer is disposed on a side of the first metal layer away from the flexible substrate.
  • the metal layer includes a first electrode and a second electrode, the first electrode is arranged correspondingly to the first gate electrode, and the second electrode is arranged correspondingly to the second gate electrode.
  • the display panel further includes a protective layer, a first insulating layer, a second insulating layer, a first encapsulation layer and a second encapsulation layer;
  • the protective layer, the first insulating layer and the second insulating layer are sequentially stacked on the flexible substrate and the between the driving circuit layers; the first encapsulation layer is disposed on the side of the first light-emitting unit away from the flexible substrate and covers the first light-emitting unit, and the second encapsulation layer is disposed on the side of the first light-emitting unit.
  • the two light-emitting units are away from the side of the flexible substrate and cover the second light-emitting unit.
  • the display panel includes a plurality of first light-emitting units and a plurality of second light-emitting units
  • the driving circuit layer includes a plurality of first transistors and a plurality of The second transistor, each first transistor is connected to at least one first light-emitting unit, and each second transistor is connected to at least one second light-emitting unit.
  • a plurality of the first light-emitting units are arranged in an array, and a plurality of the second light-emitting units are arranged in an array, with each adjacent second light-emitting unit having a At least one first lighting unit is provided.
  • This application also provides a display panel, which includes:
  • a driving circuit layer provided on the flexible substrate, the driving circuit layer including a plurality of first transistors and a plurality of second transistors;
  • a plurality of first light-emitting units are disposed on a side of the driving circuit layer away from the flexible substrate.
  • Each of the first light-emitting units is connected to a corresponding first source or first drain of the first transistor. Connected, the side of the first light-emitting unit that is away from the flexible substrate emits light;
  • a plurality of second light-emitting units are disposed on a side of the flexible substrate away from the driving circuit layer.
  • Each second light-emitting unit is connected to the corresponding second transistor through a connection hole penetrating the flexible substrate.
  • the second source or the second drain is connected, and the side of the second light-emitting unit that is away from the flexible substrate emits light;
  • the first light-emitting unit is an LED chip or an OLED light-emitting unit
  • the second light-emitting unit is the LED chip or the OLED light-emitting unit
  • One of the first lighting units is an LED chip or an OLED light-emitting unit
  • This application discloses a display panel. Since the first light-emitting unit and the second light-emitting unit are respectively disposed on both sides of the flexible substrate, and the second light-emitting unit is connected to the driving circuit layer through the connection hole penetrating the flexible substrate, no special film structure design or film is required. By improving the layer material, the first light-emitting unit and the second light-emitting unit can respectively emit light toward both sides of the flexible substrate, thereby reducing the difficulty of the process.
  • the driving circuit layer is arranged on one side of the flexible substrate and drives the first light-emitting unit and the second light-emitting unit through the same driving circuit layer, compared with the prior art, the two display screens are integrated through modules.
  • the combined solution at least reduces one layer of substrate and one driver circuit layer, effectively reduces production costs and is conducive to making the display panel lighter and thinner.
  • Figure 1 is a first structural schematic diagram of a display panel provided by this application.
  • FIG. 2 is a second structural schematic diagram of the display panel provided by this application.
  • FIG. 3 is a third structural schematic diagram of the display panel provided by this application.
  • Figure 4 is a fourth structural schematic diagram of the display panel provided by this application.
  • FIG. 5 is a fifth structural schematic diagram of the display panel provided by this application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first”, “second”, etc. may explicitly or implicitly include one or more of the described features, and therefore cannot be construed as a limitation of the present application.
  • FIG. 1 is a first structural schematic diagram of a display panel provided by this application.
  • the display panel 100 includes a flexible substrate 10, a driving circuit layer 20, a first light-emitting unit 30 and a second light-emitting unit 40.
  • the driving circuit layer 20 is provided on the flexible substrate 10 .
  • the driving circuit layer 20 includes a first transistor T1 and a second transistor T2.
  • the first light emitting unit 30 is disposed on a side of the driving circuit layer 20 away from the flexible substrate 10 .
  • the first light-emitting unit 30 is connected to the first source electrode 251 or the first drain electrode 252 of the first transistor T1.
  • the side of the first light-emitting unit 30 away from the flexible substrate 10 emits light.
  • the second light-emitting unit 40 is disposed on a side of the flexible substrate 10 away from the driving circuit layer 20 .
  • the second light-emitting unit 40 is connected to the second source electrode 253 or the second drain electrode 254 of the second transistor T2 through the connection hole 24b penetrating the flexible substrate 10 .
  • the side of the second light emitting unit 40 away from the flexible substrate 10 emits light.
  • a driving circuit layer 20 is provided in the display panel 100, and the driving circuit layer 20 is used to drive the first light-emitting unit 30 and the second light-emitting unit 40 respectively, and the first light-emitting unit 30 and the second light-emitting unit 40 emit light.
  • the direction is reversed, realizing double-sided display of the display panel 100 .
  • first light-emitting unit 30 and the second light-emitting unit 40 are respectively disposed on both sides of the flexible substrate 10, and the second light-emitting unit 40 is connected to the driving circuit layer 20 through the connection hole 24b penetrating the flexible substrate 10, there is no need to Special film structure design or film material improvement is required to achieve the purpose of the first light-emitting unit 30 and the second light-emitting unit 40 respectively emitting light toward both sides of the flexible substrate 10 , thereby reducing the difficulty of the process.
  • the solution of integrating module means at least reduces one layer of substrate (eg, flexible substrate) and one layer of driving circuit layer 20 , which effectively reduces production costs and is conducive to making the display panel 100 thinner and lighter.
  • the flexible substrate 10 may include one layer, two layers, or more than two layers of flexible PI (Polyimide).
  • the flexible substrate 10 may also be made of resin or other materials.
  • the flexible substrate 10 mainly plays a role of carrying and protecting the driving circuit layer 20 to improve the structural stability of the display panel 100 .
  • the driving circuit layer 20 is used to provide driving signals, such as driving voltage, power supply voltage, etc., to the first light-emitting unit 30 and the second light-emitting unit 40 .
  • the driving circuit layer 20 includes, but is not limited to, a first transistor T1 and a second transistor T2.
  • the driving circuit layer 20 may include 3T1C (three transistors and one capacitor), 4T2C (four transistors and one capacitor) for driving the first light-emitting unit 30 or the second light-emitting unit 40 2 capacitors), 7T1C (7 transistors, 1 capacitor) and other pixel drive circuits.
  • the specific structure of the above pixel driving circuit can be referred to the existing technology, and will not be described again here.
  • the embodiment of the present application only takes the first transistor T1 and the second transistor T2 as an example to illustrate the connection relationship between the driving circuit layer 20 and the first light-emitting unit 30 and the second light-emitting unit 40 , but this cannot be understood as an explanation of the present application. limited.
  • the first transistor T1 and the second transistor T2 may be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, their source and drain are interchangeable.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level. The N-type transistor is when the gate is at a high level. It is turned on when the gate is high and turned off when the gate is low.
  • the first transistor T1 and the second transistor T2 may be low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the transistors in the driving circuit layer 20 provided by the embodiment of the present application are all the same type of transistors, which can simplify the manufacturing process and prevent differences between different types of transistors from causing driving abnormalities in the driving circuit layer 20 .
  • the first light-emitting unit 30 and the second light-emitting unit 40 may be LED chips, OLED light-emitting units, quantum dot light-emitting devices, etc.
  • the first light-emitting unit 30 and the second light-emitting unit 40 are both LED chips.
  • both the first light-emitting unit 30 and the second light-emitting unit 40 are OLED light-emitting units.
  • the first light-emitting unit 30 is an LED chip
  • the second light-emitting unit 40 is an OLED light-emitting unit, or the like.
  • the display panel 100 may include a plurality of first light-emitting units 30 and a plurality of second light-emitting units 40 .
  • the driving circuit layer 20 includes a plurality of first transistors T1 and a plurality of second transistors T2. Each first transistor T1 is connected to at least one first light-emitting unit 30 .
  • Each second transistor T2 is connected to at least one second light-emitting unit 40 .
  • a first light-emitting unit 30 or a second light-emitting unit 40 can be regarded as a pixel.
  • each first transistor T1 is connected to two or more first light-emitting units 30 and each second transistor T2 is connected to two or two second light-emitting units 40, one pixel may include multiple first light-emitting units 40.
  • the light-emitting unit 30 or a plurality of second light-emitting units 40 are used to improve the brightness of the pixels.
  • Each of the following embodiments of the present application takes as an example a first transistor T1 connected to a first light-emitting unit 30 and a second transistor T2 connected to a second light-emitting unit 40 for description, but this should not be construed as limiting the present application.
  • the driving circuit layer 20 includes a stacked active layer 21 , a gate insulating layer 22 , and a first metal layer. 23. Interlayer insulating layer 24 and second metal layer 25 .
  • the active layer 21 is provided on the side of the flexible substrate 10 close to the driving circuit layer 20 .
  • the active layer 21 includes a first active layer 211 and a second active layer 212 that are spaced apart.
  • the gate insulation layer 22 is provided on the side of the active layer 21 away from the flexible substrate 10 .
  • the gate insulating layer 22 covers the active layer 21 .
  • the first metal layer 23 is disposed on the side of the gate insulating layer 22 away from the flexible substrate 10 .
  • the first metal layer 23 includes a first gate electrode 231 and a second gate electrode 232 that are spaced apart.
  • the first gate 231 is provided corresponding to the first active layer 211 .
  • the second gate 232 is provided corresponding to the second active layer 212 .
  • the interlayer insulating layer 24 is provided on the side of the first metal layer 23 away from the flexible substrate 10 .
  • the second metal layer 25 is disposed on the side of the interlayer insulating layer 24 away from the flexible substrate 10 .
  • the second metal layer 25 includes a first source electrode 251 , a first drain electrode 252 , a second source electrode 253 and a second drain electrode 254 .
  • the first source electrode 251 and the first drain electrode 252 are connected to the first active layer 211 respectively.
  • the second source electrode 253 and the second drain electrode 254 are respectively connected to the second active layer 212.
  • the contact connection between the first active layer 211 and the first source electrode 251 and the first drain electrode 252 is a heavily doped region.
  • the contact connections between the second active layer 212 and the second source electrode 253 and the second drain electrode 254 are heavily doped regions.
  • the first transistor T1 includes a first active layer 211, a first gate electrode 231, a first source electrode 251 and a first drain electrode 252.
  • the second transistor T2 includes a second active layer 212, a second gate electrode 232, a second source electrode 253, and a second drain electrode 254.
  • the first transistor T1 and the second transistor T2 are arranged on the same layer, that is, each functional film layer in the first transistor T1 and the corresponding functional film layer in the second transistor T2 are arranged on the same layer, which can simplify the manufacturing process. reduce manufacturing cost. At the same time, it is beneficial to realize the thinness and lightness of the display panel 100 .
  • the first transistor T1 and the second transistor T2 can also be arranged in different layers.
  • the first transistor T1 and the second transistor T2 are both disposed on a side of the flexible substrate 10 close to the first light-emitting unit 30 , but the first transistor T1 is located between the first light-emitting unit 30 and the second light-emitting unit 40 .
  • the first active layer 211 of the first transistor T1 and the second active layer 212 of the second transistor T2 can be arranged in the same layer, but other film layers of the first transistor T1 and other films of the second transistor T2 are in different layers. Layers of different settings.
  • the interlayer insulating layer 24 has a plurality of contact holes 24a and connection holes 24b.
  • Each contact hole 24 a penetrates the interlayer insulating layer 24 and extends to a side of the active layer 21 away from the flexible substrate 10 .
  • the contact hole 24 a exposes a side surface of the active layer 21 away from the flexible substrate 10 .
  • the connection hole 24 b penetrates the interlayer insulating layer 24 and extends to a side of the flexible substrate 10 away from the driving circuit layer 20 .
  • the first source electrode 251 and the first drain electrode 252 are respectively connected to the first active layer 211 through corresponding contact holes 24a.
  • the second source electrode 253 and the second drain electrode 254 are respectively connected to the second active layer 212 through corresponding contact holes 24a.
  • One of the second source electrode 253 and the second drain electrode 254 is connected to the second light emitting unit 40 through the connection hole 24b.
  • connection between the second light-emitting unit 40 and the second transistor T2 is realized by setting a deep hole, that is, the connection hole 24b, that penetrates the interlayer insulating layer 24, the flexible substrate 10 and other functional film layers, thereby achieving
  • the driving circuit layer 20 drives the second light-emitting unit 40 to ensure that both sides of the display panel 100 emit light normally.
  • the embodiment of the present application uses a flexible substrate 10. Due to the material characteristics of the flexible substrate 10, when forming the connection hole 24b, the process difficulty can be reduced and cracks can be avoided in the flexible substrate 10, thereby improving product quality.
  • both the first light-emitting unit 30 and the second light-emitting unit 40 are LED chips.
  • multiple LED chips are arranged on both sides of the flexible substrate 10 in the display panel 100 through mass transfer and other technologies, which can reduce the difficulty of the process while realizing double-sided display.
  • the display panel 100 further includes a flat layer 11 , a third metal layer 12 , a buffer layer 13 and a fourth metal layer 14 .
  • the flat layer 11 is provided on the side of the second metal layer 25 away from the flexible substrate 10 .
  • the flat layer 11 is provided with via holes 11a.
  • the via hole 11 a exposes a side surface of the first source electrode 251 or the first drain electrode 252 away from the flexible substrate 10 .
  • the third metal layer 12 is provided on the flat layer 11 .
  • the third metal layer 12 includes a first bonding pad 121 and a second bonding pad 122 .
  • the first pad 121 is connected to the first source electrode 251 or the first drain electrode 252 through the via hole 11a.
  • the first light emitting unit 30 is connected to the first bonding pad 121 and the second bonding pad 122 respectively.
  • the buffer layer 13 is provided on the side of the flexible substrate 10 away from the driving circuit layer 20 .
  • the fourth metal layer 14 is disposed on the side of the buffer layer 13 away from the flexible substrate 10 .
  • the fourth metal layer 14 includes third bonding pads 141 and fourth bonding pads 142 .
  • the third pad 141 is connected to one of the second source electrode 253 and the second drain electrode 254 .
  • the second light emitting unit 40 is connected to the third bonding pad 141 and the fourth bonding pad 142 respectively.
  • the via hole 11 a exposes a side surface of the first drain electrode 252 away from the flexible substrate 10 .
  • the first pad 121 is connected to the first drain electrode 252 through the via hole 11a.
  • the first light-emitting unit 30 is bonded and connected to the first transistor T1 through the first bonding pad 121 .
  • the third pad 141 is connected to the second drain electrode 254 .
  • the second light emitting unit 40 is connected to the second transistor T2 through the third bonding pad 141 .
  • the LED chip may be a Mini-LED (Mini Light-Emitting Diode (sub-millimeter light-emitting diode) chip, Micro-LED (Micro Light-Emitting Diode, micro-light-emitting diode) chip, etc.
  • Each LED chip includes two connection electrodes 41 . Two connecting electrodes 41 are deposited on the layer of luminescent material. One of the connection electrodes 41 is the positive electrode of the LED chip, and the other connection electrode 41 is the negative electrode of the LED chip.
  • the structure of the LED chip in the embodiment of the present application is not limited to this.
  • connection electrodes 41 are connected to the first pad 121 , and the other connection electrode 41 is connected to the second pad 122 .
  • connection electrodes 41 is connected to the third bonding pad 141 , and the other connection electrode 41 is connected to the fourth bonding pad 142 .
  • the first bonding pad 121 , the second bonding pad 122 , the third bonding pad 141 and the fourth bonding pad 142 are connected to the corresponding connection electrodes 41 through metal bonding.
  • metallic bonds are chemical bonds that connect atoms in metals together. They differ from covalent and ionic bonds because the electrons in metallic bonds are delocalized, that is, they are not shared between just two atoms. In contrast, the electrons in a metallic bond float freely within the crystal lattice of the metal's nuclei. This type of bonding gives the metal many unique material properties, including excellent thermal and electrical conductivity, high melting point, and ductility. Metal bonding enables good electrical conductivity between the first pad 121 , the second pad 122 , the third pad 141 and the fourth pad 142 and the corresponding connection electrodes 41 .
  • the luminescent material of the LED chip may be an inorganic luminescent material such as gallium nitride or quantum dots or an organic luminescent material.
  • LED chips can emit red light, blue light, green light, white light or yellow light, etc.
  • different luminescent materials can be selected according to different luminous color requirements.
  • the driving circuit layer 20 may also include an insulating layer 26 and a fifth metal layer 27 .
  • the insulating layer 26 is disposed on the side of the first metal layer 23 away from the flexible substrate 10 .
  • the fifth metal layer 27 is provided between the insulating layer 26 and the interlayer insulating layer 24 .
  • the fifth metal layer 27 includes a first electrode 271 and a second electrode 272 .
  • the first electrode 271 and the first gate electrode 231 are arranged correspondingly.
  • the second electrode 272 and the second gate electrode 232 are arranged correspondingly.
  • the first electrode 271 and the first gate 231 form a two-pole plate of a storage capacitor.
  • the second electrode 272 and the second gate electrode 232 form another two-pole plate of the storage capacitor.
  • the embodiment of the present application uses the first gate 231 (the second gate 232) as one of the poles of the storage capacitor, which can further simplify the process and reduce the thickness of the display panel 100.
  • the display panel 100 may further include a protective layer 17, a first insulating layer 18, a second insulating layer 19, a first encapsulation layer 101 and a second encapsulation layer 102.
  • the protective layer 17 , the first insulating layer 18 and the second insulating layer 19 are sequentially stacked and disposed between the flexible substrate 10 and the driving circuit layer 20 .
  • the first encapsulation layer 101 is disposed on a side of the first light-emitting unit 30 away from the flexible substrate 10 and covers the first light-emitting unit 30 .
  • the second encapsulation layer 102 is disposed on a side of the second light-emitting unit 40 away from the flexible substrate 10 and covers the second light-emitting unit 40 .
  • the protective layer 17 may be made of silicon oxide.
  • the material of the first insulating layer 18 may be silicon nitride.
  • the material of the second insulating layer 19 may be silicon oxide.
  • the protective layer 17, the first insulating layer 18 and the second insulating layer 19 are used to isolate the flexible substrate 10 and the driving circuit layer 20, and play the role of blocking water and oxygen.
  • the second insulating layer 19 also plays a role in heat preservation.
  • the materials of the first encapsulation layer 101 and the second encapsulation layer 102 are usually transparent to improve the light transmittance of the display panel 100 .
  • the material of the first encapsulation layer 101 and the second encapsulation layer 102 may be OCA (Optically Clear Adhesive, optical glue) or other transparent glue.
  • transparent glue is used to form the first encapsulation layer 101 and the second encapsulation layer 102.
  • the light extraction efficiency of the display panel 100 can be improved.
  • the first encapsulation layer 101 covers the first light-emitting unit 30 and the second encapsulation layer 102 covers the second light-emitting unit 40, it can play a role in fixing and protecting the first light-emitting unit 30 and the second light-emitting unit 40.
  • a plurality of first light-emitting units 30 are arranged in an array
  • a plurality of second light-emitting units 40 are arranged in an array
  • at least one first light-emitting unit is disposed between each two adjacent second light-emitting units 40.
  • one first light-emitting unit 30 , two first light-emitting units 30 , or more than two first light-emitting units 30 may be provided between every two adjacent second light-emitting units 40 .
  • the plurality of first light-emitting units 30 and the plurality of second light-emitting units 40 can also be arranged according to other rules, which is not limited by this application.
  • a first light-emitting unit 30 is disposed between every two adjacent second light-emitting units 40 . That is, the pixel resolutions of the display images on the front and back sides of the display panel 100 are equal.
  • FIG. 2 is a second structural schematic diagram of the display panel provided by the present application.
  • the difference from the display panel 100 shown in FIG. 1 is that in the embodiment of the present application, two first light-emitting units 30 are disposed between every two adjacent second light-emitting units 40 .
  • the pixel resolution of the side of the display panel 100 where the first light-emitting unit 30 is provided is greater than the pixel resolution of the side where the second light-emitting unit 40 is provided.
  • At least two second light-emitting units 40 are disposed between every two adjacent first light-emitting units 30 . In this way, the pixel resolution of the side of the display panel 100 where the first light-emitting unit 30 is provided is smaller than the pixel resolution of the side where the second light-emitting unit 40 is provided.
  • FIG. 3 is a third structural schematic diagram of the display panel provided by the present application.
  • the difference from the display panel 100 shown in FIG. 1 is that in the embodiment of the present application, the first bonding pad 121 , the second bonding pad 122 , the third bonding pad 141 and the fourth bonding pad 142 are connected to the corresponding connection electrodes. 41 are connected through conductive glue 43 .
  • the display panel 100 also includes conductive glue 43 .
  • the material of the conductive adhesive 43 may be anisotropic conductive adhesive film (Anisotropic Conductive Film, ACF).
  • ACF isotropic Conductive Film
  • the conductive particles in the anisotropic conductive adhesive film are used to connect the first pad 121, the second pad 122, the third pad 141 and the fourth pad 142 with the corresponding connection electrodes 41, which can avoid or prevent the connection between adjacent pads. Adjacent connection electrodes 41 are short-circuited.
  • the conductive adhesive 43 is ACF, the conductive adhesive 43 can be provided as a whole layer.
  • the conductive glue 43 can also be made of other conductive glue materials.
  • first bonding pad 121 , the second bonding pad 122 , the third bonding pad 141 and the fourth bonding pad 142 and the corresponding connection electrode 41 can also be connected by other methods such as fusion welding.
  • FIG. 4 is a fourth structural schematic diagram of a display panel provided by this application.
  • the difference from the display panel 100 shown in FIG. 1 is that in the embodiment of the present application, the first light-emitting unit 30 is an OLED light-emitting unit, and the second light-emitting unit 40 is an LED chip.
  • the display panel 100 further includes the pixel definition layer 32 .
  • the first light-emitting unit 30 includes an anode 31 , a light-emitting layer 33 and a cathode 34 .
  • the flat layer 11 is provided with a via hole 11a.
  • the via hole 11 a exposes a side surface of the first source electrode 251 or the first drain electrode 252 away from the flexible substrate 10 .
  • Anode 31 is provided on flat layer 11 .
  • the anode 31 is connected to the first source electrode 251 or the first drain electrode 252 through the via hole 11a.
  • the pixel definition layer 32 is disposed on a side of the anode 31 away from the flexible substrate 10 .
  • Pixel definition layer 32 has openings 32a.
  • the opening 32 a exposes a side surface of the anode 31 away from the flexible substrate 10 .
  • the light-emitting layer 33 is provided within the opening 32a.
  • the cathode 34 is disposed on the side of the light-emitting layer 33 away from the flexible substrate 10 .
  • the cathode 34 can be provided on the entire surface, or can be patterned according to the requirements of the display panel 100 .
  • the OLED light-emitting unit may further include one or more of a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer.
  • the details can be set according to the actual requirements of the display panel 100 .
  • the light-emitting layer 33 of the OLED light-emitting unit may be an inorganic light-emitting material such as gallium nitride or quantum dots or an organic light-emitting material.
  • OLED light-emitting units can emit red light, blue light, green light, white light or yellow light, etc.
  • different light-emitting materials can be selected according to different light-emitting color requirements.
  • the structure of the second light-emitting unit 40 and its connection relationship with the driving circuit layer 20 are the same as the structure of the relevant film layers in the display panel 100 shown in FIG. 1 , and will not be described again here.
  • the first light-emitting unit 30 is an OLED light-emitting unit
  • the second light-emitting unit 40 is an LED chip, thereby achieving structural diversification of the display panel 100 .
  • FIG. 5 is a fifth structural schematic diagram of a display panel provided by this application.
  • the first light-emitting unit 30 is an LED chip
  • the second light-emitting unit 40 is an OLED light-emitting unit.
  • the display panel 100 further includes the pixel definition layer 32 .
  • the second light-emitting unit 40 includes an anode 31 , a light-emitting layer 33 and a cathode 34 .
  • the buffer layer 13 is disposed on the side of the flexible substrate 10 away from the driving circuit layer 20 .
  • the anode 31 is provided on the buffer layer 13 .
  • the anode 31 is connected to the second drain electrode 254 .
  • the pixel definition layer 32 is disposed on a side of the anode 31 away from the flexible substrate 10 .
  • Pixel definition layer 32 has openings 32a.
  • the opening 32 a exposes a side surface of the anode 31 away from the flexible substrate 10 .
  • the light-emitting layer 33 is provided within the opening 32a.
  • the cathode 34 is disposed on the side of the light-emitting layer 33 away from the flexible substrate 10 .
  • the structure of the first light-emitting unit 30 and its connection relationship with the driving circuit layer 20 are the same as the structure of the relevant film layers in the display panel 100 shown in FIG. 1 , and will not be described again here.
  • both the first light-emitting unit 30 and the second light-emitting unit 40 may be OLED light-emitting units.
  • the specific structure of the display panel 100 can be obtained based on the above embodiments, and will not be described again here.
  • the embodiment of the present application takes the display panel 100 shown in FIG. 1 as an example to describe the manufacturing method of the display panel 100 .
  • the manufacturing method of the display panel 100 may include but is not limited to the following steps:
  • the hard substrate may be a glass substrate.
  • the PI material can be coated on the glass substrate to form a substrate.
  • a fourth metal layer 14 is then formed on the substrate.
  • the fourth metal layer 14 includes third bonding pads 141 and fourth bonding pads 142 .
  • the buffer layer 13 Form the buffer layer 13, the flexible substrate 10, the protective layer 17, the first insulating layer 18 and the second insulating layer 19 in sequence on the substrate. Then, the active layer 21, the gate insulating layer 22, the first metal layer 23, the insulating layer 26, the fifth metal layer 27 and the interlayer insulating layer 24 are sequentially formed on the second insulating layer 19.
  • the active layer 21 includes a first active layer 211 and a second active layer 212 .
  • the gate insulating layer 22 covers the active layer 21 and the second insulating layer 19 .
  • the first metal layer 23 includes a first gate electrode 231 and a second gate electrode 232 that are spaced apart.
  • the first gate 231 is provided corresponding to the first active layer 211 .
  • the second gate 232 is provided corresponding to the second active layer 212 .
  • the fifth metal layer 27 includes a first electrode 271 and a second electrode 272 .
  • the first electrode 271 and the first gate electrode 231 are arranged correspondingly.
  • the second electrode 272 and the second gate electrode 232 are arranged correspondingly.
  • each contact hole 24 a penetrates the interlayer insulating layer 24 and extends to a side of the active layer 21 away from the flexible substrate 10 .
  • the contact hole 24 a exposes a side surface of the active layer 21 away from the flexible substrate 10 .
  • the connection hole 24b penetrates the interlayer insulating layer 24 and extends to the third pad 141 .
  • the connection hole 24b exposes a side surface of the third pad 141 away from the flexible substrate 10 .
  • the second metal layer 25 includes a first source electrode 251 , a first drain electrode 252 , a second source electrode 253 and a second drain electrode 254 .
  • the first source electrode 251 and the first drain electrode 252 are connected to the first active layer 211 respectively.
  • the second source electrode 253 and the second drain electrode 254 are respectively connected to the second active layer 212.
  • the second source electrode 253 or the second drain electrode 254 is connected to the third pad 141 through the connection hole 24b.
  • the flat layer 11 is formed on the second metal layer 25 .
  • the flat layer 11 is etched to form a via hole 11a.
  • the via hole 11 a exposes a side surface of the first source electrode 251 or the first drain electrode 252 away from the flexible substrate 10 .
  • a third metal layer 12 is formed on the flat layer 11 .
  • the third metal layer 12 includes a first bonding pad 121 and a second bonding pad 122 .
  • the first pad 121 is connected to the first source electrode 251 or the first drain electrode 252 through the via hole 11a.
  • the first encapsulation layer 101 is formed on the side of the first light-emitting unit 30 away from the flexible substrate 10 .
  • a second packaging layer 102 is formed on the side of the second light-emitting unit 40 away from the flexible substrate 10 .
  • the above embodiment only describes the manufacturing process of the display panel 100 shown in FIG. 1 .
  • the display panel 100 introduced in other embodiments of the present application can be obtained by deforming one or more steps in the above process, and will not be described again one by one.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示面板（100）。其中，驱动电路层（20）包括第一晶体管（T1）和第二晶体管（T2）。第一发光单元（30）设置在驱动电路层（20）远离柔性衬底（10）的一侧，并与第一晶体管（T1）连接，第一发光单元（30）远离柔性衬底（10）的一面发光。第二发光单元（40）设置在柔性衬底（10）远离驱动电路层（20）的一侧，并通过贯穿柔性衬底（10）的连接孔（24b）与第二晶体管（T2）连接，第二发光单元（40）远离柔性衬底（10）的一面发光。

Description

显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板。
 背景技术
目前显示面板以单面显示为主，但是在一些特殊的场合和领域，会使用到双面显示面板。比如，数字标牌、窗口询问设施、大型活动场所、户外广告等播放设施中往往存在需要从显示面板的正反两面同时观看显示画面的情况。现有的显示面板通常将两块显示屏通过模组手段整合在一起实现双面显示，成本较高，且不利于实现显示面板的轻薄化。
 技术问题
本申请提供一种显示面板，以解决现有技术中的双面显示面板成本较高、不利于轻薄化的技术问题。
 技术解决方案
本申请提供一种显示面板，其包括：
柔性衬底；
驱动电路层，设置在所述柔性衬底上，所述驱动电路层包括第一晶体管和第二晶体管；
第一发光单元，设置在所述驱动电路层远离所述柔性衬底的一侧，所述第一发光单元与所述第一晶体管的第一源极或第一漏极连接，所述第一发光单元远离所述柔性衬底的一面发光；
第二发光单元，设置在所述柔性衬底远离所述驱动电路层的一侧，所述第二发光单元通过贯穿所述柔性衬底的连接孔与所述第二晶体管的第二源极或第二漏极连接，所述第二发光单元远离所述柔性衬底的一面发光。
可选的，在本申请实施例中，沿所述柔性衬底朝向所述第一发光单元的方向上，所述驱动电路层包括层叠设置的有源层、栅绝缘层、第一金属层、层间绝缘层以及第二金属层；
其中，所述有源层包括间隔设置的第一有源层和第二有源层，所述第一金属层包括间隔设置的第一栅极和第二栅极，所述第一栅极对应所述第一有源层设置，所述第二栅极对应所述第二有源层设置，所述第二金属层包括所述第一源极、所述第一漏极、所述第二源极以及所述第二漏极，所述第一源极和所述第一漏极分别与所述第一有源层连接，所述第二源极和所述第二漏极分别与所述第二有源层连接。
可选的，在本申请实施例中，所述层间绝缘层具有多个接触孔和连接孔，每一所述接触孔贯穿所述层间绝缘层并延伸至所述有源层远离所述柔性衬底的一侧，所述接触孔暴露出所述有源层远离所述柔性衬底的一侧表面，所述连接孔贯穿所述层间绝缘层并延伸至所述柔性衬底远离所述驱动电路层的一侧；
其中，所述第一源极和所述第一漏极分别通过相应的所述接触孔与所述第一有源层连接，所述第二源极和所述第二漏极分别通过相应的所述接触孔与所述第二有源层连接，所述第二源极或所述第二漏极通过所述连接孔与所述第二发光单元连接。
可选的，在本申请实施例中，所述第一发光单元为LED芯片或OLED发光单元，所述第二发光单元为所述LED芯片或所述OLED发光单元。
可选的，在本申请实施例中，所述第一发光单元和所述第二发光单元均为LED芯片，所述显示面板还包括平坦层、第三金属层、缓冲层以及第四金属层；
所述平坦层设置在所述第二金属层远离所述柔性衬底的一侧，所述平坦层设有过孔，所述过孔暴露出所述第一源极或所述第一漏极远离所述柔性衬底的一侧表面，所述第三金属层设置在所述平坦层上，所述第三金属层包括第一焊盘和第二焊盘，所述第一焊盘通过所述过孔与所述第一源极或所述第一漏极连接，所述第一发光单元与所述第一焊盘以及所述第二焊盘连接；所述缓冲层设置在所述柔性衬底远离所述驱动电路层的一侧，所述第四金属层设置在所述缓冲层远离所述柔性衬底的一侧，所述第四金属层包括第三焊盘和第四焊盘，所述第三焊盘与所述第二源极或所述第二漏极连接，所述第二发光单元与所述第三焊盘以及所述第四焊盘连接。
可选的，在本申请实施例中，所述LED芯片包括连接电极，所述第一焊盘、所述第二焊盘、所述第三焊盘以及所述第四焊盘分别与相应的所述连接电极通过导电胶或金属键合连接。
可选的，在本申请实施例中，所述第一发光单元为OLED发光单元，所述第二发光单元为LED芯片，所述显示面板还包括平坦层和像素定义层，所述第一发光单元包括阳极、发光层以及阴极；
其中，所述平坦层设置在所述第二金属层远离所述柔性衬底的一侧，所述平坦层设有过孔，所述过孔暴露出所述第一源极或所述第一漏极远离所述柔性衬底的一侧表面，所述阳极设置在所述平坦层上，所述阳极通过所述过孔与所述第一源极或所述第一漏极连接，所述像素定义层设置在所述阳极远离所述柔性衬底的一侧，所述像素定义层具有开口，所述开口暴露出所述阳极远离所述柔性衬底的一侧表面，所述发光层设置在所述开口内，所述阴极设置在所述发光层远离所述柔性衬底的一侧。
可选的，在本申请实施例中，所述第一发光单元为LED芯片，所述第二发光单元为OLED发光单元，所述显示面板还包括缓冲层和第一像素定义层，所述第二发光单元包括阳极、发光层以及阴极；
其中，所述缓冲层设置在所述柔性衬底远离所述驱动电路层的一侧，所述阳极设置在所述缓冲层上，所述阳极通过所述连接孔与所述第二源极或所述第二漏极连接，所述像素定义层设置在所述阳极远离所述柔性衬底的一侧，所述像素定义层具有开口，所述开口暴露出所述阳极远离所述柔性衬底的一侧表面，所述发光层设置在所述开口内，所述阴极设置在所述发光层远离所述柔性衬底的一侧。
可选的，在本申请实施例中，所述驱动电路层还包括绝缘层和第五金属层；
其中，所述绝缘层设置在所述第一金属层远离所述柔性衬底的一侧，所述第五金属层设置在所述绝缘层和所述层间绝缘层之间，所述第五金属层包括第一电极和第二电极，所述第一电极和所述第一栅极对应设置，所述第二电极和所述第二栅极对应设置。
可选的，在本申请实施例中，所述显示面板还包括保护层、第一绝缘层、第二绝缘层、第一封装层以及第二封装层；
其中，沿所述柔性衬底朝向所述第一发光单元的方向上，所述保护层、所述第一绝缘层以及所述第二绝缘层依次叠层设置在所述柔性衬底和所述驱动电路层之间；所述第一封装层设置在所述第一发光单元远离所述柔性衬底的一侧，并覆盖所述第一发光单元，所述第二封装层设置在所述第二发光单元远离所述柔性衬底的一侧，并覆盖所述第二发光单元。
可选的，在本申请实施例中，所述显示面板包括多个所述第一发光单元和多个所述第二发光单元，所述驱动电路层包括多个所述第一晶体管和多个所述第二晶体管，每一所述第一晶体管与至少一个所述第一发光单元连接，每一所述第二晶体管与至少一所述第二发光单元连接。
可选的，在本申请实施例中，多个所述第一发光单元呈阵列排布，多个所述第二发光单元呈阵列排布，每相邻两个所述第二发光单元之间设有至少一个所述第一发光单元。
本申请还提供一种显示面板，其包括：
柔性衬底；
驱动电路层，设置在所述柔性衬底上，所述驱动电路层包括多个第一晶体管和多个第二晶体管；
多个第一发光单元，设置在所述驱动电路层远离所述柔性衬底的一侧，每一所述第一发光单元与相应的所述第一晶体管的第一源极或第一漏极连接，所述第一发光单元远离所述柔性衬底的一面发光；
多个第二发光单元，设置在所述柔性衬底远离所述驱动电路层的一侧，每一所述第二发光单元通过贯穿所述柔性衬底的连接孔与相应的所述第二晶体管的第二源极或第二漏极连接，所述第二发光单元远离所述柔性衬底的一面发光；
其中，所述第一发光单元为LED芯片或OLED发光单元，所述第二发光单元为所述LED芯片或所述OLED发光单元，每相邻两个所述第二发光单元之间设有至少一个所述第一发光单元。
 有益效果
本申请公开一种显示面板。由于第一发光单元和第二发光单元分别设置在柔性衬底的两侧，且第二发光单元通过贯穿柔性衬底的连接孔与驱动电路层连接，因此不需要特殊的膜层结构设计或膜层材料改进，即可实现第一发光单元和第二发光单元分别朝向柔性衬底的两侧发光的目的，降低了工艺制程的难度。此外，由于驱动电路层设置在柔性衬底的一侧，并通过同一驱动电路层驱动第一发光单元和第二发光单元，相较于现有技术中将两块显示屏通过模组手段整合在一起的方案，至少减少了一层基板和一层驱动电路层，有效降低了生产成本，且利于实现显示面板的轻薄化。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1是本申请提供的显示面板的第一结构示意图；
图2是本申请提供的显示面板的第二结构示意图；
图3是本申请提供的显示面板的第三结构示意图；
图4是本申请提供的显示面板的第四结构示意图；
图5是本申请提供的显示面板的第五结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获取的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”和“第二”等的特征可以明示或者隐含地包括一个或者更多个所述特征，因此不能理解为对本申请的限制。
本申请提供一种显示面板，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1，图1是本申请提供的显示面板的第一结构示意图。在本申请实施例中，显示面板100包括柔性衬底10、驱动电路层20、第一发光单元30以及第二发光单元40。
其中，驱动电路层20设置在柔性衬底10上。驱动电路层20包括第一晶体管T1和第二晶体管T2。第一发光单元30设置在驱动电路层20远离柔性衬底10的一侧。第一发光单元30与第一晶体管T1的第一源极251或第一漏极252连接。第一发光单元30远离柔性衬底10的一面发光。第二发光单元40设置在柔性衬底10远离驱动电路层20的一侧。第二发光单元40通过贯穿柔性衬底10的连接孔24b与第二晶体管T2的第二源极253或第二漏极254连接。第二发光单元40远离柔性衬底10的一面发光。
本申请实施例通过在显示面板100中设置驱动电路层20，并利用驱动电路层20分别驱动第一发光单元30和第二发光单元40，且第一发光单元30和第二发光单元40的发光方向反向，实现了显示面板100的双面显示。
此外，由于第一发光单元30和第二发光单元40分别设置在柔性衬底10的两侧，且第二发光单元40通过贯穿柔性衬底10的连接孔24b与驱动电路层20连接，因此不需要特殊的膜层结构设计或膜层材料改进，即可实现第一发光单元30和第二发光单元40分别朝向柔性衬底10的两侧发光的目的，降低了工艺制程的难度。再则，由于驱动电路层20设置在柔性衬底10的一侧，并通过同一驱动电路层20驱动第一发光单元30和第二发光单元40，相较于相关技术中将两块显示屏通过模组手段整合在一起的方案，至少减少了一层基板（如，柔性衬底）和一层驱动电路层20，有效降低了生产成本，且利于实现显示面板100的轻薄化。
在本申请实施例中，柔性衬底10可以包括一层、两层或两层以上的柔性PI（Polyimide，聚酰亚胺）。柔性衬底10也可以由树脂等材料制成。柔性衬底10主要起到承载以及保护驱动电路层20的作用，以提高显示面板100的结构稳定性。
在本申请实施例中，驱动电路层20用于为第一发光单元30以及第二发光单元40提供驱动信号，如驱动电压、电源电压等。驱动电路层20包括但不限于第一晶体管T1和第二晶体管T2。比如，为了补偿晶体管的阈值电压偏移或迁移率偏移，驱动电路层20可以包括驱动第一发光单元30或第二发光单元40的3T1C（3个晶体管1个电容）、4T2C（4个晶体管2个电容）、7T1C（7个晶体管1个电容）等像素驱动电路。上述像素驱动电路的具体结构可以参照现有技术，在此不再赘述。本申请实施例仅以第一晶体管T1和第二晶体管T2为例，对驱动电路层20与第一发光单元30以及第二发光单元40之间的连接关系进行说明，但不能理解为对本申请的限定。
在本申请实施例中，第一晶体管T1和第二晶体管T2可以为薄膜晶体管、场效应管或其他特性相同的器件。由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。此外本申请实施例所采用的晶体管可以包括P型晶体管和/或N型晶体管两种，其中，P型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
在本申请实施例中，第一晶体管T1和第二晶体管T2可以为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。本申请实施例提供的驱动电路层20中的晶体管均为同一种类型的晶体管，从而可以简化制程工艺，且避免不同类型的晶体管之间的差异性对驱动电路层20造成驱动异常。
在本申请实施例中，第一发光单元30和第二发光单元40可以是LED芯片、OLED发光单元、量子点发光器件等。比如，第一发光单元30和第二发光单元40均为LED芯片。或者第一发光单元30和第二发光单元40均为OLED发光单元。又或者第一发光单元30为LED芯片，第二发光单元40为OLED发光单元等。具体将在以下实施例中进行说明，在此不再赘述。
在本申请实施例中，显示面板100可以包括多个第一发光单元30和多个第二发光单元40。驱动电路层20包括多个第一晶体管T1和多个第二晶体管T2。每一第一晶体管T1与至少一个第一发光单元30连接。每一第二晶体管T2与至少一第二发光单元40连接。
可以理解的是，在本申请实施例中，当多个第一晶体管T1与多个第一发光单元30一一对应连接，且多个第二晶体管T2与多个第二发光单元40一一对应连接时，一个第一发光单元30或一个第二发光单元40可以认为是一个像素点。当每一第一晶体管T1与两个或两个以上第一发光单元30连接，每一第二晶体管T2与两个或两个第二发光单元40连接时，一个像素点可以包括多个第一发光单元30或多个第二发光单元40，从而提高像素点的亮度。
本申请以下各实施例均以一个第一晶体管T1与一个第一发光单元30连接，且一个第二晶体管T2与一个第二发光单元40连接为例进行说明，但不能理解为对本申请的限定。
在本申请实施例中，请继续参阅图1，沿柔性衬底10朝向第一发光单元30的方向上，驱动电路层20包括层叠设置的有源层21、栅绝缘层22、第一金属层23、层间绝缘层24以及第二金属层25。
具体的，有源层21设置在柔性衬底10靠近驱动电路层20的一侧。有源层21包括间隔设置的第一有源层211和第二有源层212。栅绝缘层22设置在有源层21远离柔性衬底10的一侧。栅绝缘层22覆盖有源层21。第一金属层23设置在栅绝缘层22远离柔性衬底10的一侧。第一金属层23包括间隔设置的第一栅极231和第二栅极232。第一栅极231对应第一有源层211设置。第二栅极232对应第二有源层212设置。层间绝缘层24设置在第一金属层23远离柔性衬底10的一侧。第二金属层25设置在层间绝缘层24远离柔性衬底10的一侧。第二金属层25包括第一源极251、第一漏极252、第二源极253以及第二漏极254。第一源极251和第一漏极252分别与第一有源层211连接。第二源极253和第二漏极254分别与第二有源层212连接。
其中，第一有源层211与第一源极251以及第一漏极252的接触连接处为重掺杂区。第二有源层212与第二源极253以及第二漏极254的接触连接处为重掺杂区。
其中，第一晶体管T1包括第一有源层211、第一栅极231、第一源极251以及第一漏极252。第二晶体管T2包括第二有源层212、第二栅极232、第二源极253以及第二漏极254。
本申请实施例将第一晶体管T1和第二晶体管T2同层设置，也即第一晶体管T1中的各功能膜层与第二晶体管T2中相应的功能膜层同层设置，可以简化制程工艺，降低生产成本。同时有利于实现显示面板100的轻薄化。
当然，在本申请其它实施例中，也可将第一晶体管T1和第二晶体管T2异层设置。比如，第一晶体管T1和第二晶体管T2均设置在柔性衬底10靠近第一发光单元30的一侧，但第一晶体管T1位于第一发光单元30和第二发光单元40之间。又比如，第一晶体管T1的第一有源层211和第二晶体管T2的第二有源层212可以同层设置，但第一晶体管T1的其它膜层异层和第二晶体管T2的其它膜层异层设置。
进一步的，在本申请实施例中，层间绝缘层24具有多个接触孔24a和连接孔24b。每一接触孔24a贯穿层间绝缘层24并延伸至有源层21远离柔性衬底10的一侧。接触孔24a暴露出有源层21远离柔性衬底10的一侧表面。连接孔24b贯穿层间绝缘层24并延伸至柔性衬底10远离驱动电路层20的一侧。
其中，第一源极251和第一漏极252分别通过相应的接触孔24a与第一有源层211连接。第二源极253和第二漏极254分别通过相应的接触孔24a与第二有源层212连接。第二源极253和第二漏极254中的一者通过连接孔24b与第二发光单元40连接。
需要说明的是，本申请实施例中的附图均以第一发光单元30与第一漏极252连接，以及第二漏极254通过连接孔24b与第二发光单元40连接为例进行说明，但不能理解为对本申请的限定。
在本申请实施例中，通过设置贯穿层间绝缘层24、柔性衬底10等功能膜层的深孔，即连接孔24b，实现了第二发光单元40与第二晶体管T2的连接，从而实现驱动电路层20对第二发光单元40的驱动，保证显示面板100双面正常发光。此外，本申请实施例采用了柔性衬底10，由于柔性衬底10的材料特性，在形成连接孔24b时，可以降低制程难度，并避免在柔性衬底10中产生裂纹，从而提高产品质量。
在本申请一实施例中，第一发光单元30和第二发光单元40均为LED芯片。本申请实施例通过巨量转移等技术将多个LED芯片设置在显示面板100中柔性衬底10的两侧，在实现双面显示的同时，可以降低工艺制程的难度。
当第一发光单元30和第二发光单元40均为LED芯片时，显示面板100还包括平坦层11、第三金属层12、缓冲层13以及第四金属层14。
其中，平坦层11设置在第二金属层25远离柔性衬底10的一侧。平坦层11设有过孔11a。过孔11a暴露出第一源极251或第一漏极252远离柔性衬底10的一侧表面。第三金属层12设置在平坦层11上。第三金属层12包括第一焊盘121和第二焊盘122。第一焊盘121通过过孔11a与第一源极251或第一漏极252连接。第一发光单元30分别与第一焊盘121以及第二焊盘122连接。缓冲层13设置在柔性衬底10远离驱动电路层20的一侧。第四金属层14设置在缓冲层13远离柔性衬底10的一侧。第四金属层14包括第三焊盘141和第四焊盘142。第三焊盘141与第二源极253和第二漏极254中的一者连接。第二发光单元40分别与第三焊盘141以及第四焊盘142连接。
具体的，在本申请实施例中，过孔11a暴露出第一漏极252远离柔性衬底10的一侧表面。第一焊盘121通过过孔11a与第一漏极252连接。第一发光单元30通过第一焊盘121与第一晶体管T1绑定连接。第三焊盘141与第二漏极254连接。第二发光单元40通过第三焊盘141与第二晶体管T2连接。
在本申请实施例中，LED芯片可以是Mini-LED（Mini Light-Emitting Diode, 次毫米发光二极管）芯片、Micro-LED（Micro Light-Emitting Diode, 微发光二极管）芯片等。每一LED芯片均包括两个连接电极41。两个连接电极41沉积在发光材料层上。其中一连接电极41为LED芯片的正极，另一连接电极41为LED芯片的负极。当然，本申请实施例中的LED芯片的结构并不限于此。
具体的，在第一发光单元30中，其中一连接电极41与第一焊盘121连接，另一连接电极41与第二焊盘122连接。在第二发光单元40中，其中一连接电极41与第三焊盘141连接，另一连接电极41与第四焊盘142连接。
在本申请实施例中，第一焊盘121、第二焊盘122、第三焊盘141以及第四焊盘142与相应的连接电极41之间通过金属键合连接。
其中，金属键是将金属中的原子连接在一起的化学键。它们不同于共价键和离子键，因为金属键合中的电子是非定域的，也就是说，它们不是只在两个原子之间共享的。相反，金属键中的电子在金属原子核的晶格中自由浮动。这种键合类型赋予金属许多独特的材料特性，包括优异的导热性和导电性、高熔点和延展性。金属键合使得第一焊盘121、第二焊盘122、第三焊盘141以及第四焊盘142与相应的连接电极41之间具有良好的导电性。
在本申请实施例中，LED芯片的发光材料可以是氮化镓、量子点等无机发光材料或有机发光材料。LED芯片可以发射红光、蓝光、绿光、白光或黄光等。在制作LED芯片时，可根据不同的发光颜色需求选择不同的发光材料。
在本申请实施例中，驱动电路层20还可以包括绝缘层26和第五金属层27。绝缘层26设置在第一金属层23远离柔性衬底10的一侧。第五金属层27设置在绝缘层26和层间绝缘层24之间。第五金属层27包括第一电极271和第二电极272。第一电极271和第一栅极231对应设置。第二电极272和第二栅极232对应设置。
其中，第一电极271和第一栅极231构成一存储电容的两极板。第二电极272和第二栅极232构成另一存储电容的两极板。本申请实施例利用第一栅极231（第二栅极232）作为存储电容的其中一极，可以进一步简化工艺制程，减小显示面板100的厚度。
在本申请实施例中，显示面板100还可以包括保护层17、第一绝缘层18、第二绝缘层19、第一封装层101以及第二封装层102。
其中，沿柔性衬底10朝向第一发光单元30的方向上，保护层17、第一绝缘层18以及第二绝缘层19依次叠层设置在柔性衬底10和驱动电路层20之间。第一封装层101设置在第一发光单元30远离柔性衬底10的一侧，并覆盖第一发光单元30。第二封装层102设置在第二发光单元40远离柔性衬底10的一侧，并覆盖第二发光单元40。
其中，保护层17的材料可以是氧化硅。第一绝缘层18的材料可以是氮化硅。第二绝缘层19的材料可以是氧化硅。保护层17、第一绝缘层18以及第二绝缘层19用于隔离柔性衬底10和驱动电路层20，起到阻水隔氧的作用。在对有源层21进行高温处理时，第二绝缘层19还起到保温的作用。
其中，在本申请实施例中，第一封装层101和第二封装层102的材料通常是透明的，以提高显示面板100的光线透过率。具体的，第一封装层101和第二封装层102的材料可以是OCA（Optically Clear Adhesive，光学胶）或者其它透明胶。本申请实施例采用透明胶形成第一封装层101和第二封装层102，一方面可以提高显示面板100的出光效率。另一方面，由于第一封装层101覆盖第一发光单元30，第二封装层102覆盖第二发光单元40，可以起到固定保护第一发光单元30和第二发光单元40的作用。
在本申请实施例中，多个第一发光单元30呈阵列排布，多个第二发光单元40呈阵列排布，每相邻两个第二发光单元40之间设有至少一个第一发光单元30。
具体的，每相邻两个第二发光单元40之间可以设有一个第一发光单元30、两个第一发光单元30或两个以上第一发光单元30。当然，在本申请其它实施例中，多个第一发光单元30和多个第二发光单元40也可按照其他规律排布，本申请对此不作限定。
如图1所示，每相邻两个第二发光单元40之间设有一个第一发光单元30。也即，显示面板100正反两侧显示画面的像素分辨率相等。
请参阅图2，图2是本申请提供的显示面板的第二结构示意图。与图1所示的显示面板100的不同之处在于，在本申请实施例中，每相邻两个第二发光单元40之间设有两个第一发光单元30。如此，显示面板100设有第一发光单元30的一侧的像素分辨率大于设有第二发光单元40的一侧的像素分辨率。
在本申请其它实施例中，每相邻两个第一发光单元30之间设有至少两个第二发光单元40。如此，显示面板100设有第一发光单元30的一侧的像素分辨率小于设有第二发光单元40的一侧的像素分辨率。
请参阅图3，图3是本申请提供的显示面板的第三结构示意图。与图1所示的显示面板100的不同之处在于，在本申请实施例中，第一焊盘121、第二焊盘122、第三焊盘141以及第四焊盘142与相应的连接电极41之间通过导电胶43连接。
具体的，显示面板100还包括导电胶43。导电胶43的材料可以是异方性导电胶膜（Anisotropic Conductive Film, ACF）。利用异方性导电胶膜中的导电粒子连接第一焊盘121、第二焊盘122、第三焊盘141以及第四焊盘142与相应的连接电极41，能够避免相邻焊盘之间或相邻连接电极41之间短路。当导电胶43为ACF时，导电胶43可以整层设置。当然，导电胶43也可以由其它导电胶材制成。
在本申请其它实施例中，第一焊盘121、第二焊盘122、第三焊盘141以及第四焊盘142与相应的连接电极41也可通过熔融焊接等其他方式连接。
请参阅图4，图4是本申请提供的显示面板的第四结构示意图。与图1所示的显示面板100的不同之处在于，在本申请实施例中，第一发光单元30为OLED发光单元，第二发光单元40为LED芯片。
在这种情况下，显示面板100还包括像素定义层32。第一发光单元30包括阳极31、发光层33以及阴极34。
其中，平坦层11设有过孔11a。过孔11a暴露出第一源极251或第一漏极252远离柔性衬底10的一侧表面。阳极31设置在平坦层11上。阳极31通过过孔11a与第一源极251或第一漏极252连接。像素定义层32设置在阳极31远离柔性衬底10的一侧。像素定义层32具有开口32a。开口32a暴露出阳极31远离柔性衬底10的一侧表面。发光层33设置在开口32a内。阴极34设置在发光层33远离柔性衬底10的一侧。阴极34可以整面设置，也可以根据显示面板100的需求图案化设置。
其中，OLED发光单元还可以包括空穴注入层、空穴传输层、电子传输层以及电子注入层中的一个或多个。具体可根据显示面板100的实际需求进行设置。
其中，OLED发光单元的发光层33可以是氮化镓、量子点等无机发光材料或有机发光材料。OLED发光单元可以发射红光、蓝光、绿光、白光或黄光等。在制作OLED发光单元时，可根据不同的发光颜色需求选择不同的发光材料。
需要说明的是，第二发光单元40的结构以及其与驱动电路层20的连接关系与图1所示的显示面板100中相关膜层结构一样，在此不再赘述。
本申请实施例设置第一发光单元30为OLED发光单元，第二发光单元40为LED芯片，实现了显示面板100的结构多元化。
请参阅图5，图5是本申请提供的显示面板的第五结构示意图。与图1所示的显示面板100的不同之处在于，在本申请实施例中，第一发光单元30为LED芯片，第二发光单元40为OLED发光单元。
在这种情况下，显示面板100还包括像素定义层32。第二发光单元40包括阳极31、发光层33以及阴极34。
其中，缓冲层13设置在柔性衬底10远离驱动电路层20的一侧。阳极31设置在缓冲层13上。阳极31与第二漏极254连接。像素定义层32设置在阳极31远离柔性衬底10的一侧。像素定义层32具有开口32a。开口32a暴露出阳极31远离柔性衬底10的一侧表面。发光层33设置在开口32a内。阴极34设置在发光层33远离柔性衬底10的一侧。
需要说明的是，第一发光单元30的结构以及其与驱动电路层20的连接关系与图1所示的显示面板100中相关膜层结构一样，在此不再赘述。
当然，在本申请其它实施例中，也可以设置第一发光单元30和第二发光单元40均为OLED发光单元。在这种情况下，显示面板100的具体结构可根据上述实施例结合得到，在此不再赘述。
此外，本申请实施例以图1所示的显示面板100为例，对显示面板100的制作方法进行说明。具体的，显示面板100的制作方法可包括但不限于以下步骤：
101、提供一硬质基板，在所述硬质基板上衬底，并在衬底上形成第三焊盘141和第四焊盘142。
具体的，硬质基板可以是玻璃基板。在玻璃基板可涂布PI材料，形成衬底。然后在衬底上形成第四金属层14。第四金属层14包括第三焊盘141和第四焊盘142。
102、在衬底上依次形成缓冲层13、柔性衬底10、保护层17、第一绝缘层18以及第二绝缘层19。然后在第二绝缘层19上依次形成有源层21、栅绝缘层22、第一金属层23、绝缘层26、第五金属层27以及层间绝缘层24。
其中，有源层21包括第一有源层211和第二有源层212。栅绝缘层22覆盖有源层21和第二绝缘层19。第一金属层23包括间隔设置的第一栅极231和第二栅极232。第一栅极231对应第一有源层211设置。第二栅极232对应第二有源层212设置。第五金属层27包括第一电极271和第二电极272。第一电极271和第一栅极231对应设置。第二电极272和第二栅极232对应设置。
103、对层间绝缘层24进行刻蚀处理，形成多个接触孔24a和连接孔24b。每一接触孔24a贯穿层间绝缘层24并延伸至有源层21远离柔性衬底10的一侧。接触孔24a暴露出有源层21远离柔性衬底10的一侧表面。连接孔24b贯穿层间绝缘层24并延伸至第三焊盘141。连接孔24b暴露出第三焊盘141远离柔性衬底10的一侧表面。
104、在层间绝缘层24上形成第二金属层25。第二金属层25包括第一源极251、第一漏极252、第二源极253以及第二漏极254。第一源极251和第一漏极252分别与第一有源层211连接。第二源极253和第二漏极254分别与第二有源层212连接。第二源极253或第二漏极254通过连接孔24b与第三焊盘141连接。
然后，在第二金属层25上形成平坦层11。对平坦层11进行刻蚀处理，形成过孔11a。过孔11a暴露出第一源极251或第一漏极252远离柔性衬底10的一侧表面。在平坦层11上形成第三金属层12。第三金属层12包括第一焊盘121和第二焊盘122。第一焊盘121通过过孔11a与第一源极251或第一漏极252连接。
105、通过巨量转移等技术将LED芯片与第一焊盘121和第二焊盘122绑定连接，形成第一发光单元30。然后，在第一发光单元30远离柔性衬底10的一侧形成第一封装层101。
106、通过激光剥离、机械剥离、药液浸泡等方法剥离去除硬质基板和衬底，暴露出第三焊盘141和第四焊盘142远离柔性衬底10的一侧表面。
107、将上述制成的半成品显示面板翻转，通过巨量转移等技术将LED芯片与第三焊盘141和第四焊盘142绑定连接，形成第二发光单元40。然后，在第二发光单元40远离柔性衬底10的一侧形成第二封装层102。
需要说明的是，上述实施例仅对图1所示的显示面板100的制作过程进行了描述。本申请其它实施例中介绍的显示面板100均可以通过对上述工艺制程中的一个或多个步骤进行变形得到，在此不再一一赘述。
以上对本申请提供的显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其包括：
    柔性衬底；
    驱动电路层，设置在所述柔性衬底上，所述驱动电路层包括多个第一晶体管和多个第二晶体管；
    多个第一发光单元，设置在所述驱动电路层远离所述柔性衬底的一侧，每一所述第一发光单元与相应的所述第一晶体管的第一源极或第一漏极连接，所述第一发光单元远离所述柔性衬底的一面发光；
    多个第二发光单元，设置在所述柔性衬底远离所述驱动电路层的一侧，每一所述第二发光单元通过贯穿所述柔性衬底的连接孔与相应的所述第二晶体管的第二源极或第二漏极连接，所述第二发光单元远离所述柔性衬底的一面发光；
    其中，所述第一发光单元为LED芯片或OLED发光单元，所述第二发光单元为所述LED芯片或所述OLED发光单元，每相邻两个所述第二发光单元之间设有至少一个所述第一发光单元。
  2. 根据权利要求1所述的显示面板，其中，沿所述柔性衬底朝向所述第一发光单元的方向上，所述驱动电路层包括层叠设置的有源层、栅绝缘层、第一金属层、层间绝缘层以及第二金属层；
    其中，所述有源层包括间隔设置的第一有源层和第二有源层，所述第一金属层包括间隔设置的第一栅极和第二栅极，所述第一栅极对应所述第一有源层设置，所述第二栅极对应所述第二有源层设置，所述第二金属层包括所述第一源极、所述第一漏极、所述第二源极以及所述第二漏极，所述第一源极和所述第一漏极分别与所述第一有源层连接，所述第二源极和所述第二漏极分别与所述第二有源层连接。
  3. 根据权利要求2所述的显示面板，其中，所述层间绝缘层具有多个接触孔和所述连接孔，每一所述接触孔贯穿所述层间绝缘层并延伸至所述有源层远离所述柔性衬底的一侧，所述接触孔暴露出所述有源层远离所述柔性衬底的一侧表面，所述连接孔贯穿所述层间绝缘层并延伸至所述柔性衬底远离所述驱动电路层的一侧；
    其中，所述第一源极和所述第一漏极分别通过相应的所述接触孔与所述第一有源层连接，所述第二源极和所述第二漏极分别通过相应的所述接触孔与所述第二有源层连接，所述第二源极或所述第二漏极通过所述连接孔与所述第二发光单元连接。
  4. 根据权利要求1所述的显示面板，其中，所述第一发光单元和所述第二发光单元均为LED芯片，所述显示面板还包括平坦层、第三金属层、缓冲层以及第四金属层；
    所述平坦层设置在所述第二金属层远离所述柔性衬底的一侧，所述平坦层设有过孔，所述过孔暴露出所述第一源极或所述第一漏极远离所述柔性衬底的一侧表面，所述第三金属层设置在所述平坦层上，所述第三金属层包括第一焊盘和第二焊盘，所述第一焊盘通过所述过孔与所述第一源极或所述第一漏极连接，所述第一发光单元与所述第一焊盘以及所述第二焊盘连接；所述缓冲层设置在所述柔性衬底远离所述驱动电路层的一侧，所述第四金属层设置在所述缓冲层远离所述柔性衬底的一侧，所述第四金属层包括第三焊盘和第四焊盘，所述第三焊盘与所述第二源极或所述第二漏极连接，所述第二发光单元与所述第三焊盘以及所述第四焊盘连接。
  5. 根据权利要求4所述的显示面板，其中，每一所述LED芯片均包括两个连接电极，所述第一焊盘、所述第二焊盘、所述第三焊盘以及所述第四焊盘分别与相应的所述连接电极通过导电胶或金属键合连接。
  6. 根据权利要求1所述的显示面板，其中，所述第一发光单元为OLED发光单元，所述第二发光单元为LED芯片，所述显示面板还包括平坦层和像素定义层，所述第一发光单元包括阳极、发光层以及阴极；
    其中，所述平坦层设置在所述第二金属层远离所述柔性衬底的一侧，所述平坦层设有过孔，所述过孔暴露出所述第一源极或所述第一漏极远离所述柔性衬底的一侧表面，所述阳极设置在所述平坦层上，所述阳极通过所述过孔与所述第一源极或所述第一漏极连接，所述像素定义层设置在所述阳极远离所述柔性衬底的一侧，所述像素定义层具有开口，所述开口暴露出所述阳极远离所述柔性衬底的一侧表面，所述发光层设置在所述开口内，所述阴极设置在所述发光层远离所述柔性衬底的一侧。
  7. 根据权利要求1所述的显示面板，其中，所述第一发光单元为LED芯片，所述第二发光单元为OLED发光单元，所述显示面板还包括缓冲层和第一像素定义层，所述第二发光单元包括阳极、发光层以及阴极；
    其中，所述缓冲层设置在所述柔性衬底远离所述驱动电路层的一侧，所述阳极设置在所述缓冲层上，所述阳极通过所述连接孔与所述第二源极或所述第二漏极连接，所述像素定义层设置在所述阳极远离所述柔性衬底的一侧，所述像素定义层具有开口，所述开口暴露出所述阳极远离所述柔性衬底的一侧表面，所述发光层设置在所述开口内，所述阴极设置在所述发光层远离所述柔性衬底的一侧。
  8. 根据权利要求1所述的显示面板，其中，每相邻两个所述第二发光单元之间设有两个所述第一发光单元。
  9. 一种显示面板，其包括：
    柔性衬底；
    驱动电路层，设置在所述柔性衬底上，所述驱动电路层包括第一晶体管和第二晶体管；
    第一发光单元，设置在所述驱动电路层远离所述柔性衬底的一侧，所述第一发光单元与所述第一晶体管的第一源极或第一漏极连接，所述第一发光单元远离所述柔性衬底的一面发光；
    第二发光单元，设置在所述柔性衬底远离所述驱动电路层的一侧，所述第二发光单元通过贯穿所述柔性衬底的连接孔与所述第二晶体管的第二源极或第二漏极连接，所述第二发光单元远离所述柔性衬底的一面发光。
  10. 根据权利要求9所述的显示面板，其中，沿所述柔性衬底朝向所述第一发光单元的方向上，所述驱动电路层包括层叠设置的有源层、栅绝缘层、第一金属层、层间绝缘层以及第二金属层；
    其中，所述有源层包括间隔设置的第一有源层和第二有源层，所述第一金属层包括间隔设置的第一栅极和第二栅极，所述第一栅极对应所述第一有源层设置，所述第二栅极对应所述第二有源层设置，所述第二金属层包括所述第一源极、所述第一漏极、所述第二源极以及所述第二漏极，所述第一源极和所述第一漏极分别与所述第一有源层连接，所述第二源极和所述第二漏极分别与所述第二有源层连接。
  11. 根据权利要求10所述的显示面板，其中，所述层间绝缘层具有多个接触孔和所述连接孔，每一所述接触孔贯穿所述层间绝缘层并延伸至所述有源层远离所述柔性衬底的一侧，所述接触孔暴露出所述有源层远离所述柔性衬底的一侧表面，所述连接孔贯穿所述层间绝缘层并延伸至所述柔性衬底远离所述驱动电路层的一侧；
    其中，所述第一源极和所述第一漏极分别通过相应的所述接触孔与所述第一有源层连接，所述第二源极和所述第二漏极分别通过相应的所述接触孔与所述第二有源层连接，所述第二源极或所述第二漏极通过所述连接孔与所述第二发光单元连接。
  12. 根据权利要求9所述的显示面板，其中，所述第一发光单元为LED芯片或OLED发光单元，所述第二发光单元为所述LED芯片或所述OLED发光单元。
  13. 根据权利要求12所述的显示面板，其中，所述第一发光单元和所述第二发光单元均为LED芯片，所述显示面板还包括平坦层、第三金属层、缓冲层以及第四金属层；
    所述平坦层设置在所述第二金属层远离所述柔性衬底的一侧，所述平坦层设有过孔，所述过孔暴露出所述第一源极或所述第一漏极远离所述柔性衬底的一侧表面，所述第三金属层设置在所述平坦层上，所述第三金属层包括第一焊盘和第二焊盘，所述第一焊盘通过所述过孔与所述第一源极或所述第一漏极连接，所述第一发光单元与所述第一焊盘以及所述第二焊盘连接；所述缓冲层设置在所述柔性衬底远离所述驱动电路层的一侧，所述第四金属层设置在所述缓冲层远离所述柔性衬底的一侧，所述第四金属层包括第三焊盘和第四焊盘，所述第三焊盘与所述第二源极或所述第二漏极连接，所述第二发光单元与所述第三焊盘以及所述第四焊盘连接。
  14. 根据权利要求13所述的显示面板，其中，每一所述LED芯片均包括两个连接电极，所述第一焊盘、所述第二焊盘、所述第三焊盘以及所述第四焊盘分别与相应的所述连接电极通过导电胶或金属键合连接。
  15. 根据权利要求12所述的显示面板，其中，所述第一发光单元为OLED发光单元，所述第二发光单元为LED芯片，所述显示面板还包括平坦层和像素定义层，所述第一发光单元包括阳极、发光层以及阴极；
    其中，所述平坦层设置在所述第二金属层远离所述柔性衬底的一侧，所述平坦层设有过孔，所述过孔暴露出所述第一源极或所述第一漏极远离所述柔性衬底的一侧表面，所述阳极设置在所述平坦层上，所述阳极通过所述过孔与所述第一源极或所述第一漏极连接，所述像素定义层设置在所述阳极远离所述柔性衬底的一侧，所述像素定义层具有开口，所述开口暴露出所述阳极远离所述柔性衬底的一侧表面，所述发光层设置在所述开口内，所述阴极设置在所述发光层远离所述柔性衬底的一侧。
  16. 根据权利要求12所述的显示面板，其中，所述第一发光单元为LED芯片，所述第二发光单元为OLED发光单元，所述显示面板还包括缓冲层和第一像素定义层，所述第二发光单元包括阳极、发光层以及阴极；
    其中，所述缓冲层设置在所述柔性衬底远离所述驱动电路层的一侧，所述阳极设置在所述缓冲层上，所述阳极通过所述连接孔与所述第二源极或所述第二漏极连接，所述像素定义层设置在所述阳极远离所述柔性衬底的一侧，所述像素定义层具有开口，所述开口暴露出所述阳极远离所述柔性衬底的一侧表面，所述发光层设置在所述开口内，所述阴极设置在所述发光层远离所述柔性衬底的一侧。
  17. 根据权利要求11所述的显示面板，其中，所述驱动电路层还包括绝缘层和第五金属层；
    其中，所述绝缘层设置在所述第一金属层远离所述柔性衬底的一侧，所述第五金属层设置在所述绝缘层和所述层间绝缘层之间，所述第五金属层包括第一电极和第二电极，所述第一电极和所述第一栅极对应设置，所述第二电极和所述第二栅极对应设置。
  18. 根据权利要求11所述的显示面板，其中，所述显示面板还包括保护层、第一绝缘层、第二绝缘层、第一封装层以及第二封装层；
    其中，沿所述柔性衬底朝向所述第一发光单元的方向上，所述保护层、所述第一绝缘层以及所述第二绝缘层依次叠层设置在所述柔性衬底和所述驱动电路层之间；所述第一封装层设置在所述第一发光单元远离所述柔性衬底的一侧，并覆盖所述第一发光单元，所述第二封装层设置在所述第二发光单元远离所述柔性衬底的一侧，并覆盖所述第二发光单元。
  19. 根据权利要求9所述的显示面板，其中，所述显示面板包括多个所述第一发光单元和多个所述第二发光单元，所述驱动电路层包括多个所述第一晶体管和多个所述第二晶体管，每一所述第一晶体管与至少一个所述第一发光单元连接，每一所述第二晶体管与至少一所述第二发光单元连接。
  20. 根据权利要求19所述的显示面板，其中，多个所述第一发光单元呈阵列排布，多个所述第二发光单元呈阵列排布，每相邻两个所述第二发光单元之间设有至少一个所述第一发光单元。
PCT/CN2022/105323 2022-06-28 2022-07-13 显示面板 WO2024000653A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/759,374 US20240215429A1 (en) 2022-06-28 2022-07-13 Display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210753485.6A CN115117135A (zh) 2022-06-28 2022-06-28 显示面板
CN202210753485.6 2022-06-28

Publications (1)

Publication Number Publication Date
WO2024000653A1 true WO2024000653A1 (zh) 2024-01-04

Family

ID=83330443

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/105323 WO2024000653A1 (zh) 2022-06-28 2022-07-13 显示面板

Country Status (3)

Country Link
US (1) US20240215429A1 (zh)
CN (1) CN115117135A (zh)
WO (1) WO2024000653A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117750818A (zh) * 2023-11-07 2024-03-22 惠科股份有限公司 显示面板及其制备方法
CN117412639A (zh) * 2023-12-14 2024-01-16 惠科股份有限公司 显示面板及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040195959A1 (en) * 2002-12-28 2004-10-07 Lg.Philips Lcd Co., Ltd. Dual panel-type organic electroluminescent device and method for fabricating the same
CN107833904A (zh) * 2017-10-30 2018-03-23 深圳市华星光电半导体显示技术有限公司 双面oled显示面板及其制造方法
CN107863368A (zh) * 2017-09-18 2018-03-30 合肥惠科金扬科技有限公司 一种双面显示装置
CN109997230A (zh) * 2019-01-29 2019-07-09 京东方科技集团股份有限公司 像素单元及其制造方法和双面oled显示装置
CN112086488A (zh) * 2020-09-07 2020-12-15 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785381B (zh) * 2017-10-13 2020-12-22 深圳市华星光电半导体显示技术有限公司 Oled面板的制作方法及oled面板
CN109671748B (zh) * 2018-12-12 2020-06-16 武汉华星光电半导体显示技术有限公司 一种显示面板及其制作方法
CN112750965A (zh) * 2021-01-05 2021-05-04 武汉华星光电半导体显示技术有限公司 显示面板、显示面板的制作方法以及显示装置
CN113097286B (zh) * 2021-04-15 2024-05-24 京东方科技集团股份有限公司 一种阵列基板、双面显示装置以及制作方法
CN113571560A (zh) * 2021-07-15 2021-10-29 Tcl华星光电技术有限公司 双面显示面板及显示装置
CN114613752B (zh) * 2022-03-08 2024-07-19 厦门天马微电子有限公司 一种双面显示面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040195959A1 (en) * 2002-12-28 2004-10-07 Lg.Philips Lcd Co., Ltd. Dual panel-type organic electroluminescent device and method for fabricating the same
CN107863368A (zh) * 2017-09-18 2018-03-30 合肥惠科金扬科技有限公司 一种双面显示装置
CN107833904A (zh) * 2017-10-30 2018-03-23 深圳市华星光电半导体显示技术有限公司 双面oled显示面板及其制造方法
CN109997230A (zh) * 2019-01-29 2019-07-09 京东方科技集团股份有限公司 像素单元及其制造方法和双面oled显示装置
CN112086488A (zh) * 2020-09-07 2020-12-15 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法

Also Published As

Publication number Publication date
CN115117135A (zh) 2022-09-27
US20240215429A1 (en) 2024-06-27

Similar Documents

Publication Publication Date Title
US11424227B2 (en) Display panel, display module, and display device
US20210296394A1 (en) Array substrate and preparation method therefor, and display panel and display device
US11798958B2 (en) Driving backplane, manufacturing method thereof, and display apparatus
US20180158808A1 (en) Led display module, display device and method of manufacturing led display module
WO2019223567A1 (zh) 显示基板、显示装置以及显示基板的制作方法
WO2024000653A1 (zh) 显示面板
TWI235014B (en) Organic electroluminescent display device and method of fabricating the same
TW202001843A (zh) 顯示裝置
TW201923729A (zh) 微型led顯示面板的製備方法
JP2001092381A (ja) 有機ｅｌディスプレイおよびその製造方法
WO2021160089A1 (zh) 显示面板以及显示装置
TWI768594B (zh) 透明顯示裝置
US11107800B2 (en) Display device
US11257852B2 (en) Circuit backplane of display panel, method for manufacturing the circuit backplane, and display panel
WO2023097779A1 (zh) 显示面板和显示装置
WO2020103349A1 (zh) Oled显示装置及其制作方法
TW202127660A (zh) 有機發光二極體顯示裝置及製造其之方法
CN108877520A (zh) 一种显示装置及其制作方法
CN113782561B (zh) 一种高亮度高可靠性的Micro-LED显示装置
WO2023097727A1 (zh) 柔性双面显示屏及其制作方法
US20240047464A1 (en) Display panel and manufacture method thereof
CN110634923A (zh) 一种双面amoled显示面板及其制备方法
WO2024179052A1 (zh) 显示面板及其制作方法与拼接式显示屏
WO2024000661A1 (zh) 显示面板及其制作方法、电子终端
WO2024197852A1 (zh) 驱动背板、发光基板、显示面板和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 17759374

Country of ref document: US