WO2020087525A1 - 阵列基板及其制作方法、电子装置 - Google Patents

阵列基板及其制作方法、电子装置 Download PDF

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Publication number
WO2020087525A1
WO2020087525A1 PCT/CN2018/113792 CN2018113792W WO2020087525A1 WO 2020087525 A1 WO2020087525 A1 WO 2020087525A1 CN 2018113792 W CN2018113792 W CN 2018113792W WO 2020087525 A1 WO2020087525 A1 WO 2020087525A1
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Prior art keywords
electrode
connection electrode
light emitting
emitting device
base substrate
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PCT/CN2018/113792
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English (en)
French (fr)
Inventor
李海旭
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201880001916.5A priority Critical patent/CN110073495B/zh
Priority to US16/631,016 priority patent/US11239221B2/en
Priority to PCT/CN2018/113792 priority patent/WO2020087525A1/zh
Publication of WO2020087525A1 publication Critical patent/WO2020087525A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • At least one embodiment of the present disclosure relates to an array substrate, a manufacturing method thereof, and an electronic device.
  • the current required by the light emitting device (such as a Micro LED device) is relatively large, and it is necessary to meet the large current requirement of the light emitting device.
  • the display substrate has higher resolution requirements, it is necessary to ensure the high-density arrangement of the array elements in the driving circuit.
  • At least one embodiment of the present disclosure provides an array substrate including: a base substrate, a thin film transistor, a first connection electrode, and a first insulating layer.
  • the thin film transistor is disposed on the base substrate and includes a first electrode and a second electrode; the first connection electrode is disposed in a different layer from the first electrode and electrically connected to the first electrode; the first insulating layer covers at least a portion The first connection electrode; on a plane parallel to the base substrate, the area of the first connection electrode is larger than the area of the first electrode; the material of the first insulating layer is an organic insulating material.
  • the first connection electrode includes a first portion parallel to the base substrate and a second portion having an angle with the base substrate, the first The electrode includes a first portion parallel to the base substrate and a second portion having an angle with the base substrate; a first signal is transmitted to the light emitting device via the first electrode and the first connection electrode, On a plane parallel to the base substrate, the width of the first portion of the first connection electrode in the direction perpendicular to the first signal transmission direction is greater than that of the first portion of the first electrode The width in the signal transmission direction so that the area of the first connection electrode is larger than the area of the first electrode.
  • the width of the first portion of the first connection electrode in the direction perpendicular to the first signal transmission direction is greater than 10 ⁇ m .
  • the array substrate provided by at least one embodiment of the present disclosure further includes: a second insulating layer between the thin film transistor and the first connection electrode to isolate the thin film transistor and the first connection electrode from each other Open; the second insulating layer includes at least two vias, and the first connection electrode and the first electrode of the thin film transistor are electrically connected through the at least two vias.
  • the array substrate provided by at least one embodiment of the present disclosure further includes a light emitting device and a second connection electrode.
  • the light emitting device is provided on the base substrate, the first electrode is connected to the light emitting device via the first connection electrode; the second connection electrode is provided on the same layer as the first connection electrode, The first insulating layer also covers at least part of the second connection electrode, and on a plane parallel to the base substrate, the area of the second connection electrode is larger than the area of the first electrode; the light emitting device includes The first terminal, the light emitting layer, and the second terminal, the first connection electrode is electrically connected to the first terminal, and the second connection electrode is electrically connected to the second terminal.
  • a second signal is transmitted from the second connection electrode to the light-emitting device, and on a plane parallel to the base substrate, the second connection electrode
  • the width in the direction perpendicular to the second signal transmission direction is greater than 10 ⁇ m.
  • the material of the first connection electrode and the material of the second connection electrode are metal materials.
  • an array substrate provided by at least one embodiment of the present disclosure includes: a plurality of array units arranged in an array, wherein the light-emitting device is located in the array unit; and an opaque black matrix located in the plurality of array units Between adjacent array elements.
  • an array substrate provided in at least one embodiment of the present disclosure further includes a first terminal lead and a second terminal lead, wherein the first connection electrode is electrically connected to the first terminal through the first terminal lead, the The second connection electrode is electrically connected to the second terminal through the second terminal lead; there is a gap between the black matrix and the first terminal lead and the second terminal lead.
  • the array substrate provided in at least one embodiment of the present disclosure further includes a protrusion and a light emitting device, the protrusion is located on a side of the first insulating layer away from the base substrate, the light emitting device is disposed on the protrusion, so The first electrode is connected to the light emitting device via the first connection electrode.
  • the protrusion is integrally formed with the first insulating layer.
  • the light-emitting device is a small light-emitting diode or a micro light-emitting diode (Micro LED).
  • At least one embodiment of the present disclosure also provides an electronic device including any array substrate provided by an embodiment of the present disclosure.
  • At least one embodiment of the present disclosure also provides a method for manufacturing an array substrate.
  • the method includes: providing a base substrate; forming a thin film transistor on the base substrate, the thin film transistor including a first electrode and a second electrode; Forming a first connection electrode on the base substrate, the first connection electrode and the first electrode being provided in different layers and electrically connected to the first electrode; and forming a first insulating layer, the first insulating layer covering at least a portion The first signal line; on a plane parallel to the base substrate, the area of the first connection electrode is larger than the area of the first electrode; the material of the first insulating layer is an organic insulating material.
  • the method for manufacturing an array substrate further includes: forming a light emitting device on the base substrate, wherein the light emitting device is disposed on the base substrate, and the first electrode is The first connection electrode is connected to the light emitting device; and a second connection electrode is formed, the second connection electrode and the first connection electrode are formed by a patterning process using the same mask, and the first insulating layer further Covering at least part of the second connection electrode, and on a plane parallel to the base substrate, the area of the second connection electrode is larger than the area of the first electrode; the light emitting device includes a first terminal, light emitting Layer and a second terminal, the first connection electrode is electrically connected to the first terminal, and the second connection electrode is electrically connected to the second terminal.
  • the method for fabricating an array substrate further includes: forming a first insulating material layer covering the first connection electrode and the second connection electrode using an organic insulating material, wherein the coating method is used to form A first insulating material layer; and performing a patterning process on the first insulating material layer to form the first insulating layer.
  • a method for manufacturing an array substrate includes: forming a protrusion on a side of the first insulating layer away from the base substrate; and forming a light emitting device on the protrusion; the first The electrode is connected to the light emitting device via the first connection electrode.
  • the first insulating layer and the protrusions are formed through a patterning process using the same two-tone mask.
  • the first insulating layer is formed by a patterning process using a first mask; and the protrusion is formed by a patterning process using a second mask.
  • FIG. 1 is a schematic plan view of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2A is a schematic cross-sectional view taken along line I-I 'in FIG. 1;
  • FIG. 2B is a schematic diagram of an orthographic projection of the first connection electrode and the first electrode on the base substrate in the array substrate shown in FIG. 2A;
  • FIG. 2C is another schematic cross-sectional view taken along line I-I 'in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a driving circuit of an array unit in an array substrate provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of an electronic device provided by an embodiment of the present disclosure.
  • 5A-5J are schematic diagrams of a method for manufacturing an array substrate provided by an embodiment of the present disclosure.
  • 6A-6G are schematic diagrams of another method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • one patterning process refers to one exposure through one mask.
  • At least one embodiment of the present disclosure provides an array substrate including: a base substrate, a thin film transistor, a first connection electrode, and a first insulating layer.
  • the light emitting device is provided on the base substrate;
  • the thin film transistor is provided on the base substrate and includes a first electrode and a second electrode;
  • the first connection electrode is provided in a different layer from the first electrode and electrically connected to the first electrode; and the first insulating layer Covering at least part of the first connection electrode;
  • the area of the orthographic projection of the first connection electrode on the base substrate is larger than the area of the orthographic projection of the first electrode on the base substrate;
  • the material of the first insulating layer is an organic insulating material.
  • the base substrate further includes a light emitting device, the light emitting device is provided on the base substrate, and the first electrode is connected to the light emitting device via the first connection electrode.
  • the first insulating layer is located between the first connection electrode and the light emitting device.
  • FIG. 1 is a schematic plan view of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2A is a schematic cross-sectional view taken along line I-I 'in FIG. 1.
  • the array substrate 100 includes: a base substrate 1, a light emitting device 2, a thin film transistor 3, a first connection electrode 41, and a first insulating layer 51.
  • the light emitting device 2 is provided on the base substrate 1, and the thin film crystal 3 is provided on the base substrate 1 and includes a first electrode 31 and a second electrode 32.
  • the first electrode 31 is a source and the second electrode 32 is a drain, or the first electrode 31 is a source and the second electrode 32 is a drain.
  • the thin film transistor 3 further includes a gate 33 and a semiconductor layer 34, and a gate insulating layer 9 is provided between the gate 33 and the semiconductor layer 34 to insulate the gate 33 and the semiconductor layer 34 from each other.
  • An interlayer insulating layer 11 is also provided on the base substrate 1 to insulate the gate electrode 33 from the first electrode 31 and the second electrode 32.
  • the thin film transistor is a switching transistor. It should be noted that, in the present disclosure, the first connection electrode 41 and the first electrode 31 are provided in different layers, which means that the first connection electrode 41 and the first electrode 31 are provided in different layers, in a direction perpendicular to the base substrate Above, there are other layers between the first connection electrode 41 and the first electrode 31.
  • the first electrode 31 is connected to the light emitting device 2 via the first connection electrode 41, that is, the first electrode 31 is connected to the first connection electrode 41, and the first connection electrode 41 is connected to the light emitting device 2.
  • the first insulating layer 51 is located between the first connection electrode 41 and the light-emitting device 2 and covers a part of the first connection electrode 41 to insulate the first connection electrode 41 from other components that do not require electrical connection and prevent the influence of the first connection electrode 41 Transmission of electrical signals.
  • the first insulation layer can avoid etching the pattern of the first connection electrode when patterning the first terminal 61; further, the first insulation layer can realize the insulation of the first connection electrode and the black matrix.
  • the area of the orthographic projection of the first connection electrode 41 on the base substrate 1 is larger than the area of the orthographic projection of the first electrode 31 on the base substrate 1, as shown in FIG. 2B.
  • the size of the base substrate of the array substrate 10 is 5 inches (for example, the base substrate is rectangular and the diagonal of the rectangle is 5 inches), and the area of the first connection electrode 41 accounts for the area of the base substrate of the array substrate 90%.
  • the material of the first insulating layer 51 is an organic insulating material.
  • a first connection electrode 41 located at a different layer from the first electrode 31 is provided to provide an electrical signal to the light emitting device 2, for example, by rationally designing the first connection
  • the connection relationship between the electrode 41 and the first electrode 31 and making the area of the first connection electrode 41 larger than the area of the first electrode 31 can reduce the resistance of the signal from the thin film transistor 3 to the light emitting device 2 in the process.
  • the first insulating layer 51 is made of an organic material.
  • a coating method may be used to form the first insulating layer 51.
  • the first insulating layer 51 is made of an inorganic material, chemical vapor deposition (CVD) or the like is generally used, and the first connection electrode 41 with a larger area is a conductive material such as a metal material, and plasma gas is present during the CVD process.
  • the first connection electrode 41 made of metal material will cause abnormal discharge phenomenon in the CVD equipment, damage the equipment, and is not conducive to the quality of film formation. Therefore, the first insulating layer 51 is made of an organic material to avoid this problem, and at the same time, the organic material can achieve better planarization.
  • the material of the first insulating layer 51 is a resin material, such as polyimide, polyester, or the like.
  • Polyimide has the characteristics of high temperature resistance and bending resistance, and is suitable as a material for manufacturing a flexible substrate, which can adapt to the temperature rise of the substrate due to heat generated during the operation of the light-emitting device 2.
  • the material of the first insulating layer 51 is not limited to the types listed above.
  • the first connection electrode 41 includes a first portion 411 parallel to the base substrate 1 and a second portion 412 having an angle with the base substrate 1, and the first electrode 31 includes a parallel portion to the substrate The first portion 311 of the substrate 1 and the second portion 312 having an angle with the base substrate 1.
  • the angle between the first portion 411 of the first connection electrode and the base substrate 1 and the angle between the second portion 412 of the first connection electrode and the base substrate 1 are both greater than 0 ° and less than 180 °.
  • the first signal is transmitted to the light-emitting device 2 via the first electrode 31 and the first connection electrode 41.
  • the first portion 411 of the first connection electrode is perpendicular to the first signal transmission direction (FIG. 2C width in the direction of the arrow in) L 1 is greater than the first portion of the first electrode 311 perpendicular to the width of the first signal transmission direction L 2, so that the area of the first connection electrode 41 is larger than the area of the first electrode 31.
  • the width L 1 of the first portion 411 of the first connection electrode is larger than the width L 2 of the first portion 311 of the first electrode, which is beneficial to reduce the resistance of the first portion 411 of the first connection electrode and increase the current supplied to the light emitting device 2.
  • the width L 1 of the first portion 411 of the first connection electrode in the direction perpendicular to the first signal transmission direction is greater than 10 ⁇ m.
  • the size of the width L 1 can be reasonably designed according to the current required by the light emitting device 2, the area of the base substrate 1, and the arrangement density of the thin film transistor 3 and the light emitting device 2.
  • the array substrate 10 further includes a second insulating layer 52 to separate the thin film transistor 3 and the first connection electrode from each other
  • the layer where the first connection electrode 41 is located is insulated.
  • the second insulating layer 52 is located between the thin film transistor 3 and the first connection electrode 41.
  • the second insulating layer 51 includes a plurality of first vias 101 exposing the first electrode.
  • the first signal is transmitted to the light emitting device 2 via the first portion 311 of the first electrode, for example, a plurality of first vias 101 are arranged in the direction in which the first signal is transmitted in the first portion 311 of the first electrode. For example, as shown in FIG.
  • the number of first vias 101 is two, and the first connection electrode 41 and the first electrode 31 of the thin film transistor are electrically connected through the two first vias 101, for example, the two first The via holes 101 are arranged in the direction in which the first signal is transmitted in the first portion 311 of the first electrode. In this way, the first connection electrode 41 and the first electrode 31 of the thin film transistor form a parallel structure 200 electrically connected to the light emitting device 2.
  • the first connection electrode 41 in the parallel structure 200 (the B 1 B 2 segment of the first portion 411 of the first connection electrode and the second portion 412 of the first connection electrode located in the two vias) and the first in the parallel structure 200
  • An electrode 31 (A 1 A 2 section of the first part 311 of the first electrode) is connected in parallel to reduce the resistance of the electrical signal transmitted from point A 1 to point B 2 , thereby reducing the electrical signal transmitted from the thin film transistor 3 to the light emitting device The resistance of 2, thereby increasing the current that the electrical signal transmits from the thin film transistor 3 to the light emitting device 2.
  • the current required by the light emitting device 2 is relatively large, it can satisfy the large current demand of the light emitting device 2.
  • the resistance of the first connection electrode 41 is smaller than the resistance of the first electrode 31. Affected by the arrangement density of the thin film transistor 3, the degree of freedom for adjusting the resistance of the first electrode 31 is small, but since the first connection electrode 41 and the first electrode 31 are provided in different layers, the degree of freedom for adjusting the resistance of the first connection electrode 41 is adjusted It is large, so the resistance of the first connection electrode 41 can be conveniently reduced to reduce the resistance of the entire parallel structure 200.
  • the resistance of the first connection electrode 41 can be further reduced conveniently to reduce the resistance of the entire parallel structure 200 and increase the current supplied to the light emitting device 2 to achieve Satisfying the larger current demand of the light emitting device 2 can also ensure the high-density arrangement of the thin film transistor 3 and the light emitting device 2.
  • the resistance of the first connection electrode 41 is less than the resistance of the first electrode 31 including at least one of the following cases: on a plane parallel to the base substrate 1, the area of the first connection electrode 41 is larger than the area of the first electrode 31; In the direction perpendicular to the base substrate 1, the thickness of the first connection electrode 41 is greater than the thickness of the first electrode 31; and the resistivity of the material of the first connection electrode 41 is smaller than that of the material of the first electrode 31.
  • the parameters in the other cases remain unchanged; in any two of the above cases, the parameters in the other cases remain unchanged.
  • the array substrate 10 includes a plurality of array units 100 arranged in an array.
  • the resistance of the first connection electrode 41 and the resistance of the first electrode 31 are compared within a single array unit 100 ongoing.
  • the size comparison between the area of the first connection electrode 41 and the area of the first electrode 31 is also performed within a single array unit 100.
  • the array substrate 10 further includes a second connection electrode 42, the second connection electrode 42 is disposed in the same layer as the first connection electrode 41, and the first insulating layer 51 also covers a portion of the second connection electrode 42, the second The area of the front projection of the connection electrode 42 on the base substrate is larger than the area of the front projection of the first electrode 31 on the base substrate.
  • the light emitting device 2 includes a first terminal 21, a light emitting layer 22 and a second terminal 23, the first connection electrode 41 is electrically connected to the first terminal 21, and the second connection electrode 42 is electrically connected to the second terminal 23.
  • the first insulating layer 51 exposes a part of the first connection electrode 41 and a part of the second connection electrode 42
  • the light emitting device 2 includes a first terminal pin 241 and a second terminal pin 242.
  • the array substrate also includes a first terminal lead 61 and a second terminal lead 62.
  • the first terminal lead 61 is connected to the first connection electrode 41 exposed by the first insulating layer 51, and the first terminal lead 61 is connected to the first terminal pin 241, so that the first connection electrode 41 passes through the first terminal lead 61 and
  • the first terminal pin 241 is electrically connected to the first terminal 21.
  • the second terminal lead 62 is connected to the second connection electrode 42 exposed by the first insulating layer 51, and the second terminal lead 62 is connected to the second terminal pin 242 so that the second connection electrode 42 passes through the second terminal lead 62 and
  • the second terminal pin 242 is electrically connected to the second terminal 22. That is, the first connection electrode 41 is electrically connected to the first terminal 21 through the first terminal lead 61 and the first terminal pin 241, and the second connection electrode 42 is connected to the second terminal through the second terminal lead 62 and the second terminal pin 242 22 Electrical connection.
  • the first connection electrode 41 transmits the first signal from the second electrode of the thin film transistor 3 to the first terminal 21 of the light emitting device 2, and the second connection electrode 42 is connected to the low voltage signal line as the low voltage of the second signal
  • the signal is transmitted from the second connection electrode 42 to the light-emitting device 2, the light-emitting device 2 works under the action of the first signal and the second signal, and controls the operation of the light-emitting device 2 through the first signal and the second signal, such as whether or not to emit light and emit light Strength etc.
  • the first signal voltage is a high voltage signal
  • the second signal is a low voltage signal.
  • the second connection electrode 42 and the first connection electrode 41 are disposed in the same layer means that the second connection electrode 42 and the first connection electrode 41 are formed by patterning the same film layer, for example, after The same film layer is patterned once.
  • the width of the second connection electrode 42 in the direction perpendicular to the second signal transmission direction is greater than 10 ⁇ m.
  • the width of the second connection electrode 42 in the direction perpendicular to the second signal transmission direction is large, so that the resistance of the second connection electrode 42 can be reduced and the current supplied to the light emitting device 2 can be increased to further satisfy the light emitting device 2 Larger current demand.
  • the material of the first connection electrode 41 and the material of the second connection electrode 42 are metallic materials.
  • the metal material includes, for example, copper, copper alloy, molybdenum, molybdenum alloy, and the like.
  • the material of the first connection electrode 41 and the material of the second connection electrode 42 are not limited to the above types, and the embodiment of the present disclosure does not limit the material of the second connection electrode 42.
  • the array substrate 10 further includes protrusions 7 located on the side of the first insulating layer 51 away from the base substrate 1, and the light emitting device 2 is disposed on the protrusions 7.
  • the light-emitting device 2 is then disposed at a predetermined position of the array substrate 10, for example, the light-emitting device 2 is bonded to the predetermined position of the array substrate 10.
  • the protrusion 7 can assist in identifying the predetermined position, so that the position of the light emitting device 2 is more accurate.
  • the upper surface of the protrusion 7 away from the base substrate 1 is a flat surface to facilitate the arrangement of the light emitting device 2 on the upper surface.
  • the protrusion 7 is integrally formed with the first insulating layer 51 to simplify the manufacturing process of the array substrate 10.
  • the integral formation of the protrusion 7 and the first insulating layer 51 means that the protrusion 7 and the first insulating layer 51 are formed by patterning the same material layer once, and the integral formation of the protrusion 7 and the first insulating layer 51 means the protrusion 7
  • the material is the same as that of the first insulating layer 51 and the protrusion 7 and the first insulating layer 51 constitute an overall structure without a seam.
  • the protrusion 7 and the first insulating layer 51 may not be integrally formed, as shown in FIG. 2C.
  • the protrusion 7 and the first insulating layer 51 are not integrally formed, and the protrusion 7 is formed on the first insulating layer 51 after the first insulating layer 51 is formed.
  • the light emitting device 2 may be a light emitting diode.
  • the light emitting element 4 may be a small light emitting diode or a micro light emitting diode (Micro LED).
  • the first terminal is an anode and the second terminal is a cathode, or the first terminal is a cathode and the second terminal is an anode.
  • each light-emitting device 2 is driven independently, and the current required is larger than the current required by a normal light-emitting diode.
  • Small-sized light-emitting diodes or Micro LEDs are small in size and can be arranged at high density, which requires small-sized light-emitting diodes or Micro LED devices.
  • the arrangement density of the thin film transistors, electrodes, and signal lines that provide electrical signals is also relatively high, so that the array substrate provided by the embodiments of the present disclosure can also provide high current for small light-emitting diodes or Micro LED devices while ensuring High density arrangement. For example, when the array substrate 10 is applied to a display panel, such a high-density arrangement can achieve a high display resolution.
  • the internal circuit structure of the array unit 100 may be a commonly used 2T1C structure.
  • 3 is a schematic structural diagram of a driving circuit of an array unit in an array substrate provided by an embodiment of the present disclosure.
  • the driving part of the array unit 100 may include a switching transistor T1, a driving transistor T2, and a capacitor C.
  • the driving transistor T2 is the thin film transistor 3 in the above embodiment.
  • the second electrode of the switching transistor T1, the control electrode of the driving transistor T2 and the first electrode plate of the capacitor C are respectively connected, the second electrode of the capacitor C and the first electrode of the driving transistor T2 are respectively connected to the power supply terminal VDD, and the driving transistor T2
  • the second electrode is connected to the positive electrode of the light-emitting diode Micro-LED, and the negative electrode of the Micro-LED is connected to the power supply terminal VSS.
  • the array substrate 10 further includes a black matrix 8 that is opaque, and the black matrix 8 is located between the plurality of array units 100 to prevent crosstalk of light emitted by the light emitting elements 2 of the adjacent array units 100 .
  • the black matrix 8 does not contact the first terminal lead 61 and the second terminal lead 62. Since the general material of the black matrix 8 (such as an organic insulating material containing a light-shielding material) has a large resistance, it can prevent the black matrix 8 from contacting the first terminal lead 61 and the second terminal lead 62 to increase the power supply to the light emitting device 2 The resistance of the signal circuit.
  • the black matrix 8 is a conductive material
  • the black matrix 8 if the black matrix 8 is in contact with the first terminal lead 61 and the second terminal lead 62, it will be transmitted to the light emission via the first terminal lead 61 and the second terminal lead 62
  • the signal of the device causes interference.
  • the second insulating layer 51 includes more than two first vias 101.
  • the number of vias is four, but the number of first vias 101 is not limited to four.
  • the first connection electrode 41 and the first electrode 31 of the thin film transistor are electrically connected through the four vias 520.
  • the four first vias 101 are arranged along the direction in which the first signal is transmitted in the first portion 311 of the first electrode. In this way, the first connection electrode 41 and the first electrode 31 of the thin film transistor form a parallel structure 200 electrically connected to the light emitting device 2.
  • the first connection electrode 41 (the B 1 B 2 segment of the first portion 411 of the first connection electrode and the second portion 412 of the first connection electrode located in the four vias) in the parallel structure 200 and the first An electrode 31 (A 1 A 2 section of the first part 311 of the first electrode) is connected in parallel to reduce the resistance of the electrical signal transmitted from point A 1 to point B 2 , thereby reducing the electrical signal transmitted from the thin film transistor 3 to the light emitting device The resistance of 2, thereby increasing the current that the electrical signal transmits from the thin film transistor 3 to the light emitting device 2.
  • the current required by the light emitting device 2 is relatively large, it can satisfy the large current demand of the light emitting device 2.
  • the other features of the embodiment in FIG. 2C are the same as those of the embodiment shown in FIG. 2A. Please refer to the previous description.
  • An electronic device also provided in at least one embodiment of the present disclosure includes any array substrate provided in an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an electronic device provided by an embodiment of the present disclosure.
  • at least one embodiment of the present disclosure further provides an electronic device 13 that includes any array substrate 10 provided by an embodiment of the present disclosure.
  • the electronic device 13 can not only meet the large current demand of the light emitting device, but also ensure the high density arrangement of the thin film transistor and the light emitting device.
  • the electronic device 13 may be a display device (for example, Micro-LED display device, OLED display device / inorganic electroluminescence display device, etc.), for example, the electronic device 13 may be a mobile phone, tablet computer, television, display, notebook computer, digital Products or parts with display functions such as cameras and navigators.
  • the electronic device 13 may also be a lighting device (for example, a Micro-LED lighting device, an OLED lighting device, etc.), for example, a lighting fixture, a decorative colored light, or the like.
  • the embodiments of the present disclosure do not limit the types of electronic devices.
  • FIG. 4 is only a schematic diagram of an electronic device including any packaging structure provided by an embodiment of the present disclosure, and other structures of the electronic device not shown. Those skilled in the art may refer to conventional technologies. Not limited.
  • At least one embodiment of the present disclosure also provides an array substrate manufacturing method.
  • the method includes: providing a base substrate; forming a thin film transistor on the base substrate, the thin film transistor including a first electrode and a second electrode; and forming the base substrate
  • a first connection electrode, the first connection electrode and the first electrode are provided in different layers and electrically connected to the first electrode; and a first insulating layer is formed between the first connection electrode and the light emitting device and covers at least part of the first signal Line; on a plane parallel to the base substrate, the area of the first connection electrode is larger than the area of the first electrode; the material of the first insulating layer is an organic insulating material.
  • FIGS. 5A-5J are schematic diagrams of an array substrate manufacturing method provided by an embodiment of the present disclosure.
  • a base substrate 1 is provided, and a thin film transistor 3 is formed on the base substrate 1, the thin film transistor 3 includes a semiconductor layer 34, a first electrode 31 and a second electrode 32 electrically connected to the semiconductor layer 34, and a gate 33.
  • the first electrode 31 includes a first portion 311 parallel to the base substrate 1 and a second portion 312 having an angle with the base substrate 1.
  • the angle between the first portion 311 of the first electrode and the base substrate 1 and the angle between the second portion 312 of the first electrode and the base substrate 1 are both greater than 0 ° and less than 180 °.
  • the manufacturing method of the array substrate further includes forming a gate insulating layer 9 on the base substrate 1 to insulate the gate 33 and the semiconductor layer 34 from each other; forming an interlayer insulating layer 11 on the base substrate 1 so that the gate 33 and the first One electrode 31 and the second electrode 32 are insulated.
  • a second insulating layer 52 is formed, the second insulating layer 52 covers the thin film transistor 3, and the second insulating layer 52 includes a first via 101 that exposes the first electrode 31.
  • the material of the second insulating layer 52 may be an organic material or an inorganic material.
  • a coating method or a deposition method may be used to form the second insulating layer 52, and the specific method may be selected according to the material of the second insulating layer 52.
  • the manufacturing method of the array substrate further includes: forming a second connection electrode, the second connection electrode and the first connection electrode are formed by a patterning process using the same mask, and the first insulating layer further covers at least part of the second connection electrode, And on a plane parallel to the base substrate, the area of the second connection electrode is larger than the area of the first electrode.
  • the first connection electrode layer 4 is formed on the side of the second insulating layer 52 away from the base substrate 1 for subsequent formation of the first connection electrode 41 and the second connection electrode 42.
  • the first connection electrode layer 4 is a metal material.
  • the metal material includes, for example, copper, copper alloy, molybdenum, molybdenum alloy, and the like.
  • the first connection electrode layer 4 is formed by chemical vapor deposition (CVD) or magnetron sputtering method. A person skilled in the art can control the thickness of the first connection electrode layer 4 as needed.
  • the first connection electrode layer 4 is patterned once using the same mask to form the first connection electrode 41 and the second connection electrode 42.
  • the first connection electrode layer 4 is exposed once using the same mask, and the first connection electrode 41 and the second connection electrode 42 are formed through a development process or a development-etching process.
  • the first connection electrode 41 and the second connection electrode 42 are sequentially formed by patterning twice, it is advantageous in simplifying the manufacturing process of the array substrate and improving the production efficiency.
  • the first connection electrode 41 and the first electrode 31 are provided in different layers.
  • the area of the first connection electrode 41 is larger than the area of the first electrode 31.
  • the area of the second connection electrode 42 is larger than the area of the first electrode 31. Please refer to the previous description for the specific description and technical effect of the area relationship, and it will not be repeated here.
  • 5E is a cross-sectional view in another direction, which is perpendicular to the direction in which the cross-section of the array substrate shown in FIG. 5D is located.
  • a plurality of first via holes 101 exposing the first electrode 31 may be formed.
  • the first signal is transmitted to the light emitting device via the first portion 311 of the first electrode, for example, a plurality of first vias 101 are arranged in the direction in which the first signal is transmitted in the first portion 311 of the first electrode. For example, as shown in FIG.
  • the number of first vias 101 is two, and the first connection electrode 41 and the first electrode 31 of the thin film transistor are electrically connected through the two first vias 101, for example, the two first The via holes 101 are arranged in the direction in which the first signal is transmitted in the first portion 311 of the first electrode.
  • the number of the first vias 101 is not limited to two, for example, three or four. In this way, the first connection electrode 41 and the first electrode 31 of the thin film transistor form a parallel structure 200 electrically connected to the light emitting device.
  • the first connection electrode 41 (the B 1 B 2 segment of the first part 411 of the first connection electrode and the second part 412 of the first connection electrode located in the two first vias 101) in the parallel structure 200 and the parallel structure 200
  • the first electrode 31 (the A 1 A 2 section of the first part 311 of the first electrode) in parallel is connected to reduce the resistance of the electrical signal transmitted from the point A 1 to the point B 2 , thereby reducing the electrical signal transmitted from the thin film transistor 3
  • the resistance to the light emitting device thereby increasing the current that the electrical signal is transmitted from the thin film transistor 3 to the light emitting device.
  • the current required by the light emitting device is relatively large, it can meet the larger current demand of the light emitting device.
  • the manufacturing method further includes forming a first insulating material layer 5 covering the first connecting electrode 41 and the second connecting electrode 42 using an organic insulating material, forming the first insulating material layer 5 using a coating method, and subsequently using The first insulating material layer 5 forms a first insulating layer.
  • the first insulating layer 51 is made of an organic material, and during the manufacturing process, the first insulating material layer 5 may be formed by, for example, a coating method.
  • the first insulating layer 51 is made of an inorganic material, chemical vapor deposition (CVD) or the like is generally used, and the first connection electrode 41 with a larger area is a conductive material such as a metal material, and plasma gas is present during the CVD process.
  • the first connection electrode 41 made of metal material will cause abnormal discharge phenomenon in the CVD equipment, damage the equipment, and is not conducive to the quality of film formation. Therefore, the first insulating material layer 5 is made of an organic material and forming the first insulating material layer 5 by a coating method can avoid this problem.
  • the manufacturing method of the array substrate further includes: forming a light emitting device on the base substrate, the light emitting device is disposed on the base substrate, and the first electrode is connected to the light emitting device via the first connection electrode.
  • the manufacturing method of the array substrate further includes: forming a protrusion on a side of the first insulating layer away from the base substrate; and forming the light emitting device on the protrusion.
  • the first insulating material layer 5 is subjected to a patterning process using the same two-tone mask 12 to form the first insulating layer 51 and the protrusions 7.
  • the first insulating layer 51 and the protrusion 7 are formed through one exposure process.
  • the following description takes the case where the first insulating material layer 5 includes a photoresist material and the photoresist material is a positive photoresist.
  • the two-tone mask 11 includes a non-exposed area A, a fully exposed area B, and an incompletely exposed area C, respectively corresponding to the first insulating material layer 5 for forming protrusions, the first insulating layer 51, exposing the first connection electrode 41 and The area of the second via 102 of the second connection electrode 42.
  • the first insulating layer 51 and the protrusion 7 as shown in FIG. 5G are obtained.
  • the first insulating layer 51 covers part of the first connection electrode 41 and part of the second connection electrode 42 and includes a second via 102 that exposes the first connection electrode 41 and the second connection electrode 42.
  • the first insulating layer and the protrusions are formed through a single exposure process using the same two-tone mask to simplify the manufacturing process of the array substrate.
  • the thickness of the first insulating material layer 5 may be controlled so that its thickness meets the requirements for forming the protrusion 7.
  • the two-tone mask may be a gray-tone mask or a half-tone mask.
  • the manufacturing method further includes forming a photoresist on the first insulating material layer 5 and etching the first insulating material layer 5 after the development step.
  • the manufacturing method of the array substrate further includes forming a black matrix 8, the black matrix 8 is located between the plurality of array units 100, so as to prevent crosstalk of the light emitted by the adjacent units 2 in the column.
  • Contact with the second terminal lead 62 increases the resistance of the circuit that provides the electrical signal to the light-emitting device 2.
  • the black matrix 8 is, for example, an opaque organic material.
  • the black matrix 8 is formed by coating and patterning processes.
  • the first terminal lead 61 and the second terminal lead 62 are formed.
  • the first terminal lead 61 is connected to the first connection electrode 41 exposed by the first insulating layer 51
  • the second terminal lead 62 is connected to the second connection electrode 42 exposed by the first insulating layer 51.
  • the first terminal lead 61 and the second terminal lead 62 are located on the protrusion 7, and a part of the first terminal lead 61 and a part of the second terminal lead 62 are located on the upper surface of the protrusion 7 away from the base substrate 1.
  • the upper surface of the protrusion 7 is a flat surface to facilitate subsequent formation of a light emitting device on the upper surface.
  • the light emitting device 2 may be formed, and then the light emitting device 2 is disposed at a predetermined position of the array substrate 10, for example, the light emitting device 2 is bonded to the predetermined position of the array substrate 10.
  • the light emitting device 2 is provided on the protrusion 7, for example, the light emitting device 2 is provided on the upper surface of the protrusion 7 so that the first insulating layer 51 is located between the first connection electrode 41 and the light emitting device 2.
  • the light emitting device 2 includes a first terminal pin 241 and a second terminal pin 242.
  • the first terminal lead 61 is connected to the first terminal pin 241 so that the first connection electrode 41 is electrically connected to the first terminal 21 via the first terminal lead 61 and the first terminal pin 241 in sequence, so that the first electrode 31 is connected via the first
  • the connection electrode 41 is connected to the light emitting device 2.
  • the second terminal lead 62 is connected to the second terminal pin 242 so that the second connection electrode 42 is electrically connected to the second terminal 22 via the second terminal lead 62 and the second terminal pin 242 in order.
  • a predetermined position needs to be identified, and the protrusion 7 can assist in identifying the predetermined position, and identifying the position of the protrusion 7 can more accurately identify the predetermined position, making the position of the light emitting device 2 more accurate .
  • FIGS. 6A-6G are schematic diagrams of another method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • the difference between the manufacturing method and the embodiment shown in FIGS. 5A-5I is that the first mask is used to form The first insulating layer; and using the second mask to form the protrusion through a patterning process.
  • a first insulating material layer 5 is formed for subsequent formation of the first insulating layer 51, for example, the thickness of the first insulating material layer 5 is small as shown in FIG. 5F
  • the thickness of the first insulating material layer 5 is the same as that in FIG. 5F, please refer to the previous description.
  • the first insulating layer 51 is formed by a patterning process using a first mask (not shown).
  • the first insulating material layer 5 is sequentially exposed, developed, or exposed, developed, and etched to form a first insulating layer 51, and the first insulating layer 51 includes exposed first and second connection electrodes 41 and 42 Second via 102.
  • the mask is a monotone mask.
  • a protruding material layer 71 covering the first insulating layer 51 is formed, and the protruding material layer 71 is used to form protrusions subsequently.
  • the material of the protrusion material layer 71 is an organic material.
  • the material of the protruding material layer 71 may be different from the material of the first insulating layer 51, or may be the same as the material of the first insulating layer 51.
  • the protrusion 7 is formed by a patterning process using a second mask (not shown).
  • a patterning process for example, a photolithography process, such as a photolithography process using a single-tone mask
  • the structural features of the protrusion 7 are the same as in the previous embodiment.
  • the protrusion material removed can be controlled
  • the thickness of the layer 71 to prevent the first insulating layer 51 from being over-etched For example, it can be achieved by controlling the etching time and etching rate, etc., and those skilled in the art can implement it according to common techniques in the art.
  • FIGS. 6E-6G are performed to obtain an array substrate.
  • the steps are the same as those in Fig. 5H-5G, please refer to the description of Fig. 5H-5G.

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Abstract

一种阵列基板及其制作方法以及电子装置。该阵列基板(10)包括：衬底基板(1)、薄膜晶体管(3)、第一连接电极(41)和第一绝缘层(51)。发光器件(2)和薄膜晶体管(3)设置于衬底基板(1)上；薄膜晶体管(3)包括第一电极(31)和第二电极(32)；第一连接电极(41)与第一电极(31)异层设置且与所述第一电极(31)电连接；第一绝缘层(51)覆盖至少部分第一连接电极(41)；所述第一连接电极(41)在所述衬底基板(1)的正投影的面积大于所述第一电极(31)在所述衬底基板(1)的正投影的面积；第一绝缘层(51)的材料为有机绝缘材料。该阵列基板在满足发光器件的较大的电流需求，以及保证薄膜晶体管和发光器件的高密度排布的同时，能够防止损伤阵列基板制备过程中的设备。

Description

阵列基板及其制作方法、电子装置 技术领域
本公开至少一实施例涉及一种阵列基板及其制作方法以及电子装置。
背景技术
在显示基板或照明基板中，有的情况下，发光器件(例如Micro LED器件)需要的电流比较大，需要满足发光器件较大的电流要求。同时，当显示基板有较高的分辨率要求时，还要保证驱动电路中各个阵列元件的高密度排布。
发明内容
本公开至少一实施例提供一种阵列基板，该阵列基板包括：衬底基板、薄膜晶体管、第一连接电极和第一绝缘层。薄膜晶体管设置于所述衬底基板上并包括第一电极和第二电极；第一连接电极与所述第一电极异层设置且与所述第一电极电连接；第一绝缘层覆盖至少部分所述第一连接电极；在平行于所述衬底基板的平面上，所述第一连接电极的面积大于所述第一电极的面积；所述第一绝缘层的材料为有机绝缘材料。
例如，本公开至少一实施例提供的阵列基板中，所述第一连接电极包括平行于所述衬底基板的第一部分和与所述衬底基板具有夹角的第二部分，所述第一电极包括平行于所述衬底基板的第一部分和与所述衬底基板具有夹角的第二部分；第一信号经所述第一电极和所述第一连接电极传递到所述发光器件，在平行于所述衬底基板的平面上，所述第一连接电极的第一部分在垂直于所述第一信号传输方向上的宽度大于所述第一电极的第一部分在垂直于所述第一信号传输方向上的宽度，以使得所述第一连接电极的面积大于所述第一电极的面积。
例如，本公开至少一实施例提供的阵列基板中，在平行于所述衬底基板的平面上，所述第一连接电极的第一部分在垂直于所述第一信号传输方向上的宽度大于10μm。
例如，本公开至少一实施例提供的阵列基板还包括：第二绝缘层，位于所述薄膜晶体管与所述第一连接电极之间，以将所述薄膜晶体管和所述第一 连接电极彼此隔开；所述第二绝缘层包括至少两个过孔，所述第一连接电极与所述薄膜晶体管的第一电极通过所述至少两个过孔电连接。
例如，本公开至少一实施例提供的阵列基板还包括发光器件和第二连接电极。所述发光器件设置于所述衬底基板上，所述第一电极经由所述第一连接电极连接到所述发光器件；所述第二连接电极与所述第一连接电极同层设置，所述第一绝缘层还覆盖至少部分所述第二连接电极，在平行于所述衬底基板的平面上，所述第二连接电极的面积大于所述第一电极的面积；所述发光器件包括第一端子、发光层和第二端子，所述第一连接电极与所述第一端子电连接，所述第二连接电极与所述第二端子电连接。
例如，本公开至少一实施例提供的阵列基板中，第二信号从所述第二连接电极传输到所述发光器件，在平行于所述衬底基板的平面上，所述第二连接电极的在垂直于所述第二信号传输方向上的宽度大于10μm。
例如，本公开至少一实施例提供的阵列基板中，所述第一连接电极的材料和所述第二连接电极的材料为金属材料。
例如，本公开至少一实施例提供的阵列基板包括：呈阵列排布的多个阵列单元，其中，所述发光器件位于所述阵列单元中；以及不透光的黑矩阵，位于多个阵列单元中相邻的阵列单元之间。
例如，本公开至少一实施例提供的阵列基板还包括第一端子引线和第二端子引线，其中，所述第一连接电极通过所述第一端子引线与所述第一端子电连接，所述第二连接电极通过所述第二端子引线与所述第二端子电连接；所述黑矩阵与所述第一端子引线和第二端子引线之间均存在空隙。
例如，本公开至少一实施例提供的阵列基板还包括突起与发光器件，突起位于所述第一绝缘层的远离所述衬底基板的一侧，所述发光器件设置于所述突起上，所述第一电极经由所述第一连接电极连接到所述发光器件。
例如，本公开至少一实施例提供的阵列基板中，所述突起与所述第一绝缘层一体成型。
例如，本公开至少一实施例提供的阵列基板中，所述发光器件为小型发光二极管或者微型发光二极管(Micro LED)。
本公开至少一实施例还提供一种电子装置，该电子装置包括本公开实施例提供的任意一种阵列基板。
本公开至少一实施例还提供一种阵列基板制作方法，该方法包括：提供 衬底基板；在所述衬底基板上形成薄膜晶体管，所述薄膜晶体管包括第一电极和第二电极；在所述衬底基板上形成第一连接电极，所述第一连接电极和所述第一电极异层设置且与所述第一电极电连接；以及形成第一绝缘层，第一绝缘层覆盖至少部分所述第一信号线；在平行于所述衬底基板的平面上，所述第一连接电极的面积大于所述第一电极的面积；所述第一绝缘层的材料为有机绝缘材料。
例如，本公开至少一实施例提供的阵列基板制作方法还包括：在所述衬底基板上形成发光器件，其中，所述发光器件设置于所述衬底基板上，所述第一电极经由所述第一连接电极连接到所述发光器件；以及形成第二连接电极，所述第二连接电极与所述第一连接电极是利用同一掩模通过一次构图工艺形成，所述第一绝缘层还覆盖至少部分所述第二连接电极，并且在平行于所述衬底基板的平面上，所述第二连接电极的面积大于所述第一电极的面积；所述发光器件包括第一端子、发光层和第二端子，所述第一连接电极与所述第一端子电连接，所述第二连接电极与所述第二端子电连接。
例如，本公开至少一实施例提供的阵列基板制作方法还包括：采用有机绝缘材料形成覆盖所述第一连接电极和所述第二连接电极的第一绝缘材料层，其中，采用涂布方法形成第一绝缘材料层；以及对所述第一绝缘材料层执行构图工艺以形成所述第一绝缘层。
例如，本公开至少一实施例提供的阵列基板制作方法包括：在所述第一绝缘层的远离所述衬底基板的一侧形成突起；以及在所述突起上形成发光器件；所述第一电极经由所述第一连接电极连接到所述发光器件。
例如，本公开至少一实施例提供的阵列基板制作方法中，利用同一双色调掩模经过一次构图工艺形成所述第一绝缘层和所述突起。
例如，本公开至少一实施例提供的阵列基板制作方法中，采用第一掩模通过一次构图工艺形成所述第一绝缘层；以及采用第二掩模通过一次构图工艺形成所述突起。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本公开一实施例提供的一种阵列基板的平面示意图；
图2A为沿图1中的I-I’线的一种截面示意图；
图2B为图2A所示的阵列基板中的第一连接电极和第一电极在衬底基板的正投影的示意图；
图2C为沿图1中的I-I’线的另一种截面示意图；
图3为本公开一实施例所提供的阵列基板中的阵列单元的驱动电路的结构示意图；
图4为本公开一实施例提供的电子装置示意图；
图5A-5J为本公开一实施例提供的一种阵列基板制作方法示意图；
图6A-6G为本公开一实施例提供的另一种阵列基板制作方法示意图。
附图标记
1-衬底基板；2-发光器件；21-第一端子；22-发光层；23-第二端子；241-第一端子引脚；242-第二端子引脚；3-薄膜晶体管；31-第一电极；311-第一电极的第一部分；312-第一电极的第二部分；32-第二电极；33-栅极；34-半导体层41；-第一连接电极；411-第一连接电极的第一部分；412-第一连接电极的第二部分；42-第二连接电极；51-第一绝缘层；52-第一绝缘层；61-第一端子引线；62-第二端子引线；7-突起；8-黑矩阵；9-栅绝缘层；10-阵列基板；11-层间绝缘层；12-双色调掩模；13-电子装置；100-阵列单元；101-第一过孔；102-第二过孔；200-并联结构。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等 类似的词语意指出现在该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开所使用的附图并不是严格按实际比例绘制，各个结构的具体尺寸和数量可根据实际需要进行确定。本公开的附图中只示出了与实现相应的技术效果直接相关的结构，其他结构可参考常规技术。本公开中所描述的附图仅是结构示意图。
例如，在本申请中，一次构图工艺是指利用一个掩模经过一次曝光。
本公开至少一实施例提供一种阵列基板，该阵列基板包括：衬底基板、薄膜晶体管、第一连接电极和第一绝缘层。发光器件设置于衬底基板上；薄膜晶体管设置于衬底基板上并包括第一电极和第二电极；第一连接电极与第一电极异层设置且与第一电极电连接；第一绝缘层覆盖至少部分第一连接电极；第一连接电极在衬底基板的正投影的面积大于第一电极在衬底基板上的正投影的面积；第一绝缘层的材料为有机绝缘材料。例如，衬底基板还包括发光器件，发光器件设置于衬底基板上，第一电极经由第一连接电极连接到发光器件。例如，第一绝缘层位于第一连接电极与发光器件之间。
示范性地，图1为本公开一实施例提供的一种阵列基板的平面示意图，图2A为沿图1中的I-I’线的一种截面示意图。如图1、图2A所示，阵列基板100包括：衬底基板1、发光器件2、薄膜晶体管3、第一连接电极41和第一绝缘层51。发光器件2设置于衬底基板1上，薄膜晶体3设置于衬底基板1上并包括第一电极31和第二电极32。例如，第一电极31为源极，第二电极32为漏极，或者，第一电极31为源极，第二电极32为漏极。例如，薄膜晶体管3还包括栅极33和半导体层34，在栅极33和半导体层34之间设置有栅绝缘层9，以使栅极33和半导体层34彼此绝缘。在衬底基板1上还设置有层间绝缘层11，以使栅极33与第一电极31和第二电极32绝缘。例如，薄膜晶体管为开关晶体管。需要说明的是，在本公开中，第一连接电极41与第一电极31异层设置是指第一连接电极41与第一电极31分别设置于不同的层，在垂直于衬底基板的方向上，第一连接电极41与第一电极31之间存在其他的层。第一电极31经由第一连接电极41连接到发光器件2，即第一电极31与第一连接电极41连接，第一连接电极41与发光器件2连 接。第一绝缘层51位于第一连接电极41与发光器件2之间且覆盖部分第一连接电极41，以使第一连接电极41与其他不需要电连接的部件绝缘，防止影响经第一连接电极41传输的电信号。同时第一绝缘层可避免对第一端子61图案化时，刻蚀第一连接电极的图案；进一步，第一绝缘层可实现第一连接电极和黑矩阵的绝缘。第一连接电极41在衬底基板1的正投影的面积大于第一电极31在衬底基板1的正投影的面积，如图2B所示。例如，阵列基板10的衬底基板的尺寸为5英寸(例如，衬底基板为矩形，矩形的对角线为5英寸)，第一连接电极41的面积占阵列基板的衬底基板的面积的90％。第一绝缘层51的材料为有机绝缘材料。如此，与将不设置第一连接电极41而将第一电极31直接连接到发光器件2的情况相比，例如当发光器件2需要的电流比较大且需要薄膜晶体管3分布较密集时(例如当在显示面板中需要实现高分辨率时)，在本公开实施例中，设置与第一电极31位于不同层的第一连接电极41来给发光器件2提供电信号，例如通过合理设计第一连接电极41和第一电极31之间的连接关系且使得第一连接电极41的面积大于第一电极31的面积，可以减小信号从薄膜晶体管3传导至发光器件2过程中的电阻。这种情况下，第一绝缘层51采用有机材料制作，在制作过程中，例如可采用涂布方法形成第一绝缘层51。如果第一绝缘层51采用无机材料制作，通常使用化学气相沉积(CVD)等方法，而面积较大的第一连接电极41为导电材料例如金属材料，CVD过程中存在等离子气体，面积较大的金属材料制成的第一连接电极41会造成CVD设备中发生异常放电现象，损伤设备，也不利于成膜质量。因此，第一绝缘层51采用有机材料制作可避免这一问题，同时有机材料能够实现较好的平坦化。
例如，第一绝缘层51的材料为树脂材料，例如聚酰亚胺、聚酯类等。聚酰亚胺具有耐高温性、抗弯折性能均比较优异的特点，适合作为制作柔性基板的材料，能够适应由于发光器件2工作过程中发热导致的基板温度升高。当然，第一绝缘层51的材料不仅限于是上述列举种类。
例如，如图2A和2C所示，第一连接电极41包括平行于衬底基板1的第一部分411和与衬底基板1具有夹角的第二部分412，第一电极31包括平行于衬底基板1的第一部分311和与衬底基板1具有夹角的第二部分312。第一连接电极的第一部分411与衬底基板1的夹角和第一连接电极的第二部分412与衬底基板1的夹角均大于0°且小于180°。第一信号经第一电极31 和第一连接电极41传递到发光器件2，在平行于衬底基板1的平面上，第一连接电极的第一部分411在垂直于第一信号传输方向(图2C中的箭头方向)上的宽度L 1大于第一电极的第一部分311在垂直于第一信号传输方向上的宽度L 2，以使得第一连接电极41的面积大于第一电极31的面积。第一连接电极的第一部分411的宽度L 1大于第一电极的第一部分311的宽度L 2，有利于减小第一连接电极第一部分411的电阻，增大提供给发光器件2的电流。
例如，在平行于衬底基板1的平面上，第一连接电极的第一部分411在垂直于第一信号传输方向上的宽度L 1大于10μm。可以根据发光器件2所需要的电流大小、衬底基板1的面积以及薄膜晶体管3和发光器件2的排布密度，合理设计宽度L 1的大小。
例如，阵列基板10还包括第二绝缘层52，以将薄膜晶体管3和第一连接电极彼此隔开，例如使薄膜晶体管3所在的层中的不需要与第一连接电极41电连接的部分与第一连接电极41所在的层绝缘。例如，第二绝缘层52位于薄膜晶体管3与第一连接电极41之间。例如，第二绝缘层51包括暴露第一电极的多个第一过孔101。第一信号经由第一电极的第一部分311传输给发光器件2，例如多个第一过孔101沿第一信号在第一电极的第一部分311中传输的方向排列。例如，如图2A所示，第一过孔101的数量为两个，第一连接电极41与薄膜晶体管的第一电极31通过该两个第一过孔101电连接，例如该两个第一过孔101沿第一信号在第一电极的第一部分311中传输的方向排列。如此，第一连接电极41和薄膜晶体管的第一电极31形成与发光器件2电连接的并联结构200。并联结构200中的第一连接电极41(第一连接电极的第一部分411的B 1B 2段和位于两个过孔中的第一连接电极的第二部分412)与并联结构200中的第一电极31(第一电极的第一部分311的A 1A 2段)并联，以减小电信号从点A 1传输至点B 2的电阻，从而减小电信号从薄膜晶体管3传输至发光器件2的电阻，从而增大电信号从薄膜晶体管3传输至发光器件2的电流。当发光器件2需要的电流比较大时，能够满足发光器件2的较大的电流需求。
例如，第一连接电极41的电阻小于第一电极31的电阻。受薄膜晶体管3排布密度的影响，调整第一电极31的电阻的自由度小，但是由于第一连接电极41与第一电极31异层设置，因此调整第一连接电极41的电阻的自由度大，因此可以方便地减小第一连接电极41的电阻，以降低整个并联结构 200的电阻。如此，在本公开实施例提供的阵列基板10中，能够方便地进一步减小第一连接电极41的电阻，以降低整个并联结构200的电阻，增大提供给发光器件2的电流，达到不仅能够满足发光器件2的较大的电流需求，还可以保证薄膜晶体管3和发光器件2的高密度排布。
第一连接电极41的电阻小于第一电极31的电阻包括以下情形中的至少之一：在平行于衬底基板1的平面上，第一连接电极41的面积大于第一电极31的面积；在垂直于衬底基板1的方向上，第一连接电极41的厚度大于第一电极31的厚度；以及第一连接电极41的材料的电阻率小于第一电极31的材料的电阻率。在上述任意一种情形下，其他情形中的参数保持不变；在上述几种情形中的任意两种情形下，其他情形中的参数保持不变。
需要说明的是，如图1所示，阵列基板10包括呈阵列排布的多个阵列单元100，第一连接电极41的电阻和第一电极31的电阻的大小比较是在单个阵列单元100内进行的。第一连接电极41的面积和第一电极31的面积的大小比较也是在单个阵列单元100内进行的。
例如，如图2A所示，阵列基板10还包括第二连接电极42，第二连接电极42与第一连接电极41同层设置，第一绝缘层51还覆盖部分第二连接电极42，第二连接电极42在衬底基板的正投影的面积大于第一电极31在衬底基板的正投影的面积。发光器件2包括第一端子21、发光层22和第二端子23，第一连接电极41与第一端子21电连接，第二连接电极42与第二端子23电连接。例如，第一绝缘层51暴露第一连接电极41的一部分和第二连接电极42的一部分，发光器件2包括第一端子引脚241和第二端子引脚242。阵列基板还包括第一端子引线61和第二端子引线62。第一端子引线61与被第一绝缘层51暴露的第一连接电极41连接，并且第一端子引线61与第一端子引脚241连接，从而第一连接电极41依次经由第一端子引线61和第一端子引脚241与第一端子21电连接。第二端子引线62与被第一绝缘层51暴露的第二连接电极42连接，并且第二端子引线62与第二端子引脚242连接，从而第二连接电极42依次经由第二端子引线62和第二端子引脚242与第二端子22电连接。即，第一连接电极41通过第一端子引线61和第一端子引脚241与第一端子21电连接，第二连接电极42通过第二端子引线62和第二端子引脚242与第二端子22电连接。例如，第一连接电极41将来自薄膜晶体管3的第二电极的第一信号传输给发光器件2的第一端子21，第 二连接电极42连接到低电压信号线，作为第二信号的低电压信号从第二连接电极42传输到发光器件2，发光器件2在第一信号和第二信号的作用下工作，通过第一信号和第二信号控制发光器件2的工作情况，例如是否发光以及发光强度等。例如，第一信号电压为高电压信号，第二信号为低电压信号。
需要说明的是，在本公开中，第二连接电极42与第一连接电极41同层设置是指第二连接电极42与第一连接电极41经过对同一个膜层进行构图形成，例如经过对同一个膜层进行一次构图形成。
例如，在平行于衬底基板1的平面上，第二连接电极42的在垂直于第二信号传输方向上的宽度大于10μm。如此，第二连接电极42在垂直于第二信号传输方向上的宽度较大，从而能够减小第二连接电极42的电阻，增大提供给发光器件2的电流，以进一步满足发光器件2的较大的电流需求。
例如，第一连接电极41的材料和第二连接电极42的材料为金属材料。该金属材料例如包括铜，铜合金，钼，钼合金等。当然，第一连接电极41的材料和第二连接电极42的材料不限于是上述种类，本公开实施例对第二连接电极42的材料不作限定。
例如，阵列基板10还包括突起7，突起7位于第一绝缘层51的远离衬底基板1的一侧，发光器件2设置于突起7上。例如，可以形成发光器件2之后，然后将发光器件2设置于在阵列基板10的预定位置处，例如将发光器件2粘结于阵列基板10的预定位置处。在放置发光器件2的过程中，突起7可以辅助识别该预定位置，使得发光器件2的位置更加精准。发光器件2的排布密度越高，对发光器件2的位置精度要求越高，以防止相邻发光器件2之间的干扰的问题以及局部发光不均的问题等。例如，突起7的远离衬底基板1的上表面为平坦表面，以有利于在上表面上设置发光器件2。
例如，在一个实施例中，如图2A所示，突起7与第一绝缘层51一体成型，以简化阵列基板10的制作工艺。本公开中突起7与第一绝缘层51一体成型是指突起7与第一绝缘层51是对同一材料层进行一次构图而形成的，突起7与第一绝缘层51一体成型是指突起7的材料与第一绝缘层51的材料相同且突起7与第一绝缘层51构成没有接缝的整体结构。
例如，在另一个实施例中，突起7与第一绝缘层51也可以不是一体成型的，如图2C所示。突起7与第一绝缘层51不是一体成型的，突起7在形成第一绝缘层51之后形成于第一绝缘层51上。
例如，在本公开实施例中，发光器件2可以为发光二极管。例如，发光元件4可为小型发光二极管或者微型发光二极管(Micro LED)。此时，例如，第一端子为阳极，第二端子为阴极，或者，第一端子为阴极，第二端子为阳极。例如，每个发光器件2为独立驱动，需要的电流比通常的发光二极管所需的电流大，小型发光二极管或者Micro LED尺寸小，可以高密度排布，从而需要为小型发光二极管或者Micro LED器件提供电信号的薄膜晶体管、电极和信号线等的排布密度也比较高，从而本公开实施例提供的阵列基板还能够在实现为小型发光二极管或者Micro LED器件提供较高的电流的同时，保证高密度排布。例如，当阵列基板10应用于显示面板中时，这种高密度排布能够实现高显示分辨率。
例如，当发光元件4为发光二极管时，阵列单元100的内部电路结构可为常用的2T1C结构。图3为本公开一实施例所提供的阵列基板中的阵列单元的驱动电路的结构示意图。如图3所示，阵列单元100的驱动部件可包括开关晶体管T1、驱动晶体管T2和电容C。其中，例如，驱动晶体管T2为上述实施例中的薄膜晶体管3。开关晶体管T1的第二电极、驱动晶体管T2的控制极和电容C的第一极板分别相连，电容C的第二极板和驱动晶体管T2的第一电极分别与电源端VDD相连，驱动晶体管T2的第二电极与发光二极管Micro-LED的正极相连，Micro-LED的负极与电源端VSS相连。
如图2A和图2B所示，阵列基板10还包括不透光的黑矩阵8，黑矩阵8位于多个阵列单元100之间，以防止相邻阵列单元100的发光元件2发出的光发生串扰。黑矩阵8与第一端子引线61和第二端子引线62均存在空隙，以使黑矩阵8不与第一端子引线61和第二端子引线62接触。由于黑矩阵8通常的材料(例如含有遮光材料的有机绝缘材料)的电阻较大，如此可防止黑矩阵8与第一端子引线61和第二端子引线62接触而增大为发光器件2提供电信号的电路的电阻。或者，在黑矩阵8的材料为导电材料的情况下，如果黑矩阵8与第一端子引线61和第二端子引线62接触，会对经由第一端子引线61和第二端子引线62传递到发光器件的信号造成干扰。
如图2C所示，第二绝缘层51包括多于两个的第一过孔101，例如过孔的数量为四个，当然第一过孔101的数量不限于上是四个。第一连接电极41与薄膜晶体管的第一电极31通过该四个过孔520电连接。例如该四个第一过孔101沿第一信号在第一电极的第一部分311中传输的方向排列。如此， 第一连接电极41和薄膜晶体管的第一电极31形成与发光器件2电连接的并联结构200。并联结构200中的第一连接电极41(第一连接电极的第一部分411的B 1B 2段和位于四个过孔中的第一连接电极的第二部分412)与并联结构200中的第一电极31(第一电极的第一部分311的A 1A 2段)并联，以减小电信号从点A 1传输至点B 2的电阻，从而减小电信号从薄膜晶体管3传输至发光器件2的电阻，从而增大电信号从薄膜晶体管3传输至发光器件2的电流。当发光器件2需要的电流比较大时，能够满足发光器件2的较大的电流需求。图2C中的实施例的其他特征均与图2A所示的实施例的特征相同，请参考之前的描述。
本公开至少一实施例还提供的一种电子装置，该电子装置包括本公开实施例提供的任意一种阵列基板。
图4为本公开一实施例提供的一种电子装置示意图。例如，如图4所示，本公开至少一实施例还提供的一种电子装置13，该电子装置13包括本公开实施例提供的任意一种阵列基板10。该电子装置13不仅能够满足发光器件的较大的电流需求，还可以保证薄膜晶体管和发光器件的高密度排布。
例如，电子装置13可以为显示装置(例如Micro-LED显示装置、OLED显示装置/无机电致发光显示装置等)，例如电子装置13可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相机、导航仪等具有显示功能的产品或部件。例如，电子装置13也可以是照明装置(例如Micro-LED照明装置、OLED照明装置等)，例如，照明灯具、装饰性彩灯等。当然，本公开实施例对电子装置的种类没有限定。
需要说明的是，图4只是包括本公开实施例提供的任意一种封装结构的电子装置的示意图，电子装置的未示出的其他结构，本领域技术人员可参考常规技术，本实施例对此不作限定。
本公开至少一实施例还提供一种阵列基板制作方法，该方法包括：提供衬底基板；在衬底基板上形成薄膜晶体管，薄膜晶体管包括第一电极和第二电极；在衬底基板上形成第一连接电极，第一连接电极和第一电极异层设置且与所述第一电极电连接；以及形成第一绝缘层，位于第一连接电极与发光器件之间且覆盖至少部分第一信号线；在平行于衬底基板的平面上，第一连接电极的面积大于第一电极的面积；第一绝缘层的材料为有机绝缘材料。
示范性地，图5A-5J为本公开一实施例提供的一种阵列基板制作方法示 意图。如图5A所示，提供衬底基板1，在衬底基板1上形成薄膜晶体管3，薄膜晶体管3包括半导体层34、与半导体层34电连接的第一电极31和第二电极32、栅极33。第一电极31包括平行于衬底基板1的第一部分311和与衬底基板1具有夹角的第二部分312。第一电极的第一部分311与衬底基板1的夹角和第一电极的第二部分312与衬底基板1的夹角均大于0°且小于180°。阵列基板制作方法还包括在衬底基板1上形成栅绝缘层9，以使栅极33和半导体层34彼此绝缘；在衬底基板1上形成层间绝缘层11，以使栅极33与第一电极31和第二电极32绝缘。
如图5B所示，形成第二绝缘层52，第二绝缘层52覆盖薄膜晶体管3，且第二绝缘层52包括暴露第一电极31的第一过孔101。例如，第二绝缘层52的材料可以为有机材料或无机材料。例如可以采用涂覆法或沉积法形成第二绝缘层52，具体方法可根据第二绝缘层52的材料进行选择。
例如，阵列基板制作方法还包括：形成第二连接电极，第二连接电极与第一连接电极是利用同一掩模通过一次构图工艺形成，第一绝缘层还覆盖至少部分所述第二连接电极，并且在平行于衬底基板的平面上，第二连接电极的面积大于第一电极的面积。
如图5C所示，在第二绝缘层52的远离衬底基板1的一侧形成第一连接电极层4，以用于后续形成第一连接电极41和第二连接电极42。例如第一连接电极层4为金属材料。该金属材料例如包括铜，铜合金，钼，钼合金等。例如，采用化学气沉积(CVD)或磁控溅射方法形成第一连接电极层4。本领域技术人员可根据需要控制第一连接电极层4的厚度。
如图5D所示，利用同一掩模对第一连接电极层4进行一次构图工艺而形成第一连接电极41和第二连接电极42。例如，用同一掩模对第一连接电极层4进行一次曝光，在经过显影工序或者显影-刻蚀工序而形成第一连接电极41和第二连接电极42。与分别通过两次构图形依次形成第一连接电极41和第二连接电极42的情形相比，有利于简化阵列基板的制作工艺，提高生产效率。如此，第一连接电极41和第一电极31异层设置。在平行于衬底基板1的平面上，第一连接电极41的面积大于第一电极31的面积。例如，在平行于衬底基板1的平面上，第二连接电极42的面积大于第一电极31的面积。关于该面积关系的具体描述以及技术效果请参考之前的描述，在此不再赘述。
图5E为另一个方向上的截面图，该方向与图5D所示的阵列基板的截面所在的方向垂直。如图5E所示，在形成第一过孔101时，可形成多个暴露第一电极31的第一过孔101。第一信号经由第一电极的第一部分311传输给发光器件，例如多个第一过孔101沿第一信号在第一电极的第一部分311中传输的方向排列。例如，如图5E所示，第一过孔101的数量为两个，第一连接电极41与薄膜晶体管的第一电极31通过该两个第一过孔101电连接，例如该两个第一过孔101沿第一信号在第一电极的第一部分311中传输的方向排列。当然，在其他实施中，第一过孔101的数量不限于是两个，例如也可以为三个、四个等。如此，第一连接电极41和薄膜晶体管的第一电极31形成与发光器件电连接的并联结构200。并联结构200中的第一连接电极41(第一连接电极的第一部分411的B 1B 2段和位于两个第一过孔101中的第一连接电极的第二部分412)与并联结构200中的第一电极31(第一电极的第一部分311的A 1A 2段)并联，以减小电信号从点A 1传输至点B 2的电阻，从而减小电信号从薄膜晶体管3传输至发光器件的电阻，从而增大电信号从薄膜晶体管3传输至发光器件的电流。当发光器件需要的电流比较大时，能够满足发光器件的较大的电流需求。
如图5F所示，该制作方法还包括采用有机绝缘材料形成覆盖第一连接电极41和第二连接电极42的第一绝缘材料层5，采用涂布方法形成第一绝缘材料层5，后续利用第一绝缘材料层5形成第一绝缘层。这种情况下，第一绝缘层51是采用有机材料制作的，在制作过程中可采用例如涂布法形成第一绝缘材料层5。如果第一绝缘层51采用无机材料制作，通常使用化学气相沉积(CVD)等方法，而面积较大的第一连接电极41为导电材料例如金属材料，CVD过程中存在等离子气体，面积较大的金属材料制成的第一连接电极41会造成CVD设备中发生异常放电现象，损伤设备，也不利于成膜质量。因此，第一绝缘材料层5采用有机材料制作并且采用涂覆法形成第一绝缘材料层5可避免这一问题。
例如，阵列基板的制作方法还包括：在衬底基板上形成发光器件，发光器件设置于衬底基板上，第一电极经由第一连接电极连接到发光器件。
例如，阵列基板制作方法还包括：在第一绝缘层的远离衬底基板的一侧形成突起；以及将所述发光器件形成于所述突起上。
如图5F-5G所示，利用同一双色调掩模12对第一绝缘材料层5进行一 次构图工艺形成第一绝缘层51和突起7。例如，经过一次曝光工艺形成第一绝缘层51和突起7。例如，下面以第一绝缘材料层5包括光刻胶材料且该光刻胶材料为正性光刻胶的情况为例进行介绍。双色调掩模11包括非曝光区A、完全曝光区B和不完全曝光区C，分别对应于第一绝缘材料层5的用于形成突起、第一绝缘层51、暴露第一连接电极41和第二连接电极42的第二过孔102的区域。再经显影工序，得到如图5G所示的第一绝缘层51和突起7。第一绝缘层51覆盖部分第一连接电极41和部分第二连接电极42，且包括暴露第一连接电极41和第二连接电极42的第二过孔102。即，利用同一双色调掩模经过一次曝光工艺形成第一绝缘层和突起，以简化阵列基板的制作工艺。例如，在形成第一绝缘材料层5的过程中，可以控制第一绝缘材料层5的厚度，以使其厚度满足形成突起7的要求。
例如，该双色调掩模可以为灰色调掩模或半色调掩模。
例如，当第一绝缘材料层5不包括光刻胶材料时，制作方法还包括在第一绝缘材料层5上形成光刻胶以及在显影步骤之后对第一绝缘材料层5进行刻蚀。
如图5H所示，阵列基板制作方法还包括形成黑矩阵8，黑矩阵8位于多个阵列单元100之间，以防止相邻这列单元2发出的光发生串扰。黑矩阵8与第一端子引线61和第二端子引线62均存在空隙，以使黑矩阵8不与第一端子引线61和第二端子引线62接触，可防止黑矩阵8与第一端子引线61和第二端子引线62接触而增大为发光器件2提供电信号的电路的电阻。黑矩阵8例如为不透光的有机材料，例如采用涂覆和构图工艺形成黑矩阵8。
如图5I所示，形成第一端子引线61和第二端子引线62。第一端子引线61与被第一绝缘层51暴露的第一连接电极41连接，第二端子引线62与被第一绝缘层51暴露的第二连接电极42连接。并且，第一端子引线61和第二端子引线62位于突起7上，第一端子引线61的一部分和第二端子引线62的一部分位于突起7的远离衬底基板1的上表面上。例如，突起7的上表面为平坦表面，以有利于后续在该上表面上形成发光器件。
例如，可以形成发光器件2，然后将发光器件2设置于在阵列基板10的预定位置处，例如将发光器件2粘结于阵列基板10的预定位置处。如图5J所示，将发光器件2设置于突起7上，例如将发光器件2设置于突起7的上表面上，从而使得第一绝缘层51位于第一连接电极41与发光器件2之间。 发光器件2包括第一端子引脚241和第二端子引脚242。第一端子引线61与第一端子引脚241连接，从而第一连接电极41依次经由第一端子引线61和第一端子引脚241与第一端子21电连接，从而第一电极31经由第一连接电极41连接到发光器件2。第二端子引线62与第二端子引脚242连接，从而第二连接电极42依次经由第二端子引线62和第二端子引脚242与第二端子22电连接。例如，将在设置发光器件2的过程中，需要对预定位置进行识别，突起7可以辅助识别该预定位置，识别突起7的位置可更加准确地识别出预定位置，使得发光器件2的位置更加精准。发光器件2的排布密度越高，对发光器件2的位置精度要求越高，以防止相邻发光器件2之间的干扰的问题以及局部发光不均的问题等。
阵列基板制作方法所形成的阵列基板具备的技术效果请参考之前的实施例中的描述，在此不再赘述。
例如，图6A-6G为本公开一实施例提供的另一种阵列基板制作方法示意图，该制作方法与图5A-5I所示的实施例的区别在于采用第一掩模通过一次构图工艺形成所述第一绝缘层；以及采用第二掩模通过一次构图工艺形成所述突起。如图6A所示，在完成图5A-5D所示的步骤之后，形成第一绝缘材料层5，以用于后续形成第一绝缘层51，例如该第一绝缘材料层5的厚度小图5F中的第一绝缘材料层5的厚度。形成第一绝缘材料层5的方法与图5F中的相通，请参考之前的描述。
如图6B所示，采用第一掩模(图未示出)通过一次构图工艺形成第一绝缘层51。例如，对第一绝缘材料层5依次进行曝光、显影之后或曝光、显影、刻蚀之后，形成第一绝缘层51，第一绝缘层51包括暴露第一连接电极41和第二连接电极42的第二过孔102。例如，该掩模为单色调掩模。
如图6C所示，形成覆盖第一绝缘层51的突起材料层71，突起材料层71用于后续形成突起。例如，突起材料层71的材料为有机材料。突起材料层71的材料可以与第一绝缘层51的材料不同，也可以与第一绝缘层51的材料相同。
如图6D所示，采用第二掩模(图未示出)通过一次构图工艺形成突起7。例如，配合掩模对突起材料层71进行构图工艺(例如光刻工艺，例如采用单色调掩模进行光刻工艺)，得到突起7。突起7的结构特征与之前实施例中的相同。在突起材料层71的材料与第一绝缘层51的材料相同的情况下， 在对突起材料层71的构图工艺过程中，当对突起材料层71进行刻蚀时，可以控制去除掉的突起材料层71的厚度，以防止第一绝缘层51被过度刻蚀。例如，可通过控制刻蚀时间和刻蚀速率等方法实现，本领域技术人员可以根据本领域常用技术实现。
然后，执行图6E-6G所示的步骤而得到阵列基板。分别与图5H-5G的步骤相同，请参考对图5H-5G的描述。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (19)

  1. 一种阵列基板，包括：
    衬底基板；
    薄膜晶体管，设置于所述衬底基板上并包括第一电极和第二电极；
    第一连接电极，与所述第一电极异层设置且与所述第一电极电连接以及
    第一绝缘层，覆盖至少部分所述第一连接电极；其中，
    所述第一连接电极在所述衬底基板的正投影的面积大于所述第一电极在所述衬底基板的正投影的面积；并且
    所述第一绝缘层的材料为有机绝缘材料。
  2. 根据权利要求1所述的阵列基板，还包括发光器件，其中，所述发光器件设置于所述衬底基板上，所述第一电极经由所述第一连接电极电连接到所述发光器件；
    所述第一连接电极包括平行于所述衬底基板的第一部分和与所述衬底基板具有夹角的第二部分，所述第一电极包括平行于所述衬底基板的第一部分和与所述衬底基板具有夹角的第二部分；
    第一信号经所述第一电极和所述第一连接电极传递到所述发光器件，在平行于所述衬底基板的平面上，所述第一连接电极的第一部分在垂直于所述第一信号传输方向上的宽度大于所述第一电极的第一部分在垂直于所述第一信号传输方向上的宽度，以使得所述第一连接电极的面积大于所述第一电极的面积。
  3. 根据权利要求2所述的阵列基板，其中，
    在平行于所述衬底基板的平面上，所述第一连接电极的第一部分在垂直于所述第一信号传输方向上的宽度大于10μm。
  4. 根据权利要求1-3任一所述的阵列基板，还包括：
    第二绝缘层，位于所述薄膜晶体管与所述第一连接电极之间，以将所述薄膜晶体管和所述第一连接电极彼此隔开；
    其中，所述第二绝缘层包括至少两个过孔，所述第一连接电极与所述薄膜晶体管的第一电极通过所述至少两个过孔电连接。
  5. 根据权利要求1所述的阵列基板，还包括发光器件，其中，所述发光 器件设置于所述衬底基板上，所述第一电极经由所述第一连接电极连接到所述发光器件；以及
    第二连接电极，其中，所述第二连接电极与所述第一连接电极同层设置，所述第一绝缘层还覆盖至少部分所述第二连接电极，所述第二连接电极在所述衬底基板的正投影的面积大于所述第一电极在所述衬底基板的正投影的面积；
    所述发光器件包括第一端子、发光层和第二端子，所述第一连接电极与所述第一端子电连接，所述第二连接电极与所述第二端子电连接。
  6. 根据权利要求5所述的阵列基板，其中，
    第二信号从所述第二连接电极传输到所述发光器件，在平行于所述衬底基板的平面上，所述第二连接电极的在垂直于所述第二信号传输方向上的宽度大于10μm。
  7. 根据权利要求5所述的阵列基板，其中，所述第一连接电极的材料和所述第二连接电极的材料为金属材料。
  8. 根据权利要求5所述的阵列基板，包括：
    呈阵列排布的多个阵列单元，其中，所述发光器件位于所述阵列单元中；以及
    不透光的黑矩阵，位于所述多个阵列单元中相邻的阵列单元之间。
  9. 根据权利要求8所述的阵列基板，还包括第一端子引线和第二端子引线，其中，所述第一连接电极通过所述第一端子引线与所述第一端子电连接，所述第二连接电极通过所述第二端子引线与所述第二端子电连接；
    所述黑矩阵与所述第一端子引线和所述第二端子引线之间均存在空隙。
  10. 根据权利要求1所述的阵列基板，还包括：
    突起，位于所述第一绝缘层的远离所述衬底基板的一侧；以及
    发光器件，设置于所述突起上，所述第一电极经由所述第一连接电极电连接到所述发光器件。
  11. 根据权利要求10所述的阵列基板，其中，所述突起与所述第一绝缘层一体成型。
  12. 根据权利要求2-3或5-11任一所述的阵列基板，其中，所述发光器 件为小型发光二极管或者微型发光二极管(Micro LED)。
  13. 一种电子装置，包括权利要求1-12任一所述的阵列基板。
  14. 一种阵列基板制作方法，包括：
    提供衬底基板；
    在所述衬底基板上形成薄膜晶体管，所述薄膜晶体管包括第一电极和第二电极；
    在所述衬底基板上形成第一连接电极，所述第一连接电极和所述第一电极异层设置且与所述第一电极电连接；以及
    形成第一绝缘层，所述第一绝缘层覆盖至少部分所述第一连接电极；
    其中，在平行于所述衬底基板的平面上，所述第一连接电极的面积大于所述第一电极的面积；并且
    所述第一绝缘层的材料为有机绝缘材料。
  15. 根据权利要求14所述的阵列基板制作方法，还包括：
    在所述衬底基板上形成发光器件，其中，所述发光器件设置于所述衬底基板上，所述第一电极经由所述第一连接电极电连接到所述发光器件；以及
    形成第二连接电极，其中，
    所述第二连接电极与所述第一连接电极是利用同一掩模通过一次构图工艺形成，所述第一绝缘层还覆盖至少部分所述第二连接电极，并且在平行于所述衬底基板的平面上，所述第二连接电极的面积大于所述第一电极的面积；
    所述发光器件包括第一端子、发光层和第二端子，所述第一连接电极与所述第一端子电连接，所述第二连接电极与所述第二端子电连接。
  16. 根据权利要求15所述的阵列基板制作方法，还包括：
    采用有机绝缘材料形成覆盖所述第一连接电极和所述第二连接电极的第一绝缘材料层，其中，采用涂布方法形成第一绝缘材料层；以及
    对所述第一绝缘材料层执行构图工艺以形成所述第一绝缘层。
  17. 根据权利要求14-16任一所述的阵列基板制作方法，还包括：
    在所述第一绝缘层的远离所述衬底基板的一侧形成突起；以及
    在所述突起上形成发光器件；其中，
    所述第一电极经由所述第一连接电极电连接到所述发光器件。
  18. 根据权利要求17所述的阵列基板制作方法，其中，利用同一双色调掩模经过一次构图工艺形成所述第一绝缘层和所述突起。
  19. 根据权利要求17所述的阵列基板制作方法，还包括：
    采用第一掩模通过一次构图工艺形成所述第一绝缘层；以及
    采用第二掩模通过一次构图工艺形成所述突起。
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