WO2015035818A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2015035818A1
WO2015035818A1 PCT/CN2014/081118 CN2014081118W WO2015035818A1 WO 2015035818 A1 WO2015035818 A1 WO 2015035818A1 CN 2014081118 W CN2014081118 W CN 2014081118W WO 2015035818 A1 WO2015035818 A1 WO 2015035818A1
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Prior art keywords
electrode
drain
layer
source
gate
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PCT/CN2014/081118
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English (en)
French (fr)
Inventor
张锋
姚琪
刘志勇
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京东方科技集团股份有限公司
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Priority to US14/422,843 priority Critical patent/US9515095B2/en
Publication of WO2015035818A1 publication Critical patent/WO2015035818A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to an array substrate, a preparation method thereof, and a display device. Background technique
  • the flat panel display device has the characteristics of small size, low power consumption, no radiation, etc., and has gradually replaced the bulky CRT (Cathode Ray Tube) display device and occupied the dominant position in the display market.
  • CRT Cathode Ray Tube
  • Commonly used flat panel display devices include LCD
  • Liquid Crystal Display Liquid Crystal Display Device
  • PDP Plasma Display Panel
  • OLED Organic Light-Emitting Diode
  • each pixel in the LCD and the Active Matrix Organic Light Emission Display (AMOLED) display device is composed of a thin film transistor (TFT) integrated in the array substrate. Drive to achieve image display.
  • TFT thin film transistor
  • Thin film transistor As the light-emitting control switch, it is the key to realize the display of LCD and 0LED display devices, which is directly related to the development direction of high-performance display devices.
  • LCD includes TN (Twisted Nematic) mode, VA
  • the array substrate includes both the pixel electrode and the common electrode, and the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer form a multi-dimensional electric field, so that the liquid crystal cell All of the aligned liquid crystal molecules between the inner slit electrodes and directly above the electrodes are capable of generating rotation, which increases the working efficiency of the liquid crystal molecules and increases the light transmission efficiency while increasing the viewing angle.
  • the thin film transistor mainly includes a gate, a gate insulating layer, an active layer, a source and a drain.
  • 1 is a cross-sectional view of an array substrate of an ADSDS mode in the prior art, in which the patterning process is performed five times from bottom to top.
  • the art (or mask process) is completed, including: a common electrode mask, a gate mask, an active layer and a source/drain mask, a passivation layer via mask, and a pixel electrode mask.
  • the common electrode and the gate are respectively formed of a transparent conductive material and a metal material by two patterning processes.
  • FIG. 2 is a cross-sectional view of another ADSDS mode array substrate in the prior art, in which the bottom substrate is prepared by 6 patterning processes (or mask processes) from bottom to top, including : a gate mask, an active layer mask, a source/drain mask, a pixel electrode mask, a passivation layer via mask, a common electrode mask.
  • the source/drain electrodes and the pixel electrodes are respectively formed of a metal material and a transparent conductive material by two patterning processes.
  • the common electrode and the gate, the source/drain and the pixel electrode are all completed by two mask processes, and the process is relatively complicated and costly.
  • the same problem exists in the preparation of the array substrate of the TN mode, the VA mode, and the 0LED display device.
  • the invention provides an array substrate, a preparation method thereof, and a display device.
  • the method for preparing the array substrate and the corresponding array substrate effectively simplifies the preparation process of the array substrate, reduces the cost of the mask plate and the material, and reduces the device. Investment, saving manufacturing costs, increasing production capacity, and improving the competitiveness of display device products.
  • the technical solution to solve the technical problem to be solved by the present invention is an array substrate comprising a substrate substrate and a thin film transistor and at least one driving electrode disposed on the substrate, the thin film transistor including a gate And a source/drain disposed in the same layer, wherein the gate or the source/the drain and one of the at least one driving electrode are a film formed of the same material And the thickness thereof is greater than the thickness of the one driving electrode.
  • the at least one driving electrode includes a first electrode and a second electrode, the first electrode and the second electrode at least partially overlap in a right projection direction, and the second electrode is disposed on the Below the first electrode, the gate and the An electrode in an upper layer of the source/the drain, a film formed of the same material as the first electrode, and a thickness of the first electrode is smaller than a thickness of the electrode; and/or, An electrode in a lower layer of the gate and the source/the drain, a film layer formed of the same material as the second electrode, and a thickness of the second electrode is smaller than a thickness of the electrode.
  • the film formed of the same material is a single layer or a multilayer composite film layer formed of aluminum, copper, molybdenum, aluminum bismuth alloy, chromium, titanium or silver.
  • the transmittance of the at least one driving electrode is in the range of
  • thickness range from 100-1000 people.
  • the film formed of the same material is a multilayer composite film layer having a one-dimensional metal I dielectric photonic crystal structure, the metal including silver, and the medium includes ruthenium or indium tin oxide.
  • the at least one drive electrode has a transmittance ranging from 30 to 90% and a thickness ranging from 100 to 1000 persons.
  • the first electrode is a slit-shaped pixel electrode
  • the second electrode is a plate-shaped common electrode
  • the pixel electrode is electrically connected to the drain; or the first electrode is narrow a slit-shaped common electrode, wherein the second electrode is a plate-shaped pixel electrode, and the pixel electrode is electrically connected to the drain.
  • the driving electrode includes a pixel electrode, the source/the drain, and the pixel electrode are a film formed of the same material, and the thickness of the pixel electrode is smaller than the The thickness of the source/the drain.
  • the film formed of the same material is a single layer or a multilayer composite film layer formed of aluminum, copper, molybdenum, aluminum bismuth alloy, chromium, titanium or silver.
  • the pixel electrode is electrically connected to the drain, and the pixel electrode has a transmittance ranging from 30 to 90% and a thickness ranging from 10 to 100 ⁇ .
  • the film formed of the same material is a multilayer composite film layer having a one-dimensional metal I dielectric photonic crystal structure, the metal including silver, and the medium includes ruthenium or indium tin oxide.
  • the pixel electrode is electrically connected to the drain, and the pixel electrode has a transmittance ranging from 30 to 90% and a thickness ranging from 100 to 1000.
  • a display device comprising the above array substrate.
  • a method for fabricating an array substrate comprising the steps of forming a thin film transistor and a at least one driving electrode on a substrate, the thin film transistor including a gate and a source/drain disposed in the same layer, wherein the gate And a film formed by one of the source/the drain and one of the at least one driving electrode by the same patterning process and formed of the same material, and having a thickness greater than the one The thickness of the drive electrode.
  • forming one of the gate and the source/the drain with one of the at least one drive electrode by the same patterning process comprises the following steps:
  • Step S1 forming a metal electrode layer
  • Step S2 forming a photoresist layer over the metal electrode layer
  • Step S3 performing a exposure and development process on the photoresist layer by using a halftone mask or a gray tone mask, corresponding to forming the gate and the source/the drain
  • a halftone mask or a gray tone mask corresponding to forming the gate and the source/the drain
  • Step S4 performing a first etching process on the metal electrode layer, and forming a region corresponding to the region forming the gate and the one of the source/the drain and correspondingly forming the one driving Removal of the metal electrode material outside the area of the electrode;
  • Step S5 performing a thinning process on the photoresist layer, and retaining a portion of the photoresist corresponding to a region where the gate and the source/the drain are formed, correspondingly forming The photoresist of the region of the one driving electrode is completely removed;
  • Step S6 performing a second etching process on the metal electrode layer, and partially removing the metal electrode material corresponding to the region forming the one driving electrode to form a pattern including the gate and the one of the source/the drain and the one driving electrode;
  • Step S7 removing the remaining photoresist in the photoresist layer.
  • the step of forming the metal electrode layer comprises forming a single layer or a multilayer composite film layer using aluminum, copper, molybdenum, aluminum bismuth alloy, chromium, titanium or silver.
  • the pattern including the one of the gate and the source/the drain and the one driving electrode includes forming a thickness range of
  • the one drive electrode having a transmittance ranging from 30 to 90%.
  • the step of forming a metal electrode layer comprises forming a multilayer composite film layer having a one-dimensional metal/dielectric photonic crystal structure, the metal comprising silver, and the medium comprising 3 ⁇ 4 chemical or indium tin oxide.
  • the pattern including the one of the gate and the source/the drain and the one driving electrode includes forming a thickness ranging from 100 to 1000 persons, and a transmittance The one drive electrode ranges from 30 to 90%.
  • the step of thinning the photoresist layer comprises thinning the photoresist layer by an ashing process.
  • the at least driving electrode includes a first electrode and a second electrode, the first electrode and the second electrode at least partially overlapping in a right projection direction, and the second electrode is disposed at the first electrode Below, where
  • the step of forming one of the gate and the source/the drain and one of the at least one driving electrode by the same patterning process comprises: simultaneously forming the gate and the gate by the same patterning process An electrode in the upper layer and the first electrode in the source/the drain; and/or
  • the lower electrode and the second electrode of the gate and the source/the drain are simultaneously formed by the same patterning process.
  • the first electrode is a slit-shaped pixel electrode
  • the second electrode is a plate-shaped common electrode
  • the pixel electrode is electrically connected to the drain; or the first electrode is a slit-shaped common electrode, the second electrode is a plate-shaped pixel electrode, and the pixel electrode is electrically connected to the drain.
  • the driving electrode includes a pixel electrode
  • the step of forming one of the gate and the source/the drain and one of the at least one driving electrode by the same patterning process comprises:
  • the source/the drain and the pixel electrode are simultaneously formed by the same patterning process, and the pixel electrode is electrically connected to the drain.
  • the beneficial effects of the present invention are: in the array substrate of the present invention, the gate or the The source/the drain and one of the at least one driving electrode are formed of the same material, the thickness of which is greater than the thickness of the one driving electrode; and the gate or the source/s The drain is formed by the same patterning process as the one driving electrode, which satisfies the transmittance, effectively simplifies the preparation process of the array substrate, reduces the cost of the mask and the material, reduces equipment investment, and saves manufacturing cost. , increased production capacity and improved the competitiveness of display device products.
  • 1 and 2 are cross-sectional views of two array substrates in the prior art.
  • Figure 3 is a cross-sectional view showing an array substrate in Embodiment 1 of the present invention.
  • FIG. 4-1 to FIG. 4-6 are diagrams showing the preparation process of the array substrate in FIG. 3, wherein:
  • Figure 4-1 is a cross-sectional view showing a structure in which a metal electrode layer is formed
  • FIG. 4-2 is a cross-sectional view showing a structure after exposure and development of a photoresist layer
  • FIG. 4-3 is a cross-sectional view showing a structure after a first etching process
  • Figure 4-4 is a cross-sectional view showing the structure after the ashing process
  • FIG. 4-5 are cross-sectional views showing the structure after the second etching process
  • 4-6 are cross-sectional views showing the structure after peeling off the remaining photoresist.
  • Figure 5 is a cross-sectional view showing an array substrate in Embodiment 3 of the present invention.
  • FIG. 6-1 to Figure 6-7 are diagrams showing the preparation process of the array substrate of Figure 5, wherein:
  • Figure 6-1 is a cross-sectional view showing a structure for forming a metal electrode layer
  • FIG. 6-2 is a cross-sectional view showing the structure after exposure and development of the photoresist layer
  • FIG. 6-3 is a cross-sectional view showing the structure after the first etching process
  • Figure 6-4 is a cross-sectional view showing the structure after the ashing process
  • 6-5 is a cross-sectional view showing the structure after the second etching process
  • 6-6 is a cross-sectional view showing the structure after the third etching process
  • Fig. 6-7 is a cross-sectional view showing the structure after peeling off the remaining photoresist.
  • Figure 7 is a cross-sectional view showing an array substrate in a fifth embodiment of the present invention.
  • Figure 8 is a cross-sectional view showing an array substrate in a sixth embodiment of the present invention.
  • Figure 9 is a cross-sectional view showing an array substrate in Embodiment 7 of the present invention.
  • Figure 10 is a cross-sectional view showing an array substrate in an eighth embodiment of the present invention.
  • Figure 11 is a cross-sectional view showing an array substrate in Embodiment 9 of the present invention.
  • Figure 12 is a cross-sectional view showing an array substrate in Embodiment 10 of the present invention.
  • Figure 13 is a cross-sectional view showing an array substrate in Embodiment 11 of the present invention.
  • Fig. 14 is a graph showing changes in transmittance and film thickness of a silver (Ag) film.
  • Figure 15 is a graph showing the transmittance and thickness variation of a one-dimensional metal-dielectric photonic crystal structure.
  • the present invention provides an array substrate including a substrate substrate and a thin film transistor and at least one driving electrode disposed on the substrate, the thin film transistor including a gate and a source/drain disposed in the same layer, Wherein the gate or the source/the drain and one of the at least one driving electrode are formed of the same material and have a thickness greater than a thickness of the one driving electrode.
  • Example 1
  • the embodiment provides an array substrate including a substrate substrate and a thin film transistor disposed on the substrate and a first electrode and a second electrode as driving electrodes, wherein the thin film transistor includes a gate and is disposed on the same layer The source/drain, the first electrode and the second electrode at least partially overlap in a right projection direction, and the second electrode is disposed below the first electrode.
  • the thin film transistor is a bottom gate type structure. That is, in the thin film transistor, the gate, the source and the drain are in the lower layer as the gate, the upper layer is the source and the drain, the first electrode is the slit-shaped pixel electrode, and the second electrode is Plate-shaped common electrode.
  • the top surface of the base substrate 10 is sequentially provided with the gate electrode 11 and the common electrode 21, the gate insulating layer 12, and the active layer 13 in the same layer (as can be seen from FIG. 3,
  • the active layer 13 is a two-layer sub-layer structure), the source 14 and the drain 15 disposed in the same layer, and the passivation layer 16 are disposed above the passivation layer 16 and pass through the passivation layer via and the drain 15
  • the pixel electrode 20 is electrically connected.
  • the gate electrode 11 and the common electrode 21 are formed of the same material, and the thickness of the common electrode 21 is smaller than the thickness of the gate electrode 11.
  • the gate electrode 11 and the common electrode 21 are single-layer or multi-layer composite film layers, and 4 Lu (A1), 4 (Cu), (Mo), 4 Lu 4 female alloys (AlNd), 4 (Cr), titanium (T i ) or silver (Ag ) are formed.
  • the common electrode 21 has a thickness ranging from 10 to 100 ⁇ and a transmittance ranging from 30 to 90%.
  • the method for fabricating the array substrate in the embodiment includes the steps of forming a thin film transistor and a pixel electrode and a common electrode as a driving electrode on the substrate, the thin film transistor including the gate and the source/drain disposed in the same layer
  • the common electrode is disposed under the pixel electrode, wherein the gate electrode in the opposite lower layer and the common electrode are formed simultaneously by the same material, and the thickness of the common electrode is smaller than the thickness of the gate electrode.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • the lithography process refers to a process of forming a pattern by using a photoresist, a reticle, an exposure machine, or the like, including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the gate and the common electrode are simultaneously formed by the same patterning process, and specifically include the following steps S1 to S7.
  • Step SI Forming a metal electrode layer.
  • a metal is formed over the base substrate 10.
  • the electrode layer specifically, the gate metal layer 110 is formed by a method of deposition, sputtering, or evaporation.
  • the gate metal layer 110 is formed of aluminum (A1), copper (Cu), molybdenum (Mo), aluminum-niobium alloy (AlNd), chromium (Cr), titanium (T i ) or silver (Ag),
  • the gate metal layer 110 in the embodiment is preferably formed of silver (Ag).
  • Step S2 forming a photoresist layer over the metal electrode layer.
  • a photoresist layer 19 is formed over the gate metal layer 110 by a coating method.
  • Step S3 using a halftone mask or a gray tone mask, exposing and developing the photoresist layer, completely retaining the photoresist corresponding to the region where the gate is formed, corresponding to the region where the common electrode is formed. The photoresist is partially retained and the photoresist in the remaining areas is completely removed.
  • the photoresist layer 19 is exposed by using a halftone mask or a gray tone mask, so that the photoresist in different regions of the photoresist layer 19 is completely generated and partially The photocuring reaction occurs or does not occur.
  • the photoresist corresponding to the region where the gate electrode is formed in the photoresist layer 19 is completely retained, and the photoresist portion corresponding to the region where the common electrode is formed remains, and the remaining regions are retained.
  • the photoresist is completely removed, that is, a photoresist pattern having different thicknesses of different regions is formed over the gate metal layer 110.
  • Step S4 performing a first etching process on the metal electrode layer to remove the metal electrode material corresponding to the region where the gate electrode is formed and the region corresponding to the common electrode.
  • the gate metal layer 110 not protected by the photoresist is etched by the first etching process to form the gate electrode 11 and the patterned gate which is contoured.
  • Metal pattern 111 is formed to form a common electrode and a common electrode line in a subsequent process, the common electrode is used to drive the liquid crystal to rotate, and the common electrode line is used to input an electrical signal to the common electrode, which is common to The electrodes are electrically connected.
  • Step S5 The photoresist layer is thinned, and the photoresist portion corresponding to the region where the gate electrode and the common electrode line are formed is left, and the photoresist corresponding to the region where the common electrode is formed is completely removed.
  • the photoresist layer 19 is thinned by an ashing process to remove a portion of the photoresist, that is, the photoresist electrode layer 19 is removed to form a common electrode for driving.
  • the thinning of the photoresist is not limited to the ashing process, and other thinning processes having the same thinning effect can be applied to the step, which is not limited in this embodiment.
  • Step S6 performing a second etching process on the metal electrode layer, partially removing the metal electrode material corresponding to the region where the common electrode is formed, and forming a pattern including the gate electrode and the common electrode.
  • a portion of the gate metal layer not protected by the photoresist is etched by a second etching process, specifically, the exposed contoured pattern is formed.
  • a portion of the gate metal pattern 1 1 1 corresponding to the common electrode for driving is etched, and since the metal electrode material of the portion is exposed without being covered by the photoresist, the parameters of the etching process are controlled such that the The thickness of the portion of the gate metal layer ranges from 1 to 00 00, and the transmittance ranges from 30 to 90%, that is, the common electrode 21 is formed, and correspondingly forms a common electrode line for electrically connecting with the common electrode.
  • the thickness of the portion of the metal electrode material remains as the thickness of the gate metal layer, that is, the common electrode line 22 is formed, and the thickness of the common electrode line 22 is the same as the thickness of the gate electrode 11. . Since the common electrode line 22 has a larger thickness with respect to the common electrode 21, good electrical conductivity can be ensured and a good electrical connection can be achieved.
  • Step S7 removing the remaining photoresist in the photoresist layer.
  • the thickness of the gate electrode 1 in the embodiment ranges from 500 to 2000, and the thickness of the common electrode 21 formed after thinning is 50, and the transmittance of the common electrode 21 is about 90%.
  • the gate 1 1 may be aluminum (A 1 ), a single-layer metal film layer formed of copper (Cu), molybdenum (Mo), aluminum-niobium alloy (AlNd), chromium (Cr), titanium (T i ) or silver (Ag) or a multilayer composite film layer composed thereof
  • the common electrode 21 can be obtained by thinning by a etching process using a single-layer metal film layer of the same material as that of the gate electrode described above or a multilayer composite film layer composed of the same.
  • Fig. 14 is a graph showing changes in transmittance and film thickness of a silver (Ag) film. As can be seen from Fig. 14, as the thickness of the silver (Ag) film increases, the transmittance thereof gradually decreases. Therefore, in the actual preparation process, a relatively balanced and reasonable thickness range can be obtained according to the preparation conditions of the process equipment and the design requirements of the array substrate for light transmittance.
  • the data line and the gate line are also formed in the embodiment (not shown in FIG. 3, FIG. 4-1 to FIG. 4-6), and the data line and the gate line are disposed at the intersection and
  • the base substrate 10 is divided into a plurality of pixel regions, and the thin film transistor is disposed in or within the pixel region i.
  • the method for fabricating the array substrate in this embodiment further includes: forming a gate insulating layer 12 over the common electrode 21 and the gate electrode 11, and forming an active layer 13 over the gate insulating layer 12, in the active layer 13
  • a source 14/drain 15 is formed above
  • a passivation layer 16 is formed over the source 14/drain 15
  • a pixel electrode 20 is formed over the passivation layer 16 to electrically connect the pixel electrode 20 with the drain 15.
  • the common electrode 21 has a plate shape
  • the pixel electrode 20 has a slit shape
  • the pixel electrode 20 is disposed above the common electrode 21 and at least partially overlaps the common electrode 21 in the forward projection direction.
  • the gate insulating layer, the active layer, the source/drain, the passivation layer, and the pixel electrode are formed and the gate insulating layer, the active layer, the source/drain, the passivation layer, and the like in the prior art.
  • the formation of the pixel electrodes is the same and will not be described here.
  • the present embodiment further provides a display device using the above array substrate, in which the array substrate includes both a pixel electrode and a common electrode, that is, a display device in an ADSDS mode.
  • the display device can be: any product or component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like.
  • the gate electrode and the common electrode are prepared by a patterning process using a halftone mask or a gray tone mask, and the gate electrode and the common electrode are both formed of the same material, and the thickness of the common electrode is smaller than The thickness of the gate ensures the public The transmittance of the common electrode satisfies the display requirements of the ADSDS mode display device.
  • the gate electrode and the common electrode are made of different materials and are prepared by two patterning processes (or mask processes), the embodiment reduces the patterning process and effectively simplifies the array substrate.
  • the preparation process reduces the cost of the mask and materials, reduces equipment investment, saves costs, increases productivity, and improves the competitiveness of display device products.
  • Example 2 Example 2:
  • the gate electrode 11 and the common electrode 21 are formed by using a multilayer composite film layer having a one-dimensional metal/dielectric photonic crystal structure, wherein the metal Including silver g), the medium includes sulfide (ZnS) or Indium Tin Oxide (ITO), and the thickness of the common electrode 21 ranges from 100 to 1000 persons.
  • the gate electrode 11 is a ZnS/Ag/ZnS/Ag or ITO/Ag/ITO/Ag composite film layer structure, wherein the thickness of the vulcanization is in the range of 200-800 people, and the thickness range of the indium tin oxide is 200-800 people, the inner layer of metallic silver has a thickness ranging from 50 to 200 A, and the outer layer of metallic silver has a thickness ranging from 500 to 2000 A, for example, the structure of each layer of ZnS/Ag/ZnS/Ag The thickness is 400 A/180 A /400 A /2000 A, respectively, and the structure of the common electrode 21 is a ZnS/Ag/ZnS or ITO/Ag/ITO composite film layer structure, for example, each of the structures ZnS/Ag/ZnS The thickness of the film layer is 400 A / 180 A / 400 people, respectively.
  • step S1 when the gate metal layer 110 is formed, ZnS is sequentially formed on the substrate substrate 10 in sequence.
  • Each of the /Ag/ZnS/Ag film layers, the above-mentioned multilayer composite film layer, is the gate metal layer 110.
  • each of the ZnS/Ag/ZnS/Ag layers is formed by deposition, sputtering or evaporation.
  • step S6 the Ag film layer of the surface layer of the gate metal layer 110 is removed by an etching process to obtain a common electrode 21 for driving the rotation of the liquid crystal, and the transmittance of the common electrode 21 is ensured, and the common electrode 21 is ZnS/Ag/ The ZnS composite film layer structure, and the gate electrode 11 and the common electrode line 11 maintain the ZnS/Ag/ZnS/Ag composite film layer structure.
  • Other structures of the array substrate in this embodiment are the same as those in Embodiment 1, and are not described herein again.
  • This embodiment also provides a display device using the above array substrate.
  • Example 3
  • the thin film transistor in the array substrate is still a bottom gate type structure
  • the driving electrode still includes a first electrode and a second electrode
  • the second electrode is disposed under the first electrode, wherein the first electrode
  • the slit-shaped common electrode is a plate-shaped pixel electrode.
  • the source/drain and the pixel electrode are formed of the same material, and the thickness of the pixel electrode is smaller than the thickness of the source/drain.
  • the array substrate of this embodiment includes a gate electrode 11 formed over the substrate substrate 10, a gate insulating layer 12 formed over the gate electrode 11, and an active layer 13 formed over the gate insulating layer 12.
  • the pixel electrode 20 has a plate shape
  • the common electrode 21 has a slit shape
  • the common electrode 21 is disposed opposite to the pixel electrode 20 and at least partially overlaps the pixel electrode 20 in the forward projection direction.
  • the source 14/drain 15 and the pixel electrode 20 are simultaneously formed by the same material by the same patterning process, and the thickness of the pixel electrode 20 is smaller than the source 14/drain.
  • the source 14/drain 15 and the pixel electrode 20 are simultaneously formed by the same patterning process, and specifically include the following steps S1 to S7.
  • Step SI A metal electrode layer is formed.
  • the gate electrode 11, the gate insulating layer 12, and the active layer 13 have been prepared in the array substrate.
  • a metal electrode layer is formed over the active layer 13, and specifically, a source/drain metal is formed by deposition, sputtering, or evaporation.
  • Layer 140 a source/drain metal is formed by deposition, sputtering, or evaporation.
  • the source/drain metal layer 140 is made of aluminum (A 1 ), copper (Cu), molybdenum ( ⁇ ⁇ ), aluminum bismuth alloy (A lNd ), chromium (Cr), titanium (T i ) or silver (Ag).
  • the source/drain metal layer in this embodiment is preferably formed of silver (Ag).
  • Step S2 forming a photoresist layer over the metal electrode layer.
  • a photoresist layer 19 is formed over the source/drain metal layer 140 by a coating method.
  • Step S3 using a halftone mask or a gray tone mask, exposing and developing the photoresist layer, completely retaining the photoresist corresponding to the region forming the source/drain, corresponding to forming the pixel electrode The photoresist portion of the region remains, and the photoresist in the remaining regions is completely removed.
  • the photoresist layer 19 is exposed by using a halftone mask or a gray tone mask, so that photoresists in different regions of the photoresist layer 19 are completely generated. Part of the photocuring reaction occurs or does not occur.
  • the photoresist corresponding to the source/drain region in the photoresist layer 19 is completely retained, and the photoresist portion corresponding to the region where the pixel electrode is formed remains.
  • the photoresist in the remaining regions is completely removed, that is, a photoresist pattern having different thicknesses of different regions is formed over the source/drain metal layer 140.
  • Step S4 performing a first etching process on the metal electrode layer to remove the metal electrode material corresponding to the region where the source/drain is formed and the region corresponding to the pixel electrode.
  • the source/drain metal layer 140 not protected by the photoresist is etched by a first etching process to form a patterned source/drain metal pattern 141.
  • the patterned patterned source/drain metal pattern 141 will form a pixel electrode and a source/drain in a subsequent process, and, after the first etching process, the source/drain corresponds to the source/drain
  • the patterned source/drain metal pattern 141 of the pole region has formed a trench or gap, and the subsequently formed source and drain will be distributed on opposite sides of the trench or gap.
  • Step S5 thinning the photoresist layer, leaving a portion of the photoresist corresponding to the region where the source/drain is formed, and completely removing the photoresist corresponding to the region where the pixel electrode is formed.
  • the photoresist is thinned by an ashing process, for example, plasma is directly processed by a gas to remove a portion of the remaining photoresist, that is, the photoresist layer is removed.
  • a portion of the corresponding patterned source/drain metal pattern 141 is exposed, and a portion of the photoresist for forming the source/drain is left to be covered.
  • This portion corresponds to a partial region of the patterned source/drain metal pattern 141.
  • the thinning of the photoresist is not limited to the ashing process, and other thinning processes having the same thinning effect can be applied to the step, which is not limited in this embodiment.
  • Step S6 performing a second etching process on the metal electrode layer, partially removing the metal electrode material corresponding to the region where the driving electrode is formed, and forming a pattern including the source/drain and the pixel electrode.
  • the source/drain portions that are not protected (ie, covered) by the photoresist are etched by a second etching process to control the parameters of the etching process.
  • the pixel electrode 20 has a thickness ranging from 10 to 100 A and a transmittance ranging from 30 to 90%.
  • a third etching process is further included, as shown in FIG. 6-6, by dry etching the trenches in the active layer 13 corresponding to the patterned source/drain metal pattern 141 or The gap region is n+ etched (the structure of the active layer 13 in FIGS. 6-1 to 6-7 may be the same as that of the active layer in the prior art, and both are double-layer sub-layer structures), forming a true In the sense of the source 14 / the drain 15, the pixel electrode 20 and the drain 15 are directly electrically connected.
  • Step S7 removing the remaining photoresist in the photoresist layer.
  • the thickness of the source 14/drain 15 ranges from 500 to 2000, and the thickness of the thinned pixel electrode 20 is 50, and the pixel electrode at this time The transmission rate of 20 is about 90%.
  • the source 14 / drain 15 may be aluminum (A 1 ), copper (Cu), phase (Mo), aluminum-bismuth alloy (A l Nd ), chromium (Cr), titanium (T).
  • the pixel electrode 20 may be a single-layer metal film layer of the same material as that of the source 14/drain 15 Or a multilayer composite film layer composed of the same is obtained by thinning by an etching process.
  • the method for fabricating the array substrate in this embodiment further includes: forming a passivation layer 16 over the source/drain 15 and the pixel electrode 20, and forming a common electrode 21 over the passivation layer 16.
  • the common electrode 21 is electrically connected to the common electrode line 22 through the via holes in the gate insulating layer 12 and the via holes in the passivation layer 16.
  • the pixel electrode 20 has a plate shape
  • the common electrode 21 has a slit shape.
  • the common electrode 21 is disposed opposite to the pixel electrode 20 and at least partially overlaps the pixel electrode 20 in the forward projection direction.
  • the formation of the gate, the gate insulating layer, the active layer, the passivation layer, and the common electrode is the same as the formation of the gate, the gate insulating layer, the active layer, the passivation layer, and the common electrode in the prior art. I won't go into details here.
  • this embodiment also provides a display device in the ADSDS mode.
  • the embodiment is a modification of the embodiment 1.
  • the pixel electrode in the array substrate may be a plate shape or a slit shape, and correspondingly, the common electrode may be a slit shape. It can also be plate-shaped.
  • the display device of ADSDS mode has the advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no pus h Mura, and has good picture quality.
  • the source/drain electrodes and the pixel electrodes are prepared by a patterning process using a halftone mask or a gray tone mask, and the source/drain electrodes and the pixel electrodes are formed of the same material. Moreover, the thickness of the pixel electrode is smaller than the thickness of the source/drain, which ensures that the transmittance of the pixel electrode satisfies the display requirement of the ADSDS mode display device.
  • the embodiment reduces the patterning process, effectively simplifies the preparation process of the array substrate, and reduces The cost of masks and materials reduces equipment investment, saves costs, increases productivity, and improves visibility Show the competitiveness of the device products.
  • Example 4
  • the source 14/drain 15 and the pixel electrode 20 are formed by using a multilayer composite film layer having a one-dimensional metal/dielectric photonic crystal structure.
  • the metal comprises silver (Ag)
  • the medium comprises sulfided (ZnS) or indium tin oxide (IT0)
  • the thickness of the pixel electrode 20 ranges from 100 to 1000.
  • the structure of the source 14 / the drain 15 is a ZnS / Ag / ZnS / Ag or ITO / Ag / ITO / Ag composite film layer structure, wherein the thickness of the vulcanization is in the range of 200-800 people, oxidation
  • the thickness of indium tin ranges from 200 to 800 A
  • the thickness of metallic silver in the inner layer ranges from 50 to 200 A
  • the thickness of metallic silver in the outer layer ranges from 500 to 2000 A, for example, structure ZnS/Ag/ZnS/
  • the thickness of each film layer in Ag is 400 A /180 A /400 A /2000 A, respectively.
  • the structure of the pixel electrode 20 is a ZnS/Ag/ZnS or ITO/Ag/ITO composite film layer structure, for example, a structure ZnS.
  • the thickness of each film in /Ag/ZnS is 400 A /180 A /400 k, respectively.
  • step S1 when the source/drain metal layer 140 is formed, in the active layer 13
  • the ZnS/Ag/ZnS/Ag film layers is sequentially formed on the upper side, and the above-mentioned multilayer composite film layer is the source/drain metal layer 140.
  • each of the ZnS/Ag/ZnS/Ag film layers is formed by deposition, sputtering or evaporation.
  • step S6 the Ag film layer of the surface layer of the source/drain metal layer 140 is removed by an etching process to obtain a ZnS/Ag/ZnS composite film layer structure for driving the pixel electrode 20, while the source 14/drain 15 remains.
  • ZnS/Ag/ZnS/Ag composite film layer structure is obtained by an etching process.
  • This embodiment also provides a display device using the above array substrate.
  • Example 5
  • the thin film crystal in the array substrate is compared with any of the embodiments 1-4 in this embodiment.
  • the body tube is still a bottom gate type structure, and the driving electrode still includes a common electrode and a pixel electrode.
  • the source/drain and the pixel electrode are formed of the same material, and the thickness of the pixel electrode is smaller than the thickness of the source/drain; and the gate and the common electrode are formed of the same material, and The thickness of the common electrode is smaller than the thickness of the gate.
  • the gate and the common electrode are formed in the same manner as in Embodiment 1 or 2.
  • the source/drain and the pixel electrode are formed in the same manner as in Embodiment 3 or 4, and the gate insulating layer is formed.
  • the formation manner of the active layer and the passivation layer is the same as that of the prior art in which the gate insulating layer, the active layer and the passivation layer are formed, and details are not described herein again.
  • the transmittance of the pixel electrode ranges from 30 to 90%.
  • the thickness of the pixel electrode ranges from 1 to 10 1 00 A
  • the thickness ranges from 1 0 to 0 000
  • the transmittance of the common electrode ranges from 30 to 90%.
  • the common electrode is made of aluminum
  • the thickness ranges from 1 0-1 00 A.
  • the thickness ranges from 1 0 to 0 000. people.
  • This embodiment also provides a display device using the above array substrate.
  • the gate electrode and the common electrode are made of the same material and are prepared by a patterning process using a halftone mask or a gray tone mask, and the thickness of the common electrode is smaller than the thickness of the gate electrode, and
  • the source/drain and the pixel electrode are made of the same material and are prepared by one patterning process using a halftone mask or a gray tone mask, and the thickness of the pixel electrode is smaller than the thickness of the source/drain to ensure the common electrode.
  • the transmittance of the pixel electrode and the pixel electrode satisfy the display requirements of the ADSDS mode display device.
  • the embodiment reduces the number of patterning processes twice, effectively It simplifies the preparation process of the array substrate, reduces the cost of the mask plate and materials, reduces equipment investment, saves cost, improves productivity, and improves the competitiveness of the display device product.
  • Example 6
  • the film in the array substrate of this embodiment is compared with the first embodiment and the second embodiment.
  • the transistor is a top gate type structure
  • the driving electrode still includes a common electrode and a pixel electrode
  • the common electrode and the pixel electrode at least partially overlap in a right projection direction.
  • the gate, the source and the drain are in the lower layer as the source and the drain, the upper layer is the gate, and the second electrode is disposed below the first electrode.
  • the first electrode is a slit-shaped common electrode, and the second electrode is a plate-shaped pixel electrode.
  • the source/drain and the pixel electrode are formed of the same material, and the thickness of the pixel electrode is smaller than the thickness of the source/drain.
  • the upper surface of the base substrate 10 is an active layer 13 , a source 14 and a drain 15 provided in the same layer, a gate insulating layer 12 , and a gate 11 .
  • the pixel electrode 20 is disposed in the same layer as the source electrode 14 and the drain electrode 15 (the pixel electrode 20 is directly electrically connected to the drain electrode 15), and the common electrode 21 is disposed in the same layer as the gate electrode 11.
  • the source 14/drain 15 and the pixel electrode 20 are formed of the same material and in the same patterning process.
  • the source 14/drain 15 may be 4 Lu (A1), 4 (Cu), (Mo), 4 Lu 4 female alloy (AlNd), 4 (Cr), Titanium (Ti) or silver.
  • the multilayer composite film layer is obtained by thinning by an etching process.
  • the pixel electrode 20 has a thickness ranging from 10 to 100 A and a transmittance ranging from 30 to 90%.
  • the source 14/drain 15 is a ZnS/Ag/ZnS/Ag or ITO/Ag/ITO/Ag composite film layer structure, and preferably each film layer has a thickness of 400 A /180 A /400 A /2000 A, respectively.
  • the pixel electrode 20 is a ZnS/Ag/ZnS or ITO/Ag/ITO composite film layer structure, and preferably each film layer has a thickness of 400 A / 180 A / 400 k, respectively.
  • this embodiment also provides a display device in the ADSDS mode.
  • Example 7 Similar to Embodiments 1 and 2, this embodiment also provides a display device in the ADSDS mode.
  • the film in the array substrate of the embodiment is compared with the embodiment.
  • the transistor is a top gate type structure
  • the driving electrode still includes a common electrode and a pixel electrode
  • the common electrode and the pixel electrode at least partially overlap in a right projection direction.
  • the gate, the source and the drain are in the lower layer as the source and the drain, the upper layer is the gate, and the second electrode is disposed below the first electrode.
  • the first electrode is a slit-shaped common electrode, and the second electrode is a plate-shaped pixel electrode.
  • the gate electrode and the common electrode are formed of the same material, and the thickness of the common electrode is smaller than the thickness of the gate electrode.
  • the upper surface of the base substrate 10 is an active layer 13 , a source 14 and a drain 15 provided in the same layer, a gate insulating layer 12 , and a gate 11 .
  • the pixel electrode 20 is disposed in the same layer as the source electrode 14 and the drain electrode 15 (the pixel electrode 20 is directly electrically connected to the drain electrode 15), and the common electrode 21 is disposed in the same layer as the gate electrode 11.
  • the common electrode 21 and the gate electrode 11 are formed of the same material and in the same patterning process.
  • the gate electrode 11 may be a single layer metal formed of aluminum (A1), copper (Cu), molybdenum (Mo), aluminum-niobium alloy (AlNd), chromium (Cr), titanium (Ti) or silver (Ag). a film layer or a multilayer composite film layer composed thereof, and the common electrode 21 may be thinned by an etching process using a single metal film layer of the same material as that of the gate electrode 11 or a multilayer composite film layer composed of the same obtain.
  • the thickness of the common electrode 21 ranges from 10 to 100 persons, and the transmittance ranges from 30 to 90%.
  • the gate electrode 11 is a ZnS/Ag/ZnS/Ag or ITO/Ag/ITO/Ag composite film layer structure, and preferably each film layer has a thickness of 400 persons/180 persons/400 persons/2000 A, and the common electrode 21 is For the ZnS/Ag/ZnS or ITO/Ag/ITO composite film layer structure, it is preferred that the thickness of each film layer be 400 A /180 A /400 k, respectively.
  • this embodiment also provides a display device in the ADSDS mode.
  • the thin film transistor in the array substrate is a top gate type structure, and the driving electrode still includes a common electrode and a pixel electrode.
  • the source/drain and the pixel electrode are formed of the same material, and the thickness of the pixel electrode is smaller than the thickness of the source/drain, and the gate and the common electrode are formed of the same material, and are common.
  • the thickness of the electrode is less than the thickness of the gate.
  • the upper surface of the base substrate 10 is an active layer 13, a source 14 and a drain 15 disposed in the same layer, a gate insulating layer 12, and a gate electrode 11, wherein
  • the pixel electrode 20 is disposed in the same layer as the source electrode 14 and the drain electrode 15 (the pixel electrode 20 is directly electrically connected to the drain electrode 15), and the common electrode 21 is disposed in the same layer as the gate electrode 11.
  • the source/drain and the pixel electrode are formed in the same manner as in the sixth embodiment.
  • the gate and the common electrode are formed in the same manner as in the seventh embodiment, and the gate insulating layer, the active layer and the passivation layer are formed.
  • the manner of forming the gate insulating layer, the active layer and the passivation layer is the same as that in the prior art, and details are not described herein again.
  • this embodiment also provides a display device in the ADSDS mode.
  • Example 9 Similar to Embodiments 6 and 7, this embodiment also provides a display device in the ADSDS mode.
  • the thin film transistor in the array substrate is a bottom gate type structure, and the driving electrode still includes the common electrode and the pixel electrode.
  • the gate electrode and the pixel electrode are formed of the same material, and the thickness of the pixel electrode is smaller than the thickness of the gate electrode.
  • the upper surface of the substrate substrate 10 is sequentially a gate electrode 11 , a gate insulating layer 12 , and an active layer 13 (as seen in FIG. 11 , active
  • the layer 13 is a two-layer sub-layer structure)
  • the source electrode 14 and the drain electrode 15 are disposed in the same layer
  • the pixel electrode 20 is disposed in the same layer as the gate electrode 11 (the pixel electrode 20 is electrically connected through the pixel electrode connection line 23 and the drain electrode 15) Connect).
  • the pixel electrode connection line 23 for connecting the pixel electrode 20 and the drain electrode 15 is formed of the same material as the common electrode 21 and formed in the same patterning process, and is used for the common electrode connected to the common electrode 21.
  • the line 22 is formed of the same material as the gate electrode 11 and the pixel electrode 20, and is formed in the same patterning process.
  • the manner in which the gate and the pixel electrode are formed can be referred to the embodiment 1-5.
  • the manner in which the middle gate and the common electrode are formed, and the manner in which the common electrode, the gate insulating layer, the active layer, and the passivation layer are formed, and the manner in which the common electrode, the gate insulating layer, the active layer, and the passivation layer are formed in the prior art The same, no longer repeat here.
  • this embodiment also provides a display device in the ADSDS mode.
  • Example 10
  • the difference between this embodiment and any of the embodiments 1-9 is that the thin film transistor in the array substrate of the embodiment is of a bottom gate type, and the driving electrode includes only the first electrode, and the first electrode is the pixel electrode.
  • the upper surface of the base substrate 10 is a gate electrode 11, a gate insulating layer 12, an active layer 13, and a source electrode 14 and a drain electrode 15 disposed in the same layer.
  • the pixel electrode 20 is disposed in the same layer as the source 14/drain 15 (the pixel electrode 20 is directly electrically connected to the drain 15).
  • the source/drain in the upper layer is formed of the same material as the pixel electrode, and the thickness of the pixel electrode is smaller than the thickness of the source/drain, and the pixel electrode is electrically connected to the drain, and the pixel electrode
  • the transmission range is 30-90%.
  • the source/drain and the pixel electrode are single-layer or multi-layer composite film layers, and are formed of aluminum, copper, molybdenum, aluminum-bismuth alloy, chromium, titanium or silver, or source/drain
  • the pixel electrode is a multilayer composite film layer having a one-dimensional metal/dielectric photonic crystal structure, the metal includes silver, and the medium includes sulfurized or indium tin oxide.
  • the source/drain and the pixel electrode are simultaneously formed by the same patterning process.
  • a specific preparation method reference may be made to the method of preparing the source/drain and the pixel electrode of the array substrate in any one of Embodiments 3-5.
  • the gate, the gate insulating layer, the active layer, and the passivation layer are formed in the same manner as the gate, the gate insulating layer, the active layer, and the passivation layer in the prior art, and are not described herein again. .
  • This embodiment also provides a display device using the above array substrate.
  • the display device can be a TN (Twisted Nematic) LCD, a VA (Vertical Alignment) mode LCD, or an OLED display.
  • TN Transmission Nematic
  • VA Very Alignment
  • OLED OLED
  • the difference between this embodiment and the embodiment 10 is that the thin film transistor in the array substrate of the present embodiment is of a top gate type, and the driving electrode includes only the first electrode, and the first electrode is a pixel electrode.
  • the upper side of the base substrate 10 is an active layer 13 , a source 14 and a drain 15 disposed in the same layer, and a gate insulating layer 1 2 . 1 , wherein the pixel electrode 20 is disposed in the same layer as the source 14 / the drain 1 5 , and the pixel electrode 20 is directly electrically connected to the drain 15 .
  • the source/drain in the opposite layer is formed of the same material as the pixel electrode, and the thickness of the pixel electrode is smaller than the thickness of the source/drain, and the pixel electrode is directly electrically connected to the drain, and the pixel
  • the transmittance of the electrode ranges from 30 to 90%.
  • the source/drain and the pixel electrode are single-layer or multi-layer composite film layers, and are formed of aluminum, copper, molybdenum, aluminum-bismuth alloy, chromium, titanium or silver, or source/drain
  • the pixel electrode is a multilayer composite film layer having a one-dimensional metal/dielectric photonic crystal structure, the metal includes silver, and the medium includes sulfurized or indium tin oxide.
  • the source/drain and the pixel electrode are simultaneously formed by the same patterning process.
  • a specific preparation method reference may be made to the method of preparing the source/drain and pixel electrodes of the array substrate in Embodiment 6 or 8.
  • the gate, the gate insulating layer, the active layer, and the passivation layer are formed in the same manner as the gate, the gate insulating layer, the active layer, and the passivation layer in the prior art, and are not described herein again. .
  • This embodiment also provides a display device using the above array substrate.
  • the pixel electrode or the common electrode is formed of the same material as the gate or source/drain electrodes in the thin film transistor, and the pixel electrode is simultaneously formed by the same patterning process in the method of fabricating the array substrate. Or a common electrode and a gate or a source/drain in the thin film transistor, and through a thinning process, so that the pixel electrode or the common electrode satisfies the transmittance, compared to the preparation process of the array substrate in the prior art. At least one patterning process is reduced, which effectively simplifies the preparation process of the array substrate, reduces the cost of the mask and materials, reduces equipment investment, saves cost, increases productivity, and improves the competitiveness of the display device product.

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Abstract

一种阵列基板及其制备方法和显示装置，所述阵列基板包括衬底基板（10）以及设置于所述衬底基板（10）上的薄膜晶体管和至少一个驱动电极（20，21），所述薄膜晶体管包括栅极（11）以及设置在同一层的源极（14）和漏极（15），其中，所述栅极（11）、所述源极（14）或所述漏极（15）与所述至少一个驱动电极（20，21）采用相同的材料形成，且其厚度大于所述至少一个驱动电极（20，21）的厚度。所述阵列基板，在满足透过率的同时，简化了阵列基板的制备工艺，降低了掩模板和材料的成本，减少了设备投资，节约了成本，提高了产能。

Description

阵列基板及其制备方法、 显示装置
技术领域
本发明属于显示技术领域，具体涉及阵列基板及其制备方法、 显示装置。 背景技术
平板显示装置具有体积小、 功耗低、 无辐射等特点， 目前已 逐步取代笨重的 CRT (Cathode Ray Tube ，阴极射线管）显示装置 而占据了显示器市场的主导地位。 常用的平板显示装置包括 LCD
( Liquid Crystal Display:液晶显示装置 )、 PDP( Plasma Display Panel:等离子显示装置）和 OLED ( Organic Light-Emitting Diode: 有机发光二极管）显示装置。
在成像过程中， LCD和有源矩阵驱动式 OLED ( Active Matrix Organic Light Emission Display, 简称 AMOLED) 显示装置中的 每一像素都由集成在阵列基板中的薄膜晶体管 （ Thin Film Transistor: 简称 TFT)来驱动， 从而实现图像显示。 薄膜晶体管 作为发光控制开关， 是实现 LCD和 0LED显示装置显示的关键， 直 接关系到高性能显示装置的发展方向。
其中， LCD包括 TN ( Twisted Nematic, 扭曲向列）模式、 VA
( Vertical Alignment, 垂直取向 )模式、 ADSDS ( ADvanced Super Dimension Switch, 简称 ADS， 高级超维场转换）模式等。 尤其是 在 ADSDS模式中， 阵列基板同时包括像素电极和公共电极， 通过 同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电 极层间产生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极 正上方的所有取向的液晶分子都能够产生旋转， 在增大视角的同 时提高了液晶分子的工作效率并增大了透光效率。
其中， 薄膜晶体管主要包括栅极、 栅绝缘层、 有源层、 源极 和漏极。 图 1是现有技术中的一种 ADSDS模式的阵列基板的剖视 图， 在该阵列基板的制备过程中， 自下而上分别通过 5 次构图工 艺 （或者说掩模工艺） 制备完成， 依次包括： 公共电极掩模、 栅 极掩模、 有源层和源极 /漏极掩模、 钝化层过孔掩模、 像素电极掩 模。 在该阵列基板中， 公共电极和栅极分别釆用透明导电材料和 金属材料， 通过两次构图工艺形成。
图 2是现有技术中的另一种 ADSDS模式的阵列基板的剖视图， 在该阵列基板的制备过程中， 自下而上分别通过 6次构图工艺（或 者说掩模工艺） 制备完成， 依次包括： 栅极掩模、 有源层掩模、 源极 /漏极掩模、像素电极掩模、钝化层过孔掩模、公共电极掩模。 在该阵列基板中， 源极 /漏极和像素电极分别釆用金属材料和透明 导电材料， 通过两次构图工艺形成。
在上述两种结构的阵列基板中， 公共电极和栅极、 源极 /漏极 和像素电极均通过两次掩模工艺完成， 工艺相对复杂， 成本较高。 同样的， 在 TN模式、 VA模式和 0LED显示装置的阵列基板的制备 过程中也存在同样的问题。 发明内容 足， 提供一种阵列基板及其制备方法、 显示装置， 该阵列基板和 相应的阵列基板的制备方法有效地简化了阵列基板的制备工艺， 降低了掩模板和材料的成本， 减少了设备投资， 节约了制造成本， 提高了产能， 提高了显示装置产品的竟争力。
解决本发明所要解决的技术问题所釆用的技术方案是一种阵 列基板， 其包括衬底基板以及设置于所述衬底基板上的薄膜晶体 管和至少一个驱动电极， 所述薄膜晶体管包括栅极以及设置在同 一层的源极 /漏极， 其中， 所述栅极或所述源极 /所述漏极与所述 至少一个驱动电极中的一个驱动电极为釆用相同的材料形成的膜 层， 且其厚度大于所述一个驱动电极的厚度。
一种优选方案是， 所述至少一个驱动电极包括第一电极与第 二电极， 所述第一电极与所述第二电极在正投影方向上至少部分 重叠， 所述第二电极设置于所述第一电极的下方， 所述栅极和所 述源极 /所述漏极中处于上层的电极、 与所述第一电极釆用相同的 材料形成的膜层， 且所述第一电极的厚度小于该电极的厚度； 和 / 或， 所述栅极和所述源极 /所述漏极中处于下层的电极、 与所述第 二电极为釆用相同的材料形成的膜层， 且所述第二电极的厚度小 于该电极的厚度。
优选的是， 釆用相同的材料形成的膜层为釆用铝、 铜、 钼、 铝钕合金、 铬、 钛或银形成的单层或多层复合膜层。
在这种情况下， 所述至少一个驱动电极的透过率范围为
30-90% , 厚度范围为 100-1000人。
优选的是，釆用相同的材料形成的膜层为具有一维金属 I介质 光子晶体结构的多层复合膜层， 所述金属包括银， 所述介质包括 石克化辞或氧化铟锡。
在这种情况下， 所述至少一个驱动电极的透过率范围为 30-90% , 厚度范围为 100-1000人。
优选的是， 所述第一电极为狭缝状的像素电极， 所述第二电 极为板状的公共电极， 所述像素电极与所述漏极电连接； 或者， 所述第一电极为狭缝状的公共电极， 所述第二电极为板状的像素 电极， 所述像素电极与所述漏极电连接。
一种优选方案是， 所述驱动电极包括像素电极， 所述源极 / 所述漏极、 与所述像素电极为釆用相同的材料形成的膜层， 且所 述像素电极的厚度小于所述源极 /所述漏极的厚度。
优选的是， 釆用相同的材料形成的膜层为釆用铝、 铜、 钼、 铝钕合金、 铬、 钛或银形成的单层或多层复合膜层。
在这种情况下， 所述像素电极与所述漏极电连接， 所述像素 电极的透过率范围为 30-90%， 厚度范围为 10-100A。
优选的是，釆用相同的材料形成的膜层为具有一维金属 I介质 光子晶体结构的多层复合膜层， 所述金属包括银， 所述介质包括 石克化辞或氧化铟锡。
在这种情况下， 所述像素电极与所述漏极电连接， 所述像素 电极的透过率范围为 30_90%， 厚度范围为 100-1000人。 一种显示装置， 包括上述的阵列基板。
一种阵列基板的制备方法， 包括在衬底基板上形成薄膜晶体 管和至少一个驱动电极的步骤， 所述薄膜晶体管包括栅极以及设 置在同一层的源极 /漏极， 其中， 所述栅极和所述源极 /所述漏极 中的一个与所述至少一个驱动电极中的一个驱动电极通过同一构 图工艺形成、 且为釆用相同的材料形成的膜层， 且其厚度大于所 述一个驱动电极的厚度。
优选的是，所述栅极和所述源极 /所述漏极中的一个与所述至 少一个驱动电极中的一个驱动电极通过同一构图工艺形成包括如 下步骤：
步骤 S1 : 形成金属电极层；
步骤 S2 : 在所述金属电极层的上方形成光刻胶层；
步骤 S 3: 釆用半色调掩模板或灰色调掩模板， 对所述光刻胶 层进行曝光、 显影工艺， 将对应着形成所述栅极和所述源极 /所述 漏极中的所述一个的区域的光刻胶完全保留， 对应着形成所述一 个驱动电极的区域的光刻胶部分保留， 其余区域的光刻胶完全去 除；
步骤 S4 : 对所述金属电极层进行第一次刻蚀工艺， 将对应着 形成所述栅极和所述源极 /所述漏极中的所述一个的区域和对应 着形成所述一个驱动电极的区域以外的金属电极材料去除；
步骤 S5 : 对所述光刻胶层进行减薄处理， 将对应着形成所述 栅极和所述源极 /所述漏极中的所述一个的区域的光刻胶部分保 留， 对应着形成所述一个驱动电极的区域的光刻胶完全去除； 步骤 S6 : 对所述金属电极层进行第二次刻蚀工艺， 将对应着 形成所述一个驱动电极的区域的金属电极材料部分去除， 形成包 括所述栅极和所述源极 /所述漏极中的所述一个和所述一个驱动 电极的图形；
步骤 S7 : 去除所述光刻胶层中剩余的光刻胶。
优选的是， 所述形成金属电极层的步骤包括釆用铝、 铜、 钼、 铝钕合金、 铬、 钛或银形成单层或多层复合膜层。 在这种情况下，所述形成包括所述栅极和所述源极 /所述漏极 中的所述一个和所述一个驱动电极的图形包括形成厚度范围为
10-100A, 透过率范围为 30-90%的所述一个驱动电极。
优选的是， 所述形成金属电极层的步骤包括形成具有一维金 属 /介质光子晶体结构的多层复合膜层， 所述金属包括银， 所述介 质包括¾化辞或氧化铟锡。
在这种情况下，所述形成包括所述栅极和所述源极 /所述漏极 中的所述一个和所述一个驱动电极的图形包括形成厚度范围为 100-1000人、 透过率范围为 30-90%的所述一个驱动电极。
进一步优选的是， 对所述光刻胶层进行减薄处理的步骤包括 通过灰化工艺对所述光刻胶层进行减薄处理。
优选的是， 所述至少驱动电极包括第一电极与第二电极， 所 述第一电极与所述第二电极在正投影方向上至少部分重叠， 所述 第二电极设置于所述第一电极的下方， 其中
所述栅极和所述源极 /所述漏极中的一个与所述至少一个驱 动电极中的一个驱动电极通过同一构图工艺形成的步骤包括： 通过同一构图工艺同时形成所述栅极和所述源极 /所述漏极 中处于上层的电极与所述第一电极； 和 /或
通过同一构图工艺同时形成所述栅极和所述源极 /所述漏极 中处于下层的电极与所述第二电极。
进一步优选的是， 所述第一电极为狭缝状的像素电极， 所述 第二电极为板状的公共电极， 所述像素电极与所述漏极电连接； 或者， 所述第一电极为狭缝状的公共电极， 所述第二电极为板状 的像素电极， 所述像素电极与所述漏极电连接。
优选的是， 所述驱动电极包括像素电极， 所述栅极和所述源 极 /所述漏极中的一个与所述至少一个驱动电极中的一个驱动电 极通过同一构图工艺形成的步骤包括：
通过同一构图工艺同时形成所述源极 /所述漏极与所述像素 电极， 所述像素电极与所述漏极电连接。
本发明的有益效果是： 本发明的阵列基板中， 所述栅极或所 述源极 /所述漏极与所述至少一个驱动电极中的一个驱动电极釆 用相同的材料形成， 其厚度大于所述一个驱动电极的厚度； 且所 述栅极或所述源极 /所述漏极与所述一个驱动电极通过同一构图 工艺形成， 在满足透过率的同时， 有效地简化了阵列基板的制备 工艺， 降低了掩模板和材料的成本， 减少设备投资， 节约了制造 成本， 提高了产能， 提高了显示装置产品的竟争力。 附图说明
图 1、 图 2为现有技术中的两种阵列基板的剖视图。
图 3为本发明的实施例 1中的阵列基板的剖视图。
图 4-1至图 4-6为图 3中的阵列基板的制备工艺示图， 其中：
图 4-1为形成有金属电极层的结构的剖视图；
图 4-2为对光刻胶层进行曝光、显影工艺后的结构的剖视图； 图 4-3为第一次刻蚀工艺后的结构的剖视图；
图 4-4为灰化工艺后的结构的剖视图；
图 4-5为第二次刻蚀工艺后的结构的剖视图；
图 4-6为剥离剩余的光刻胶后的结构的剖视图。
图 5为本发明的实施例 3中的阵列基板的剖视图。
图 6-1至图 6-7为图 5中的阵列基板的制备工艺示图， 其中：
图 6-1为形成金属电极层的结构的剖视图；
图 6-2为对光刻胶层进行曝光、显影工艺后的结构的剖视图； 图 6-3为第一次刻蚀工艺后的结构的剖视图；
图 6-4为灰化工艺后的结构的剖视图；
图 6-5为第二次刻蚀工艺后的结构的剖视图；
图 6-6为第三次刻蚀工艺后的结构的剖视图；
图 6-7为剥离剩余的光刻胶后的结构的剖视图。
图 7为本发明的实施例 5中的阵列基板的剖视图。
图 8为本发明的实施例 6中的阵列基板的剖视图。 图 9为本发明的实施例 7中的阵列基板的剖视图。 图 10为本发明的实施例 8中的阵列基板的剖视图。
图 11为本发明的实施例 9中的阵列基板的剖视图。
图 12为本发明的实施例 10中的阵列基板的剖视图。
图 13为本发明的实施例 11中的阵列基板的剖视图。
图 14为银（ Ag)膜的透过率与膜厚变化的曲线图。
图 15为一维金属-介质光子晶体结构的透过率与厚度变化的 曲线图。
附图标记： 10 -衬底基板； 11 -栅极； 110 -栅金属层； 111- 图案化的栅金属图形； 12 -栅绝缘层； 13-有源层； 14 -源极； 15- 漏极； 140-源漏金属层； 141-图案化的源漏金属图形； 16 -钝化 层； 19-光刻胶层； 20-像素电极； 21-公共电极； 22-公共电极线； 23-像素电极连接线。 具体实施方式
为使本领域技术人员更好地理解本发明的技术方案， 下面结 合附图和具体实施方式对本发明的阵列基板及其制备方法、 以及 显示装置作进一步详细描述。
本发明提供一种阵列基板， 其包括衬底基板以及设置于所述 衬底基板上的薄膜晶体管和至少一个驱动电极， 所述薄膜晶体管 包括栅极以及设置在同一层的源极 /漏极， 其中， 所述栅极或所述 源极 /所述漏极与所述至少一个驱动电极中的一个驱动电极釆用 相同的材料形成， 且其厚度大于所述一个驱动电极的厚度。 实施例 1:
本实施例提供一种阵列基板， 该阵列基板包括衬底基板以及 设置于衬底基板上的薄膜晶体管和作为驱动电极的第一电极和第 二电极， 薄膜晶体管包括栅极以及设置在同一层的源极 /漏极， 第 一电极与第二电极在正投影方向上至少部分重叠， 第二电极设置 于第一电极的下方。 在本实施例中， 薄膜晶体管为底栅型结构， 即在该薄膜晶体管中， 栅极、 源极与漏极中处于相对下层的为栅 极， 处于相对上层的为源极与漏极， 第一电极为狭缝状的像素电 极， 第二电极为板状的公共电极。
具体的， 如图 3所示， 该阵列基板中， 衬底基板 10的上方依 次为同层设置的栅极 11和公共电极 21、 栅绝缘层 12、 有源层 13 (从图 3中可见， 有源层 1 3为双层子膜层结构） 、 同层设置的源 极 14和漏极 15、 钝化层 16、 设置在钝化层 16的上方且通过钝化 层过孔与漏极 15 电连接的像素电极 20。 在本实施例中， 栅极 11 与公共电极 21釆用相同的材料形成， 且公共电极 21 的厚度小于 栅极 11的厚度。
优选的是， 栅极 11与公共电极 21为单层或多层复合膜层， 采用 4吕（ A1 ) 、 4同（ Cu ) 、 ] ( Mo ) 、 4吕 4女合金 ( AlNd ) , 4各（ Cr ) 、 钛（ T i )或银（ Ag )形成。其中，公共电极 21的厚度范围为 10-100A, 透过率范围为 30-90%。
相应的， 本实施例中的阵列基板的制备方法包括在衬底基板 上形成薄膜晶体管和作为驱动电极的像素电极和公共电极的步 骤， 薄膜晶体管包括栅极以及设置在同一层的源极 /漏极， 公共电 极设置于像素电极的下方， 其中， 处于相对下层的栅极与公共电 极釆用相同的材料、 通过同一构图工艺同时形成， 且公共电极的 厚度小于栅极的厚度。
在具体阐述之前， 应该理解的是， 本发明中， 构图工艺可只 包括光刻工艺， 或包括光刻工艺以及刻蚀步骤， 同时还可以包括 打印、 喷墨等其他用于形成预定图形的工艺， 光刻工艺是指包括 成膜、 曝光、 显影等工艺过程的利用光刻胶、 掩模板、 曝光机等 形成图形的工艺。 可根据本发明中所形成的结构选择相应的构图 工艺。
具体的， 如图 4-1至图 4-6所示， 栅极与公共电极通过同一 构图工艺同时形成具体包括如下步骤 S1至 S7。
步骤 SI : 形成金属电极层。
如图 4-1所示， 在该步骤中， 在衬底基板 10的上方形成金属 电极层，具体的，釆用沉积、溅射或蒸镀的方法形成栅金属层 110。 优选的是， 栅金属层 110 釆用铝 （A1 ) 、 铜 （Cu ) 、 钼 （Mo ) 、 铝钕合金（AlNd ) 、 铬 （Cr ) 、 钛（T i ) 或银（ Ag ) 形成， 本实 施例中的栅金属层 110优选釆用银（Ag ) 形成。
步骤 S2 : 在金属电极层的上方形成光刻胶层。
在该步骤中， 通过涂覆方式， 在栅金属层 110的上方形成光 刻胶层 19。
步骤 S 3: 釆用半色调掩模板或灰色调掩模板， 对光刻胶层进 行曝光、 显影工艺， 将对应着形成栅极的区域的光刻胶完全保留， 对应着形成公共电极的区域的光刻胶部分保留， 其余区域的光刻 胶完全去除。
如图 4-2所示， 在该步骤中， 釆用半色调掩模或灰色调掩模 对光刻胶层 19进行曝光， 使得光刻胶层 19 中不同区域的光刻胶 完全发生、 部分发生或不发生光固化反应， 经过显影工艺后， 光 刻胶层 19中对应着形成栅极的区域的光刻胶完全保留， 对应着形 成公共电极的区域的光刻胶部分保留， 其余区域的光刻胶完全去 除， 即在栅金属层 110 的上方形成不同区域厚度不同的光刻胶图 案。
步骤 S4 : 对金属电极层进行第一次刻蚀工艺， 将对应着形成 栅极的区域和对应着形成公共电极的区域以外的金属电极材料去 除。
如图 4-3所示， 在该步骤中， 通过第一次刻蚀工艺对未被光 刻胶保护部分的栅金属层 110进行刻蚀， 形成栅极 11 以及初具轮 廓的图案化的栅金属图形 111。 其中， 初具轮廓的图案化的栅金属 图形 111 在后续工艺过程中将形成公共电极以及公共电极线， 公 共电极用于驱动液晶旋转， 公共电极线用于为公共电极输入电信 号， 其与公共电极电连接。
步骤 S5 : 对光刻胶层进行减薄处理， 将对应着形成栅极和公 共电极线的区域的光刻胶部分保留， 对应着形成公共电极的区域 的光刻胶完全去除。 如图 4-4所示， 在该步骤中， 通过灰化工艺对光刻胶层 19进 行减薄， 去除部分光刻胶， 即去除光刻胶层 19中对应着形成用于 驱动的公共电极的部分光刻胶， 露出该部分对应的图案化的栅金 属图形 1 1 1 的部分区域， 而保留对应着形成用于与公共电极电连 接的公共电极线的部分光刻胶， 使其仍覆盖在该部分对应的图案 化的栅金属图形 1 1 1 的部分区域上。 当然， 对光刻胶的减薄并不 限于釆用灰化工艺， 其他具有同样减薄效果的减薄工艺也可以应 用在该步骤中， 本实施例对此不做限定。
步骤 S6 : 对金属电极层进行第二次刻蚀工艺， 将对应着形成 公共电极的区域的金属电极材料部分去除， 形成包括栅极和公共 电极的图形。
如图 4-5所示， 在该步骤中， 通过第二次刻蚀工艺对未被光 刻胶保护的栅金属层部分进行刻蚀， 具体的说是对露出的初具轮 廓的图案化的栅金属图形 1 1 1 中对应着形成用于驱动的公共电极 的部分进行刻蚀， 由于该部分的金属电极材料未被光刻胶覆盖而 露出， 通过对刻蚀工艺的参数进行控制， 使得该部分栅金属层的 厚度范围为 1 0-1 00人， 透过率范围为 30-90%， 也即形成了公共电 极 21 , 而在对应着形成用于与公共电极电连接的公共电极线的部 分， 由于仍被光刻胶覆盖着， 因此该部分金属电极材料的厚度仍 保持为栅金属层的厚度， 也即形成公共电极线 22， 公共电极线 22 的厚度与栅极 1 1 的厚度相同。 由于公共电极线 22相对公共电极 21具有更大的厚度， 因此能保证良好的导电性， 起到良好的电连 接作用。
步骤 S7 : 去除光刻胶层中剩余的光刻胶。
如图 4-6所示， 在该步骤中， 通过剥离工艺对剩余的所有光 刻胶进行剥离以将其完全去除。
至此， 即完成了本实施例中的公共电极和栅极的制备。
优选地， 本实施例中的栅极 1 1的厚度范围为 500-2000人， 减 薄后形成的公共电极 21 的厚度为 50人， 此时公共电极 21 的透过 率约为 90%。 当然， 在本实施例中， 栅极 1 1可以为釆用铝（ A 1 ) 、 铜 （ Cu ) 、 钼 （ Mo ) 、 铝钕合金 ( AlNd ) 、 铬 （ Cr ) 、 钛 （ T i ) 或银（Ag ) 形成的单层金属膜层或者由其构成的多层复合膜层， 而公共电极 21可以釆用上述与形成栅极相同的材料的单层金属膜 层或者由其构成的多层复合膜层通过刻蚀工艺减薄获得。
图 14 示出银（Ag )膜的透过率与膜厚变化的曲线图， 从图 14 中可见， 随着银（Ag )膜厚度的增加， 其透过率逐渐降低。 因 此， 在实际制备工艺中， 可根据工艺设备的制备条件和阵列基板 对光线透过率的设计要求， 从中取得较为均衡和合理的厚度范围。
另外， 本实施例在制备阵列基板的过程中， 还形成了数据线、 栅线（图 3、 图 4-1至图 4-6中均未示出） ， 数据线与栅线交叉设 置且将衬底基板 10划分为多个像素区域， 薄膜晶体管设置在像素 区 i或内。
如图 3所示， 本实施例中阵列基板的制备方法还包括： 在公 共电极 21与栅极 11上方形成栅绝缘层 12，在栅绝缘层 12上方形 成有源层 13， 在有源层 13上方形成源极 14/漏极 15， 在源极 14/ 漏极 15上方形成钝化层 16， 在钝化层 16上方形成像素电极 20 以使得像素电极 20与漏极 15 电连接。 在本实施例中， 公共电极 21为板状， 像素电极 20为狭缝状， 像素电极 20相对于公共电极 21设置在上方、 且与公共电极 21在正投影方向上至少部分重叠。
本实施例中， 栅绝缘层、 有源层、 源极 /漏极、 钝化层和像素 电极的形成与现有技术中栅绝缘层、 有源层、 源极 /漏极、 钝化层 和像素电极的形成相同， 这里不再赘述。
本实施例还提供一种釆用上述阵列基板的显示装置， 在该显 示装置中， 阵列基板中同时包括像素电极和公共电极， 即形成 ADSDS模式的显示装置。 该显示装置可以为： 液晶面板、 电子纸、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导 航仪等任何具有显示功能的产品或部件。
本实施例的阵列基板中， 栅极和公共电极釆用半色调掩模或 灰色调掩模通过一次构图工艺制备完成， 栅极和公共电极均釆用 相同的材料形成， 且公共电极的厚度小于栅极的厚度， 保证了公 共电极的透过率满足 ADSDS模式显示装置的显示要求。 相对于现 有技术中栅极、公共电极釆用不同材料、且通过两次构图工艺（或 者说掩模工艺）制备完成的方式， 本实施例减少了一次构图工艺， 有效地简化了阵列基板的制备工艺， 降低了掩模板和材料的成本， 减少了设备投资， 节约了成本， 提高了产能， 提高了显示装置产 品的竟争力。 实施例 2:
本实施例与实施例 1的区别在于， 在本实施例中， 参考图 3， 栅极 11、 公共电极 21釆用具有一维金属 /介质光子晶体结构的多 层复合膜层形成，其中，金属包括银 g)，介质包括硫化辞（ZnS ) 或氧化铟锡 ( Indium Tin Oxide, 简称 ITO ) ， 公共电极 21的厚 度范围为 100-1000人。
在本实施例中， 栅极 11为 ZnS/Ag/ZnS/Ag或 ITO/Ag/ ITO/Ag 复合膜层结构， 其中， 硫化辞的厚度范围为 200-800人， 氧化铟锡 的厚度范围为 200-800人，处于内层的金属银的厚度范围为 50-200 A, 处于外层的金属银的厚度范围为 500-2000 A, 例如， 结构 ZnS/Ag/ZnS/Ag 中各膜层的厚度分别为 400 A/180 A /400 A /2000 A，相应的，公共电极 21的结构为 ZnS/Ag/ZnS或 ITO/Ag/ITO 复合膜层结构，例如，结构 ZnS/Ag/ZnS中各膜层的厚度分别为 400 A /180 A /400 人。
相应的， 该阵列基板的制备方法中 ， 以栅极 11 为 ZnS/Ag/ZnS/Ag结构为示例， 在步骤 S1中， 形成栅金属层 110时， 在衬底基板 10的上方分别依次形成 ZnS/Ag/ZnS/Ag各膜层， 上述 的多层复合膜层即栅金属层 110。 具体的， 釆用沉积、 溅射或蒸镀 的方法形成 ZnS/Ag/ZnS/Ag各膜层。
在步骤 S6中， 通过刻蚀工艺去除栅金属层 110表层的 Ag膜 层， 以获得用于驱动液晶旋转的公共电极 21， 并保证公共电极 21 的透过率， 公共电极 21为 ZnS/Ag/ZnS复合膜层结构， 而栅极 11 和公共电极线 11保持 ZnS/Ag/ZnS/Ag复合膜层结构。 本实施例中阵列基板的其他结构与实施例 1相同， 这里不再 赘述。
在本实施例中，公共电极在釆用上述 ZnS/Ag/ZnS复合膜层结 构时， 在可见光范围内的透过率曲线如图 15所示， 最大透过率接 近 90%(λ=550ηπι)。
本实施例还提供一种釆用上述阵列基板的显示装置。 实施例 3:
本实施例与实施例 1相比， 阵列基板中的薄膜晶体管仍为底 栅型结构， 驱动电极仍包括第一电极和第二电极， 第二电极设置 于第一电极的下方， 其中第一电极为狭缝状的公共电极， 第二电 极为板状的像素电极。 在本实施例中， 源极 /漏极与像素电极釆用 相同的材料形成， 且像素电极的厚度小于源极 /漏极的厚度。
如图 5所示， 本实施例的阵列基板包括， 形成于衬底基板 10 上方的栅极 11， 形成于栅极 11上方的栅绝缘层 12， 形成在栅绝 缘层 12上方的有源层 13， 形成在有源层 13上方的源极 14/漏极 15和像素电极 20 (像素电极 20直接与漏极 15电连接） ， 形成在 源极 14/漏极 15和像素电极 20上方的钝化层 16， 形成在钝化层 16上方的公共电极 21。 在本实施例中， 像素电极 20为板状， 公 共电极 21为狭缝状，且公共电极 21相对设置在像素电极 20上方、 且与像素电极 20在正投影方向上至少部分重叠。
相应的， 本实施例中阵列基板的制备方法中， 源极 14/漏极 15与像素电极 20釆用相同的材料、 通过同一构图工艺同时形成， 且像素电极 20的厚度小于源极 14/漏极 15的厚度。
具体的， 如图 6-1至图 6-7所示， 源极 14/漏极 15与像素电 极 20通过同一构图工艺同时形成具体包括如下步骤 S1至 S7。
步骤 SI: 形成金属电极层。
如图 6-1所示， 此时， 阵列基板中已制备形成栅极 11、 栅绝 缘层 12 以及有源层 13。 在该步骤中， 在有源层 13的上方形成金 属电极层， 具体的， 釆用沉积、 溅射或蒸镀的方法形成源漏金属 层 140。 优选的是， 源漏金属层 140釆用铝（A 1 ) 、 铜 （Cu ) 、 钼 ( Μο ) , 铝钕合金 （ A lNd ) 、 铬（ Cr ) 、 钛 （ T i ) 或银 （ Ag ) 形 成， 本实施例中的源漏金属层优选釆用银（Ag ) 形成。
步骤 S2 : 在金属电极层的上方形成光刻胶层。
在该步骤中， 通过涂覆方式， 在源漏金属层 140的上方形成 光刻胶层 19。
步骤 S 3 : 釆用半色调掩模板或灰色调掩模板， 对光刻胶层进 行曝光、 显影工艺， 将对应着形成源极 /漏极的区域的光刻胶完全 保留， 对应着形成像素电极的区域的光刻胶部分保留， 其余区域 的光刻胶完全去除。
如图 6-2所示， 在该步骤中， 釆用半色调掩模或灰色调掩模 对光刻胶层 1 9进行曝光， 使得光刻胶层 19 中不同区域的光刻胶 完全发生、 部分发生或不发生光固化反应， 经过显影工艺后， 光 刻胶层 19 中对应着形成源极 /漏极的区域的光刻胶完全保留， 对 应着形成像素电极的区域的光刻胶部分保留， 其余区域的光刻胶 完全去除， 即在源漏金属层 140 的上方形成不同区域厚度不同的 光刻胶图案。
步骤 S4 : 对金属电极层进行第一次刻蚀工艺， 将对应着形成 源极 /漏极的区域和对应着形成像素电极的区域以外的金属电极 材料去除。
如图 6-3所示， 在该步骤中， 通过第一次刻蚀工艺对未被光 刻胶保护的源漏金属层 140进行刻蚀， 形成初具轮廓的图案化的 源漏金属图形 141。初具轮廓的图案化的源漏金属图形 141在后续 工艺过程中将形成像素电极以及源极 /漏极， 而且， 经过第一次刻 蚀工艺， 有源层 1 3 上方对应着源极 /漏极的区域的图案化的源漏 金属图形 141 已经形成沟槽或间隙， 后续形成的源极和漏极将分 布于该沟槽或间隙的相对两侧。
步骤 S5 : 对光刻胶层进行减薄处理， 将对应着形成源极 /漏 极的区域的光刻胶部分保留， 对应着形成像素电极的区域的光刻 胶完全去除。 如图 6-4所示， 在该步骤中， 通过灰化工艺对光刻胶进行减 薄， 例如釆用气体直接进行等离子体处理， 去除部分保留的光刻 胶， 即去除光刻胶层 19中对应着形成像素电极的部分光刻胶， 露 出该部分对应的图案化的源漏金属图形 141 的部分区域， 而保留 用于形成源极 /漏极的部分光刻胶， 使其仍覆盖在该部分对应的图 案化的源漏金属图形 141 的部分区域。 同样， 对光刻胶的减薄并 不限于釆用灰化工艺， 其他具有同样减薄效果的减薄工艺也可以 应用在该步骤中， 本实施例对此不做限定。
步骤 S6: 对金属电极层进行第二次刻蚀工艺， 将对应着形成 驱动电极的区域的金属电极材料部分去除， 形成包括源极 /漏极和 像素电极的图形。
如图 6-5所示， 在该步骤中， 通过第二次刻蚀工艺对未被光 刻胶保护 （即覆盖） 的源极 /漏极部分进行刻蚀， 对刻蚀工艺的参 数进行控制， 直至形成像素电极 20， 像素电极 20 的厚度范围为 10-100A, 透过率范围为 30_90%。
为了进一步形成被限制在源极和漏极之间的导电区域（即形 成薄膜晶体管在栅压作用下开启时源极和漏极之间的间隙相对应 的半导体部分） ， 在本实施例中， 在形成像素电极 20之后还进一 步包括第三次刻蚀工艺， 如图 6-6 所示， 通过干法刻蚀对有源层 13中对应着图案化的源漏金属图形 141中的沟槽或间隙区域进行 n+刻蚀（图 6-1至图 6-7中的有源层 13的结构可以与现有技术中 的有源层的结构相同， 均为双层子膜层结构） ， 形成真正意义上 的源极 14/漏极 15， 像素电极 20与漏极 15直接电连接。
步骤 S7: 去除光刻胶层中剩余的光刻胶。
如图 6-7所示， 在该步骤中， 通过剥离工艺对剩余的所有光 刻胶进行剥离以将其完全去除。
至此， 即完成了本实施例中源极 14/漏极 15以及像素电极 20 的制备。
优选地， 本实施例中源极 14/漏极 15 的厚度范围为 500-2000人， 减薄后的像素电极 20的厚度为 50人， 此时像素电极 20的透过率约为 90%。 在本实施例中， 源极 14 /漏极 15可以为釆 用铝（ A 1 ) 、 铜（ Cu ) 、 相（ Mo ) 、 铝钕合金 ( A l Nd ) 、 铬（ Cr ) 、 钛 （T i ) 或银（ Ag ) 形成的单层金属膜层或者由其构成的多层复 合膜层，而像素电极 20可以釆用上述与形成源极 14/漏极 15相同 材料的单层金属膜层或者由其构成的多层复合膜层通过刻蚀工艺 减薄获得。
另外， 如图 5所示， 本实施例中阵列基板的制备方法还包括： 在源极 14 /漏极 15以及像素电极 20上方形成钝化层 16， 以及在 钝化层 16上方形成公共电极 21以使得公共电极 21通过栅绝缘层 1 2中的过孔和钝化层 16中的过孔与公共电极线 22电连接。 在本 实施例中， 像素电极 20为板状， 公共电极 21 为狭缝状， 公共电 极 21相对设置于像素电极 20的上方、 且与像素电极 20在正投影 方向上至少部分重叠。
本实施例中， 栅极、 栅绝缘层、 有源层、 钝化层和公共电极 的形成与现有技术中栅极、 栅绝缘层、 有源层、 钝化层和公共电 极的形成相同， 这里不再赘述。
与实施例 1相同， 本实施例还提供一种 ADSDS模式的显示装 置。 实际上， 本实施例为实施例 1 的一种变型， 在 ADSDS模式的 显示装置中， 阵列基板中的像素电极可以为板状也可以为狭缝状， 相应的，公共电极可以为狭缝状也可以为板状。 ADSDS模式的显示 装置具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低 色差、 无挤压水波纹（ pus h Mura )等优点， 具有较好的画面品质。
本实施例的阵列基板中， 源极 /漏极以及像素电极釆用半色调 掩模或灰色调掩模通过一次构图工艺制备完成， 源极 /漏极以及像 素电极均釆用相同的材料形成， 且像素电极的厚度小于源极 /漏极 的厚度， 保证了像素电极的透过率满足 ADSDS模式显示装置的显 示要求。 相对于现有技术中源极 /漏极、 像素电极釆用不同材料、 且通过两次构图工艺制备完成的方式， 本实施例减少了一次构图 工艺， 有效地简化了阵列基板的制备工艺， 降低了掩模板和材料 的成本， 减少了设备投资， 节约了成本， 提高了产能， 提高了显 示装置产品的竟争力。 实施例 4:
本实施例与实施例 3的区别在于， 在本实施例中， 参考图 5， 源极 14/漏极 15、 像素电极 20釆用具有一维金属 /介质光子晶体 结构的多层复合膜层形成， 其中， 金属包括银（Ag ) ， 介质包括 硫化辞 （ZnS ) 或氧化铟锡 （ IT0) ， 像素电极 20 的厚度范围为 100- 1000人。
在本实施例中， 源极 14/漏极 15的结构为 ZnS/Ag/ZnS/Ag或 ITO/Ag/ITO/Ag 复合膜层结构， 其中， 硫化辞的厚度范围为 200-800人， 氧化铟锡的厚度范围为 200-800 A, 处于内层的金属 银的厚度范围为 50-200 A, 处于外层的金属银的厚度范围为 500-2000 A, 例如， 结构 ZnS/Ag/ZnS/Ag中各膜层的厚度分别为 400 A /180 A /400 A /2000 A, 相应的， 像素电极 20 的结构 为 ZnS/Ag/ZnS 或 ITO/Ag/ITO 复合膜层结构， 例如， 结构 ZnS/Ag/ZnS中各膜层的厚度分别为 400 A /180 A /400 k。
相应的， 该阵列基板的制备方法中， 以源极 14/漏极 15 为 ZnS/Ag/ZnS/Ag结构为示例， 在步骤 S1 中， 形成源漏金属层 140 时， 在有源层 13的上方分别依次形成 ZnS/Ag/ZnS/Ag各膜层， 上 述的多层复合膜层即源漏金属层 140。 具体的， 釆用沉积、 溅射或 蒸镀的方法形成 ZnS/Ag/ZnS/Ag各膜层。
在步骤 S6 中， 通过刻蚀工艺去除源漏金属层 140表层的 Ag 膜层， 以获得用于驱动的像素电极 20的 ZnS/Ag/ZnS复合膜层结 构， 而源极 14/漏极 15保持 ZnS/Ag/ZnS/Ag复合膜层结构。
本实施例中阵列基板的其他结构与实施例 3相同， 这里不再 赘述。
本实施例还提供一种釆用上述阵列基板的显示装置。 实施例 5:
本实施例与实施例 1-4 中任一个相比， 阵列基板中的薄膜晶 体管仍为底栅型结构， 驱动电极仍包括公共电极和像素电极。 在 本实施例中， 源极 /漏极与像素电极釆用相同的材料形成， 且像素 电极的厚度小于源极 /漏极的厚度； 并且， 栅极与公共电极釆用相 同的材料形成， 且公共电极的厚度小于栅极的厚度。
如图 7所示， 本实施例中， 栅极与公共电极的形成方式与实 施例 1或 2相同， 源极 /漏极与像素电极的形成方式与实施例 3或 4相同， 而栅绝缘层、有源层和钝化层的形成方式与现有技术中栅 绝缘层、 有源层和钝化层的形成方式相同， 这里不再赘述。
本实施例中， 像素电极的透过率范围为 30-90%， 当像素电极 釆用铝、 铜、 钼、 铝钕合金、 铬、 钛或银形成时， 像素电极的厚 度范围为 1 0-1 00 A, 当像素电极釆用一维金属 /介质光子晶体形 成时， 厚度范围为 1 00-1 000人， 并且， 公共电极的透过率范围为 30-90% , 当公共电极釆用铝、 铜、 钼、 铝钕合金、 铬、 钛或银形 成时， 厚度范围为 1 0-1 00 A , 当公共电极釆用一维金属 /介质光 子晶体形成时， 厚度范围为 1 00-1 000 人。
本实施例还提供一种釆用上述阵列基板的显示装置。
本实施例的阵列基板中， 栅极与公共电极釆用相同的材料且 釆用半色调掩模或灰色调掩模通过一次构图工艺制备完成， 且公 共电极的厚度小于栅极的厚度， 并且， 源极 /漏极与像素电极釆用 相同的材料且釆用半色调掩模或灰色调掩模通过一次构图工艺制 备完成， 且像素电极的厚度小于源极 /漏极的厚度， 保证了公共电 极和像素电极的透过率满足 ADSDS模式显示装置的显示要求。 相 对于现有技术中源极 /漏极与像素电极以及栅极与公共电极釆用 不同材料、 且均通过两次掩模工艺制备完成的方式， 本实施例减 少了两次构图工艺， 有效地简化了阵列基板的制备工艺， 降低了 掩模板和材料的成本， 减少了设备投资， 节约了成本， 提高了产 能， 提高了显示装置产品的竟争力。 实施例 6 :
本实施例与实施例 1、 2相比， 本实施例的阵列基板中的薄膜 晶体管为顶栅型结构， 驱动电极仍包括公共电极和像素电极， 且 公共电极与像素电极在正投影方向上至少部分重叠。
在本实施例的阵列基板的薄膜晶体管中， 栅极、 源极与漏极 中处于相对下层的为源极与漏极， 处于相对上层的为栅极， 第二 电极设置于第一电极的下方， 其中第一电极为狭缝状的公共电极， 第二电极为板状的像素电极。 其中， 源极 /漏极与像素电极釆用相 同的材料形成， 且像素电极的厚度小于源极 /漏极的厚度。
具体的， 如图 8所示， 该阵列基板中， 衬底基板 10的上方依 次为有源层 13、 同层设置的源极 14和漏极 15、 栅绝缘层 12、 栅 极 11， 另外， 像素电极 20与源极 14和漏极 15同层设置（像素电 极 20直接与漏极 15电连接） ， 公共电极 21与栅极 11同层设置。
在本实施例中， 源极 14/漏极 15和像素电极 20釆用相同的 材料、 且在同一构图工艺中形成。 其中， 源极 14/漏极 15可以为 采用 4吕 （ A1 ) 、 4同（ Cu ) 、 ] ( Mo ) 、 4吕 4女合金 ( AlNd ) , 4各（ Cr ) 、 钛 （Ti ) 或银（ Ag ) 形成的单层金属膜层或者由其构成的多层复 合膜层，而像素电极 20可以釆用上述与形成源极 14/漏极 15相同 材料的单层金属膜层或者由其构成的多层复合膜层通过刻蚀工艺 减薄获得。 本实施例中， 像素电极 20 的厚度范围为 10-100 A, 透过率范围为 30-90%。
或者， 源极 14/漏极 15为 ZnS/Ag/ZnS/Ag或 ITO/Ag/ ITO/Ag 复合膜层结构， 优选各膜层的厚度分别为 400 A /180 A /400 A /2000 A, 像素电极 20为 ZnS/Ag/ZnS或 ITO/Ag/ITO复合膜层结 构， 优选各膜层的厚度分别为 400 A /180 A /400 k。
本实施例的阵列基板中各层结构的制备方法具体可参考实施 例 1、 2， 这里不再赘述。
与实施例 1、 2相同， 本实施例还提供一种 ADSDS模式的显示 装置。 实施例 7:
本实施例与实施例 3、 4相比， 本实施例的阵列基板中的薄膜 晶体管为顶栅型结构， 驱动电极仍包括公共电极和像素电极， 且 公共电极与像素电极在正投影方向上至少部分重叠。
在本实施例的阵列基板的薄膜晶体管中， 栅极、 源极与漏极 中处于相对下层的为源极与漏极， 处于相对上层的为栅极， 第二 电极设置于第一电极的下方， 其中第一电极为狭缝状的公共电极， 第二电极为板状的像素电极。 其中， 栅极与公共电极釆用相同的 材料形成， 且公共电极的厚度小于栅极的厚度。
具体的， 如图 9所示， 该阵列基板中， 衬底基板 10的上方依 次为有源层 13、 同层设置的源极 14和漏极 15、 栅绝缘层 12、 栅 极 11， 另外， 像素电极 20与源极 14和漏极 15同层设置（像素电 极 20直接与漏极 15电连接） ， 公共电极 21与栅极 11同层设置。
在本实施例中， 公共电极 21与栅极 11釆用相同的材料、 且 在同一构图工艺中形成。 其中， 栅极 11可以为釆用铝 （ A1 ) 、 铜 ( Cu) 、 钼 （ Mo ) 、 铝钕合金 ( AlNd ) 、 铬 （ Cr ) 、 钛 （ Ti ) 或 银 （Ag ) 形成的单层金属膜层或者由其构成的多层复合膜层， 而 公共电极 21可以釆用上述与形成栅极 11相同材料的单层金属膜 层或者由其构成的多层复合膜层通过刻蚀工艺减薄获得。 本实施 例中，公共电极 21的厚度范围为 10-100人，透过率范围为 30-90%。
或者，栅极 11为 ZnS/Ag/ZnS/Ag或 ITO/Ag/ ITO/Ag复合膜层 结构， 优选各膜层的厚度分别为 400人 /180人 /400人 /2000 A， 公共电极 21为 ZnS/Ag/ZnS或 ITO/Ag/ITO复合膜层结构， 优选各 膜层的厚度分别为 400 A /180 A /400 k。
本实施例的阵列基板中各层结构的制备方法具体可参考实施 例 3、 4， 这里不再赘述。
与实施例 3、 4相同， 本实施例还提供一种 ADSDS模式的显示 装置。 实施例 8:
本实施例与实施例 6-7 中任一个相比， 阵列基板中的薄膜晶 体管为顶栅型结构， 而驱动电极仍包括公共电极和像素电极。 在 本实施例中， 源极 /漏极与像素电极釆用相同的材料形成， 且像素 电极的厚度小于源极 /漏极的厚度， 并且， 栅极与公共电极釆用相 同的材料形成， 且公共电极的厚度小于栅极的厚度。
具体的， 如图 10所示， 该阵列基板中， 衬底基板 10的上方 依次为有源层 13、 同层设置的源极 14和漏极 15、 栅绝缘层 12、 栅极 11， 其中， 像素电极 20与源极 14和漏极 15同层设置（像素 电极 20直接与漏极 15电连接） ， 公共电极 21与栅极 11 同层设 置。
本实施例中，源极 /漏极与像素电极的形成方式与实施例 6相 同， 栅极与公共电极的形成方式与实施例 7相同， 而栅绝缘层、 有源层和钝化层的形成方式与现有技术中栅绝缘层、 有源层和钝 化层的形成方式相同， 这里不再赘述。
与实施例 6、 7相同， 本实施例还提供一种 ADSDS模式的显示 装置。 实施例 9:
本实施例与实施例 1-8 中任一个的区别在于， 阵列基板中的 薄膜晶体管为底栅型结构， 而驱动电极仍包括公共电极和像素电 极。 在本实施例中， 栅极与像素电极釆用相同的材料形成， 且像 素电极的厚度小于栅极的厚度。
具体的， 如图 11所示， 在本实施例中， 该阵列基板中， 衬底 基板 10的上方依次为栅极 11、 栅绝缘层 12、 有源层 13 (从图 11 中可见， 有源层 13为双层子膜层结构） 、 同层设置的源极 14和 漏极 15， 另外， 像素电极 20与栅极 11 同层设置 （像素电极 20 通过像素电极连接线 23与漏极 15电连接） 。
在本实施例中， 用于连接像素电极 20与漏极 15的像素电极 连接线 23与公共电极 21釆用相同的材料、 且在同一构图工艺中 形成， 用于与公共电极 21连接的公共电极线 22与栅极 11、 像素 电极 20釆用相同的材料、 且在同一构图工艺中形成。
本实施例中， 栅极与像素电极的形成方式可参考实施例 1-5 中栅极与公共电极的形成方式， 而公共电极、 栅绝缘层、 有源层 和钝化层的形成方式与现有技术中公共电极、 栅绝缘层、 有源层 和钝化层的形成方式相同， 这里不再赘述。
与实施例 1-8相同， 本实施例还提供一种 ADSDS模式的显示 装置。 实施例 10 :
本实施例与实施例 1-9 中任一个的区别在于， 本实施例的阵 列基板中的薄膜晶体管为底栅型， 且驱动电极仅包括第一电极， 第一电极为像素电极。
具体的， 如图 12所示， 该阵列基板中， 衬底基板 10的上方 依次为栅极 11、 栅绝缘层 12、 有源层 13、 同层设置的源极 14和 漏极 15， 其中， 像素电极 20与源极 14/漏极 15 同层设置 （像素 电极 20直接与漏极 15电连接） 。
在本实施例中， 处于相对上层的源极 /漏极、 与像素电极釆用 相同的材料形成， 且像素电极的厚度小于源极 /漏极的厚度， 像素 电极与漏极电连接， 像素电极的透过率范围为 30-90%。
在本实施例中， 源极 /漏极与像素电极为单层或多层复合膜 层， 釆用铝、 铜、 钼、 铝钕合金、 铬、 钛或银形成， 或者， 源极 / 漏极与像素电极为具有一维金属 /介质光子晶体结构的多层复合 膜层， 金属包括银， 介质包括硫化辞或氧化铟锡。
在本实施例的阵列基板中，源极 /漏极与像素电极通过同一构 图工艺同时形成。 具体的制备方法可参考实施例 3-5 中任一个中 阵列基板的源极 /漏极与像素电极的制备方法。
本实施例中， 栅极、 栅绝缘层、 有源层和钝化层的形成方式 与现有技术中栅极、 栅绝缘层、 有源层和钝化层的形成方式相同， 这里不再赘述。
本实施例还提供一种釆用上述阵列基板的显示装置。 该显示 装置可以为 TN ( Twi s ted Nema t i c , 扭曲向列）模式的 LCD、 VA ( Ver t i ca l Al i gnment , 垂直取向）模式的 LCD、 或 0LED显示装 置。 实施例 1 1 :
本实施例与实施例 1 0的区别在于，本实施例的阵列基板中薄 膜晶体管为顶栅型， 且驱动电极仅包括第一电极， 第一电极为像 素电极。
具体的， 如图 1 3所示， 该阵列基板中， 衬底基板 1 0的上方 依次为有源层 1 3、 同层设置的源极 14和漏极 15、 栅绝缘层 1 2、 栅极 1 1， 其中， 像素电极 20与源极 14/漏极 1 5 同层设置， 像素 电极 20直接与漏极 1 5电连接。
在本实施例中， 处于相对下层的源极 /漏极、 与像素电极釆用 相同的材料形成， 且像素电极的厚度小于源极 /漏极的厚度， 像素 电极与漏极直接电连接， 像素电极的透过率范围为 30-90%。
在本实施例中， 源极 /漏极与像素电极为单层或多层复合膜 层， 釆用铝、 铜、 钼、 铝钕合金、 铬、 钛或银形成， 或者， 源极 / 漏极与像素电极为具有一维金属 /介质光子晶体结构的多层复合 膜层， 金属包括银， 介质包括硫化辞或氧化铟锡。
在本实施例的阵列基板中，源极 /漏极与像素电极通过同一构 图工艺同时形成。 具体的制备方法可参考实施例 6或 8 中阵列基 板的源极 /漏极与像素电极的制备方法。
本实施例中， 栅极、 栅绝缘层、 有源层和钝化层的形成方式 与现有技术中栅极、 栅绝缘层、 有源层和钝化层的形成方式相同， 这里不再赘述。
本实施例还提供一种釆用上述阵列基板的显示装置。 本发明的阵列基板中， 通过将像素电极或公共电极与薄膜晶 体管中的栅极或源极 /漏极釆用相同的材料形成， 并且在阵列基板 的制备方法中通过同一构图工艺同时形成像素电极或公共电极与 薄膜晶体管中的栅极或源极 /漏极， 且经过减薄工艺， 使得像素电 极或公共电极满足透过率， 相比现有技术中阵列基板的制备工艺 至少减少了一次构图工艺， 有效地简化了阵列基板的制备工艺， 降低了掩模板和材料的成本， 减少了设备投资， 节约了成本， 提 高了产能， 提高了显示装置产品的竟争力。
而釆用的示例性实施方式， 然而本发明并不局限于此。 对于本领 域内的普通技术人员而言， 在不脱离本发明的精神和实质的情况 下， 可以做出各种变型和改进， 这些变型和改进也视为本发明的 保护范围。

Claims

权 利 要 求 书
1. 一种阵列基板， 包括衬底基板以及设置于所述衬底基板上 的薄膜晶体管和至少一个驱动电极， 所述薄膜晶体管包括栅极以 及设置在同一层的源极和漏极， 其中， 所述栅极、 所述源极或所 述漏极与所述至少一个驱动电极为釆用相同的材料形成的膜层， 且其厚度大于所述至少一个驱动电极的厚度。
2. 根据权利要求 1所述的阵列基板， 其中， 所述至少一个驱 动电极包括第一电极与第二电极， 所述第一电极与所述第二电极 在正投影方向上至少部分重叠， 所述第二电极设置于所述第一电 极的下方，
所述栅极、 所述源极和所述漏极中处于上层的电极、 与所述 第一电极为釆用相同的材料形成的膜层， 且所述第一电极的厚度 小于该电极的厚度； 和 /或， 所述栅极、 所述源极和所述漏极中处 于下层的电极、 与所述第二电极为釆用相同的材料形成的膜层， 且所述第二电极的厚度小于该电极的厚度。
3. 根据权利要求 2所述的阵列基板， 其中， 釆用相同的材料 形成的膜层为釆用铝、 铜、 钼、 铝钕合金、 铬、 钛或银形成的单 层或多层复合膜层。
4. 根据权利要求 2所述的阵列基板， 其中， 釆用相同的材料 形成的膜层为具有一维金属 /介质光子晶体结构的多层复合膜层， 所述金属包括银， 所述介质包括硫化辞或氧化铟锡。
5. 根据权利要求 2所述的阵列基板， 其中， 所述第一电极为 狭缝状的像素电极， 所述第二电极为板状的公共电极， 所述像素 电极与所述漏极电连接； 或者， 所述第一电极为狭缝状的公共电 极， 所述第二电极为板状的像素电极， 所述像素电极与所述漏极 电连接。
6. 根据权利要求 3所述的阵列基板， 其中， 所述至少一个驱 动电极的透过率范围为 30-90%， 厚度范围为 1 0-1 00A。
7. 根据权利要求 4所述的阵列基板， 其中， 所述至少一个驱 动电极的透过率范围为 30_90%， 厚度范围为 1 00-1 000人。
8. 根据权利要求 1所述的阵列基板， 其中， 所述至少一个驱 动电极包括像素电极， 所述源极或所述漏极与所述像素电极为釆 用相同的材料形成的膜层， 且所述像素电极的厚度小于所述源极 或所述漏极的厚度。
9. 根据权利要求 8所述的阵列基板， 其中， 釆用相同的材料 形成的膜层为釆用铝、 铜、 钼、 铝钕合金、 铬、 钛或银形成的单 层或多层复合膜层。
1 0.根据权利要求 9所述的阵列基板， 其中， 所述像素电极与 所述漏极电连接， 所述像素电极的透过率范围为 30-90%， 厚度范 围为 1 0-1 00 人。
1 1. 根据权利要求 8所述的阵列基板， 其中， 釆用相同的材 料形成的膜层为具有一维金属 /介质光子晶体结构的多层复合膜 层， 所述金属包括银， 所述介质包括硫化辞或氧化铟锡。
12. 根据权利要求 1 1所述的阵列基板， 其中， 所述像素电极 与所述漏极电连接， 所述像素电极的透过率范围为 30-90%， 厚度 范围为 1 00-1 000 人。
1 3. 一种显示装置， 包括权利要求 1-12任一项所述的阵列基 板。
14. 一种阵列基板的制备方法， 包括在衬底基板上形成薄膜 晶体管和至少一个驱动电极的步骤， 所述薄膜晶体管包括栅极以 及设置在同一层的源极和漏极， 其中， 所述栅极、 所述源极和所 述漏极中的一个与所述至少一个驱动电极为釆用相同的材料形成 的膜层， 且其厚度大于所述至少一个驱动电极的厚度。
1 5. 根据权利要求 1 4所述的制备方法， 其中， 所述栅极、 所 述源极和所述漏极中的一个与所述至少一个驱动电极中的一个驱 动电极通过同一构图工艺形成。
1 6. 根据权利要求 1 5所述的制备方法， 其中， 所述栅极、 所 述源极和所述漏极中的一个与所述至少一个驱动电极中的一个驱 动电极通过同一构图工艺形成包括如下步骤：
步骤 S 1 : 形成金属电极层；
步骤 S 2 : 在所述金属电极层的上方形成光刻胶层；
步骤 S 3 : 釆用半色调掩模板或灰色调掩模板， 对所述光刻胶 层进行曝光、 显影工艺， 将对应着形成所述栅极、 所述源极和所 述漏极中的所述一个的区域的光刻胶完全保留， 对应着形成所述 一个驱动电极的区域的光刻胶部分保留， 其余区域的光刻胶完全 去除；
步骤 S4 : 对所述金属电极层进行第一次刻蚀工艺， 将对应着 形成所述栅极、 所述源极和所述漏极中的所述一个的区域和对应 着形成所述一个驱动电极的区域以外的金属电极材料去除；
步骤 S 5 : 对所述光刻胶层进行减薄处理， 将对应着形成所述 栅极、 所述源极和所述漏极中的所述一个的区域的光刻胶部分保 留， 对应着形成所述一个驱动电极的区域的光刻胶完全去除； 步骤 S 6 : 对所述金属电极层进行第二次刻蚀工艺， 将对应着 形成所述一个驱动电极的区域的金属电极材料部分去除， 形成包 括所述栅极、 所述源极和所述漏极中的所述一个和所述一个驱动 电极的图形；
步骤 S7 : 去除所述光刻胶层中剩余的光刻胶。
17. 根据权利要求 1 6所述的制备方法， 其中， 所述形成金属 电极层的步骤包括釆用铝、 铜、 钼、 铝钕合金、 铬、 钛或银形成 单层或多层复合膜层。
18. 根据权利要求 1 7所述的制备方法， 其中， 所述形成包括 所述栅极、 所述源极和所述漏极中的所述一个和所述一个驱动电 极的图形包括形成厚度范围为 1 0-1 00A、 透过率范围为 30-90%的 所述一个驱动电极。
19. 根据权利要求 1 6所述的制备方法， 其中， 所述形成金属 电极层的步骤包括形成具有一维金属 /介质光子晶体结构的多层 复合膜层， 所述金属包括银， 所述介质包括硫化辞或氧化铟锡。
20. 根据权利要求 1 9所述的制备方法， 其中， 所述形成包括 所述栅极、 所述源极和所述漏极中的所述一个和所述一个驱动电 极的图形包括形成厚度范围为 1 00-1 000人、 透过率范围为 30-90% 的所述一个驱动电极。
21. 根据权利要求 1 6所述的制备方法， 其中， 对所述光刻胶 层进行减薄处理的步骤包括通过灰化工艺对所述光刻胶层进行减 薄处理。
22. 根据权利要求 1 5至 21 中任意一项所述的制备方法， 其 中， 所述至少一个驱动电极包括第一电极与第二电极， 所述第一 电极与所述第二电极在正投影方向上至少部分重叠， 所述第二电 极设置于所述第一电极的下方， 其中 所述栅极、 所述源极和所述漏极中的一个与所述至少一个驱 动电极中的一个驱动电极通过同一构图工艺形成的步骤包括： 通过同一构图工艺同时形成所述栅极、 所述源极和所述漏极 中处于上层的电极与所述第一电极； 和 /或
通过同一构图工艺同时形成所述栅极、 所述源极和所述漏极 中处于下层的电极与所述第二电极。
23. 根据权利要求 22所述的制备方法， 其中， 所述第一电极 为狭缝状的像素电极， 所述第二电极为板状的公共电极， 所述像 素电极与所述漏极电连接； 或者
所述第一电极为狭缝状的公共电极， 所述第二电极为板状的 像素电极， 所述像素电极与所述漏极电连接。
24. 根据权利要求 15至 21 中任意一项所述的制备方法， 其 中， 所述驱动电极包括像素电极，
所述栅极、 所述源极和所述漏极中的一个与所述至少一个驱 动电极中的一个驱动电极通过同一构图工艺形成的步骤包括： 通过同一构图工艺同时形成所述源极和所述漏极与所述像素 电极， 所述像素电极与所述漏极电连接。
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