WO2016011727A1 - 薄膜晶体管及其制作方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板和显示装置 Download PDF

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WO2016011727A1
WO2016011727A1 PCT/CN2014/090623 CN2014090623W WO2016011727A1 WO 2016011727 A1 WO2016011727 A1 WO 2016011727A1 CN 2014090623 W CN2014090623 W CN 2014090623W WO 2016011727 A1 WO2016011727 A1 WO 2016011727A1
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insulating layer
gate
film transistor
gate insulating
thin film
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PCT/CN2014/090623
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English (en)
French (fr)
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方汉铿
谢应涛
欧阳世宏
蔡述澄
石强
刘则
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京东方科技集团股份有限公司
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Priority to US14/769,670 priority Critical patent/US10290822B2/en
Publication of WO2016011727A1 publication Critical patent/WO2016011727A1/zh

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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
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    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material

Definitions

  • At least one embodiment of the present invention is directed to a thin film transistor and a method of fabricating the same, an array substrate, and a display device.
  • the organic semiconductor layer on the array substrate is not formed on a completely flat plane, and is often formed on other layers having a step.
  • An organic semiconductor layer is disposed above or below the source drain to ensure normal conduction of the source and drain during the on state.
  • At least one embodiment of the present invention provides a thin film transistor and a method of fabricating the same, an array substrate, and a display device to avoid disconnection of an active layer, improve performance and stability of the thin film transistor, and reduce production cost.
  • At least one embodiment of the present invention provides a thin film transistor having a gate bottom contact type, the thin film transistor including: a gate and a gate insulating layer, the gate insulating layer and the A groove is provided at a position corresponding to the gate.
  • At least one embodiment of the present invention provides an array substrate, the array substrate comprising the thin film transistor of the first aspect.
  • At least one embodiment of the present invention provides a display device comprising the array substrate of the second aspect.
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor, the method comprising: forming a gate metal layer including a gate, a gate line, and a gate line lead, and forming on the gate metal layer A layer is provided with a recessed gate insulating layer at a position corresponding to the gate.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method for fabricating a thin film transistor according to an embodiment of the present invention
  • FIG. 5 is a schematic flow chart of another method for fabricating a thin film transistor according to an embodiment of the present invention.
  • FIG. 6 is a schematic flow chart of still another method for fabricating a thin film transistor according to an embodiment of the present invention.
  • the inventors of the present application have noticed that since there are step differences between the source and drain patterns and the gate insulating layer and are not at the same interface, the semiconductor material spreads on the source/drain electrodes and the gate insulating layer when the organic semiconductor layer is formed. Different behaviors result in different film thicknesses, and the film thickness is more difficult to control, which may cause the organic semiconductor layer to be broken, and may even cause the source and drain electrodes to be not normally turned on.
  • At least one embodiment of the present invention provides a thin film transistor which may be of a gate bottom contact type.
  • the thin film transistor includes a substrate 1, a gate 3 and a gate insulating layer 2, and a gate insulating layer.
  • a groove 4 is provided at a position corresponding to the gate 3 at 2.
  • the recess at the corresponding position on the gate of the gate insulating layer may be formed by a patterning process using exposure, development, and etching using a mask when the gate insulating layer is formed.
  • the substrate may be a glass substrate, a plastic substrate, or a substrate of stainless steel and an insulating film.
  • the gate insulating layer may be formed using a photosensitive organic material, and the gate insulating layer may have a thickness of 200 to 500 nanometers (nm).
  • the gate electrode may be formed of metal, indium tin oxide (ITO) or an organic conductive material, and the gate electrode may have a thickness of 60 to 300 nm.
  • the recess is disposed at a position corresponding to the gate on the gate insulating layer of the thin film transistor, so that the active layer can be disposed at a position corresponding to the recess on the gate insulating layer, such that It can be better to form the active layer, the source and the drain better, and solves the structure of the thin film transistor because there is a step difference between the source and drain electrodes and the insulating layer and is not at the same interface, so that when the active layer is finally formed,
  • the film thickness on the source/drain electrodes and the insulating layer is not easily controlled, and the problem of disconnection of the active layer at the channel of the source and drain occurs, which improves the performance and stability of the thin film transistor and reduces the production cost.
  • the thin film transistor further includes a source 5 and a drain 6, and a partial pattern of the source 5 and the drain 6 is formed on the gate insulating layer 2, and on the gate insulating layer 2.
  • the groove 4 corresponds to the position.
  • the source and the drain can be formed by using a metal material such as gold Au, silver Ag, molybdenum Mo, aluminum Al, or copper Cu, a metal oxide material such as ITO, or a conductive polymer material.
  • the source drain may have a thickness of 60 to 300 nm.
  • the thin film transistor further includes an active layer 7 formed on the gate insulating layer 2 at a position corresponding to the groove 4 on the gate insulating layer 2. .
  • the material of the active layer can be an organic semiconductor material.
  • the active layer in the embodiment of the present invention may be formed by a solution method, and the material forming the active layer may be an organic material prepared by a solution method; generally, the active layer may have a thickness of 40 to 200 nm, which is implemented by the present invention. In the example, it is preferably 40 to 100 nm.
  • a solution spin coating method may be employed to form an active layer on the gate insulating layer and at a position corresponding to the recess on the gate insulating layer.
  • the width W1 of the recess 4 on the gate insulating layer is greater than or equal to the width W2 of the gate 3.
  • the height H1 of the groove 4 on the gate insulating layer is greater than or equal to the thickness H2 of the active layer 7.
  • the width of the groove on the gate insulating layer is greater than or equal to the width of the gate, and the height of the groove is greater than or equal to the thickness of the active layer, so that a partial pattern of the source and the drain may be ensured when the source and the drain are subsequently formed.
  • the active layer Located at a position corresponding to the groove on the gate insulating layer, the active layer may be entirely disposed at a position corresponding to the groove, so that the material for forming the source and the drain is facilitated to flow into the groove during the manufacturing process. It is beneficial to form the source and the drain, and at the same time, since the active layer is disposed in the groove, when the material of the active layer is coated, the film thickness can be well controlled, and the problem of disconnection on the active layer can be avoided. The function of the active layer to ensure the connection of the source and the drain is ensured, the waste of the production material is effectively avoided, and the production cost is reduced.
  • the thin film transistor provided by the embodiment of the present invention may further include a protective layer disposed on the source, the drain, and the active layer and coated on the entire substrate, and the thickness thereof may be
  • the material is usually silicon nitride or a transparent organic resin material.
  • the recess is disposed at a position corresponding to the gate on the gate insulating layer of the thin film transistor, so that the active layer can be disposed at a position corresponding to the recess on the gate insulating layer, such that It can be better to form the active layer, the source and the drain better, and solves the structure of the thin film transistor because there is a step difference between the source and drain electrodes and the insulating layer and is not at the same interface, so that when the active layer is finally formed, The film thickness on the source/drain electrodes and the insulating layer is not easily controlled, and the formed active layer is broken, which improves the performance and stability of the thin film transistor and reduces the production cost. Further, the production efficiency can be improved.
  • At least one embodiment of the present invention provides an array substrate including any of the thin film transistors provided in the embodiments corresponding to FIGS. 1 to 3, which may be of a gate bottom contact type.
  • the array substrate provided by the embodiment of the invention may further include a plurality of gate lines and a plurality of data lines, and the gate lines Intersection with the data lines defines pixel cells arranged in an array, each pixel cell including a thin film transistor in accordance with an embodiment of the present invention as a switching element.
  • the array substrate can be an array substrate for use in an OLED, an electronic paper, or an LCD.
  • the array substrate provided by the embodiment of the present invention provides a recess at a position corresponding to the gate on the gate insulating layer of the thin film transistor of the array substrate, so that the active layer can be disposed on the recess corresponding to the gate insulating layer.
  • this can facilitate better formation of the active layer, the source and the drain, and solves the structure of the thin film transistor because there is a step difference between the source and drain electrodes and the insulating layer and is not at the same interface, so that the active is finally formed.
  • the film thickness on the source/drain electrodes and the insulating layer is not easily controlled, and the formed active layer is broken, which improves the performance and stability of the thin film transistor and reduces the production cost. Further, the production efficiency can be improved.
  • At least one embodiment of the present invention provides a display device including the array substrate or the thin film transistor provided by the above embodiments of the present invention.
  • the display device may be: a liquid crystal panel, an OLED panel, an electronic paper, a mobile phone, a tablet computer. , TV, laptop, digital photo frame, navigator, etc. Any product or component with display function.
  • a display device provides a recess in a position corresponding to a gate on a gate insulating layer of a thin film transistor of a display device, so that an active layer can be disposed on a recess corresponding to the gate insulating layer. At the position, this can facilitate better formation of the active layer, the source and the drain, and solves the structure of the thin film transistor because there is a step difference between the source and drain electrodes and the insulating layer and is not at the same interface, so that the active is finally formed.
  • the film thickness on the source/drain electrodes and the insulating layer is not easily controlled, and the formed active layer is broken, which improves the performance and stability of the thin film transistor and reduces the production cost. Further, the production efficiency can be improved.
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor, which may be of a gate bottom contact type. Referring to FIG. 4, the method includes the following steps 101 and 102, which are described one by one below.
  • Step 101 forming a gate metal layer including a gate, a gate line, and a gate line lead on the substrate.
  • a thickness can be deposited on a substrate (such as a glass substrate or a quartz substrate) by magnetron sputtering.
  • a substrate such as a glass substrate or a quartz substrate
  • the metal thin film at least one or a combination of several kinds of metal thin films such as molybdenum, aluminum, aluminum nickel alloy, molybdenum tungsten alloy, chromium, or copper can be usually used.
  • the gate metal layer is formed on a certain area of the substrate by a patterning process such as exposure, development, etching, and peeling using a mask.
  • the thickness can be deposited on a glass substrate by chemical vapor deposition or magnetron sputtering.
  • the gate insulating layer film is usually made of silicon nitride, and silicon oxide, silicon oxynitride or the like can also be used.
  • a photosensitive organic material is preferred. By using a mask, ultraviolet exposure is performed over the gate so that the gate insulating layer has a shape of a groove at a position corresponding to the gate.
  • the fabrication method further includes forming a partial pattern of source and drain at a location on the gate insulating layer corresponding to a recess on the gate insulating layer.
  • the fabricating method further includes forming an active layer on the gate insulating layer at a position corresponding to a groove on the gate insulating layer.
  • the material of the active layer may be an organic semiconductor material.
  • the order of forming the source drain and the active layer is not limited in the embodiment of the present invention.
  • the method may include the following steps 201 to 205.
  • Step 201 forming a gate metal layer including a gate, a gate line, and a gate line lead on the substrate.
  • Step 202 Form a gate insulating layer on the gate metal layer with a groove at a position corresponding to the gate.
  • Step 203 forming an active layer on the gate insulating layer at a position corresponding to the groove on the gate insulating layer.
  • a metal oxide semiconductor thin film may be deposited on the gate insulating layer by chemical vapor deposition, and then the metal oxide semiconductor thin film is patterned once to form an active layer, that is, after the photoresist is coated, a common mask is used.
  • the template may expose, develop, and etch the substrate to form an active layer.
  • Step 204 forming a source and a drain on the active layer.
  • a partial pattern of the source and the drain is at a position on the gate insulating layer corresponding to the groove on the gate insulating layer.
  • a layer-like thickness is deposited on the substrate in a manner similar to that of the gate line.
  • To Metal film Forming a source and a drain in a certain region by a patterning process, and finally forming a source and a drain having a thickness of
  • Step 205 forming a protective layer on the source and the drain.
  • the protective layer is usually made of silicon nitride or a transparent organic resin material.
  • the method includes the following steps 301 to 305.
  • Step 301 forming a gate metal layer including a gate, a gate line, and a gate line lead on the substrate.
  • Step 302 Form a gate insulating layer on the gate metal layer with a groove at a position corresponding to the gate.
  • Step 303 forming a source and a drain on the gate insulating layer.
  • a partial pattern of the source and the drain is at a position on the gate insulating layer corresponding to the groove on the gate insulating layer.
  • a negative photoresist may be coated on the gate insulating layer, a pattern of source and drain regions may be formed through the mask, and then a metal film is deposited on the gate insulating layer by vacuum coating, and finally A negative photoresist stripping process forms a source and a drain.
  • Step 304 forming an active layer at a position on the source and the drain corresponding to the groove on the gate insulating layer.
  • the organic semiconductor material may be applied by a solution method to form an active layer.
  • Step 305 forming a protective layer on the active layer.
  • the method for fabricating the thin film transistor provided by the embodiment of the present invention is such that a recess is provided at a position corresponding to the gate on the gate insulating layer when the thin film transistor is fabricated, so that the active layer can be disposed on the recess on the gate insulating layer.
  • the position corresponding to the groove can facilitate the better formation of the active layer, the source and the drain, and solve the structure of the thin film transistor because there is a step difference between the source and drain electrodes and the insulating layer and is not at the same interface, so that When the active layer is formed, the film thickness on the source/drain electrodes and the insulating layer is not easily controlled, and the formed active layer is broken, which improves the performance and stability of the thin film transistor and reduces the production cost. Further, the production efficiency can be improved.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种薄膜晶体管及其制作方法、阵列基板和显示装置，薄膜晶体管为栅极底接触型，包括栅极（3）和栅绝缘层（2），栅绝缘层（2）上与栅极（3）对应的位置处设置有凹槽（4）。薄膜晶体管避免了源漏极的沟道处的有源层断线的问题，提高了薄膜晶体管的性能和稳定性，降低了生产成本。

Description

薄膜晶体管及其制作方法、阵列基板和显示装置 技术领域
本发明的至少一个实施例涉及一种薄膜晶体管及其制作方法、阵列基板和显示装置。
背景技术
包括有机薄膜晶体管器件的显示面板的结构中，阵列基板上的有机半导体层并不是形成在完全平整的平面上，往往是形成在有段差的其它层上面。源漏极上面或者下面及之间设置有机半导体层，以保证在开态时源极和漏极可以正常导通。
发明内容
本发明的至少一个实施例提供一种薄膜晶体管及其制作方法、阵列基板和显示装置，以避免有源层出现断线，提高了薄膜晶体管的性能和稳定性，降低了生产成本。
第一方面，本发明的至少一个实施例提供一种薄膜晶体管，所述薄膜晶体管为栅极底接触型，所述薄膜晶体管包括：栅极和栅绝缘层，所述栅绝缘层上与所述栅极对应的位置处设置有凹槽。
第二方面，本发明的至少一个实施例提供一种阵列基板，所述阵列基板包括第一方面所述的薄膜晶体管。
第三方面，本发明的至少一个实施例提供一种显示装置，所述显示装置包括第二方面所述的阵列基板。
第四方面，本发明的至少一个实施例提供一种薄膜晶体管的制作方法，所述方法包括：形成包括栅极、栅线和栅线引线的栅金属层，以及在所述栅金属层上形成一层在与所述栅极对应的位置处设置有凹槽的栅绝缘层。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明的实施例提供的一种薄膜晶体管的结构示意图；
图2为本发明的实施例提供的另一种薄膜晶体管的结构示意图；
图3为本发明的实施例提供的又一种薄膜晶体管的结构示意图；
图4为本发明的实施例提供的一种薄膜晶体管的制作方法的流程示意图；
图5为本发明的实施例提供的另一种薄膜晶体管的制作方法的流程示意图；
图6为本发明的实施例提供的又一种薄膜晶体管的制作方法的流程示意图。
附图标记：1-基板；2-栅绝缘层；3-栅极；4-栅绝缘层上的凹槽；5-源极；6-漏极；7-有源层。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地 改变。
本申请的发明人注意到，由于源极和漏极图案与栅绝缘层之间均存在段差且不在同一界面，因此在形成有机半导体层时，半导体材料在源漏电极和栅绝缘层上的铺展行为不同，形成的膜厚度不一样，膜厚比较难控制，这容易导致有机半导体层断线，甚至会导致源漏电极无法正常导通。
本发明的至少一个实施例提供一种薄膜晶体管，该薄膜晶体管可以是栅极底接触类型，参照图1所示，该薄膜晶体管包括：基板1、栅极3和栅绝缘层2，栅绝缘层2上与栅极3对应的位置处设置有凹槽4。
例如，栅绝缘层上栅极对应位置处的凹槽可以是在制作栅绝缘层时，使用掩膜板，采用曝光、显影、刻蚀通过一次构图工艺形成的。例如，基板可以是玻璃基板、塑料基板或者不锈钢与绝缘薄膜的衬底等。
本发明实施例中，栅绝缘层可以是使用光敏有机材料形成的，栅绝缘层的厚度可以为200～500纳米(nm)。栅极可以是采用金属、氧化铟锡(Indium Tin Oxide，简称ITO)或者有机导电材料形成的，栅极的厚度可以为60～300nm。
本发明实施例提供的薄膜晶体管，通过在薄膜晶体管的栅绝缘层上与栅极对应的位置处设置凹槽，使得有源层可以设置于与栅绝缘层上的凹槽对应的位置处，这样可以有利于更好的形成有源层、源极和漏极，解决了薄膜晶体管的结构中由于源漏电极与绝缘层之间存在段差且不在同一界面，使得最终在形成有源层时，在源漏电极和绝缘层上的膜厚不易控制，出现源漏极的沟道处的有源层断线的问题，提高了薄膜晶体管的性能和稳定性，降低了生产成本。
在一个实施例中，参照图2所示，该薄膜晶体管还包括：源极5和漏极6，源极5和漏极6的部分图案形成在栅绝缘层2上，与栅绝缘层2上的凹槽4对应的位置处。
例如，源极和漏极可以采用例如金Au、银Ag、钼Mo、铝Al、铜Cu等金属材料、ITO等金属氧化物材料或者导电高分子材料等制作形成。例如，源漏极的厚度可以为60～300nm。
在至少一个实施例中，参照图3所示，该薄膜晶体管还包括：有源层7，有源层7形成在栅绝缘层2上，与栅绝缘层2上的凹槽4对应的位置处。
在至少一个实施例中，有源层的材料可以为有机半导体材料。
例如，本发明实施例中的有源层可以是采用溶液法制备形成的，形成有源层的材料可以是溶液法制备的有机材料；一般有源层的厚度可以为40～200nm，本发明实施例中优选40～100nm。本发明实施例中可以采用溶液旋涂法来在栅绝缘层上和与栅绝缘层上的凹槽对应的位置处制作有源层。
在至少一个实施例中，栅绝缘层上的凹槽4的宽度W1大于或者等于栅极3的宽度W2。
在至少一个实施例中，栅绝缘层上的凹槽4的高度H1大于或者等于有源层7的厚度H2。
栅绝缘层上的凹槽的宽度大于或者等于栅极的宽度、凹槽的高度大于或者等于有源层的厚度，可以保证后续制作源极和漏极时，源极和漏极的部分图案可以位于与栅绝缘层上的凹槽对应的位置处，同时可以使得有源层整个设置在于凹槽对应的位置处，这样制作过程中有利于形成源极和漏极的材料流到凹槽中从而有益于形成源极和漏极，同时，由于有源层设置在凹槽中，这样涂敷有源层的材料时，可以很好的控制膜厚，避免有源层上出现断线的问题，保证有源层实现连通源漏极的功能，有效的避免了对生产材料的浪费，降低了生产成本。
此外，本发明实施例提供的薄膜晶体管还可以包括设置在源极、漏极和有源层上并涂覆在整个基板上的保护层，其厚度可以为
Figure PCTCN2014090623-appb-000001
其材料通常是氮化硅或透明的有机树脂材料。
本发明实施例提供的薄膜晶体管，通过在薄膜晶体管的栅绝缘层上与栅极对应的位置处设置凹槽，使得有源层可以设置于与栅绝缘层上的凹槽对应的位置处，这样可以有利于更好的形成有源层、源极和漏极，解决了薄膜晶体管的结构中由于源漏电极与绝缘层之间存在段差且不在同一界面，使得最终在形成有源层时，在源漏电极和绝缘层上的膜厚不易控制，形成的有源层出现断线的问题，提高了薄膜晶体管的性能和稳定性，降低了生产成本。进而，可以提高生产效率。
本发明的至少一个实施例提供一种阵列基板，该阵列基板包括附图1～3对应的实施例提供的任一薄膜晶体管，该薄膜晶体管可以是栅极底接触类型。
本发明实施例提供的阵列基板还可以包括多条栅线和多条数据线，栅线 与数据线相交叉限定了按阵列排列的像素单元，每个像素单元包括作为开关元件的根据本发明实施例的薄膜晶体管。例如，所述阵列基板可以为用于OLED、电子纸或LCD中的阵列基板。
本发明的实施例提供的阵列基板，通过在阵列基板的薄膜晶体管的栅绝缘层上与栅极对应的位置处设置凹槽，使得有源层可以设置于与栅绝缘层上的凹槽对应的位置处，这样可以有利于更好的形成有源层、源极和漏极，解决了薄膜晶体管的结构中由于源漏电极与绝缘层之间存在段差且不在同一界面，使得最终在形成有源层时，在源漏电极和绝缘层上的膜厚不易控制，形成的有源层出现断线的问题，提高了薄膜晶体管的性能和稳定性，降低了生产成本。进而，可以提高生产效率。
本发明的至少一个实施例提供一种显示装置，该显示装置包括本发明的上述实施例提供的阵列基板或薄膜晶体管，该显示装置可以为：液晶面板、OLED面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明的实施例提供的显示装置，通过在显示装置的薄膜晶体管的栅绝缘层上与栅极对应的位置处设置凹槽，使得有源层可以设置于与栅绝缘层上的凹槽对应的位置处，这样可以有利于更好的形成有源层、源极和漏极，解决了薄膜晶体管的结构中由于源漏电极与绝缘层之间存在段差且不在同一界面，使得最终在形成有源层时，在源漏电极和绝缘层上的膜厚不易控制，形成的有源层出现断线的问题，提高了薄膜晶体管的性能和稳定性，降低了生产成本。进而，可以提高生产效率。
本发明的至少一个实施例提供一种薄膜晶体管的制作方法，该薄膜晶体管可以是栅极底接触类型，参照图4所示，该方法包括以下步骤101和步骤102，下面逐一介绍这些步骤。
步骤101、在基板上形成包括栅极、栅线和栅线引线的栅金属层。
例如，可以采用磁控溅射的方法在基板(例如玻璃基板或石英基板)上沉积一层厚度在
Figure PCTCN2014090623-appb-000002
至
Figure PCTCN2014090623-appb-000003
的金属薄膜，该金属薄膜通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属薄膜中的至少一种或几种的组合。然后，用掩模板通过曝光、显影、刻蚀、剥离等构图工艺处理，在基板的一定区域上形成栅金属层。
102、在栅金属层上形成一层在与栅极对应的位置处设置有凹槽的栅绝缘层。
例如，可以利用化学汽相沉积法或者磁控溅射的方法在玻璃基板上沉积厚度为
Figure PCTCN2014090623-appb-000004
至
Figure PCTCN2014090623-appb-000005
的栅绝缘层薄膜，该栅绝缘层薄膜的材料通常是氮化硅，也可以使用氧化硅和氮氧化硅等，本发明实施例中优选光敏有机材料。通过使用掩膜板，在栅极上方进行紫外曝光使栅绝缘层在与栅极对应的位置处具有凹槽的形状。
在至少一个实施例中，所述制作方法还包括：在所述栅绝缘层上与所述栅绝缘层上的凹槽对应的位置处形成源极和漏极的部分图案。
在至少一个实施例中，所述制作方法还包括：在所述栅绝缘层上与所述栅绝缘层上的凹槽对应的位置处形成一层有源层。例如，有源层的材料可以为有机半导体材料。
本发明实施例对源漏极和有源层的形成顺序不做限定。
例如，当有源层在源极和漏极之前形成时，参照图5所示，该方法可以包括以下步骤201至步骤205。
步骤201、在基板上形成包括栅极、栅线和栅线引线的栅金属层。
步骤202、在栅金属层上形成一层在与栅极对应的位置处设置有凹槽的栅绝缘层。
步骤203、在栅绝缘层上与栅绝缘层上的凹槽对应的位置处形成一层有源层。
例如，可以利用化学汽相沉积法在栅绝缘层上沉积金属氧化物半导体薄膜，然后对金属氧化物半导体薄膜进行一次构图工艺形成有源层，即在光刻胶涂覆后，用普通的掩模板对基板进行曝光、显影、刻蚀形成有源层即可。
步骤204、在有源层上形成一层源极和漏极。
在该步骤中，源极和漏极的部分图案在栅绝缘层上与栅绝缘层上的凹槽对应的位置处。
采用和制作栅线类似的方法，在基板上沉积一层类似于栅金属的厚度在
Figure PCTCN2014090623-appb-000006
到
Figure PCTCN2014090623-appb-000007
金属薄膜。通过构图工艺处理在一定区域形成源极、漏极，最终形成的源极和漏极的厚度在
Figure PCTCN2014090623-appb-000008
步骤205、在源极和漏极上形成一层保护层。
例如，采用和制作栅绝缘层以及有源层相类似的方法，在整个基板上涂覆一层厚度在
Figure PCTCN2014090623-appb-000009
到
Figure PCTCN2014090623-appb-000010
的保护层，其材料通常是氮化硅或透明的有机树脂材料。
需要说明的是，本实施例中的流程与上述实施例中的步骤相同的描述可以参照上述实施例中的说明，此处不再赘述。
例如，当有源层在源极和漏极之后形成时，参照图6所示，该方法包括以下步骤301至步骤305。
步骤301、在基板上形成包括栅极、栅线和栅线引线的栅金属层。
步骤302、在栅金属层上形成一层在与栅极对应的位置处设置有凹槽的栅绝缘层。
步骤303、在栅绝缘层上形成源极和漏极。
在该步骤中，源极和漏极的部分图案在栅绝缘层上与栅绝缘层上的凹槽对应的位置处。
例如，可以采用在栅绝缘层上涂敷一层负性光刻胶，通过掩膜板形成源漏极区域的图案，然后通过真空镀膜的方法在栅绝缘层上沉积一层金属薄膜，最终进行负性光刻胶脱模工艺形成源极和漏极。
步骤304、在源极和漏极上与栅绝缘层上的凹槽对应的位置处形成一层有源层。
例如，可以采用溶液法涂敷有机半导体材料，形成有源层。
步骤305、在有源层上形成一层保护层。
需要说明的是，本实施例中的流程与上述实施例中的步骤相同的描述可以参照上述实施例中的说明，此处不再赘述。
本发明的实施例提供的薄膜晶体管的制作方法，通过在制作薄膜晶体管时，在栅绝缘层上与栅极对应的位置处设置凹槽，使得有源层可以设置于与栅绝缘层上的凹槽对应的位置处，这样可以有利于更好的形成有源层、源极和漏极，解决了薄膜晶体管的结构中由于源漏电极与绝缘层之间存在段差且不在同一界面，使得最终在形成有源层时，在源漏电极和绝缘层上的膜厚不易控制，形成的有源层出现断线的问题，提高了薄膜晶体管的性能和稳定性，降低了生产成本。进而，可以提高生产效率。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范 围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年7月25日递交的中国专利申请第201410360841.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管为栅极底接触型，并包括栅极和栅绝缘层，
    所述栅绝缘层上与所述栅极对应的位置处设置有凹槽。
  2. 根据权利要求1所述的薄膜晶体管，还包括源极和漏极，其中，
    所述源极和漏极的部分图案形成在所述栅绝缘层上，与所述栅绝缘层上的凹槽对应的位置处。
  3. 根据权利要求1或2所述的薄膜晶体管，还包括：有源层，其中，
    所述有源层形成在所述栅绝缘层上，与所述栅绝缘层上的凹槽对应的位置处。
  4. 根据权利要求1-3任一所述的薄膜晶体管，其中，
    所述栅绝缘层上的凹槽的宽度大于或者等于所述栅极的宽度。
  5. 根据权利要求3所述的薄膜晶体管，其中，
    所述栅绝缘层上的凹槽的高度大于或者等于所述有源层的厚度。
  6. 根据权利要求3或5所述的薄膜晶体管，其中，
    所述有源层的材料为有机半导体材料。
  7. 一种阵列基板，包括权利要求1-6任一所述的薄膜晶体管。
  8. 一种显示装置，包括如权利要求7所述的阵列基板。
  9. 一种薄膜晶体管的制作方法，包括：
    形成包括栅极、栅线和栅线引线的栅金属层，以及
    在所述栅金属层上形成一层在与所述栅极对应的位置处设置有凹槽的栅绝缘层。
  10. 根据权利要求9所述的方法，还包括：
    在所述栅绝缘层上与所述栅绝缘层上的凹槽对应的位置处形成源极和漏极的部分图案。
  11. 根据权利要求9或10所述的方法，还包括：
    在所述栅绝缘层上与所述栅绝缘层上的凹槽对应的位置处形成一层有源层。
  12. 根据权利要求9-11任一所述的方法，其中，
    所述栅绝缘层上的凹槽的宽度大于或者等于所述栅极的宽度。
  13. 根据权利要求11所述的方法，其中，
    所述栅绝缘层上的凹槽的高度大于或者等于所述有源层的厚度。
  14. 根据权利要求11或13所述的方法，其中，
    所述有源层的材料为有机半导体材料。
PCT/CN2014/090623 2014-07-25 2014-11-07 薄膜晶体管及其制作方法、阵列基板和显示装置 WO2016011727A1 (zh)

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