WO2017088272A1 - 像素结构、阵列基板、液晶显示面板及像素结构制造方法 - Google Patents

像素结构、阵列基板、液晶显示面板及像素结构制造方法 Download PDF

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WO2017088272A1
WO2017088272A1 PCT/CN2015/100281 CN2015100281W WO2017088272A1 WO 2017088272 A1 WO2017088272 A1 WO 2017088272A1 CN 2015100281 W CN2015100281 W CN 2015100281W WO 2017088272 A1 WO2017088272 A1 WO 2017088272A1
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layer
metal
indium tin
tin oxide
mask
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PCT/CN2015/100281
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English (en)
French (fr)
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曾勉
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深圳市华星光电技术有限公司
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Priority to US15/034,175 priority Critical patent/US10665720B2/en
Publication of WO2017088272A1 publication Critical patent/WO2017088272A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/464—Lateral top-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a pixel structure, an array substrate, a liquid crystal display panel, and a pixel structure manufacturing method.
  • An active matrix type flat display panel for example, a liquid crystal display panel uses a thin film transistor (TFT) element as a driving element.
  • TFT thin film transistor
  • an inorganic semiconductor material has a high carrier mobility, it is widely used as a material of a semiconductor layer of a thin film transistor.
  • organic semiconductor materials have low carrier mobility, but they are characterized by lightness, flexibility, and low-temperature process preparation. Therefore, in recent years, the industry has begun to try to use organic semiconductor materials. Thin film transistor device.
  • organic semiconductor materials are P-type materials, and in order to make metal and organic semiconductor materials have good ohmic contact, materials with larger work functions such as gold (Au), silver (Ag), aluminum (usually) are usually used.
  • Al), indium tin oxide (ITO) or the like is used as a source-drain electrode material to reduce the Schottky barrier height of the interface between the metal and the semiconductor, and is more advantageous for carrier injection, thereby effectively reducing the contact resistance thereof.
  • Au is higher in terms of cost of use, so it is less practical.
  • Metals such as Ag and Al are susceptible to oxidation or corrosion by subsequent processes such as plasma etching, and the connection to the pixel electrode is affected.
  • ITO is currently used as a transparent pixel electrode material, has good electrical properties, high work function, and is not easily oxidized. It is also widely used in anode materials of organic light-emitting diodes (OLED), but its resistivity is relatively large. Therefore, its development and application on organic semiconductor thin film transistor devices and their array panels are also limited.
  • the invention provides a pixel structure, an array substrate, a liquid crystal display panel and a pixel structure manufacturing method.
  • the contact resistance between the source and the drain of the organic thin film transistor and the organic semiconductor layer is reduced.
  • a pixel structure provided by an embodiment of the present invention includes a pixel electrode layer and a thin film transistor.
  • the thin film transistor includes a gate, a source and a drain insulated from the gate, and an organic semiconductor layer.
  • the pixel structure further includes an indium tin oxide layer and a metal layer disposed on a portion of the indium tin oxide layer.
  • the source and the drain are formed on the indium tin oxide layer.
  • the pattern formed by the organic semiconductor layer is electrically connected to the indium tin oxide layer and the metal layer, and the pixel electrode layer is electrically connected to the metal layer and the indium tin oxide layer.
  • the pixel electrode layer is electrically connected to the metal layer and the indium tin oxide layer through via holes.
  • the metal layer includes a first metal sublayer and a second metal sublayer disposed on the first metal sublayer.
  • Embodiments of the present invention also provide an array substrate comprising a plurality of pixel structures as described above.
  • Embodiments of the present invention also provide a liquid crystal display panel including the array substrate as described above.
  • Embodiments of the present invention also provide a pixel structure manufacturing method, including:
  • Coating a layer of photoresist on the metal layer exposing and developing through a mask to remove all photoresist on the substrate corresponding to the all-transmissive region of the mask, Retaining the photoresist on the substrate corresponding to the total light-shielding region of the mask, and removing a portion of the photoresist at a position corresponding to the semi-transmissive region of the mask;
  • a gate insulating layer, a gate electrode layer, a passivation layer, and a pixel electrode layer are sequentially formed.
  • the metal layer includes a first metal sublayer and a second metal sublayer disposed on the first metal sublayer.
  • the method further includes: forming a via connecting the passivation layer and the gate insulating layer and connecting with the metal layer by an etching process; and fabricating the pixel electrode layer includes: The pixel electrode layer is formed on the passivation layer, and the pixel electrode layer is electrically connected to the metal layer and the indium tin oxide layer through the via hole.
  • Embodiments of the present invention also provide another method of fabricating a pixel structure, including:
  • Coating a layer of photoresist on the metal layer exposing and developing through a mask to remove all photoresist on the substrate corresponding to the all-transmissive region of the mask, Retaining the photoresist on the substrate corresponding to the total light-shielding region of the mask, and removing a portion of the photoresist at a position corresponding to the semi-transmissive region of the mask;
  • a passivation layer and a pixel electrode layer are sequentially formed.
  • the metal layer includes a first metal sublayer and a second metal sublayer disposed on the first metal sublayer.
  • a source and a drain of an organic thin film transistor are formed on an ITO layer. Moreover, since a metal layer is disposed on a portion of the ITO layer, the contact resistance between the source and the drain of the organic thin film transistor and the organic semiconductor layer can be greatly reduced, and further, the ITO layer and the metal layer are disposed as an organic thin film transistor.
  • the data electrode layer can make the resistance of the data conduction line in the liquid crystal display panel having the pixel structure not excessive.
  • the pixel structure is fabricated using only one mask, which reduces the manufacturing cost.
  • FIG. 1 is a schematic diagram of a top gate bottom contact type pixel structure according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a bottom gate bottom contact type pixel structure according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of a method for fabricating a top gate bottom contact type pixel structure according to an embodiment of the present invention
  • FIG. 4 is a flowchart of a method for fabricating a bottom gate bottom contact type pixel structure according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a mask according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a top gate bottom contact type pixel structure 100 according to an embodiment of the present invention.
  • the pixel structure 100 includes a substrate 11 , an indium tin oxide (ITO) layer 12 , a metal layer 13 , an organic semiconductor layer 14 , a gate insulating layer 15 , a gate electrode layer 16 , a passivation layer 17 , and a pixel electrode layer 18 .
  • the material of the substrate 11 may be glass, polyethylene terephthalate (PEN) or the like.
  • the ITO layer 12 and the metal layer 13 are sequentially disposed on one surface of the substrate 11, and the metal layer 13 is disposed on a portion of the ITO layer 12. A source and a drain of the organic thin film transistor are formed on the ITO layer 12.
  • the ITO layer 12 is provided with a metal layer 13 as a data electrode layer of an organic thin film transistor.
  • the metal layer 13 includes a first metal sublayer and a second metal sublayer disposed on the first metal sublayer.
  • the material of the first metal sublayer is a metal having a low resistivity, such as aluminum (Al), chromium (Cr), copper (Cu), etc.
  • the material of the second metal sublayer is a metal that is not easily oxidized, such as molybdenum (Mu) ), tungsten (W), etc.
  • the metal layer 13 may also include only one layer of metal, and the material is a metal having a low electrical resistivity and being not easily oxidized, such as silver (Ag), aluminum (Al), or the like.
  • the source and the drain of the organic thin film transistor are formed on the ITO layer 12, and since the metal layer 13 is provided on a part of the ITO layer 12, The contact resistance between the source and the drain of the organic thin film transistor and the organic semiconductor layer 14 can be greatly reduced. Further, the ITO layer 12 and the metal layer 13 are disposed as the data electrode layer of the organic thin film transistor, so that the pixel structure 100 can be provided. The resistance of the data conduction line in the liquid crystal display panel is not excessive.
  • the pattern formed on the organic semiconductor layer 14 is electrically connected to the ITO layer 12 and the metal layer 13.
  • the gate electrode layer 16 is disposed over the gate insulating layer 15.
  • the passivation layer 17 is disposed over the gate insulating layer 15.
  • the pixel structure 100 further includes a via 19 that connects the passivation layer 17 and the gate insulating layer 15 and is connected to the metal layer 13.
  • the pixel electrode layer 18 is disposed on the passivation layer 17 and electrically connected to the metal layer 13 and the ITO layer 12 through the via holes 19.
  • FIG. 2 is a schematic diagram of a bottom gate bottom contact type pixel structure 200 according to an embodiment of the present invention.
  • the pixel structure 200 includes a substrate 21, a gate electrode layer 22, a gate insulating layer 23, an ITO layer 24, a metal layer 25, an organic semiconductor layer 26, a passivation layer 27, and a pixel electrode layer 28.
  • the material of the substrate 21 may be glass, polyethylene terephthalate (PEN) or the like.
  • the gate electrode layer 22 and the gate insulating layer 23 are disposed on one surface of the substrate 21.
  • the ITO layer 24 and the metal layer 25 are sequentially disposed on the gate insulating layer 23, and the metal layer 25 is disposed on a portion of the ITO layer 24.
  • a source and a drain of the organic thin film transistor are formed on the ITO layer 24.
  • the ITO layer 24 is provided with a metal layer 25 as a data electrode layer of an organic thin film transistor.
  • the metal layer 25 includes a first metal sub-layer and a second metal sub-layer disposed over the first metal sub-layer.
  • the material of the first metal sublayer is a metal having a low resistivity, such as aluminum (Al), chromium (Cr), copper (Cu), etc.
  • the material of the second metal sublayer is a metal that is not easily oxidized, such as molybdenum (Mu) ), tungsten (W), etc.
  • the metal layer 25 may also include only one layer of metal, and the material is a metal having a low electrical resistivity and being not easily oxidized, such as silver (Ag), aluminum (Al), or the like.
  • the source and the drain of the organic thin film transistor are formed on the ITO layer 24, and since the metal layer 25 is provided on a portion of the ITO layer 24, the source and drain of the organic thin film transistor can be greatly reduced.
  • the contact resistance between the pole and the organic semiconductor layer 26, and further, the ITO layer 24 and the metal layer 25 are disposed as the data electrode layer of the organic thin film transistor, so that the resistance of the data conduction line in the liquid crystal display panel having the pixel structure 200 can be made. Not too big.
  • the pattern formed on the organic semiconductor layer 26 is electrically connected to the ITO layer 24 and the metal layer 25.
  • the passivation layer 27 is disposed over the gate insulating layer 23.
  • the pixel structure 200 further includes a via 29 formed in the passivation layer 27 and connected to the metal layer 25.
  • the pixel electrode layer 28 is disposed on the passivation layer 27 and electrically connected to the metal layer 25 and the ITO layer 24 through the via holes 29.
  • FIG. 3 is a flowchart of a method for fabricating a top gate bottom contact type pixel structure 100 according to an embodiment of the present invention.
  • step 301 a substrate 11 is provided.
  • the material of the substrate 11 may be glass, polyethylene terephthalate (PEN) or the like.
  • step 302 an ITO layer 12 and a metal layer 13 are sequentially formed on one surface of the substrate 11.
  • the ITO layer 12 and the metal layer 13 are deposited on the substrate 11 by a physical vapor deposition (PVD) film formation method according to a conventional process, and will not be described in detail herein.
  • PVD physical vapor deposition
  • the material of the metal sublayer in contact with the ITO layer 12 is a metal having a low electrical resistivity such as aluminum (Al), chromium (Cr), copper (Cu), etc., and the material of the other metal sublayer is a metal that is not easily oxidized. Such as molybdenum (Mu), tungsten (W) and so on. In other embodiments, only one layer of metal may be deposited on the ITO layer 12.
  • the material of the metal layer 13 is a metal having a low resistivity and being less susceptible to oxidation, such as silver (Ag), aluminum (Al), or the like.
  • Step 303 coating a layer of photoresist on the metal layer 13, exposing and developing through the mask plate 500 (see FIG. 5) to remove the position of the substrate 11 corresponding to the all-transmissive region 51 of the mask plate 500. All of the photoresist retains the photoresist at a position corresponding to the full light-shielding region 52 of the mask 500, and removes part of the light at a position corresponding to the semi-transmissive region 53 of the mask 500. Engraved.
  • the method of performing exposure and development by the mask 500 is a prior art, and will not be described in detail herein.
  • the mask 500 can be a halftone mask or a grayscale mask.
  • step 304 the metal layer 13 and the ITO layer 12 at positions corresponding to the all-transmissive regions 51 of the mask plate 500 are etched away by the wet etching method.
  • Step 305 treating the substrate 11 with a plasma surface treatment to remove the photoresist remaining on the substrate 11 at a position corresponding to the semi-transmissive region 53 of the mask 500, and removing the entire substrate 11 and the mask 500. A portion of the photoresist at a position corresponding to the light-shielding region 52.
  • Step 306 wetly engraving the metal layer 13 at a position corresponding to the semi-transmissive region 53 of the mask 500, leaving the substrate 11 at a position corresponding to the total light-shielding region 52 and the semi-transmissive region 53 of the mask.
  • the ITO layer 12 forms a source and a drain of the thin film transistor on the ITO layer 12.
  • a metal layer 13 is disposed on a portion of the ITO layer 12.
  • Step 307 removing the photoresist remaining on the substrate 11 at a position corresponding to the total light-shielding region 52 of the mask 500.
  • Step 308 forming an organic semiconductor layer 14 on the substrate 11, and fabricating an organic semiconductor pattern, wherein the organic semiconductor pattern is electrically connected to the ITO layer 12 and the metal layer 13.
  • an organic semiconductor pattern can be produced by a conventional exposure, development, and etching process. I will not go into details.
  • step 309 the gate insulating layer 15, the gate electrode layer 16, the passivation layer 17, and the pixel electrode layer 28 are sequentially formed.
  • the gate insulating layer 15, the gate electrode layer 16, the passivation layer 17, and the pixel electrode layer 18 are formed by a conventional organic thin film transistor fabrication process, and will not be described in detail herein.
  • the method further includes: forming a via 19 connecting the passivation layer 17 and the gate insulating layer 15 and connecting with the metal layer 13 by an etching process.
  • Fabricating the pixel electrode layer 18 includes: forming the pixel electrode layer 18 over the passivation layer 17, and electrically connecting the pixel electrode layer 18 to the metal layer 13 and the ITO layer 12 through the via holes 19.
  • the source and the drain of the organic thin film transistor are formed on the ITO layer 12, and since the metal layer 13 is provided on a portion of the ITO layer 12, the source and drain of the organic thin film transistor can be greatly reduced.
  • Contact resistance of the pole and the organic semiconductor layer 14, and further, the ITO layer 12 and the metal layer 13 are provided as the data electrode layer of the organic thin film transistor, so that the resistance of the data conduction line in the liquid crystal display panel having the pixel structure 100 can be made.
  • the present invention uses only one mask 500 to fabricate the pixel structure, which reduces the manufacturing cost.
  • FIG. 4 is a flowchart of a method for fabricating a bottom gate bottom contact type pixel structure 200 according to an embodiment of the present invention.
  • step 401 a substrate 21 is provided.
  • the material of the substrate 21 may be glass, polyethylene terephthalate (PEN) or the like.
  • step 402 a gate electrode layer 22 and a gate insulating layer 23 are sequentially formed on one surface of the substrate 21.
  • the gate electrode layer 22 and the gate insulating layer 23 are formed by using a conventional organic thin film transistor fabrication process, and will not be described in detail herein.
  • step 403 an ITO layer 24 and a metal layer 25 are sequentially formed on the gate insulating layer 23.
  • the ITO layer 24 and the metal layer 25 are deposited on the substrate 21 by a physical vapor deposition (PVD) film formation method according to a conventional process, and will not be described in detail herein.
  • PVD physical vapor deposition
  • the material of the metal sublayer in contact with the ITO layer 24 is a metal having a low electrical resistivity, such as aluminum (Al), chromium (Cr), copper (Cu), etc., and the material of the other metal sublayer is a metal that is not easily oxidized. Such as molybdenum (Mu), tungsten (W) and so on. In other embodiments, only one layer of metal may be deposited on the ITO layer 24.
  • the material of the metal layer 25 is a metal having a low resistivity and being less susceptible to oxidation, such as silver (Ag), aluminum (Al), or the like.
  • Step 404 coating a layer of photoresist on the metal layer 25, and passing through the mask 500 (see FIG. 5). Row exposure and development are performed to remove all of the photoresist at the position corresponding to the all-light-transmissive region 51 of the mask 50, and the light at the position corresponding to the total light-shielding region 52 of the mask 500 is retained. The photoresist is removed to remove a portion of the photoresist at a position corresponding to the semi-transmissive region 53 of the mask 500.
  • the method of performing exposure and development by the mask 500 is a prior art, and will not be described in detail herein.
  • the mask 500 can be a halftone mask or a grayscale mask.
  • step 405 the metal layer 25 and the ITO layer 24 at positions corresponding to the all-transmissive regions 51 of the mask 500 are etched away by the wet etching method.
  • Step 406 treating the substrate 21 with a plasma surface treatment to remove the photoresist remaining at the position corresponding to the semi-transmissive region 53 of the mask 500, and removing the entire substrate 11 and the mask 500. A portion of the photoresist at a position corresponding to the light-shielding region 52.
  • step 407 the metal layer 25 at the position corresponding to the semi-transmissive region 53 of the mask 500 is wet-etched, and the substrate 21 is retained at a position corresponding to the total light-shielding region 52 and the semi-transmissive region 53 of the mask.
  • the ITO layer 24 forms a source and a drain of the thin film transistor on the ITO layer 24.
  • a metal layer 25 is disposed over a portion of the ITO layer 24.
  • Step 408 removing the photoresist remaining on the substrate 21 at a position corresponding to the total light-shielding region 52 of the mask 500.
  • step 409 an organic semiconductor layer 26 is formed on the substrate 21, and an organic semiconductor pattern is formed, wherein the organic semiconductor pattern is electrically connected to the ITO layer 24 and the metal layer 25.
  • the organic semiconductor pattern can be formed by a conventional exposure, development, and etching process, and will not be described in detail herein.
  • step 410 a passivation layer 27 and a pixel electrode layer 28 are sequentially formed.
  • the passivation layer 27 and the pixel electrode layer 28 are formed by a conventional organic thin film transistor fabrication process, and will not be described in detail herein.
  • the method further includes: forming a via 29 connected to the metal layer 25 in the passivation layer 27 by an etching process.
  • Fabricating the pixel electrode layer 28 includes forming the pixel electrode layer 28 over the passivation layer 27, and the pixel electrode layer 28 is electrically connected to the metal layer 25 and the ITO layer 24 through the via hole 29.
  • the source and the drain of the organic thin film transistor are formed on the ITO layer 24, and since the metal layer 25 is provided on a portion of the ITO layer 24, the source and drain of the organic thin film transistor can be greatly reduced.
  • the contact resistance between the pole and the organic semiconductor layer 26, and further, the ITO layer 24 is matched with the metal layer 25
  • the data electrode layer disposed as an organic thin film transistor can prevent the resistance of the data conduction line in the liquid crystal display panel having the pixel structure 200 from being excessively large.
  • the present invention uses only one mask 500 to fabricate the pixel structure, which reduces the manufacturing cost.
  • the array substrate 600 in the embodiment of the present invention includes a plurality of pixel structures 100 or 200 distributed in an array.
  • a liquid crystal display panel includes an upper polarizer 71, a color filter 72, a liquid crystal layer 73, an array substrate 600, and a lower polarizer 75 which are disposed in this order from top to bottom.
  • the array substrate 600 is the array substrate 600 shown in FIG.

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Abstract

一种像素结构（100）、阵列基板、液晶显示面板及像素结构制造方法，像素结构包括像素电极层（18）及薄膜晶体管。薄膜晶体管包括栅极（16），与栅极（16）绝缘的源极和漏极以及有机半导体层（14）。像素结构还包括ITO层（12）及金属层（13），金属层（13）设置于ITO层（12）的一部分之上。ITO层（12）上形成有源极、漏极。有机半导体层（14）所形成的图案电连接于ITO（12）层及金属层（13），像素电极层（18）电连接于金属层（13）及ITO层（12）。在ITO层（12）上形成源极、漏极，并且由于ITO层（12）的一部分之上设置有金属层（13），因此，可极大减少源极、漏极与有机半导体层（14）的接触电阻，再者，将ITO层（12）搭配金属层（13）设置为有机薄膜晶体管的数据电极层，可使得液晶显示面板中的数据导通线的电阻不会过大。

Description

像素结构、阵列基板、液晶显示面板及像素结构制造方法
本发明要求2015年11月27日递交的发明名称为“像素结构、阵列基板、液晶显示面板及像素结构制造方法”的申请号201510846601.9的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，特别涉及一种像素结构、阵列基板、液晶显示面板及像素结构制造方法。
背景技术
主动矩阵型平面显示面板，例如液晶显示面板使用薄膜晶体管(thin film transistor，TFT)元件作为驱动元件。一般而言，由于无机半导体材料具有较高的载流子迁移率，因此被广泛地使用作为薄膜晶体管的半导体层的材料。相较于无机半导体材料，有机半导体材料虽然具有较低的载流子迁移率，但其具有轻薄、柔性、可低温工艺制备等特性，因此，近年来业界也在开始尝试使用有机半导体材料来制作薄膜晶体管器件。
目前，大部分有机半导体材料为P型材料，而为了使金属与有机半导体材料有较好的欧姆接触，通常会选用功函数较大的材料，如金(Au)、银(Ag)、铝(Al)、氧化铟锡(ITO)等来作为源漏电极材料，来降低金属与半导体界面的肖特基势垒高度，更有利于载流子的注入，从而有效地降低其接触电阻。Au在使用成本上会较高，所以在实际应用上较少。Ag、Al等金属容易受到后续工艺，如等离子(plasma)刻蚀的影响而受到氧化或者腐蚀，而导致与像素电极连接受到影响。而ITO目前通常作为透明的像素电极材料，具有良好的电学性能，功函数较高，且不易被氧化，目前还被广泛地应用于有机发光二极管(OLED)的阳极材料，但是其电阻率较大，因此也使得它在有机半导体薄膜晶体管元件及其阵列面板上的发展应用受到了限制。
发明内容
本发明提供一种像素结构、阵列基板、液晶显示面板及像素结构制造方法， 以减少有机薄膜晶体管的源极、漏极与有机半导体层的接触电阻。
本发明的实施方式提供的像素结构包括像素电极层及薄膜晶体管。所述薄膜晶体管包括栅极、与所述栅极绝缘的源极和漏极以及有机半导体层。所述像素结构还包括氧化铟锡层及金属层，所述金属层设置于所述氧化铟锡层的一部分之上。所述氧化铟锡层上形成有所述源极、漏极。所述有机半导体层所形成的图案电连接于所述氧化铟锡层及金属层，所述像素电极层电连接于所述金属层及氧化铟锡层。
其中，所述像素电极层通过过孔电连接于所述金属层及氧化铟锡层。
其中，所述金属层包括第一金属子层及设置于所述第一金属子层之上的第二金属子层。
本发明的实施方式还提供一种阵列基板，包括以上所述的若干像素结构。
本发明的实施方式还提供一种液晶显示面板，包括如上所述的阵列基板。
本发明的实施方式还提供一种像素结构制造方法，包括：
提供一基板；
在所述基板的一表面上依次形成一氧化铟锡层和一金属层；
在所述金属层上涂布一层光刻胶，通过掩膜版进行曝光、显影，以去除所述基板与所述掩膜版的全透光区域对应的位置上的全部的光刻胶，保留所述基板与所述掩膜版的全遮光区域对应的位置上的光刻胶，去除所述基板与所述掩膜版的半透光区域对应的位置上的部分光刻胶；
通过湿刻方法刻蚀掉所述基板与所述掩膜版的全透光区域对应的位置上的所述金属层和氧化铟锡层；
采用等离子表面处理处理所述基板，以去除所述基板与所述掩膜版的半透光区域对应的位置上残留的光刻胶，以及去除所述基板与所述掩膜版的全遮光区域对应的位置上的部分光刻胶；
湿刻掉所述基板与所述掩膜版的半透光区域对应的位置上的金属层，保留所述基板与所述掩膜版的全遮光区域、半透光区域对应的位置上的氧化铟锡层，以在所述氧化铟锡层上形成薄膜晶体管的源极、漏极；
去除所述基板与所述掩膜版的全遮光区域对应的位置上残留的光刻胶；
在所述基板上形成有机半导体层，并制作有机半导体图案，其中，所述有机半导体图案电连接于所述氧化铟锡层及金属层；以及
依次制作栅绝缘层、栅电极层、钝化层和像素电极层。
其中，所述金属层包括第一金属子层及设置于所述第一金属子层之上的第二金属子层。
其中，在制作所述像素电极层之前，还包括：通过蚀刻工艺形成连通所述钝化层及所述栅绝缘层并与所述金属层连接的过孔；制作所述像素电极层包括：在所述钝化层之上制作所述像素电极层，并且所述像素电极层通过所述过孔电连接于所述金属层及氧化铟锡层。
本发明的实施方式还提供另一种像素结构制造方法，包括：
提供一基板；
在所述基板上形成栅电极层及栅绝缘层；
在所述栅绝缘层上依次形成一氧化铟锡层和一金属层；
在所述金属层上涂布一层光刻胶，通过掩膜版进行曝光、显影，以去除所述基板与所述掩膜版的全透光区域对应的位置上的全部的光刻胶，保留所述基板与所述掩膜版的全遮光区域对应的位置上的光刻胶，去除所述基板与所述掩膜版的半透光区域对应的位置上的部分光刻胶；
通过湿刻方法刻蚀掉所述基板与所述掩膜版全透光区域对应的位置上的所述金属层和氧化铟锡层；
采用等离子表面处理处理所述基板，以去除所述基板与所述掩膜版的半透光区域对应的位置上残留的光刻胶，以及去除所述基板与所述掩膜版的全遮光区域对应的位置上的部分光刻胶；
湿刻掉所述基板与所述掩膜版的半透光区域对应的位置上的金属层，保留所述基板与所述掩膜版全遮光区域、半透光区域对应的位置上的氧化铟锡层，以在所述氧化铟锡层上形成薄膜晶体管的源极、漏极；
去除所述基板与所述掩膜版全遮光区域对应的位置上残留的光刻胶；
在所述基板上形成有机半导体层，并制作有机半导体图案，其中，所述有机半导体图案电连接于所述氧化铟锡层及金属层；以及
依次制作钝化层和像素电极层。
其中，所述金属层包括第一金属子层及设置于所述第一金属子层之上的第二金属子层。
本发明的实施方式中，在ITO层上形成有机薄膜晶体管的源极、漏极， 并且由于ITO层的一部分之上设置有金属层，因此，可极大减少有机薄膜晶体管的源极、漏极与有机半导体层的接触电阻，再者，将ITO层搭配金属层设置为有机薄膜晶体管的数据电极层，可使得具有该像素结构的液晶显示面板中的数据导通线的电阻不会过大。
进一步，本发明的实施方式中，仅采用一张掩膜版制作像素结构，降低了制作成本。
附图说明
图1为本发明实施方式中顶栅底接触型像素结构的示意图；
图2为本发明实施方式中底栅底接触型像素结构的示意图；
图3为本发明实施方式中顶栅底接触型像素结构制造方法的流程图；
图4为本发明实施方式中底栅底接触型像素结构制造方法的流程图；
图5为本发明实施方式中掩膜版的结构示意图；
图6为本发明实施方式中阵列基板的结构示意图；以及
图7为本发明实施方式中液晶显示面板的结构示意图。
具体实施方式
参考图1，图1为本发明实施方式中顶栅底接触型像素结构100的示意图。像素结构100包括基板11、氧化铟锡(ITO)层12、金属层13、有机半导体层14、栅绝缘层15、栅电极层16、钝化层17及像素电极层18。基板11的材料可为玻璃、聚苯二甲酸乙二醇酯(PEN)或其他。
ITO层12及金属层13依次设置于基板11的一表面上，金属层13设置于ITO层12的一部分之上。ITO层12上形成有有机薄膜晶体管的源极、漏极。ITO层12搭配金属层13作为有机薄膜晶体管的数据电极层。在本实施方式中，金属层13包括第一金属子层及设置于第一金属子层之上的第二金属子层。第一金属子层的材料为电阻率较低的金属，如铝(Al)、铬(Cr)、铜(Cu)等，第二金属子层的材料为不易被氧化的金属，如钼(Mu)、钨(W)等。在其他实施方式中，金属层13也可仅包括一层金属，材料为电阻率较低且不易被氧化的金属，如银(Ag)、铝(Al)等。本实施方式中，在ITO层12上形成有机薄膜晶体管的源极、漏极，并且由于ITO层12的一部分之上设置有金属层13，因此， 可极大减少有机薄膜晶体管的源极、漏极与有机半导体层14的接触电阻，再者，将ITO层12搭配金属层13设置为有机薄膜晶体管的数据电极层，可使得具有该像素结构100的液晶显示面板中的数据导通线的电阻不会过大。
本实施方式中，有机半导体层14上形成的图案电连接于ITO层12、金属层13。栅电极层16设置于栅绝缘层15之上。钝化层17设置于栅绝缘层15之上。像素结构100还包括连通钝化层17及栅绝缘层15并与金属层13连接的过孔19。像素电极层18设置于钝化层17之上并通过过孔19电连接于金属层13及ITO层12。
参考图2，图2为本发明实施方式中底栅底接触型像素结构200的示意图。像素结构200包括基板21、栅电极层22、栅绝缘层23、ITO层24、金属层25、有机半导体层26、钝化层27及像素电极层28。基板21的材料可为玻璃、聚苯二甲酸乙二醇酯(PEN)或其他。
栅电极层22及栅绝缘层23设置于基板21的一表面上。ITO层24及金属层25依次设置于栅绝缘层23之上，金属层25设置于ITO层24的一部分之上。ITO层24上形成有有机薄膜晶体管的源极、漏极。ITO层24搭配金属层25作为有机薄膜晶体管的数据电极层。在本实施方式中，金属层25包括第一金属子层及设置于第一金属子层之上的第二金属子层。第一金属子层的材料为电阻率较低的金属，如铝(Al)、铬(Cr)、铜(Cu)等，第二金属子层的材料为不易被氧化的金属，如钼(Mu)、钨(W)等。在其他实施方式中，金属层25也可仅包括一层金属，材料为电阻率较低且不易被氧化的金属，如银(Ag)、铝(Al)等。本实施方式中，在ITO层24上形成有机薄膜晶体管的源极、漏极，并且由于ITO层24的一部分之上设置有金属层25，因此，可极大减少有机薄膜晶体管的源极、漏极与有机半导体层26的接触电阻，再者，将ITO层24搭配金属层25设置为有机薄膜晶体管的数据电极层，可使得具有该像素结构200的液晶显示面板中的数据导通线的电阻不会过大。
本实施方式中，有机半导体层26上形成的图案电连接于ITO层24、金属层25。钝化层27设置于栅绝缘层23之上。像素结构200还包括形成于钝化层27并与金属层25连接的过孔29。像素电极层28设置于钝化层27之上并通过过孔29电连接于金属层25及ITO层24。
参考图3，图3为本发明实施方式中顶栅底接触型像素结构100制造方法的流程图。
步骤301，提供一基板11。
其中，基板11的材料可为玻璃、聚苯二甲酸乙二醇酯(PEN)或其他。
步骤302，在基板11的一表面依次形成一ITO层12和一金属层13。
其中，按传统制程采用物理气相沉积(PVD)成膜方法在基板11上沉积ITO层12和金属层13，在此不再详细赘述。
其中，可在ITO层12上沉积两个金属子层。与ITO层12接触的金属子层的材料为电阻率较低的金属，如铝(Al)、铬(Cr)、铜(Cu)等，另一金属子层的材料为不易被氧化的金属，如钼(Mu)、钨(W)等。在其他实施方式中，也可在ITO层12上仅沉积一层金属，金属层13的材料为电阻率较低且不易被氧化的金属，如银(Ag)、铝(Al)等。
步骤303，在金属层13上涂布一层光刻胶，通过掩膜版500(见图5)进行曝光、显影，以去除基板11与掩膜版500的全透光区域51对应的位置上的全部的光刻胶，保留基板11与掩膜版500的全遮光区域52对应的位置上的光刻胶，去除基板11与掩膜版500的半透光区域53对应的位置上的部分光刻胶。
其中，通过掩膜版500进行曝光、显影的方法为现有技术，在此不再详细赘述。掩膜版500可为半色调掩膜版或灰度掩膜版。
步骤304，通过湿刻方法刻蚀掉基板11与掩膜版500的全透光区域51对应的位置上的金属层13和ITO层12。
步骤305，采用等离子(plasma)表面处理处理基板11，以去除基板11与掩膜版500的半透光区域53对应的位置上残留的光刻胶，以及去除基板11与掩膜版500的全遮光区域52对应的位置上的部分光刻胶。
步骤306，湿刻掉基板11与掩膜版500的半透光区域53对应的位置上的金属层13，保留基板11与掩膜版的全遮光区域52、半透光区域53对应的位置上的ITO层12，以在ITO层12上形成薄膜晶体管的源极、漏极。经过此步骤后，ITO层12的一部分之上设置有金属层13。
步骤307，去除基板11与掩膜版500的全遮光区域52对应的位置上残留的光刻胶。
步骤308，在基板11上形成有机半导体层14，并制作有机半导体图案，其中，有机半导体图案电连接于ITO层12及金属层13。
其中，可通过传统的曝光、显影、刻蚀工艺制作出有机半导体图案，在此 不再详细赘述。
步骤309，依次制作栅绝缘层15、栅电极层16、钝化层17和像素电极层28。
其中，采用传统的有机薄膜晶体管的制作工艺制作栅绝缘层15、栅电极层16、钝化层17和像素电极层18，在此不再详细赘述。
其中，制作像素电极层18之前，还包括：通过蚀刻工艺形成连通钝化层17及栅绝缘层15并与金属层13连接的过孔19。制作像素电极层18包括：在钝化层17之上制作像素电极层18，并且像素电极层18通过过孔19电连接于金属层13及ITO层12。
本实施方式中，在ITO层12上形成有机薄膜晶体管的源极、漏极，并且由于ITO层12的一部分之上设置有金属层13，因此，可极大减少有机薄膜晶体管的源极、漏极与有机半导体层14的接触电阻，再者，将ITO层12搭配金属层13设置为有机薄膜晶体管的数据电极层，可使得具有该像素结构100的液晶显示面板中的数据导通线的电阻不会过大。再者，本发明仅采用一张掩膜版500制作像素结构，降低了制作成本。
参考图4，图4为本发明实施方式中底栅底接触型像素结构200制造方法的流程图。
步骤401，提供一基板21。
其中，基板21的材料可为玻璃、聚苯二甲酸乙二醇酯(PEN)或其他。
步骤402，在基板21的一表面依次形成栅电极层22及栅绝缘层23。
其中，采用传统的有机薄膜晶体管的制作工艺制作栅电极层22及栅绝缘层23，在此不再详细赘述。
步骤403，在栅绝缘层23上依次形成一ITO层24和一金属层25。
其中，按传统制程采用物理气相沉积(PVD)成膜方法在基板21上沉积ITO层24和金属层25，在此不再详细赘述。
其中，可在ITO层24上沉积两个金属子层。与ITO层24接触的金属子层的材料为电阻率较低的金属，如铝(Al)、铬(Cr)、铜(Cu)等，另一金属子层的材料为不易被氧化的金属，如钼(Mu)、钨(W)等。在其他实施方式中，也可在ITO层24上仅沉积一层金属，金属层25的材料为电阻率较低且不易被氧化的金属，如银(Ag)、铝(Al)等。
步骤404，在金属层25上涂布一层光刻胶，通过掩膜版500(见图5)进 行曝光、显影，以去除基板21与掩膜版500的全透光区域51对应的位置上的全部的光刻胶，保留基板21与掩膜版500的全遮光区域52对应的位置上的光刻胶，去除基板21与掩膜版500的半透光区域53对应的位置上的部分光刻胶。
其中，通过掩膜版500进行曝光、显影的方法为现有技术，在此不再详细赘述。掩膜版500可为半色调掩膜版或灰度掩膜版。
步骤405，通过湿刻方法刻蚀掉基板21与掩膜版500的全透光区域51对应的位置上的金属层25和ITO层24。
步骤406，采用等离子(plasma)表面处理处理基板21，以去除基板21与掩膜版500的半透光区域53对应的位置上残留的光刻胶，以及去除基板11与掩膜版500的全遮光区域52对应的位置上的部分光刻胶。
步骤407，湿刻掉基板21与掩膜版500的半透光区域53对应的位置上的金属层25，保留基板21与掩膜版的全遮光区域52、半透光区域53对应的位置上的ITO层24，以在ITO层24上形成薄膜晶体管的源极、漏极。经过此步骤之后，ITO层24的一部分之上设置有金属层25。
步骤408，去除基板21与掩膜版500的全遮光区域52对应的位置上残留的光刻胶。
步骤409，在基板21上形成有机半导体层26，并制作有机半导体图案，其中，有机半导体图案电连接于ITO层24及金属层25。
其中，可通过传统的曝光、显影、刻蚀工艺制作出有机半导体图案，在此不再详细赘述。
步骤410，依次制作钝化层27和像素电极层28。
其中，采用传统的有机薄膜晶体管的制作工艺制作钝化层27和像素电极层28，在此不再详细赘述。
其中，制作像素电极层28之前，还包括：通过蚀刻工艺在钝化层27中形成与金属层25连接的过孔29。制作像素电极层28包括：在钝化层27之上制作像素电极层28，并且像素电极层28通过过孔29与金属层25及ITO层24电连接。
本实施方式中，ITO层24上形成有有机薄膜晶体管的源极、漏极，并且由于ITO层24的一部分之上设置有金属层25，因此，可极大减少有机薄膜晶体管的源极、漏极与有机半导体层26的接触电阻，再者，将ITO层24搭配金属层25 设置为有机薄膜晶体管的数据电极层，可使得具有该像素结构200的液晶显示面板中的数据导通线的电阻不会过大。再者，本发明仅采用一张掩膜版500制作像素结构，降低了制作成本。
参考图6，本发明实施方式中的阵列基板600包括呈阵列分布的若干像素结构100或200。
参考图7，本发明实施方式中的液晶显示面板包括从上到下依次设置的上偏光片71、彩色滤光片72、液晶层73、阵列基板600及下偏光片75。阵列基板600为图6所示的阵列基板600。

Claims (14)

  1. 一种像素结构，包括像素电极层及薄膜晶体管，所述薄膜晶体管包括栅极、与所述栅极绝缘的源极和漏极以及有机半导体层，其中，所述像素结构还包括氧化铟锡层及金属层，所述金属层设置于所述氧化铟锡层的一部分之上，所述氧化铟锡层上形成有所述源极、漏极，所述有机半导体层所形成的图案电连接于所述氧化铟锡层及金属层，所述像素电极层电连接于所述金属层及氧化铟锡层。
  2. 如权利要求1所述的像素结构，其中，所述像素电极层通过过孔电连接于所述金属层及氧化铟锡层。
  3. 如权利要求1所述的像素结构，其中，所述金属层包括第一金属子层及设置于所述第一金属子层之上的第二金属子层。
  4. 一种阵列基板，包括若干像素结构，每一像素结构包括像素电极层及薄膜晶体管，所述薄膜晶体管包括栅极、与所述栅极绝缘的源极和漏极以及有机半导体层，其中，所述像素结构还包括氧化铟锡层及金属层，所述金属层设置于所述氧化铟锡层的一部分之上，所述氧化铟锡层上形成有所述源极、漏极，所述有机半导体层所形成的图案电连接于所述氧化铟锡层及金属层，所述像素电极层电连接于所述金属层及氧化铟锡层。
  5. 如权利要求4所述的阵列基板，其中，所述像素电极层通过过孔电连接于所述金属层及氧化铟锡层。
  6. 如权利要求4所述的阵列基板，其中，所述金属层包括第一金属子层及设置于所述第一金属子层之上的第二金属子层。
  7. 一种液晶显示面板，包括阵列基板，所述阵列基板包括若干像素结构，每一像素结构包括像素电极层及薄膜晶体管，所述薄膜晶体管包括栅极、与所述栅极绝缘的源极和漏极以及有机半导体层，其中，所述像素结构还包括氧化铟锡层及金属层，所述金属层设置于所述氧化铟锡层的一部分之上，所述氧化铟锡层上形成有所述源极、漏极，所述有机半导体层所形成的图案电连接于所述氧化铟锡层及金属层，所述像素电极层电连接于所述金属层及氧化铟锡层。
  8. 如权利要求7所述的液晶显示面板，其中，所述像素电极层通过过孔电连接于所述金属层及氧化铟锡层。
  9. 如权利要求7所述的液晶显示面板，其中，所述金属层包括第一金属子层及设置于所述第一金属子层之上的第二金属子层。
  10. 一种像素结构制造方法，包括：
    提供一基板；
    在所述基板的一表面上依次形成一氧化铟锡层和一金属层；
    在所述金属层上涂布一层光刻胶，通过掩膜版进行曝光、显影，以去除所述基板与所述掩膜版的全透光区域对应的位置上的全部的光刻胶，保留所述基板与所述掩膜版的全遮光区域对应的位置上的光刻胶，去除所述基板与所述掩膜版的半透光区域对应的位置上的部分光刻胶；
    通过湿刻方法刻蚀掉所述基板与所述掩膜版的全透光区域对应的位置上的所述金属层和氧化铟锡层；
    采用等离子表面处理处理所述基板，以去除所述基板与所述掩膜版的半透光区域对应的位置上残留的光刻胶，以及去除所述基板与所述掩膜版的全遮光区域对应的位置上的部分光刻胶；
    湿刻掉所述基板与所述掩膜版的半透光区域对应的位置上的金属层，保留所述基板与所述掩膜版的全遮光区域、半透光区域对应的位置上的氧化铟锡层，以在所述氧化铟锡层上形成薄膜晶体管的源极、漏极；
    去除所述基板与所述掩膜版的全遮光区域对应的位置上残留的光刻胶；
    在所述基板上形成有机半导体层，并制作有机半导体图案，其中，所述有机半导体图案电连接于所述氧化铟锡层及金属层；以及
    依次制作栅绝缘层、栅电极层、钝化层和像素电极层。
  11. 如权利要求10所述的像素结构制造方法，其中，所述金属层包括第一金属子层及设置于所述第一金属子层之上的第二金属子层。
  12. 如权利要求10所述的像素结构制造方法，其中，在制作所述像素电 极层之前，还包括：通过蚀刻工艺形成连通所述钝化层及所述栅绝缘层并与所述金属层连接的过孔；
    制作所述像素电极层包括：在所述钝化层之上制作所述像素电极层，并且所述像素电极层通过所述过孔电连接于所述金属层及氧化铟锡层。
  13. 一种像素结构制造方法，包括：
    提供一基板；
    在所述基板上形成栅电极层及栅绝缘层；
    在所述栅绝缘层上依次形成一氧化铟锡层和一金属层；
    在所述金属层上涂布一层光刻胶，通过掩膜版进行曝光、显影，以去除所述基板与所述掩膜版的全透光区域对应的位置上的全部的光刻胶，保留所述基板与所述掩膜版的全遮光区域对应的位置上的光刻胶，去除所述基板与所述掩膜版的半透光区域对应的位置上的部分光刻胶；
    通过湿刻方法刻蚀掉所述基板与所述掩膜版的全透光区域对应的位置上的所述金属层和氧化铟锡层；
    采用等离子表面处理处理所述基板，以去除所述基板与所述掩膜版的半透光区域对应的位置上残留的光刻胶，以及去除所述基板与所述掩膜版的全遮光区域对应的位置上的部分光刻胶；
    湿刻掉所述基板与所述掩膜版半透光区域对应的位置上的金属层，保留所述基板与所述掩膜版全遮光区域、半透光区域对应的位置上的氧化铟锡层，以在所述氧化铟锡层上形成薄膜晶体管的源极、漏极；
    去除所述基板与所述掩膜版全遮光区域对应的位置上残留的光刻胶；
    在所述基板上形成有机半导体层，并制作有机半导体图案，其中，所述有机半导体图案电连接于所述氧化铟锡层及金属层；以及
    依次制作钝化层和像素电极层。
  14. 如权利要求13所述的像素结构制造方法，其中，所述金属层包括第一金属子层及设置于所述第一金属子层之上的第二金属子层。
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