WO2020228078A1 - 显示装置及薄膜晶体管的制造方法 - Google Patents

显示装置及薄膜晶体管的制造方法 Download PDF

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Publication number
WO2020228078A1
WO2020228078A1 PCT/CN2019/090003 CN2019090003W WO2020228078A1 WO 2020228078 A1 WO2020228078 A1 WO 2020228078A1 CN 2019090003 W CN2019090003 W CN 2019090003W WO 2020228078 A1 WO2020228078 A1 WO 2020228078A1
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layer
substrate
film transistor
thin film
light
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PCT/CN2019/090003
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English (en)
French (fr)
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刘晋铨
林富良
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友达光电（昆山）有限公司
友达光电股份有限公司
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Priority to US17/312,706 priority Critical patent/US11664457B2/en
Publication of WO2020228078A1 publication Critical patent/WO2020228078A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to a display device and a method of manufacturing a thin film transistor in the display device, and more particularly to a display device including a light shielding layer and a method of manufacturing the thin film transistor.
  • FIG. 1A is a schematic top view of a thin film transistor structure in a conventional display device
  • FIG. 1B is a schematic cross-sectional view along A-A' of FIG. 1A
  • FIG. 1C is a schematic cross-sectional view along B-B' of FIG. 1A. As shown in FIGS.
  • the thin film transistor 10 includes a substrate 11, on which a light shielding layer 12, a buffer layer 13, a semiconductor layer 14, a gate insulating layer 15, a first metal layer 16, and The interlayer insulating layer 17 and the second metal layer 18.
  • a first heavily doped region SD and a second heavily doped region SD are formed on both sides of the semiconductor layer 14, and a channel region CH and a lightly doped region are formed between the first heavily doped region SD and the second heavily doped region SD.
  • the second metal layer 18 is electrically connected to the semiconductor layer 14 through the contact hole 19. It can be seen from FIG.
  • the conventional light shielding layer 12 and the semiconductor layer 14 are formed by patterning through two different masks, respectively.
  • the present invention provides a display device and a method for manufacturing a thin film transistor, which can effectively avoid the photoelectric effect of the thin film transistor outside the display area and reduce the number of masks in the production process.
  • the same mask is used for patterning the light shielding layer and patterning the semiconductor layer.
  • the step of patterning the semiconductor layer adopts an over-etching method.
  • the size of the patterned light shielding layer is larger than the size of the patterned semiconductor layer.
  • the light-shielding layer is a light-shielding metal layer, which can be titanium, molybdenum, chromium, iridium, aluminum, copper, silver, gold, or any combination of the foregoing.
  • the semiconductor layer may be amorphous silicon or polysilicon.
  • the thin film transistor is a thin film transistor in a display panel.
  • the thin film transistor is a thin film transistor in a multiplexer circuit or the thin film transistor is a thin film transistor in a gate drive shift register.
  • the display device of the embodiment of the present invention includes a first substrate with a first thin film transistor and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor respectively include: a light-shielding layer disposed on the second thin film transistor.
  • a substrate A substrate; a buffer layer covering the top and sides of the light-shielding layer; a semiconductor layer arranged above the buffer layer so that the buffer layer is located between the semiconductor layer and the light-shielding layer, and the semiconductor layer has a A first doped region, a second doped region and a channel region, and the channel region is located between the first doped region and the second doped region; a first insulating layer is disposed on the semiconductor Above the layer; a first metal layer is disposed above the first insulating layer, and the first metal layer and the channel region have an overlapping area in the vertical projection direction; a second insulating layer covers the first metal And a second metal layer disposed above the second insulating layer, and the second metal layer is connected to the first doped region or the second doped region; the semiconductor layer is vertically projected on the first substrate The projected area of the light shielding layer is smaller than the projected area of the light shielding layer on the first substrate.
  • the projection shape of the semiconductor layer perpendicularly projected on the first substrate is the same as the projection shape of the light shielding layer perpendicularly projected on the first substrate.
  • the first substrate has a display area and a peripheral circuit area, and the peripheral circuit area is located at the periphery of the display area, wherein the first thin film transistor is located in the display area, and the second thin film transistor Located in the peripheral circuit area.
  • a projected area of the light shielding layer of the second thin film transistor vertically projected on the first substrate is larger than a projected area of the light shielding layer of the first thin film transistor projected vertically on the first substrate.
  • the projection shape of the light shielding layer of the second thin film transistor projected vertically on the first substrate and the projection shape of the light shielding layer of the first thin film transistor projected perpendicularly on the first substrate are mutually different Not the same.
  • FIG. 1A is a schematic top view of a thin film transistor structure in a conventional display device.
  • Fig. 1B is a schematic cross-sectional view taken along A-A' of Fig. 1A.
  • Fig. 1C is a schematic cross-sectional view taken along B-B' of Fig. 1A.
  • FIG. 2A is a schematic top view of a thin film transistor structure according to an embodiment of the invention.
  • Fig. 2B is a schematic cross-sectional view taken along A-A' of Fig. 2A.
  • Fig. 2C is a schematic cross-sectional view taken along B-B' of Fig. 2A.
  • FIG. 3 is a schematic structural diagram of a display device according to an embodiment of the invention.
  • FIG. 2A is a schematic top view of a thin film transistor structure according to an embodiment of the present invention
  • FIG. 2B is a schematic cross-sectional view along A-A' of FIG. 2A
  • FIG. 2C is a schematic cross-sectional view along B-B' of FIG. 2A.
  • the manufacturing method of the thin film transistor 100 includes the following steps:
  • the light-shielding layer 120 is formed on the substrate 110, and the light-shielding layer 120 is patterned using a mask to form the patterned light-shielding layer 120.
  • the light-shielding layer 120 is a light-shielding metal layer, which can be titanium, Molybdenum, chromium, iridium, aluminum, copper, silver, gold or any combination of the above can be patterned by etching, but the present invention is not limited to this;
  • a buffer layer 130 is formed on the substrate 110, and the buffer layer 130 covers the patterned light shielding layer 120 and the substrate 110;
  • a semiconductor layer 140 is formed on the buffer layer 130.
  • the semiconductor layer 140 can be made of other semiconductor materials such as amorphous silicon and polysilicon, and the present invention is not limited thereto.
  • the semiconductor layer 140 is patterned to form the patterned semiconductor layer 140.
  • an etching method may be used when patterning the semiconductor layer 140, and the etching of the patterned semiconductor layer 140 is an over-etching method compared with the etching when the light shielding layer 120 is patterned. Therefore, it can be seen from FIGS. 2B and 2C that the light shielding layer 120 is formed under the patterned semiconductor layer 140.
  • the semiconductor layer 140 completely overlaps the light shielding layer 120, and the size of the light shielding layer 120 is larger than that of the semiconductor layer 140.
  • the projection area of the semiconductor layer 140 vertically projected on the substrate 110 is smaller than the projection area of the light shielding layer 120 vertically projected on the substrate 110.
  • the distance between the outer edge of the light shielding layer 120 and the outer edge of the semiconductor layer 140 is d, and d is, for example, 0.5 ⁇ m.
  • the size of d can also be selected according to the material and thickness of the light shielding layer 120. The present invention Not limited to this.
  • the semiconductor layer 140 is doped to form a first heavily doped region SD and a second heavily doped region SD on both sides of the semiconductor layer 140.
  • the first heavily doped region SD forms the thin film transistor 100
  • the source, the second heavily doped region SD forms the drain of the thin film transistor 100, and the channel region CH and the lightly doped region N- are formed between the first heavily doped region SD and the second heavily doped region SD;
  • a gate insulating layer 150 is formed on the substrate 110, and the gate insulating layer 150 covers the patterned semiconductor layer 140 and the substrate 110;
  • a first metal layer 160 is formed on the substrate 110.
  • the first metal layer 160 may be titanium, molybdenum, chromium, iridium, aluminum, copper, silver, gold, or any combination of the foregoing, to pattern the first metal layer 160 To form a patterned first metal layer 160, and the patterned first metal layer 160 forms a gate G of the thin film transistor 100;
  • a second metal layer 180 is formed on the substrate 110.
  • the second metal layer 180 can be titanium, molybdenum, chromium, iridium, aluminum, copper, silver, gold, or any combination of the foregoing, to pattern the second metal layer 180
  • the second metal layer 180 is electrically connected to the semiconductor layer 140 (the first heavily doped region SD or the second heavily doped region SD) through the contact hole 190. Sexual connection.
  • FIG. 3 is a schematic structural diagram of a display device according to an embodiment of the invention.
  • the display device 200 of this embodiment includes a display area 210 and a peripheral area 220 formed on a substrate (not shown in the figure), and the peripheral area 220 is arranged around the display area 210.
  • the peripheral area 220 surrounds the display area 210, but the present invention is not limited to this.
  • the peripheral area 220 is only provided on one side or both sides of the display area 210 side. Specifically, a plurality of pixel units (not shown in the figure) are arrayed in the display area 210. In the embodiment shown in FIG.
  • the display device 200 or the display area 210 has a rectangular shape, but the present invention is not limited to this. According to different designs and requirements, the display device 200 or the display area 210 may also be configured as Circle, ellipse, other irregular arcs, triangles, pentagons or other polygons. In addition, a plurality of pixel units may be arranged in an array in a manner such as aligned or staggered.
  • a multiplexer (MUX) 230, a gate drive shift register (Shift Register, SR) 240, etc. are formed in the peripheral area 220.
  • the multiplexer 230 and the gate drive shift register are one or more. Not limited to this. Among them, thin film transistors are formed in the pixel unit, the multiplexer 230 and the gate drive shift register 240, and the thin film transistors are formed by the above-mentioned manufacturing method.
  • the multiplexer 230 is composed of a plurality of thin film transistors, and the manufacturing process steps of the multiple thin film transistors of the multiplexer 230 can be formed according to the process steps of the foregoing embodiment. Therefore, the light-shielding layer and the semiconductor layer of the thin film transistor located in the peripheral region 220 pass through the same layer of mask, and further combine different etching levels to form a two-layer patterned structure with different areas. In this way, not only can the cost of a layer of mask be reduced, but also the influence of the photoelectric effect can be taken into account.
  • the gate driving shift register 240 is also composed of a plurality of thin film transistors, and the gate driving shift register 240 can also be formed through the manufacturing process steps of the above-mentioned embodiment, and will not be repeated here.
  • the functions of the pixel unit circuit and the circuits in the peripheral area are different. Therefore, the structure or size of the thin film transistor of each circuit may vary. Different design. For example, in the circuit in the peripheral area, the size of the thin film transistor is relatively larger than the size of the thin film transistor in the pixel unit circuit. Therefore, the projection area of the light shielding layer of the thin film transistor in the multiplexer 230 and the gate drive shift register 240 perpendicularly projected on the substrate is larger than the projection area of the light shielding layer of the thin film transistor in the pixel unit.
  • the layout pattern is different.
  • the shape of the thin film transistor in the multiplexer 230 and the gate drive shift register 240 is also different from the shape of the thin film transistor in the pixel unit, and the light shielding layer of the thin film transistor in the multiplexer 230 and the gate drive shift register 240 is vertical
  • the projection shape projected on the substrate and the projection shape of the light shielding layer of the thin film transistor in the pixel unit projected perpendicularly to the substrate are different.
  • the gate driving shift register 240 is disposed in the peripheral area 220, but the present invention is not limited to this. In another embodiment with a narrow frame, the gate driving shift register 240 is Set in the display area 210, the gate drive shift register 240 can also use the manufacturing process steps of the above-mentioned embodiment to form a thin film transistor, which will not be repeated here.
  • the semiconductor layer and the light-shielding layer of the thin film transistor use the same mask, a layer of mask can be reduced during the production process and the production cost can be saved.
  • the thin film transistors in the pixel unit of the display device but also the thin film transistors in the multiplexer 230 and the gate drive shift register 240 have a light-shielding layer formed under all the semiconductor layers. In this way, not only the pixels are avoided The photoelectric effect of the thin film transistor in the cell can also avoid the photoelectric effect of the thin film transistor in the multiplexer 230 and the gate drive shift register 240.
  • the semiconductor layer is formed by over-etching with respect to the light-shielding layer, the size of the light-shielding layer 120 in all directions is larger than that of the semiconductor layer, and the light-shielding layer can not only avoid the generation of the semiconductor layer in the direction perpendicular to the substrate. Photoelectric effect, and can prevent the semiconductor layer from generating photoelectric effect in all directions around the semiconductor layer.

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Abstract

本发明提供一种显示装置及薄膜晶体管的制造方法。薄膜晶体管的制造方法包括：(A)提供一基板；(B)在该基板上形成一遮光层，图案化所述遮光层，形成一图案化遮光层；(C)在该基板上形成一缓冲层；(D)在该基板上形成一半导体层，图案化所述半导体层，形成一图案化半导体层；(E)在该基板上形成一绝缘层；(F)在该基板上形成一导电层，图案化所述导电层，形成一图案化导电层；其中，图案化所述遮光层及图案化所述半导体层采用同一掩模。能有效避免显示区域之外薄膜晶体管的光电效应并减少生产过程中的掩模数量。

Description

显示装置及薄膜晶体管的制造方法 技术领域
本发明是有关于一种显示装置及显示装置中薄膜晶体管的制造方法，且特别是有关于一种包括遮光层的显示装置及其薄膜晶体管的制造方法。
背景技术
随着科技的发展，显示装置被广泛应用在许多电子产品上，如手机、平板电脑、手表等。为了提高显示质量，大尺寸、高解析度、高亮度的显示装置应运而生。
显示装置一般在制作有源元件阵列基板的过程中，会在显示区内薄膜晶体管的下方形成一层遮光层以避免薄膜晶体管发生的光电效应。图1A是现有显示装置中薄膜晶体管结构的俯视示意图，图1B是图1A沿A-A’的剖面示意图，图1C是图1A沿B-B’的剖面示意图。如图1A、1B以及图1C所示，薄膜晶体管10包括基板11，在基板11上依序形成有遮光层12、缓冲层13、半导体层14、栅极绝缘层15、第一金属层16、层间绝缘层17以及第二金属层18。其中，在半导体层14两侧形成第一重掺杂区SD以及第二重掺杂区SD，在第一重掺杂区SD以及第二重掺杂区SD之间形成沟道区CH与轻掺杂区N-，第二金属层18通过接触孔19与半导体层14实现电性连接。由图1C可以看出，现有显示装置中薄膜晶体管10的遮光层12仅仅形成在与半导体层14的沟道区CH相对应的位置，且遮光层12较半导体层14略宽。另外，现有的遮光层12和半导体层14是分别通过两个不同的掩模进行图案化所形成的。
因此，如何能有效避免显示区域之外薄膜晶体管的光电效应并减少生产过程中的掩模数量，实为需要解决的问题之一。
发明公开
为解决上述问题，本发明提供一种显示装置及薄膜晶体管的制造方法，能有效避免显示区域之外薄膜晶体管的光电效应并减少生产过程中的掩模数量。
本发明实施例的薄膜晶体管的制造方法，包括以下步骤：
(A)提供一基板；
(B)在该基板上形成一遮光层，图案化所述遮光层，形成一图案化遮光层；
(C)在该基板上形成一缓冲层；
(D)在该基板上形成一半导体层，图案化所述半导体层，形成一图案化半导体层；
(E)在该基板上形成一绝缘层；
(F)在该基板上形成一导电层，图案化所述导电层，形成一图案化导电层；
其中，图案化所述遮光层及图案化所述半导体层采用同一掩模。
上述的制造方法，其中，图案化所述半导体层的步骤采用过度蚀刻的方式。
上述的制造方法，其中，所述图案化遮光层与所述图案化半导体层完全重叠。
上述的制造方法，其中，所述图案化遮光层的尺寸比所述图案化半导体层的尺寸大。
上述的制造方法，其中，所述遮光层为遮光金属层，可以为钛、钼、铬、铱、铝、铜、银、金或上述的任意组合。
上述的制造方法，其中，所述半导体层可以为非晶硅、多晶硅。
上述的制造方法，其中，所述薄膜晶体管为显示面板中的薄膜晶体管。
上述的制造方法，其中，所述薄膜晶体管为多工电路中的薄膜晶体管或所述薄膜晶体管为栅极驱动移位寄存器中的薄膜晶体管。
本发明实施例的显示装置，包括一第一基板，具有一第一薄膜晶体管与一第二薄膜晶体管，其中该第一薄膜晶体管与该第二薄膜晶体管分别包括：一遮光层，设置于该第一基板；一缓冲层，覆盖于该遮光层的上方与侧边；一半导体层，设置于该缓冲层上方，使得该缓冲层位于该半导体层与该遮光层之间，且该半导体层具有一第一掺杂区、一第二掺杂区与一沟道区，而该沟道区位于该第一掺杂区与该第二掺杂区之间；一第一绝缘层，设置于该半导体层上方；一第一金属层，设置于该第一绝缘层上方，且该第一金属层与该沟道区在垂直投影方向上具有重叠区域；一第二绝缘层，覆盖于该第一金属层；以及一第二金属层，设置于该第二绝缘层上方，且该第二金属层与该第一掺杂区或第二掺杂区连接；该半导体层在垂直投影于该第一基板的投影面积小于该遮光层在垂直投影于该第一基板的投影面积。
上述的显示装置，其中，该半导体层在垂直投影于该第一基板的投影形状 与该遮光层在垂直投影于该第一基板的投影形状相同。
上述的显示装置，其中，该第一基板具有一显示区与一周边电路区，且该周边电路区位于该显示区的周边，其中该第一薄膜晶体管位于该显示区，而该第二薄膜晶体管位于该周边电路区。
上述的显示装置，其中，该第二薄膜晶体管的该遮光层在垂直投影于该第一基板的投影面积大于该第一薄膜晶体管的该遮光层在垂直投影于该第一基板的投影面积。
上述的显示装置，其中，该第二薄膜晶体管的该遮光层在垂直投影于该第一基板的投影形状与该第一薄膜晶体管的该遮光层在垂直投影于该第一基板的投影形状，彼此不相同。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图简要说明
图1A是现有显示装置中薄膜晶体管结构的俯视示意图。
图1B是图1A沿A-A’的剖面示意图。
图1C是图1A沿B-B’的剖面示意图。
图2A是本发明一实施例薄膜晶体管结构的俯视示意图。
图2B是图2A沿A-A’的剖面示意图。
图2C是图2A沿B-B’的剖面示意图。
图3是本发明一实施例显示装置的结构示意图。
其中，附图标记：
10、100：薄膜晶体管
11、110：基板
12、120：遮光层
13、130：缓冲层
14、140：半导体层
15、150：栅极绝缘层
16、160：第一金属层
17、170：层间绝缘层
18、180：第二金属层
19、190：接触孔
200：显示装置
210：显示区
220：周边区
230：多工器
240：栅极驱动移位寄存器
G：栅极
CH：沟道区
SD：重掺杂区
N-：轻掺杂区
实现本发明的最佳方式
下面结合附图对本发明的结构原理和工作原理作具体的描述：
图2A是本发明一实施例薄膜晶体管结构的俯视示意图，图2B是图2A沿A-A’的剖面示意图，图2C是图2A沿B-B’的剖面示意图。如图2A、图2B及图2C所示，薄膜晶体管100的制造方法包括以下步骤：
(A)提供一基板110；
(B)首先在基板110上形成遮光层120，利用一掩模对遮光层120进行图案化，形成图案化的遮光层120，本实施例中，遮光层120为遮光金属层，可以为钛、钼、铬、铱、铝、铜、银、金或上述的任意组合，可以采用蚀刻的方式进行图案化，但本发明并不以此为限；
(C)在基板110上形成缓冲层130，缓冲层130覆盖图案化的遮光层120以及基板110；
(D)在缓冲层130上形成半导体层140，半导体层140可以采用非晶硅、多晶硅等其他半导体材料制成，本发明并不以此为限。利用与图案化遮光层120相同的掩模，对半导体层140进行图案化，形成图案化的半导体层140。于本实施例中，图案化半导体层140时可采用蚀刻的方式，且图案化半导体层140的蚀刻相较于图案化遮光层120时的蚀刻为过度蚀刻方式。由此，由图2B、图2C可以看出，在图案化后的半导体层140的下方均形成有遮光层120，半 导体层140与遮光层120完全重叠，且遮光层120的尺寸较半导体层140的尺寸大，换句话说，半导体层140在垂直投影于基板110的投影面积小于遮光层120在垂直投影于基板110的投影面积。于本实施例中，遮光层120的外侧边缘与半导体层140的外侧边缘之间的距离为d，d例如为0.5μm，d的尺寸也可以根据遮光层120的材料及厚度进行选择，本发明并不以此为限。形成半导体层140之后，再对半导体层140进行掺杂，在半导体层140两侧形成第一重掺杂区SD以及第二重掺杂区SD，第一重掺杂区SD形成薄膜晶体管100的源极，第二重掺杂区SD形成薄膜晶体管100的漏极，在第一重掺杂区SD以及第二重掺杂区SD之间形成沟道区CH与轻掺杂区N-；
(E)在基板110上形成栅极绝缘层150，栅极绝缘层150覆盖图案化的半导体层140以及基板110；
(F)在基板110上形成第一金属层160，第一金属层160可以为钛、钼、铬、铱、铝、铜、银、金或上述的任意组合，对第一金属层160进行图案化，形成图案化的第一金属层160，图案化的第一金属层160形成薄膜晶体管100的栅极G；
(G)在基板110上形成层间绝缘层170；
(H)在基板110上形成第二金属层180，第二金属层180可以为钛、钼、铬、铱、铝、铜、银、金或上述的任意组合，对第二金属层180进行图案化，形成图案化的第二金属层180，在本实施例中，第二金属层180通过接触孔190与半导体层140(第一重掺杂区SD或第二重掺杂区SD)实现电性连接。
当然，形成薄膜晶体管100还有很多其他的层，本发明仅示例性的进行描述，并不以此为限。
图3是本发明一实施例显示装置的结构示意图。如图3所示，本实施例的显示装置200包括形成在基板(图中未示出)上的显示区210以及周边区220，周边区220围绕显示区210设置。于图3所示的实施例中，周边区220围绕显示区210，但本发明不以此为限，于另一实施例中，周边区220仅设置于显示区210的单侧边或双侧边。具体而言，多个像素单元(图中未示出)阵列设置于显示区210。于图3所示的实施例中，显示装置200或显示区210为矩形形状，但本发明并不以此为限，可因不同的设计与需求，显示装置200或显示区210也可设置为圆形、椭圆形、其他不规则的弧形、三角形、五边形或其他多 边形。另外，多个像素单元可为对齐或错位等方式排列成阵列。周边区220中形成有多工器(Multiplexer，MUX)230、栅极驱动移位寄存器(Shift Register，SR)240等，多工器230以及栅极驱动移位寄存器为一个或多个，本发明并不以此为限。其中，像素单元、多工器230以及栅极驱动移位寄存器240中均形成有薄膜晶体管，薄膜晶体管采用上述的制造方法所形成。
具体而言，在本实施例中，多工器230为多个薄膜晶体管所组成，且多工器230的多个薄膜晶体管的制造工艺步骤可依照上述实施例的工艺步骤来形成。因此，位于周边区220中薄膜晶体管的遮光层与半导体层是通过同一层掩模，且进一步结合不同的蚀刻程度所形成的面积不同的两层图案化结构。如此一来，不仅能够减少一层掩模的成本，也可兼顾光电效应的影响。同样的，栅极驱动移位寄存器240也为多个薄膜晶体管所组成，栅极驱动移位寄存器240也可通过上述实施例的制造工艺步骤来形成，在此不再赘述。
于本实施例的显示装置中，像素单元电路与周边区的电路(如多工器230、栅极驱动移位寄存器240等)的作用均不同，因此，各电路薄膜晶体管的结构或尺寸会有不相同的设计。举例而言，于周边区的电路中，其薄膜晶体管的尺寸会相对大于像素单元电路中薄膜晶体管的尺寸。因此，多工器230以及栅极驱动移位寄存器240中薄膜晶体管的遮光层在垂直投影于基板的投影面积大于像素单元中薄膜晶体管的遮光层在垂直投影于基板的投影面积。又或者，于周边区的电路中，其薄膜晶体管的组成层别虽与像素单元电路的薄膜晶体管的组成层别相同，但其布局图案则不相同。换言之，多工器230以及栅极驱动移位寄存器240中薄膜晶体管的形状也与像素单元中薄膜晶体管的形状不同，多工器230以及栅极驱动移位寄存器240中薄膜晶体管的遮光层在垂直投影于基板的投影形状与像素单元中薄膜晶体管的遮光层在垂直投影于基板的投影形状也不相同。
当然，周边区还设置有其他电路，例如静电放电保护电路、测试电路以及开关电路等，上述电路也是由薄膜晶体管所构成，其中的薄膜晶体管同样也可以采用上述的制造方法形成。于图3所示的实施例中，栅极驱动移位寄存器240设置于周边区220，但本发明不以此为限，于另一窄边框的实施例中，栅极驱动移位寄存器240则设置于显示区210内，其栅极驱动移位寄存器240同样可以采用上述实施例的制造工艺步骤来形成薄膜晶体管，在此不再赘述。
综上，依照本发明的实施例，由于薄膜晶体管的半导体层和遮光层采用同一掩模，因此，在生产过程中可以减少一层掩模，节约生产成本。而且，不仅显示装置像素单元中的薄膜晶体管，多工器230以及栅极驱动移位寄存器240中的薄膜晶体管也都在所有半导体层的下方均形成有遮光层，如此一来，不仅避免了像素单元中薄膜晶体管的光电效应，同时也可以避免多工器230以及栅极驱动移位寄存器240中薄膜晶体管的光电效应。另外，由于半导体层相对于遮光层采用过度蚀刻的方式形成，因此，遮光层120在各个方向上的尺寸均较半导体层的尺寸大，遮光层不仅可以在垂直于基板的方向上避免半导体层产生光电效应，而且可以在半导体层周边的各个方向上避免半导体层产生光电效应。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
工业应用性
采用本发明显示装置及薄膜晶体管的制造方法，具有以下有益效果：
能有效避免显示区域之外薄膜晶体管的光电效应并减少生产过程中的掩模数量。

Claims (13)

  1. 一种薄膜晶体管的制造方法，其特征在于，包括以下步骤：
    (A)提供一基板；
    (B)在该基板上形成一遮光层，图案化所述遮光层，形成一图案化遮光层；
    (C)在该基板上形成一缓冲层；
    (D)在该基板上形成一半导体层，图案化所述半导体层，形成一图案化半导体层；
    (E)在该基板上形成一绝缘层；
    (F)在该基板上形成一导电层，图案化所述导电层，形成一图案化导电层；
    其中，图案化所述遮光层及图案化所述半导体层采用同一掩模。
  2. 根据权利要求1所述的制造方法，其特征在于，图案化所述半导体层的步骤采用过度蚀刻的方式。
  3. 根据权利要求2所述的制造方法，其特征在于，所述图案化遮光层与所述图案化半导体层完全重叠。
  4. 根据权利要求3所述的制造方法，其特征在于，所述图案化遮光层的尺寸比所述图案化半导体层的尺寸大。
  5. 根据权利要求4所述的制造方法，其特征在于，所述遮光层为遮光金属层，可以为钛、钼、铬、铱、铝、铜、银、金或上述的任意组合。
  6. 根据权利要求5所述的制造方法，其特征在于，所述半导体层可以为非晶硅、多晶硅。
  7. 根据权利要求1所述的制造方法，其特征在于，所述薄膜晶体管为显示面板中的薄膜晶体管。
  8. 根据权利要求7所述的制造方法，其特征在于，所述薄膜晶体管为多工电路中的薄膜晶体管或所述薄膜晶体管为栅极驱动移位寄存器中的薄膜晶体管。
  9. 一种显示装置，包括：
    一第一基板，具有一第一薄膜晶体管与一第二薄膜晶体管，其中该第一薄膜晶体管与该第二薄膜晶体管分别包括：
    一遮光层，设置于该第一基板；
    一缓冲层，覆盖于该遮光层的上方与侧边；
    一半导体层，设置于该缓冲层上方，使得该缓冲层位于该半导体层与该遮光层之间，且该半导体层具有一第一掺杂区、一第二掺杂区与一沟道区，而该沟道区位于该第一掺杂区与该第二掺杂区之间；
    一第一绝缘层，设置于该半导体层上方；
    一第一金属层，设置于该第一绝缘层上方，且该第一金属层与该沟道区在垂直投影方向上具有重叠区域；
    一第二绝缘层，覆盖于该第一金属层；以及
    一第二金属层，设置于该第二绝缘层上方，且该第二金属层与该第一掺杂区或第二掺杂区连接；
    其特征在于，该半导体层在垂直投影于该第一基板的投影面积小于该遮光层在垂直投影于该第一基板的投影面积。
  10. 根据权利要求9所述的显示装置，其特征在于，该半导体层在垂直投影于该第一基板的投影形状与该遮光层在垂直投影于该第一基板的投影形状相同。
  11. 根据权利要求9所述的显示装置，其特征在于，该第一基板具有一显示区与一周边电路区，且该周边电路区位于该显示区的周边，其中该第一薄膜晶体管位于该显示区，而该第二薄膜晶体管位于该周边电路区。
  12. 根据权利要求11所述的显示装置，其特征在于，该第二薄膜晶体管的该遮光层在垂直投影于该第一基板的投影面积大于该第一薄膜晶体管的该遮光层在垂直投影于该第一基板的投影面积。
  13. 根据权利要求11所述的显示装置，其特征在于，该第二薄膜晶体管的该遮光层在垂直投影于该第一基板的投影形状与该第一薄膜晶体管的该遮光层在垂直投影于该第一基板的投影形状，彼此不相同。
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