WO2020047882A1 - 一种阵列基板及其制备方法、显示面板 - Google Patents

一种阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2020047882A1
WO2020047882A1 PCT/CN2018/105042 CN2018105042W WO2020047882A1 WO 2020047882 A1 WO2020047882 A1 WO 2020047882A1 CN 2018105042 W CN2018105042 W CN 2018105042W WO 2020047882 A1 WO2020047882 A1 WO 2020047882A1
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Prior art keywords
photoresist
gate insulating
insulating layer
passivation layer
region
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PCT/CN2018/105042
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English (en)
French (fr)
Inventor
李珊
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020047882A1 publication Critical patent/WO2020047882A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present invention relates to the technical field of display panel manufacturing, and in particular, to an array substrate, a manufacturing method thereof, and a display panel.
  • a gate, a gate insulating layer, an active layer, a source-drain electrode, a passivation layer, and a pixel electrode are required to make a thin film transistor TFT device.
  • the gate line and the source-drain line usually use metal copper wires, and the pixel electrode uses an oxide semiconductor for signal connection.
  • the gate insulating layer and the passivation layer need to be designed with a contact hole opening.
  • the thin film used for the gate insulating layer and the passivation layer is a composite film structure of silicon oxide SiOx and silicon nitride SiNx.
  • the film structure is complicated and the film quality is very different.
  • the etching time is long, resulting in irremovable by-products and abnormal contact angles (taper) after the dry etching is completed, resulting in abnormal contact resistance between the copper metal and the pixel electrode.
  • the display abnormality in the panel is affected, causing product yield and reliability issues.
  • the invention provides an array substrate, a manufacturing method thereof, and a display panel, which can avoid by-products in the contact hole etching process, improve abnormal contact angles, improve contact resistance, and thereby improve product yield.
  • the invention provides a method for preparing an array substrate.
  • the method includes the following steps:
  • Step S10 preparing a layer of photoresist on a substrate prepared with a gate, a gate insulating layer, a source and a drain, and a passivation layer;
  • Step S20 exposing the photoresist to form spaced photoresist completely removed areas and photoresist partial reserved areas, the photoresist partial reserved areas corresponding to areas where the first vias are formed, and the light
  • the area where the scoring is completely removed corresponds to the area where the second via is formed;
  • step S30 the passivation layer and the gate insulating layer are etched alternately in order of wet etching and dry etching in order to form a first via hole corresponding to the source and drain electrodes and a first via hole corresponding to the gate electrode, respectively.
  • a portion of the photomask corresponding to the photoresist completely removed area is a completely transparent area, and the photomask corresponds to the The part of the photoresist partially reserved area is a partially transparent area, and the rest of the photomask is an opaque area.
  • step S20 the method further includes the following steps:
  • step S201 after the exposure process is completed, a developing process is performed on the photoresist to remove the photoresist corresponding to a completely removed area of the photoresist, and partially retain the corresponding to a partially reserved area of the photoresist. Photoresist.
  • the step S30 includes the following steps:
  • Step S301 performing a first wet etching to etch away the passivation layer corresponding to a region where the second via is formed;
  • Step S302 performing the first dry etching to etch away the photoresist corresponding to the remaining area of the photoresist portion
  • Step S303 performing a second wet etching to partially or completely etch away the gate insulating layer corresponding to a region where the second via is formed, and to etch the gate insulating layer corresponding to a region where the first via is formed.
  • the passivation layer is etched away to form the first via hole.
  • the gate insulating layer includes at least a first gate insulating layer and a second gate insulating layer.
  • the second gate insulating layer is prepared on the first gate insulating layer.
  • the step S303 includes the following steps: step:
  • the second gate insulating layer corresponding to a region where the second via is formed is etched away, and the passivation layer corresponding to a region where the first via is formed is etched away.
  • the method further includes the following steps:
  • step S304 a second dry etching is performed, and the first gate insulating layer corresponding to a region where the second via is formed is etched away to form the second via.
  • the passivation layer includes at least a first passivation layer and a second passivation layer, and the second passivation layer is prepared on the first passivation layer.
  • the method further includes the following steps:
  • Step S40 removing the photoresist remaining on the passivation layer.
  • the invention also provides an array substrate prepared by using the above preparation method.
  • the present invention also provides a display panel including the above array substrate.
  • the beneficial effect of the present invention is that, compared with the contact hole formation method of the existing array substrate, the array substrate provided by the present invention, a method for preparing the same, and a display panel adopt a semi-permeable film method, and adopt a full exposure method at a deep hole.
  • a semi-permeable film exposure method is used to perform deep and shallow hole etching respectively.
  • the etching method is performed by a combination of wet etching and dry etching; thereby avoiding by-products in the dry etching process and improving the contact hole.
  • the contact angle is abnormal; in addition, the use of a semi-permeable film exposure method in the shallow hole reduces the damage of the source and drain copper metal by the dry etching gas during the etching process, thereby improving the contact resistance.
  • FIG. 1 is a schematic diagram of forming a contact hole by dry etching in the prior art
  • FIG. 2 is a flowchart of a method for manufacturing an array substrate according to the first embodiment of the present invention
  • 3A to 3E are schematic flowcharts of a method for manufacturing an array substrate according to the first embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an array substrate provided by Embodiment 2 of the present invention.
  • the present invention is directed to the prior art array substrate.
  • the etching time is long, irremovable by-products are generated, and the contact angle of the contact hole is abnormal, causing metal copper and pixels.
  • the electrode contact impedance is abnormal, thereby affecting the technical problem of the panel display. This embodiment can solve this defect.
  • FIG. 1 it is a schematic diagram of forming a contact hole by dry etching in the prior art.
  • a thin film transistor using a metal oxide as a semiconductor layer both the deep contact hole 10 and the shallow contact hole 11 are etched by a common exposure method.
  • the thin film used for the gate insulating layer 13 and the passivation layer 12 is silicon oxide.
  • the structure of the composite film layer of silicon and silicon nitride uses the dry etching process to etch the shallow contact hole 11 and the deep contact hole 10 of the passivation layer 12 and the gate insulating layer 13; due to the dry etching process time Long, resulting in the occurrence of by-products and abnormal contact angles between the shallow contact hole 11 and the deep contact hole 10, such as the recessed area 14 in the figure, which will cause metal signal lines (such as the gate 15 and source and drain in the figure) 16)
  • the contact impedance with the signal electrode is abnormal, which affects the display of the panel.
  • FIG. 2 is a flowchart of a method for preparing an array substrate according to the first embodiment of the present invention
  • FIGS. 3A to 3E are schematic flowcharts of a method for preparing an array substrate according to the first embodiment of the present invention; the method includes the following steps: :
  • Step S10 preparing a layer of photoresist on a substrate prepared with a gate, a gate insulating layer, a source and a drain, and a passivation layer;
  • an array substrate is provided.
  • the array substrate includes a gate 30, a gate insulating layer 31, a source and drain 32, and a passivation layer which are sequentially prepared on a base substrate (not shown in the figure). 33.
  • a layer of photoresist 34 is prepared on the surface of the passivation layer 33.
  • the gate insulating layer 31 includes a first gate insulating layer 310 prepared on the surface of the gate 30, and a first gate insulating layer 31 prepared on the surface of the gate 30.
  • the thin films used for the gate insulating layer 31 and the passivation layer 33 are both composite film layers of silicon oxide and silicon nitride.
  • Step S20 exposing the photoresist to form spaced photoresist completely removed areas and photoresist partial reserved areas, the photoresist partial reserved areas corresponding to areas where the first vias are formed, and the light
  • the area where the scoring is completely removed corresponds to the area where the second via is formed;
  • a part of the photomask 35 corresponding to the photoresist completely removed region 340 is a fully transparent region 350
  • the photomask 35 A portion corresponding to the photoresist partial reserved area 341 is a partially transparent area 351
  • the remaining portion of the photomask 35 is a non-transparent area.
  • the light transmission amount of the partially transparent region 351 of the photomask 35 is between 30% and 70%.
  • step S20 the following steps are further included:
  • step S201 after the exposure process is completed, a developing process is performed on the photoresist to remove the photoresist corresponding to a completely removed area of the photoresist, and partially retain the corresponding to a partially reserved area of the photoresist. Photoresist.
  • step S30 the passivation layer and the gate insulating layer are etched alternately in order of wet etching and dry etching in order to form a first via hole corresponding to the source and drain electrodes and a first via hole corresponding to the gate electrode, respectively.
  • step S30 includes the following steps:
  • Step S301 performing a first wet etching to etch away the passivation layer corresponding to a region where the second via is formed;
  • a first wet etching is performed with a hydrofluoric acid etching solution, and the passivation layer 33 corresponding to the area where the second via is formed is completely etched. This step does not By-products are produced.
  • Step S302 performing the first dry etching to etch away the photoresist corresponding to the remaining area of the photoresist portion
  • the photoresist 34 corresponding to the photoresist partial reserved area 341 is completely etched by a dry etching process.
  • Step S303 performing a second wet etching to partially or completely etch away the gate insulating layer corresponding to a region where the second via is formed, and to etch the gate insulating layer corresponding to a region where the first via is formed.
  • the passivation layer is etched away to form the first via hole.
  • a second wet etching is performed by using a hydrofluoric acid etching solution, and the second gate insulating layer 311 corresponding to a region where the second via is formed is etched away, and at the same time, the second gate insulating layer 311 corresponding to The passivation layer 33 (including the first passivation layer 330 and the second passivation layer 331) in the region of the first via hole is completely etched to form a first via hole communicating with the source and drain electrodes 32. 36; This step does not produce by-products.
  • step S303 the following steps are further included:
  • step S304 a second dry etching is performed, and the first gate insulating layer corresponding to a region where the second via is formed is etched away to form the second via.
  • the first gate insulating layer 310 corresponding to the area where the second via is formed is completely etched by a dry etching process to form a second via 37 that communicates with the gate 30.
  • This step does not produce by-products, and because the etching time is short, there is no damage to the source and drain electrodes 32 at the first via hole 36; the first via hole 36 and the first via hole 36 formed by the above method are used.
  • the two vias 37 were all normal.
  • the method further includes the following steps:
  • Step S40 removing the photoresist remaining on the passivation layer.
  • FIG. 4 it is a schematic structural diagram of an array substrate provided in Embodiment 2 of the present invention.
  • the array substrate provided in this embodiment includes a gate 40, a gate insulation layer 41, a source / drain 42 and a passivation layer 43 which are sequentially stacked and prepared, wherein the gate
  • the insulating layer 41 includes a first gate insulating layer 410 and a second gate insulating layer 411 prepared on the surface of the first gate insulating layer 410; that is, the passivation layer 43 in this embodiment is a layer of silicon oxide or nitrogen.
  • the silicon insulating film is a thin film
  • the gate insulating layer 41 is a composite film layer including silicon oxide and silicon nitride.
  • a photomask process and an etching process for preparing a first via hole communicating with the source and drain electrodes 42 and a second via hole communicating with the gate electrode 40 and the etching process in the first embodiment are prepared.
  • the manufacturing process is the same. For details, refer to the description in the first embodiment, and details are not described herein again.
  • the method for preparing an array substrate provided in the third embodiment of the present invention is different from the second embodiment in that the gate insulation layer of the array substrate provided in this embodiment is a layer made of silicon oxide or silicon nitride.
  • the steps before the step S303 in the first embodiment are consistent with those in this embodiment,
  • the gate insulating layer corresponding to the region where the second via is formed is completely etched, and the gate insulating layer corresponding to the region where the first via is formed is completely etched.
  • the passivation layer is completely etched, the first via hole and the second via hole are formed at the same time, and no by-products are generated.
  • the formed first via hole and the second via hole are not abnormal, so Does not cause abnormal impedance.
  • the materials of the passivation layer and the gate insulation layer in the above embodiments are not limited to silicon oxide and silicon nitride, and may also be other materials.
  • the method for preparing an array substrate further includes, but is not limited to, the following steps: preparing pixel electrodes and first signal electrodes spaced apart on the passivation layer, and the pixel electrodes pass through the first vias and drains. The electrodes are connected to each other, and the first signal electrode is connected to the gate through the second via.
  • the manufacturing method of the array substrate provided by the present invention is not limited to the preparation of the via holes corresponding to the source and drain electrodes and the corresponding gate electrodes, and can also be used to prepare other deep contact holes and shallow contact holes.
  • the present invention also provides an array substrate prepared by using the above preparation method, including a metal oxide semiconductor layer, a gate electrode, a gate insulation layer, a source and drain electrode, a passivation layer, a pixel electrode, and a first Signal electrodes, etc.
  • the present invention also provides a display panel including the above array substrate.
  • the array substrate provided by the present invention a method for preparing the same, and a display panel adopt a semi-transparent film method, and adopt a full exposure method at a deep hole, and a semi-transparent film exposure method at a shallow hole, respectively, for deep hole and shallow hole engraving.
  • Etching and etching are performed by a combination of wet etching and dry etching; thereby avoiding by-products generated during the dry etching process, the abnormality of the contact angle of the contact hole can be improved; in addition, the use of a semi-permeable film exposure method in shallow holes reduces The damage of the source and drain copper metal by the dry etching gas during the etching process is improved, thereby improving the contact resistance.

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Abstract

本发明提供一种阵列基板及其制备方法、显示面板，所述方法包括：在待制备过孔的基板上制备光刻胶并进行曝光，形成间隔的光刻胶完全去除区域以及光刻胶部分保留区域，所述光刻胶部分保留区域对应于形成浅孔的区域，所述光刻胶完全去除区域对应于形成深孔的区域；采用湿蚀刻与干蚀刻交替的方式蚀刻以形成所述浅孔与所述深孔。

Description

一种阵列基板及其制备方法、显示面板 技术领域
本发明涉及显示面板制造技术领域，尤其涉及一种阵列基板及其制备方法、显示面板。
 背景技术
在TFT-LCD面板设计中，制作薄膜晶体管TFT器件需要栅极、栅极绝缘层、有源层、源漏电极、钝化层、像素电极。栅极线和源漏极线通常使用金属铜导线，像素电极使用氧化物半导体进行信号连接，为了信号连接，需要将栅极绝缘层和钝化层进行接触孔开孔设计。
采用金属氧化物作为半导体层的薄膜晶体管中，栅极绝缘层和钝化层使用的薄膜是氧化硅SiOx和氮化硅SiNx的复合膜层结构，其膜层结构复杂且膜质差异很大，使用干刻制程进行深孔和浅孔刻蚀过程中，刻蚀时间长，导致干刻完成后，产生无法去除的副产物以及接触角（taper）异常，造成金属铜和像素电极接触阻抗异常，从而影响面板内的显示异常，造成产品的良率和信赖性问题。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明提供一种阵列基板及其制备方法、显示面板，能够避免在接触孔蚀刻制程中产生副产物，改善接触角异常，改善接触阻抗，从而提高产品良率。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种阵列基板的制备方法，所述方法包括以下步骤：
步骤S10，在制备有栅极、栅绝缘层、源漏极以及钝化层的基板上制备一层光刻胶；
步骤S20，对所述光刻胶进行曝光，形成间隔的光刻胶完全去除区域以及光刻胶部分保留区域，所述光刻胶部分保留区域对应于形成第一过孔的区域，所述光刻胶完全去除区域对应于形成第二过孔的区域；
步骤S30，依次采用湿蚀刻与干蚀刻交替的方式，对所述钝化层以及所述栅绝缘层进行蚀刻，分别形成对应所述源漏极的第一过孔与对应所述栅极的第二过孔，其中所述第一过孔的深度小于所述第二过孔的深度。
根据本发明一实施例，在所述步骤S20的曝光制程所使用的光罩中，所述光罩对应所述光刻胶完全去除区域的部位为完全透光区域，所述光罩对应所述光刻胶部分保留区域的部位为部分透光区域，所述光罩其余的部分为不透光区域。
根据本发明一实施例，所述步骤S20之后还包括以下步骤：
步骤S201，在曝光工艺完成后，对所述光刻胶进行显影制程，去除对应所述光刻胶完全去除区域的所述光刻胶，部分保留对应所述光刻胶部分保留区域的所述光刻胶。
根据本发明一实施例，所述步骤S30包括以下步骤：
步骤S301，进行第一次湿蚀刻，将对应于形成所述第二过孔的区域的所述钝化层蚀刻掉；
步骤S302，进行第一次干蚀刻，将对应所述光刻胶部分保留区域的所述光刻胶蚀刻掉；
步骤S303，进行第二次湿蚀刻，将对应于形成所述第二过孔的区域的所述栅绝缘层部分或完全蚀刻掉，以及将对应于形成所述第一过孔的区域的所述钝化层蚀刻掉，形成所述第一过孔。
根据本发明一实施例，所述栅绝缘层至少包括第一栅绝缘层与第二栅绝缘层，所述第二栅绝缘层制备于所述第一栅绝缘层上，所述步骤S303包括以下步骤：
将对应于形成所述第二过孔的区域的所述第二栅绝缘层蚀刻掉，以及将对应于形成所述第一过孔的区域的所述钝化层蚀刻掉。
根据本发明一实施例，所述步骤S303之后还包括以下步骤：
步骤S304，进行第二次干蚀刻，将对应于形成所述第二过孔的区域的所述第一栅绝缘层蚀刻掉，形成所述第二过孔。
根据本发明一实施例，所述钝化层至少包括第一钝化层与第二钝化层，所述第二钝化层制备于所述第一钝化层上。
根据本发明一实施例，在形成所述第一过孔和所述第二过孔之后，所述方法还包括以下步骤：
步骤S40，去除所述钝化层上剩余的所述光刻胶。
本发明还提供一种采用上述制备方法制备的阵列基板。
本发明还提供一种包括上述阵列基板的显示面板。
 有益效果
本发明的有益效果为：相较于现有阵列基板的接触孔形成方式，本发明提供的阵列基板及其制备方法、显示面板，通过采用半透膜的方式，在深孔处采用全部曝光方式，在浅孔处采用半透膜曝光方式，分别进行深孔和浅孔刻蚀，刻蚀方式采用湿蚀刻和干蚀刻复合方式进行；由此避免了干蚀刻过程产生副产物，可以改善接触孔的接触角异常；另外，由于在浅孔处采用半透膜曝光方式，减少了刻蚀过程中干刻蚀气体对源漏极铜金属的损伤，从而改善接触阻抗。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术采用干蚀刻形成接触孔的示意图；
图2为本发明实施例一提供的阵列基板的制备方法流程图；
图3A~3E为本发明实施例一提供的阵列基板的制备方法流程示意图；
图4为本发明实施例二提供的阵列基板的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有技术的阵列基板，在使用干刻制程进行深孔和浅孔刻蚀过程中，刻蚀时间长，产生无法去除的副产物以及接触孔的接触角异常，造成金属铜和像素电极接触阻抗异常，从而影响面板显示的技术问题，本实施例能够解决该缺陷。
如图1所示，为现有技术采用干蚀刻形成接触孔的示意图。该图在以金属氧化物作为半导体层的薄膜晶体管中，深接触孔10与浅接触孔11均采用普通曝光方式进行刻蚀；其中，栅绝缘层13和钝化层12使用的薄膜是氧化硅和氮化硅的复合膜层结构，采用干蚀刻制程对所述钝化层12以及所述栅绝缘层13进行所述浅接触孔11与所述深接触孔10的蚀刻；由于干蚀刻制程时间长，导致出现副产物以及所述浅接触孔11与所述深接触孔10的接触角的异常，如图中凹陷区域14，因此会造成金属信号线（如图中栅极15和源漏极16）和信号电极接触阻抗异常，从而影响面板的显示。
请参照图2，为本发明实施例一提供的阵列基板的制备方法流程图，以及参照图3A~3E，为本发明实施例一提供的阵列基板的制备方法流程示意图；所述方法包括以下步骤：
步骤S10，在制备有栅极、栅绝缘层、源漏极以及钝化层的基板上制备一层光刻胶；
具体地，如图3A所示，提供一阵列基板，所述阵列基板包括依次制备于衬底基板（图中未标示）上的栅极30、栅绝缘层31、源漏极32以及钝化层33，在所述钝化层33表面制备一层光刻胶34；其中，所述栅绝缘层31包括制备于所述栅极30表面的第一栅绝缘层310，以及制备于所述第一栅绝缘层310表面的第二栅绝缘层311；所述钝化层33包括制备于所述源漏极32表面的第一钝化层330，以及制备于所述第一钝化层330表面的第二钝化层331。所述栅绝缘层31和所述钝化层33使用的薄膜均为氧化硅和氮化硅的复合膜层。
步骤S20，对所述光刻胶进行曝光，形成间隔的光刻胶完全去除区域以及光刻胶部分保留区域，所述光刻胶部分保留区域对应于形成第一过孔的区域，所述光刻胶完全去除区域对应于形成第二过孔的区域；
具体如图3A所示，在所述步骤S20的曝光制程所使用的光罩35中，所述光罩35对应光刻胶完全去除区域340的部位为完全透光区域350，所述光罩35对应光刻胶部分保留区域341的部位为部分透光区域351，所述光罩35其余的部分为不透光区域。优选的，所述光罩35的所述部分透光区域351的透光量为 30%~70%之间。
所述步骤S20之后还包括以下步骤：
步骤S201，在曝光工艺完成后，对所述光刻胶进行显影制程，去除对应所述光刻胶完全去除区域的所述光刻胶，部分保留对应所述光刻胶部分保留区域的所述光刻胶。
步骤S30，依次采用湿蚀刻与干蚀刻交替的方式，对所述钝化层以及所述栅绝缘层进行蚀刻，分别形成对应所述源漏极的第一过孔与对应所述栅极的第二过孔，其中所述第一过孔的深度小于所述第二过孔的深度。
具体地，所述步骤S30包括以下步骤：
步骤S301，进行第一次湿蚀刻，将对应于形成所述第二过孔的区域的所述钝化层蚀刻掉；
如图3B所示，曝光后，先采用氢氟酸刻蚀液进行第一次湿蚀刻，将对应于形成所述第二过孔的区域的所述钝化层33蚀刻完全，此步骤不会产生副产物。
步骤S302，进行第一次干蚀刻，将对应所述光刻胶部分保留区域的所述光刻胶蚀刻掉；
如图3C所示，利用干蚀刻制程将对应所述光刻胶部分保留区域341的所述光刻胶34蚀刻完全。
步骤S303，进行第二次湿蚀刻，将对应于形成所述第二过孔的区域的所述栅绝缘层部分或完全蚀刻掉，以及将对应于形成所述第一过孔的区域的所述钝化层蚀刻掉，形成所述第一过孔。
如图3D所示，用氢氟酸刻蚀液进行第二次湿蚀刻，将对应于形成所述第二过孔的区域的所述第二栅绝缘层311蚀刻掉，同时将对应于形成所述第一过孔的区域的所述钝化层33（包括所述第一钝化层330与所述第二钝化层331）蚀刻完全，形成连通所述源漏极32的第一过孔36；此步骤不会产生副产物。
所述步骤S303之后还包括以下步骤：
步骤S304，进行第二次干蚀刻，将对应于形成所述第二过孔的区域的所述第一栅绝缘层蚀刻掉，形成所述第二过孔。
如图3E所示，利用干蚀刻制程将对应于形成所述第二过孔的区域的所述第一栅绝缘层310蚀刻完全，形成连通所述栅极30的第二过孔37。此步骤不会产生副产物，由于刻蚀时间较短，对所述第一过孔36处的所述源漏极32没有损伤；采用上述方法形成的所述第一过孔36以及所述第二过孔37均无异常。
在形成所述第一过孔36和所述第二过孔37之后，所述方法还包括以下步骤：
步骤S40，去除所述钝化层上剩余的所述光刻胶。
如图4所示，为本发明实施例二提供的阵列基板的结构示意图。本实施例与上述实施例一的区别特征在于：本实施例提供的所述阵列基板包括依次层叠制备的栅极40、栅绝缘层41、源漏极42以及钝化层43，其中所述栅绝缘层41包括第一栅绝缘层410，以及制备于所述第一栅绝缘层410表面的第二栅绝缘层411；即本实施例的所述钝化层43为一层以氧化硅或氮化硅为材料的薄膜，所述栅绝缘层41为包括氧化硅与氮化硅的复合膜层。本实施例的所述阵列基板在制备连通所述源漏极42的第一过孔，以及连通所述栅极40的第二过孔的光罩制程以及蚀刻制程与上述实施例一中的蚀刻制程相同，具体请参照上述实施例一中的描述，此处不再赘述。
本发明实施例三提供的一种阵列基板的制备方法，与上述实施例二的区别特征在于：本实施例提供的所述阵列基板的栅绝缘层为一层以氧化硅或氮化硅为材料的薄膜；在形成对应源漏极的第一过孔以及对应栅极的第二过孔的制备方法中，上述实施例一中在所述步骤S303之前的步骤与本实施例中是一致的，本实施例在上述步骤S303的第二次湿蚀刻中，将对应于形成所述第二过孔的区域的所述栅绝缘层蚀刻完全，以及将对应于形成所述第一过孔的区域的所述钝化层蚀刻完全，同时形成所述第一过孔与所述第二过孔，且不会产生副产物，形成的所述第一过孔与所述第二过孔无异常，因此不会造成阻抗异常。
当然，上述实施例中的所述钝化层与所述栅绝缘层的材料不限于氧化硅与氮化硅，还可以为其他材料。
上述实施例提供的阵列基板的制备方法还包括但不限于以下步骤：在所述钝化层上制备间隔分布的像素电极与第一信号电极，所述像素电极通过所述第一过孔与漏极相连，所述第一信号电极通过所述第二过孔与所述栅极相连。
当然，本发明提供的阵列基板的制备方法并不限于对应源漏极以及对应栅极的过孔的制备，还可用于其他深接触孔与浅接触孔的制备。
本发明还提供一种采用上述制备方法制备的阵列基板，包括依次制备于衬底基板上的金属氧化物半导体层、栅极、栅绝缘层、源漏极、钝化层、像素电极以及第一信号电极等。
本发明还提供一种包括上述阵列基板的显示面板。
本发明提供的阵列基板及其制备方法、显示面板，通过采用半透膜的方式，在深孔处采用全部曝光方式，在浅孔处采用半透膜曝光方式，分别进行深孔和浅孔刻蚀，刻蚀方式采用湿蚀刻和干蚀刻复合方式进行；由此避免了干蚀刻过程产生副产物，可以改善接触孔的接触角异常；另外，由于在浅孔处采用半透膜曝光方式，减少了刻蚀过程中干刻蚀气体对源漏极铜金属的损伤，从而改善接触阻抗。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

  1. 一种阵列基板的制备方法，其中，所述方法包括以下步骤：
    步骤S10，在制备有栅极、栅绝缘层、源漏极以及钝化层的基板上制备一层光刻胶；
    步骤S20，对所述光刻胶进行曝光，形成间隔的光刻胶完全去除区域以及光刻胶部分保留区域，所述光刻胶部分保留区域对应于形成第一过孔的区域，所述光刻胶完全去除区域对应于形成第二过孔的区域；
    步骤S30，依次采用湿蚀刻与干蚀刻交替的方式，对所述钝化层以及所述栅绝缘层进行蚀刻，分别形成对应所述源漏极的第一过孔与对应所述栅极的第二过孔，其中所述第一过孔的深度小于所述第二过孔的深度。
  2. 根据权利要求1所述的制备方法，其中，在所述步骤S20的曝光制程所使用的光罩中，所述光罩对应所述光刻胶完全去除区域的部位为完全透光区域，所述光罩对应所述光刻胶部分保留区域的部位为部分透光区域，所述光罩其余的部分为不透光区域。
  3. 根据权利要求1所述的制备方法，其中，所述步骤S20之后还包括以下步骤：
    步骤S201，在曝光工艺完成后，对所述光刻胶进行显影制程，去除对应所述光刻胶完全去除区域的所述光刻胶，部分保留对应所述光刻胶部分保留区域的所述光刻胶。
  4. 根据权利要求1所述的制备方法，其中，所述步骤S30包括以下步骤：
    步骤S301，进行第一次湿蚀刻，将对应于形成所述第二过孔的区域的所述钝化层蚀刻掉；
    步骤S302，进行第一次干蚀刻，将对应所述光刻胶部分保留区域的所述光刻胶蚀刻掉；
    步骤S303，进行第二次湿蚀刻，将对应于形成所述第二过孔的区域的所述栅绝缘层部分或完全蚀刻掉，以及将对应于形成所述第一过孔的区域的所述钝化层蚀刻掉，形成所述第一过孔。
  5. 根据权利要求4所述的制备方法，其中，所述栅绝缘层至少包括第一栅绝缘层与第二栅绝缘层，所述第二栅绝缘层制备于所述第一栅绝缘层上，所述步骤S303包括以下步骤：
    将对应于形成所述第二过孔的区域的所述第二栅绝缘层蚀刻掉，以及将对应于形成所述第一过孔的区域的所述钝化层蚀刻掉。
  6. 根据权利要求5所述的制备方法，其中，所述步骤S303之后还包括以下步骤：
    步骤S304，进行第二次干蚀刻，将对应于形成所述第二过孔的区域的所述第一栅绝缘层蚀刻掉，形成所述第二过孔。
  7. 根据权利要求1所述的制备方法，其中，所述钝化层至少包括第一钝化层与第二钝化层，所述第二钝化层制备于所述第一钝化层上。
  8. 根据权利要求1所述的制备方法，其中，在形成所述第一过孔和所述第二过孔之后，所述方法还包括以下步骤：
    步骤S40，去除所述钝化层上剩余的所述光刻胶。
  9. 一种采用权利要求1所述的制备方法制备的阵列基板。
  10. 一种包括权利要求9所述的阵列基板的显示面板。
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