WO2020124713A1 - 一种阵列基板及其制备方法 - Google Patents

一种阵列基板及其制备方法 Download PDF

Info

Publication number
WO2020124713A1
WO2020124713A1 PCT/CN2019/071579 CN2019071579W WO2020124713A1 WO 2020124713 A1 WO2020124713 A1 WO 2020124713A1 CN 2019071579 W CN2019071579 W CN 2019071579W WO 2020124713 A1 WO2020124713 A1 WO 2020124713A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
groove
display portion
intermediate groove
array substrate
Prior art date
Application number
PCT/CN2019/071579
Other languages
English (en)
French (fr)
Inventor
徐品全
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/631,198 priority Critical patent/US20210358968A1/en
Publication of WO2020124713A1 publication Critical patent/WO2020124713A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • the present application relates to the field of display manufacturing, in particular to an array substrate and a preparation method thereof.
  • the present application provides an array substrate and a preparation method thereof, which can reduce the number of times the photomask of the array substrate is used, thereby improving productivity and reducing costs.
  • the present application provides a method for preparing an array substrate.
  • the method includes the following steps:
  • Step S10 an array substrate is provided.
  • the array substrate includes a display portion and a non-display portion located on one side of the display portion, the non-display portion is provided with a curved area, and the display portion includes an A thin film transistor, the non-display portion includes a groove corresponding to the curved area and penetrating the inorganic film layer, and first signal lines on both sides of the groove;
  • Step S20 a first flat layer is prepared on the inorganic film layer, the first flat layer is filled into the groove, and the first flat layer is patterned to form the corresponding thin film transistor and the first The first flat layer via of the signal line;
  • Step S30 a metal layer is prepared on the first flat layer, and after patterning, an auxiliary electrode located on the display portion and connected to the thin film transistor through the first flat layer via hole is formed, and a non-display is formed on the non-display And connect the second signal line of the first signal line through the first flat layer via.
  • the method before the step S10, the method further includes the following steps:
  • Step S101 an active layer, a gate insulating layer, a gate, and an inter-insulating layer are sequentially prepared on the array substrate;
  • Step S102 a photomask process is performed on the inter-insulation layer and the gate insulation layer to form source and drain vias located in the display part and communicating with the active layer, and at the same time forming a penetration part located in the curved region
  • the first intermediate groove of the inorganic film layer
  • Step S103 a source-drain metal layer is prepared on the inter-insulation layer, and after patterning, a source-drain electrode located in the display portion and electrically connected to the active layer is formed, and the first electrode located in the non-display portion is formed The first signal line on both sides of an intermediate slot.
  • the method further includes the following steps:
  • Step S104 preparing a passivation layer on the source and drain and performing a patterning process to form a passivation layer via corresponding to the source and drain and the first signal line, and at the same time corresponding to the first intermediate groove Forming a second intermediate groove that penetrates the inorganic film layer and nests in the first intermediate groove, and the second intermediate groove overlaps with the first intermediate groove to form the groove.
  • a third intermediate groove penetrating the passivation layer and nesting the first intermediate groove is also formed in the curved region at the same time, The third intermediate groove, the second intermediate groove, and the first intermediate groove are superimposed to form the groove.
  • the method further includes the following steps:
  • Step S104 preparing a passivation layer on the source and drain and performing a patterning process to form a passivation layer via corresponding to the source and drain and the first signal line;
  • Step S105 patterning the remaining inorganic film layer corresponding to the first intermediate groove to form a second intermediate groove penetrating the inorganic film layer and nested in the first intermediate groove, the second The middle groove and the first middle groove are superimposed to form the groove.
  • a third intermediate groove penetrating the passivation layer and nesting the first intermediate groove is also formed in the curved region at the same time, The third intermediate groove, the second intermediate groove, and the first intermediate groove are superimposed to form the groove.
  • the method further includes the following steps:
  • Step S40 preparing and patterning a second flat layer on the auxiliary electrode to form a second flat layer via corresponding to the auxiliary electrode;
  • Step S50 preparing a patterned anode on the second flat layer, the anode is electrically connected to the auxiliary electrode through the second flat layer via, and is electrically connected to the thin film transistor via the auxiliary electrode.
  • the present application also provides an array substrate prepared by the above preparation method, the array substrate includes a display portion and a non-display portion located on a side of the display portion, the non-display portion is provided with a curved area ;
  • the display portion includes a thin film transistor in an inorganic film layer, the non-display portion includes a groove corresponding to the curved region and penetrating the inorganic film layer, and first signal lines on both sides of the groove; as well as
  • the first flat layer is provided on the inorganic film layer and filled into the groove;
  • the material of the first flat layer is an organic material.
  • the inorganic film layer includes a buffer layer, a gate insulating layer, an inter-insulating layer, and a passivation layer stacked on the flexible substrate.
  • the inorganic film layer is provided with a penetration hole in the display section Source-drain vias of the interlayer insulating layer and the gate insulating layer, the groove includes a first intermediate groove and a second intermediate groove that are superimposed and nested on each other, wherein the first intermediate groove and the source The drain vias are formed through the same mask.
  • a passivation layer via penetrating the passivation layer is formed corresponding to the source and drain of the thin film transistor and the first signal line, the second intermediate groove and the Passivation layer vias are formed through the same mask.
  • the groove further includes a third intermediate groove penetrating the passivation layer, the third intermediate groove nests the first intermediate groove, and the first intermediate groove nests The second intermediate slot is described.
  • the beneficial effects of the present application are: compared with the existing method for preparing an array substrate, the array substrate provided in the present application and the method for preparing the same, by passing the first intermediate groove of the curved area of the array substrate and the source and drain vias through the same The photomask process is formed, and the second intermediate groove and the passivation layer via are formed by the same photomask process, and then filled into the groove with a flat layer, thereby greatly reducing the number of times the photomask is used, saving production costs, and avoiding Damage to the device during multiple etching processes.
  • Example 1 is a flowchart of a method for preparing an array substrate provided in Example 1 of the present application;
  • 2A ⁇ 2B are schematic diagrams of the preparation process of the array substrate provided in Example 1 of the present application.
  • Example 3 is a flowchart of a method for preparing an array substrate provided in Example 2 of this application;
  • 4A ⁇ 4C are schematic diagrams of the preparation process of the array substrate provided in Example 2 of the present application.
  • 5A-5B are schematic diagrams of the preparation process of the array substrate provided in Example 3 of the present application.
  • the present application is directed to the manufacturing method of the array substrate in the prior art, which has the technical problems that the photomask is used many times, the production cost is high, and the device damage is easily caused in multiple etching processes. This embodiment can solve this defect.
  • FIG. 1 it is a flowchart of a method for preparing an array substrate provided in Example 1 of the present application.
  • 2A ⁇ 2B it is a schematic diagram of the preparation process of the array substrate provided in Example 1 of the present application. The method includes the following steps:
  • Step S10 an array substrate is provided.
  • the array substrate includes a display portion and a non-display portion located on one side of the display portion, the non-display portion is provided with a curved area, and the display portion includes an A thin film transistor, the non-display portion includes a groove corresponding to the curved area and penetrating the inorganic film layer, and first signal lines on both sides of the groove;
  • the array substrate includes a display portion 2a and a non-display portion 2b located on the side of the display portion 2a, and a curved area 20 is provided on the non-display portion 2b, the array substrate corresponds to the curved area
  • the part of 20 is used for bending, so as to achieve a narrow frame.
  • An inorganic film layer 22 is prepared on the flexible substrate 21 of the array substrate, a thin film transistor 23 is provided in the inorganic film layer 22 corresponding to the display portion 2a, and both sides of the curved region 20 of the non-display portion 2b
  • a first signal line 25 is provided in the inorganic film layer 22, wherein the first signal line 25 and the source and drain electrodes 231 of the thin film transistor 23 are made by the same mask.
  • first intermediate groove 241 and a second intermediate groove 242 are superimposed to form the The groove 24 of the film layer 22. That is, the preparation of the inorganic film layer 22 is completed first, and then the groove 24 is formed at the bending region 20.
  • the inorganic film layer 22 includes but is not limited to the first buffer layer 221, the second buffer layer 222, the first gate insulating layer 223, the second gate insulating layer 224, the inter-insulating layer 225 and the passivation layer 226.
  • Step S20 a first flat layer is prepared on the inorganic film layer, the first flat layer is filled into the groove, and the first flat layer is patterned to form the corresponding thin film transistor and the first The first flat layer via of the signal line;
  • a first flat layer 26 is prepared on the inorganic film layer 22, the first flat layer 26 is filled into the groove 24, and the first flat layer 26 is patterned to form a corresponding The source-drain 231 and the first flat layer via 261 of the first signal line 25.
  • the material of the first flat layer 26 is an organic material. Since the organic filling material in the groove 24 is directly filled with the first flat layer 26 in the subsequent process, a photomask process for forming the organic filling material in the groove 24 is omitted.
  • Step S30 a metal layer is prepared on the first flat layer, and after patterning, an auxiliary electrode located on the display portion and connected to the thin film transistor through the first flat layer via hole is formed, and a non-display is formed on the non-display And connect the second signal line of the first signal line through the first flat layer via.
  • a metal layer 27 is prepared on the first flat layer 26, and after the metal layer 27 is patterned with the same mask, a via hole is formed in the display portion 2a and passes through the first flat layer 261 is connected to the auxiliary electrode 271 of the source and drain 231, and a second signal line 272 is formed in the non-display portion 2b and connected to the first signal line 25 through the first flat layer via 261.
  • the method further includes the following steps:
  • Step S40 a second flat layer 28 is prepared on the auxiliary electrode 271 and patterned to form a second flat layer via 281 corresponding to the auxiliary electrode 271;
  • Step S50 a patterned anode 29 is prepared on the second flat layer 28, the anode 29 is electrically connected to the auxiliary electrode 271 through the second flat layer via 281, and is electrically connected via the auxiliary electrode 271 To the source/drain 231.
  • the pixel definition layer and the spacer which is not limited here.
  • the display section 2a adopts the form in which the auxiliary electrode 271 carries the thin film transistor 23, that is, a dual SD trace, the source and drain 231 are used as data signal traces, and the auxiliary electrode 271 is used as a high potential source Line (that is, Vdd trace);
  • the non-display portion 2b uses a two-layer trace design in which the second signal line 272 overlaps the first signal line 25 to reduce the pitch between traces,
  • the bent region 20 uses the second signal line 272, and the source electrode and the second gate are bridged between the auxiliary electrode 271 and the first gate and the second gate of the thin film transistor 23 to reduce
  • the difference between the layers of the connected metal film prevents abnormal etching.
  • the first flat layer 26 retains the first flat layer 26 in the groove 24 during the photomask process to complete the filling of the organic photoresist, thereby increasing the process capability of the bending region 20.
  • the passivation layer 226 of the curved region 20 is partially etched to form a third intermediate groove 243 penetrating the passivation layer 226, and the third The middle slot 243 nests the first middle slot 241, and the first middle slot 241 nests the second middle slot 242, thereby further increasing the bending capability of the array substrate.
  • the method for preparing an array substrate provided in Example 2 of the present application is different from the above Example 1 in that in this embodiment, the first intermediate groove of the groove is a source and drain formed on the inorganic film layer
  • the vias are formed at the same time through the same mask process, which further reduces the number of times the mask is used.
  • Step S101 an active layer, a gate insulating layer, a gate, and an inter-insulating layer are sequentially prepared on the array substrate;
  • a first buffer layer 421, a second buffer layer 422, an active layer 431, a first gate insulating layer 423, a first gate 432, and a second gate insulating layer 424 are sequentially formed on the flexible substrate 41 Second gate 433, inter-insulation layer 425.
  • Step S102 a photomask process is performed on the inter-insulation layer and the gate insulation layer to form source and drain vias located in the display part and communicating with the active layer, and at the same time forming a penetration part located in the curved region
  • the first intermediate groove of the inorganic film layer
  • a source-drain via 44 communicating with the active layer 431 is formed on the inorganic film layer 42 of the display portion 4a of the array substrate, while forming a non-display portion
  • the curved region 40 of 4b penetrates a part of the first intermediate groove 451 of the inorganic film layer 42.
  • Step S103 a source-drain metal layer is prepared on the inter-insulation layer, and after patterning, a source-drain electrode located in the display portion and electrically connected to the active layer is formed, and the first electrode located in the non-display portion is formed The first signal line on both sides of an intermediate slot.
  • a source-drain metal layer (not shown in the figure) is prepared on the inter-insulating layer 425, and the source-drain 434 in the thin film transistor 43 is formed after the same photomask process, and is formed on the first The first signal lines 46 on both sides of the middle slot 451.
  • Step S104 preparing a passivation layer on the source and drain and performing a patterning process to form a passivation layer via corresponding to the source and drain and the first signal line;
  • a passivation layer 47 is prepared on the source and drain 434 and a patterning process is performed to form a passivation layer via 471 corresponding to the source and drain 434 and the first signal line 46.
  • Step S105 patterning the remaining inorganic film layer corresponding to the first intermediate groove to form a second intermediate groove penetrating the inorganic film layer and nested in the first intermediate groove, the second The middle groove and the first middle groove are superimposed to form the groove.
  • the remaining inorganic film layer 42 at the corresponding position of the first intermediate groove 451 is patterned to form a first through groove of the inorganic film layer 42 nested in the first intermediate groove 451
  • Two intermediate grooves 452, the second intermediate groove 452 and the first intermediate groove 451 are superimposed to form the groove 45.
  • a first flat layer, an auxiliary electrode and a second signal line, a second flat layer, an anode, etc. are sequentially formed on the passivation layer 47, which will not be repeated here.
  • a first flat layer, an auxiliary electrode and a second signal line, a second flat layer, an anode, etc. are sequentially formed on the passivation layer 47, which will not be repeated here.
  • the preparation method of the array substrate provided in Embodiment 3 of the present application is different from the above Embodiment 2 in that in this embodiment, the second intermediate groove of the groove is the same as the passivation layer via through the same mask
  • the processes are formed at the same time, and the number of times of using the photomask is further reduced on the basis of the second embodiment.
  • steps S101 to S103 in the above-mentioned second embodiment are the same as the preparation method of this embodiment. For details, please refer to the description in the above-mentioned second embodiment.
  • Step S104 preparing a passivation layer on the source and drain and performing a patterning process to form a passivation layer via corresponding to the source and drain and the first signal line, and at the same time corresponding to the first intermediate groove Forming a second intermediate groove that penetrates the inorganic film layer and nests in the first intermediate groove, and the second intermediate groove overlaps with the first intermediate groove to form the groove.
  • the array substrate includes a display portion 5a and a non-display portion 5b.
  • the curved region 50 of the non-display portion 5b is formed with a first intermediate groove 531, which is prepared on the interlayer insulating layer 51 of the array substrate Passivation layer 52.
  • a photomask process is performed on the passivation layer 52, a passivation layer via 521 is formed through the same photomask process, and a second corresponding to the first intermediate groove 531 is formed in the curved region 50
  • An intermediate groove 532 is formed by superimposing the second intermediate groove 532 and the first intermediate groove 531 to form a groove 53 located in the curved region 50 and penetrating the inorganic film layer.
  • a third intermediate groove (not shown in the figure) may also be formed through the passivation layer 52 and nested in the first intermediate groove 531 in the bending area 50 at the same time ), the third intermediate groove, the second intermediate groove 532 and the first intermediate groove 531 are superimposed to form the groove 53.
  • a first flat layer, an auxiliary electrode and a second signal line, a second flat layer, an anode, etc. are sequentially formed on the passivation layer 52, which will not be repeated here.
  • a first flat layer, an auxiliary electrode and a second signal line, a second flat layer, an anode, etc. are sequentially formed on the passivation layer 52, which will not be repeated here.
  • the array substrate includes a display And a non-display portion located on the side of the display portion, the non-display portion is provided with a curved area;
  • the display portion includes a thin film transistor in an inorganic film layer, and the non-display portion includes a portion corresponding to the curved area And a groove penetrating the inorganic film layer and first signal lines on both sides of the groove; and a first flat layer disposed on the inorganic film layer and filling the groove; wherein
  • the material of the first flat layer is an organic material.
  • the groove includes a first intermediate groove and a second intermediate groove that are superimposed and nested on each other.
  • the first intermediate trench and the source-drain via are formed by the same mask.
  • the second intermediate groove and the passivation layer via are formed by the same mask.
  • the groove further includes a third intermediate groove nesting the first intermediate groove, the third intermediate groove and the second intermediate groove, and the passivation layer via are through The same mask is formed.
  • the array substrate and the preparation method thereof provided by the present application are formed by passing the first intermediate groove and the source-drain via of the curved region of the array substrate through the same photomask process, and the second intermediate groove and the passivation layer via passing the same light
  • the mask process is formed, and then filled into the groove with a flat layer, thereby greatly reducing the number of times the mask is used, saving production costs, and avoiding damage to the device during multiple etching processes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

一种阵列基板及其制备方法，该方法包括以下步骤：提供一阵列基板，其显示部（2a）一侧的非显示部（2b）设有弯曲区域（20），显示部（2a）包括无机膜层（22）和薄膜晶体管（23），非显示部（2b）包括对应弯曲区域（20）且贯穿无机膜层（22）的凹槽（24）；在无机膜层（22）上制备第一平坦层（26）并填充满凹槽（24），图案化后形成过孔（261）；再在第一平坦层（26）上制备通过过孔（261）连接薄膜晶体管（23）的辅助电极（271）。

Description

一种阵列基板及其制备方法 技术领域
本申请涉及显示制造领域，尤其涉及一种阵列基板及其制备方法。
 背景技术
在OLED柔性阵列基板设计中，在基板的弯曲区域会采用挖槽并在凹槽内进行有机材料的填充工艺，以增加基板的弯曲性能，同时在显示区会采用双SD结构一层作为Vdate的走线，另一层作为Vdd走线来减小Vdd的电压降的现象，提高产品品质。一般该类型的阵列基板在设计中需要光罩数量为14道，工艺繁琐，又由于需要较多的光罩数量，造成生产成本的提高，以及在多次的蚀刻工艺中容易造成器件的损伤。
因此，现有技术存在缺陷，急需改进。
 技术问题
本申请提供一种阵列基板及其制备方法，能够减少阵列基板的光罩使用次数，从而提高产能、减小成本。
 技术解决方案
为实现上述目的，本申请提供的技术方案如下：
本申请提供一种阵列基板的制备方法，所述方法包括以下步骤：
步骤S10，提供一阵列基板，所述阵列基板包括显示部以及位于所述显示部一侧的非显示部，所述非显示部上设有弯曲区域，所述显示部包括位于无机膜层中的薄膜晶体管，所述非显示部包括对应所述弯曲区域且贯穿所述无机膜层的凹槽，以及位于所述凹槽两侧的第一信号线；
步骤S20，在所述无机膜层上制备第一平坦层，所述第一平坦层填充至所述凹槽内，所述第一平坦层图案化后形成对应所述薄膜晶体管与所述第一信号线的第一平坦层过孔；
步骤S30，在所述第一平坦层上制备金属层，图案化后形成位于所述显示部并通过所述第一平坦层过孔连接所述薄膜晶体管的辅助电极，以及形成位于所述非显示部并通过所述第一平坦层过孔连接所述第一信号线的第二信号线。
在本申请的制备方法中，在所述步骤S10之前，所述方法还包括以下步骤：
步骤S101，所述阵列基板上依次制备有有源层、栅绝缘层、栅极以及间绝缘层；
步骤S102，对所述间绝缘层与所述栅绝缘层进行光罩制程，形成位于所述显示部且连通所述有源层的源漏极过孔，同时形成位于所述弯曲区域并贯穿部分所述无机膜层的第一中间槽；
步骤S103，在所述间绝缘层上制备源漏金属层，图案化后形成位于所述显示部且电连接所述有源层的源漏极，以及形成位于所述非显示部的所述第一中间槽两侧的所述第一信号线。
在本申请的制备方法中，所述方法还包括以下步骤：
步骤S104，在所述源漏极上制备钝化层并进行图案化制程，形成对应所述源漏极与所述第一信号线的钝化层过孔，同时在对应所述第一中间槽的位置形成贯穿所述无机膜层并嵌套于所述第一中间槽中的第二中间槽，所述第二中间槽与所述第一中间槽叠加后形成所述凹槽。
在本申请的制备方法中，所述钝化层的所述图案化制程中，在所述弯曲区域还同时形成贯穿所述钝化层并嵌套所述第一中间槽的第三中间槽，所述第三中间槽、所述第二中间槽以及所述第一中间槽叠加后形成所述凹槽。
在本申请的制备方法中，所述方法还包括以下步骤：
步骤S104，在所述源漏极上制备钝化层并进行图案化制程，形成对应所述源漏极与所述第一信号线的钝化层过孔；
步骤S105，对对应所述第一中间槽的剩余所述无机膜层进行图案化，形成贯穿所述无机膜层并嵌套于所述第一中间槽中的第二中间槽，所述第二中间槽与所述第一中间槽叠加后形成所述凹槽。
在本申请的制备方法中，在所述步骤S104的所述图案化制程中，在所述弯曲区域还同时形成贯穿所述钝化层并嵌套所述第一中间槽的第三中间槽，所述第三中间槽、所述第二中间槽以及所述第一中间槽叠加后形成所述凹槽。
在本申请的制备方法中，所述方法还包括以下步骤：
步骤S40，在所述辅助电极上制备第二平坦层并进行图案化，形成对应所述辅助电极的第二平坦层过孔；
步骤S50，在所述第二平坦层上制备图案化的阳极，所述阳极通过所述第二平坦层过孔电连接所述辅助电极，并经由所述辅助电极电连接至所述薄膜晶体管。
为实现上述目的，本申请还提供一种采用上述制备方法制备的阵列基板，所述阵列基板包括显示部以及位于所述显示部一侧的非显示部，所述非显示部上设有弯曲区域；
所述显示部包括位于无机膜层中的薄膜晶体管，所述非显示部包括对应所述弯曲区域且贯穿所述无机膜层的凹槽，以及位于所述凹槽两侧的第一信号线；以及
第一平坦层，设置于所述无机膜层上，且填充至所述凹槽内；
其中，所述第一平坦层的材料为有机材料。
在本申请的阵列基板中，所述无机膜层包括层叠设置于柔性基板上的缓冲层、栅绝缘层、间绝缘层以及钝化层，所述无机膜层在所述显示部设有贯穿所述间绝缘层与所述栅绝缘层的源漏极过孔，所述凹槽包括相互叠加并嵌套的第一中间槽与第二中间槽，其中，所述第一中间槽与所述源漏极过孔是通过同一道光罩形成的。
在本申请的阵列基板中，对应所述薄膜晶体管的源漏极以及所述第一信号线的位置形成有贯穿所述钝化层的钝化层过孔，所述第二中间槽与所述钝化层过孔是通过同一道光罩形成的。
在本申请的阵列基板中，所述凹槽还包括贯穿所述钝化层的第三中间槽，所述第三中间槽嵌套所述第一中间槽，所述第一中间槽嵌套所述第二中间槽。
 有益效果
本申请的有益效果为：相较于现有的阵列基板的制备方法，本申请提供的阵列基板及其制备方法，通过将阵列基板的弯曲区域的第一中间槽与源漏极过孔通过同一道光罩制程形成，以及第二中间槽与钝化层过孔通过同一道光罩制程形成，然后再用平坦层一道填充至凹槽内，从而大大减少光罩的使用次数，节省生产成本，以及避免多次的蚀刻工艺中对器件的损伤。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例一提供的阵列基板的制备方法流程图；
图2A~2B为本申请实施例一提供的阵列基板的制备过程示意图；
图3为本申请实施例二提供的阵列基板的制备方法流程图；
图4A~4C为本申请实施例二提供的阵列基板的制备过程示意图；
图5A~5B为本申请实施例三提供的阵列基板的制备过程示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有技术的阵列基板的制备方法，存在光罩使用次数较多，生产成本较高，以及在多次的蚀刻工艺中容易造成器件损伤的技术问题，本实施例能够解决该缺陷。
如图1所示，为本申请实施例一提供的阵列基板的制备方法流程图。并结合图2A~2B所示，为本申请实施例一提供的阵列基板的制备过程示意图。所述方法包括以下步骤：
步骤S10，提供一阵列基板，所述阵列基板包括显示部以及位于所述显示部一侧的非显示部，所述非显示部上设有弯曲区域，所述显示部包括位于无机膜层中的薄膜晶体管，所述非显示部包括对应所述弯曲区域且贯穿所述无机膜层的凹槽，以及位于所述凹槽两侧的第一信号线；
结合图2A所示，阵列基板包括显示部2a以及位于所述显示部2a一侧的非显示部2b，且所述非显示部2b上设有弯曲区域20，所述阵列基板对应所述弯曲区域20的部分用于弯折，从而实现窄边框化。所述阵列基板的柔性基板21上制备有无机膜层22，对应所述显示部2a的所述无机膜层22中设有薄膜晶体管23，所述非显示部2b的所述弯曲区域20两侧的所述无机膜层22中设有第一信号线25，其中，所述第一信号线25与所述薄膜晶体管23中的源漏极231是通过同一道光罩制成的。
之后，采用两道光罩工艺在所述弯曲区域20处分别形成第一中间槽241和第二中间槽242，所述第一中间槽241和所述第二中间槽242叠加后形成贯穿所述无机膜层22的凹槽24。即先完成所述无机膜层22的制备，再在所述弯曲区域20处形成所述凹槽24。
在本实施例中，所述无机膜层22包括但不限于第一缓冲层221、第二缓冲层222、第一栅绝缘层223、第二栅绝缘层224、间绝缘层225以及钝化层226。
步骤S20，在所述无机膜层上制备第一平坦层，所述第一平坦层填充至所述凹槽内，所述第一平坦层图案化后形成对应所述薄膜晶体管与所述第一信号线的第一平坦层过孔；
如图2A所示，在所述无机膜层22上制备第一平坦层26，所述第一平坦层26填充至所述凹槽24内，所述第一平坦层26图案化后形成对应所述源漏极231与所述第一信号线25的第一平坦层过孔261。
其中，所述第一平坦层26的材料为有机材料。由于所述凹槽24内的有机填充材料直接采用后续制程的所述第一平坦层26进行填充，因此，省去了一道形成所述凹槽24内的有机填充材料的光罩工艺。
步骤S30，在所述第一平坦层上制备金属层，图案化后形成位于所述显示部并通过所述第一平坦层过孔连接所述薄膜晶体管的辅助电极，以及形成位于所述非显示部并通过所述第一平坦层过孔连接所述第一信号线的第二信号线。
结合图2B所示，在所述第一平坦层26上制备金属层27，所述金属层27经同一道光罩图案化后，形成位于所述显示部2a并通过所述第一平坦层过孔261连接所述源漏极231的辅助电极271，以及形成位于所述非显示部2b并通过所述第一平坦层过孔261连接所述第一信号线25的第二信号线272。
结合图2B所示，所述方法还包括以下步骤：
步骤S40，在所述辅助电极271上制备第二平坦层28并进行图案化，形成对应所述辅助电极271的第二平坦层过孔281；
步骤S50，在所述第二平坦层28上制备图案化的阳极29，所述阳极29通过所述第二平坦层过孔281电连接所述辅助电极271，并经由所述辅助电极271电连接至所述源漏极231。当然，还可以继续制备像素定义层以及间隔垫，此处不做限制。
由于所述显示部2a采用所述辅助电极271搭载所述薄膜晶体管23的形式，即双SD走线，所述源漏极231用作数据信号走线，所述辅助电极271用作高电位源线（即Vdd走线）；所述非显示部2b采用所述第二信号线272搭接所述第一信号线25的双层走线设计以减小走线之间间距（Pitch），在所述弯曲区域20采用所述第二信号线272，所述辅助电极271与所述薄膜晶体管23中的第一栅极以及第二栅极之间采用所述源漏极进行桥接，以减小相连金属膜层间段差，防止出现蚀刻异常。所述第一平坦层26在光罩制程中保留所述凹槽24内的所述第一平坦层26以完成有机光阻的填充，从而增加所述弯曲区域20的制程能力。
另外，在所述钝化层226蚀刻过程中，对所述弯曲区域20的所述钝化层226进行部分蚀刻，形成贯穿所述钝化层226的第三中间槽243，且所述第三中间槽243嵌套所述第一中间槽241，所述第一中间槽241嵌套所述第二中间槽242，从而进一步增加所述阵列基板的弯曲能力。
本申请实施例二提供的阵列基板的制备方法，与上述实施例一的区别在于：在本实施例中，所述凹槽的第一中间槽是与所述无机膜层上形成的源漏极过孔经同一道光罩工艺同时形成的，进一步减少了光罩的使用次数。
具体如图3所示，在上述实施例一的所述步骤S10之前还包括以下步骤：
步骤S101，所述阵列基板上依次制备有有源层、栅绝缘层、栅极以及间绝缘层；
参照图4A所示，在柔性基板41上依次形成第一缓冲层421、第二缓冲层422、有源层431、第一栅绝缘层423、第一栅极432、第二栅绝缘层424、第二栅极433、间绝缘层425。
步骤S102，对所述间绝缘层与所述栅绝缘层进行光罩制程，形成位于所述显示部且连通所述有源层的源漏极过孔，同时形成位于所述弯曲区域并贯穿部分所述无机膜层的第一中间槽；
如图4A所示，经过一道光罩制程之后，在所述阵列基板的显示部4a的无机膜层42上形成连通所述有源层431的源漏极过孔44，同时形成位于非显示部4b的弯曲区域40且贯穿部分所述无机膜层42的第一中间槽451。
步骤S103，在所述间绝缘层上制备源漏金属层，图案化后形成位于所述显示部且电连接所述有源层的源漏极，以及形成位于所述非显示部的所述第一中间槽两侧的所述第一信号线。
如图4B所示，在所述间绝缘层425上制备源漏金属层（图中未标示），经同一道光罩工艺后形成薄膜晶体管43中的源漏极434，以及形成位于所述第一中间槽451两侧的第一信号线46。
步骤S104，在所述源漏极上制备钝化层并进行图案化制程，形成对应所述源漏极与所述第一信号线的钝化层过孔；
如图4B所示，在所述源漏极434上制备钝化层47并进行图案化制程，形成对应所述源漏极434与所述第一信号线46的钝化层过孔471。
步骤S105，对对应所述第一中间槽的剩余所述无机膜层进行图案化，形成贯穿所述无机膜层并嵌套于所述第一中间槽中的第二中间槽，所述第二中间槽与所述第一中间槽叠加后形成所述凹槽。
如图4C所示，对所述第一中间槽451对应位置的剩余所述无机膜层42进行图案化，形成贯穿所述无机膜层42并嵌套于所述第一中间槽451中的第二中间槽452，所述第二中间槽452与所述第一中间槽451叠加后形成所述凹槽45。
之后，在所述钝化层47上依次形成第一平坦层、辅助电极与第二信号线、第二平坦层、阳极等，此处不再赘述，具体请参照上述实施例一中的描述。
本申请实施例三提供的阵列基板的制备方法，与上述实施例二的区别在于：在本实施例中，所述凹槽的第二中间槽是与所述钝化层过孔经同一道光罩工艺同时形成的，在上述实施例二的基础上又进一步减少了光罩的使用次数。
上述实施例二中所述步骤S101~S103与本实施例的制备方法相同，具体可参照上述实施例二中描述，本实施例在形成上述步骤S103中所述的阵列基板后，转接至如下步骤:
步骤S104，在所述源漏极上制备钝化层并进行图案化制程，形成对应所述源漏极与所述第一信号线的钝化层过孔，同时在对应所述第一中间槽的位置形成贯穿所述无机膜层并嵌套于所述第一中间槽中的第二中间槽，所述第二中间槽与所述第一中间槽叠加后形成所述凹槽。
参照图5A所示，所述阵列基板包括显示部5a以及非显示部5b，所述非显示部5b的弯曲区域50形成有第一中间槽531，在所述阵列基板的间绝缘层51上制备钝化层52。
参照图5B所示，对所述钝化层52进行光罩制程，经过同一道光罩工艺形成钝化层过孔521，同时在所述弯曲区域50形成对应所述第一中间槽531的第二中间槽532，所述第二中间槽532与所述第一中间槽531叠加后形成位于所述弯曲区域50并贯穿无机膜层的凹槽53。
当然，在所述步骤S104的图案化制程中，在所述弯曲区域50还可以同时形成贯穿所述钝化层52并嵌套所述第一中间槽531的第三中间槽（图中未标示），所述第三中间槽、所述第二中间槽532以及所述第一中间槽531叠加后形成所述凹槽53。
之后，在所述钝化层52上依次形成第一平坦层、辅助电极与第二信号线、第二平坦层、阳极等，此处不再赘述，具体请参照上述实施例一中的描述。
本申请还提供一种采用上述制备方法制备的阵列基板，请参照上述实施例中的描述，以及图2A~2B、或图4A~4C、或者图5A~5B所示，所述阵列基板包括显示部以及位于所述显示部一侧的非显示部，所述非显示部上设有弯曲区域；所述显示部包括位于无机膜层中的薄膜晶体管，所述非显示部包括对应所述弯曲区域且贯穿所述无机膜层的凹槽，以及位于所述凹槽两侧的第一信号线；以及第一平坦层，设置于所述无机膜层上，且填充至所述凹槽内；其中，所述第一平坦层的材料为有机材料。所述凹槽包括相互叠加并嵌套的第一中间槽与第二中间槽。
在一种实施例中，所述第一中间槽与所述源漏极过孔是通过同一道光罩形成的。
在一种实施例中，所述第二中间槽与所述钝化层过孔是通过同一道光罩形成的。
在一种实施例中，所述凹槽还包括嵌套所述第一中间槽的第三中间槽，所述第三中间槽与所述第二中间槽以及所述钝化层过孔是通过同一道光罩形成的。
本申请提供的阵列基板及其制备方法，通过将阵列基板的弯曲区域的第一中间槽与源漏极过孔通过同一道光罩制程形成，以及第二中间槽与钝化层过孔通过同一道光罩制程形成，然后再用平坦层一道填充至凹槽内，从而大大减少光罩的使用次数，节省生产成本，以及避免多次的蚀刻工艺中对器件的损伤。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (11)

  1. 一种阵列基板的制备方法，其中，所述方法包括以下步骤：
    步骤S10，提供一阵列基板，所述阵列基板包括显示部以及位于所述显示部一侧的非显示部，所述非显示部上设有弯曲区域，所述显示部包括位于无机膜层中的薄膜晶体管，所述非显示部包括对应所述弯曲区域且贯穿所述无机膜层的凹槽，以及位于所述凹槽两侧的第一信号线；
    步骤S20，在所述无机膜层上制备第一平坦层，所述第一平坦层填充至所述凹槽内，所述第一平坦层图案化后形成对应所述薄膜晶体管与所述第一信号线的第一平坦层过孔；
    步骤S30，在所述第一平坦层上制备金属层，图案化后形成位于所述显示部并通过所述第一平坦层过孔连接所述薄膜晶体管的辅助电极，以及形成位于所述非显示部并通过所述第一平坦层过孔连接所述第一信号线的第二信号线。
  2. 根据权利要求1所述的制备方法，其中，在所述步骤S10之前，所述方法还包括以下步骤：
    步骤S101，所述阵列基板上依次制备有有源层、栅绝缘层、栅极以及间绝缘层；
    步骤S102，对所述间绝缘层与所述栅绝缘层进行光罩制程，形成位于所述显示部且连通所述有源层的源漏极过孔，同时形成位于所述弯曲区域并贯穿部分所述无机膜层的第一中间槽；
    步骤S103，在所述间绝缘层上制备源漏金属层，图案化后形成位于所述显示部且电连接所述有源层的源漏极，以及形成位于所述非显示部的所述第一中间槽两侧的所述第一信号线。
  3. 根据权利要求2所述的制备方法，其中，所述方法还包括以下步骤：
    步骤S104，在所述源漏极上制备钝化层并进行图案化制程，形成对应所述源漏极与所述第一信号线的钝化层过孔，同时在对应所述第一中间槽的位置形成贯穿所述无机膜层并嵌套于所述第一中间槽中的第二中间槽，所述第二中间槽与所述第一中间槽叠加后形成所述凹槽。
  4. 根据权利要求3所述的制备方法，其中，所述钝化层的所述图案化制程中，在所述弯曲区域还同时形成贯穿所述钝化层并嵌套所述第一中间槽的第三中间槽，所述第三中间槽、所述第二中间槽以及所述第一中间槽叠加后形成所述凹槽。
  5. 根据权利要求2所述的制备方法，其中，所述方法还包括以下步骤：
    步骤S104，在所述源漏极上制备钝化层并进行图案化制程，形成对应所述源漏极与所述第一信号线的钝化层过孔；
    步骤S105，对对应所述第一中间槽的剩余所述无机膜层进行图案化，形成贯穿所述无机膜层并嵌套于所述第一中间槽中的第二中间槽，所述第二中间槽与所述第一中间槽叠加后形成所述凹槽。
  6. 根据权利要求5所述的制备方法，其中，在所述步骤S104的所述图案化制程中，在所述弯曲区域还同时形成贯穿所述钝化层并嵌套所述第一中间槽的第三中间槽，所述第三中间槽、所述第二中间槽以及所述第一中间槽叠加后形成所述凹槽。
  7. 根据权利要求1所述的制备方法，其中，所述方法还包括以下步骤：
    步骤S40，在所述辅助电极上制备第二平坦层并进行图案化，形成对应所述辅助电极的第二平坦层过孔；
    步骤S50，在所述第二平坦层上制备图案化的阳极，所述阳极通过所述第二平坦层过孔电连接所述辅助电极，并经由所述辅助电极电连接至所述薄膜晶体管。
  8. 一种如权利要求1所述的制备方法制备的阵列基板，其中，所述阵列基板包括显示部以及位于所述显示部一侧的非显示部，所述非显示部上设有弯曲区域；
    所述显示部包括位于无机膜层中的薄膜晶体管，所述非显示部包括对应所述弯曲区域且贯穿所述无机膜层的凹槽，以及位于所述凹槽两侧的第一信号线；以及
    第一平坦层，设置于所述无机膜层上，且填充至所述凹槽内；
    其中，所述第一平坦层的材料为有机材料。
  9. 根据权利要求8所述的阵列基板，其中，所述无机膜层包括层叠设置于柔性基板上的缓冲层、栅绝缘层、间绝缘层以及钝化层，所述无机膜层在所述显示部设有贯穿所述间绝缘层与所述栅绝缘层的源漏极过孔，所述凹槽包括相互叠加并嵌套的第一中间槽与第二中间槽，其中，所述第一中间槽与所述源漏极过孔是通过同一道光罩形成的。
  10. 根据权利要求9所述的阵列基板，其中，对应所述薄膜晶体管的源漏极以及所述第一信号线的位置形成有贯穿所述钝化层的钝化层过孔，所述第二中间槽与所述钝化层过孔是通过同一道光罩形成的。
  11. 根据权利要求9所述的阵列基板，其中，所述凹槽还包括贯穿所述钝化层的第三中间槽，所述第三中间槽嵌套所述第一中间槽，所述第一中间槽嵌套所述第二中间槽。
PCT/CN2019/071579 2018-12-17 2019-01-14 一种阵列基板及其制备方法 WO2020124713A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/631,198 US20210358968A1 (en) 2018-12-17 2019-01-14 Array substrate and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811544629.7 2018-12-17
CN201811544629.7A CN109659322B (zh) 2018-12-17 2018-12-17 一种阵列基板及其制备方法

Publications (1)

Publication Number Publication Date
WO2020124713A1 true WO2020124713A1 (zh) 2020-06-25

Family

ID=66113286

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/071579 WO2020124713A1 (zh) 2018-12-17 2019-01-14 一种阵列基板及其制备方法

Country Status (3)

Country Link
US (1) US20210358968A1 (zh)
CN (1) CN109659322B (zh)
WO (1) WO2020124713A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112259579A (zh) * 2020-10-10 2021-01-22 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制作方法
CN112259579B (zh) * 2020-10-10 2024-06-07 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制作方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110429107B (zh) * 2019-07-05 2021-04-27 武汉华星光电半导体显示技术有限公司 一种柔性显示面板及其制备方法
CN110534475A (zh) * 2019-08-19 2019-12-03 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制作方法、显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103928456A (zh) * 2013-12-26 2014-07-16 上海中航光电子有限公司 一种阵列基板、显示面板及显示器
CN104915052A (zh) * 2015-04-24 2015-09-16 武汉华星光电技术有限公司 触控显示装置及其制备方法、电子设备
US20180006098A1 (en) * 2016-07-04 2018-01-04 Samsung Display Co., Ltd. Organic light-emitting display device and manufacturing method thereof
CN108550612A (zh) * 2018-05-29 2018-09-18 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103928456A (zh) * 2013-12-26 2014-07-16 上海中航光电子有限公司 一种阵列基板、显示面板及显示器
CN104915052A (zh) * 2015-04-24 2015-09-16 武汉华星光电技术有限公司 触控显示装置及其制备方法、电子设备
US20180006098A1 (en) * 2016-07-04 2018-01-04 Samsung Display Co., Ltd. Organic light-emitting display device and manufacturing method thereof
CN107579076A (zh) * 2016-07-04 2018-01-12 三星显示有限公司 有机发光显示装置及其制造方法
CN108550612A (zh) * 2018-05-29 2018-09-18 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112259579A (zh) * 2020-10-10 2021-01-22 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制作方法
CN112259579B (zh) * 2020-10-10 2024-06-07 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制作方法

Also Published As

Publication number Publication date
CN109659322A (zh) 2019-04-19
US20210358968A1 (en) 2021-11-18
CN109659322B (zh) 2020-12-08

Similar Documents

Publication Publication Date Title
US11121199B1 (en) Display panel and manufacturing method for the same
US8633066B2 (en) Thin film transistor with reduced edge slope angle, array substrate and having the thin film transistor and manufacturing method thereof
TWI453516B (zh) 畫素結構及其製作方法
WO2020042235A1 (zh) 柔性oled显示面板
WO2020015071A1 (zh) 阵列基板及其制作方法
US9971220B2 (en) COA substrate and manufacturing method thereof
WO2022000699A1 (zh) Oled显示面板及其制备方法
US20180061870A1 (en) Thin film transistor and method of fabricating the same, array substrate and display apparatus
US9450103B2 (en) Thin film transistor, method for manufacturing the same, display device and electronic product
JP2015514321A (ja) Ｔｆｔ、該ｔｆｔを製造するマスク、アレイ基板及び表示装置
WO2020253031A1 (zh) 一种阵列基板及其制备方法
WO2020077861A1 (zh) 一种阵列基板及其制备方法
CN103681514B (zh) 阵列基板及其制作方法、显示装置
WO2021114368A1 (zh) 显示面板及其制备方法
WO2020124713A1 (zh) 一种阵列基板及其制备方法
WO2018205524A1 (zh) 一种阵列基板及其制作方法、显示装置
US9799683B2 (en) Array substrate, preparation method thereof and display device
WO2022027741A1 (zh) 阵列基板、其制备方法以及显示面板
WO2016155203A1 (zh) 显示基板及其制造方法和显示装置
WO2021026990A1 (zh) 一种阵列基板及其制作方法
WO2023039934A1 (zh) 显示面板及显示面板的制造方法、显示终端
WO2019161603A1 (zh) 阵列基板、显示面板以及阵列基板的制作方法
WO2021248609A1 (zh) 一种阵列基板及其制备方法以及显示面板
WO2020047882A1 (zh) 一种阵列基板及其制备方法、显示面板
WO2020133851A1 (zh) 阵列基板及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19900926

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19900926

Country of ref document: EP

Kind code of ref document: A1