WO2019161603A1 - 阵列基板、显示面板以及阵列基板的制作方法 - Google Patents

阵列基板、显示面板以及阵列基板的制作方法 Download PDF

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WO2019161603A1
WO2019161603A1 PCT/CN2018/082797 CN2018082797W WO2019161603A1 WO 2019161603 A1 WO2019161603 A1 WO 2019161603A1 CN 2018082797 W CN2018082797 W CN 2018082797W WO 2019161603 A1 WO2019161603 A1 WO 2019161603A1
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layer
pixel electrode
electrode layer
forming
drain
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French (fr)
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陈辰
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武汉华星光电技术有限公司
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/41725—Source or drain electrodes for field effect devices
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Definitions

  • the flat layer is provided with a common electrode layer
  • the common electrode layer is provided with a passivation layer
  • the passivation layer covers the common electrode layer and sidewalls of the first through hole
  • the pixel electrode layer is disposed on the layer, the pixel electrode layer covers the passivation layer, and the pixel electrode layer is in contact with the drain through the first via hole.
  • step 1 a substrate 10 is provided.
  • a source 202 and a drain 201 are formed on the dielectric insulating layer 100, wherein the drain 201 is in contact with the polysilicon layer 90 through the second via 1002, and the source 201 passes through the first
  • the three-via hole 1002 is in contact with the polysilicon layer 90, and the planarization layer 30 is disposed on the drain 201, the source 202, and the dielectric insulating layer 100.

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Abstract

一种阵列基板，用于形成显示面板，包括基板（10），设于该基板（10）上的薄膜晶体管（20）以及设于该基板（10）和该薄膜晶体管（20）上的平坦层（30），该平坦层（30）中设有露出该薄膜晶体管（20）的漏极（201）的第一通孔（301），该平坦层（30）远离该基板（10）的表面上设有像素电极层（40），该像素电极层（40）覆盖该第一通孔（301）并与该漏极（201）接触，该像素电极层（40）上覆盖有光阻层（50），且该光阻层（50）填充覆盖有该像素电极层（40）的该第一通孔（301）。该阵列基板解决了由于产品高度差距所导致的不良。

Description

阵列基板、显示面板以及阵列基板的制作方法
本发明要求2018年02月26日递交的发明名称为“阵列基板、显示面板以及阵列基板的制作方法”的申请号201810163135.8的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板、显示面板以及阵列基板的制作方法。
背景技术
在显示屏制造中，由于低温多晶硅技术制造的产品成本较低、器件电子迁移率高等特点，低温多晶硅技术越来越受到手机、平板屏幕等制造商的青睐。但是，由于使用低温多晶硅技术技术所需的膜层较多，膜层结构复杂，导致薄膜晶体管阵列面板在经过数次膜层累加后，产品高度差距明显，在后续的成盒制程中对液晶的配向易造成较大影响，进而造成产品的不良。
发明内容
本发明的目的在于提供一种阵列基板、显示面板以及阵列基板的制作方法，以解决由于产品高度差距所导致的不良。
本发明提供一种阵列基板，用于形成显示面板，包括基板，设于所述基板上的薄膜晶体管以及设于所述基板和所述薄膜晶体管上的平坦层，所述平坦层中设有露出所述薄膜晶体管的漏极的第一通孔，所述平坦层远离所述基板的表面上设有像素电极层，所述像素电极层覆盖所述第一通孔并与所述漏极接触，所述像素电极层上覆盖有光阻层，且所述光阻层填充覆盖有所述像素电极层的所述第一通孔。
其中，所述光阻层上设有光阻柱，所述光阻柱用于支撑所述显示面板。
其中，所述基板上设有遮光层，所述遮光层上设有覆盖所述遮光层的缓冲层，所述缓冲层上设有多晶硅层，所述多晶硅层上覆盖有介电绝缘层，所述介 电绝缘层中形成有两个间隔设置的且露出所述多晶硅层部分表面的第二通孔与第三通孔，所述薄膜晶体管的所述漏极与源极设于所述介电绝缘层上，且所述漏极通过所述第二通孔与所述多晶硅层接触，所述源极通过所述第三通孔与所述多晶硅层接触，所述平坦层设于所述漏极、所述源极以及所述介电绝缘层上。
其中，所述介电绝缘层包括绝缘层以及层叠于所述绝缘层上的介电层，所述薄膜晶体管的栅极设于所述绝缘层上，所述介电层覆盖所述栅极。
其中，所述平坦层上设有公共电极层，所述公共电极层上设有钝化层，所述钝化层覆盖所述公共电极层以及所述第一通孔的侧壁；所述钝化层上设有所述像素电极层，所述像素电极层覆盖所述钝化层，且所述像素电极层通过所述第一通孔与所述漏极接触。
本发明提供一种显示面板，包括上述的阵列基板。
本发明提供一种阵列基板的制作方法，包括：
提供一基板；
在所述基板上形成薄膜晶体管；
在所述基板和所述薄膜晶体管上形成平坦层；
在所述平坦层中形成露出所述薄膜晶体管的漏极的第一通孔；
在所述平坦层远离所述基板的表面上形成像素电极层，其中，所述像素电极层覆盖所述第一通孔并与所述漏极接触；
在所述像素电极层上形成覆盖所述像素电极层的光阻层，其中，所述光阻层填充覆盖有所述像素电极层的所述第一通孔。
其中，在所述基板上形成薄膜晶体管的步骤还包括：
在所述基板上形成遮光层；
在所述遮光层上形成覆盖所述遮光层的缓冲层；
在所述缓冲层上形成多晶硅层；
在所述多晶硅层上形成覆盖所述多晶硅层的介电绝缘层，在所述介电绝缘层中形成两个间隔设置的且露出所述多晶硅层部分表面的第二通孔与第三通孔；
在所述介电绝缘层上形成源极与漏极，其中，所述漏极通过所述第二通孔 与所述多晶硅层接触，所述源极通过所述第三通孔与所述多晶硅层接触。
其中，在所述平坦层远离所述基板的表面上形成像素电极层的步骤包括：
在所述平坦层上形成公共电极层；
在所述公共电极层上形成覆盖所述公共电极层以及所述第一通孔侧壁的钝化层；
在所述钝化层上形成覆盖所述钝化层的像素电极层，其中，所述像素电极层通过所述第一通孔与所述漏极连接。
其中，在所述像素电极层上形成覆盖所述像素电极层的光阻层的步骤之后还包括：在所述光阻层上形成光阻柱。
综上所述，本发明的所述光阻层填充覆盖有所述像素电极层的所述第一通孔，实现了对所述阵列基板的平坦化，进而解决了由于产品高度差距明显所导致的在后续的成盒制程中对液晶的配向造成影响的技术问题，提升了产品的良率与竞争力。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的阵列基板的结构示意图。
图2是本发明实施例提供的显示面板的结构示意图。
具体实施方式
请参阅图1，本发明提供一种阵列基板，用于形成显示面板，包括基板10，设于所述基板10上的薄膜晶体管20以及设于所述基板10和所述薄膜晶体管20上的平坦层30，所述平坦层30中设有露出所述薄膜晶体管20的漏极201的第一通孔301，所述平坦层30远离所述基板10的表面上设有像素电极层40，所述像素电极层40覆盖所述第一通孔301并与所述漏极201接触，所述像素电极层40上覆盖有光阻层50，且所述光阻层50填充覆盖有所述像素电极层 40的所述第一通孔301。
本发明的所述光阻层50填充覆盖有所述像素电极层40的所述第一通孔301实现了对所述阵列基板的平坦化，进而解决了由于产品高度差距明显所导致的在后续的成盒制程中对液晶的配向造成影响的技术问题，提升了产品的良率与竞争力。
具体为，所述光阻层50包括第一子光阻层501以及与所述第一子光阻层501相连的第二子光阻层502，所述第一子光阻层501填充在覆盖有所述像素电极层40的所述第一通孔301中，所述像素电极层40包括第一子像素电极层401以及与所述第一子像素电极层401相连的第二子像素电极层402，所述第一子像素电极层401设于所述第一通孔301中且与所述漏极201相连接，所述第二子光阻层502覆盖所述第二子像素电极层402。由于所述平坦层30较厚，进而所述第一通孔301的深度较大，而所述像素电极层40的厚度较薄，即使有所述第一子像素电极层401设于所述第一通孔301中，所述第一子像素电极层401并不能把所述第一通孔301填满，而所述第一子光阻层501对覆盖有所述像素电极层40的所述第一通孔301的填充实现了对所述阵列基板的平坦化，进而提升了所述产品的良率与竞争力。
所述光阻层50上设有光阻柱60，所述光阻柱60用于支撑所述显示面板。在本实施例中，所述光阻层50与所述光阻柱60一起制成。所述光阻层50上的所述光阻柱60可实现对后续的成盒制程提供空间以及支撑所述显示面板。
在本实施例中，所述基板10上设有遮光层70，所述遮光层70上设有覆盖所述遮光层70的缓冲层80，所述缓冲层80上设有多晶硅层90，所述多晶硅层90上覆盖有介电绝缘层100，所述介电绝缘层100中形成有两个间隔设置的且露出所述多晶硅层90部分表面的第二通孔1001与第三通孔1002，所述薄膜晶体管20的所述漏极201与源极202设于所述介电绝缘层100上，且所述漏极201通过所述第二通孔1001与所述多晶硅层90接触，所述源极202通过所述第三通孔1002与所述多晶硅层90接触，所述平坦层30设于所述漏极201、所述源极202以及所述介电绝缘层100上。
在本实施例中，所述介电绝缘层100包括绝缘层1003以及层叠于所述绝缘层1003上的介电层1004，所述薄膜晶体管20的栅极203设于所述绝缘层 1003上，所述介电层1004覆盖所述栅极203。
所述平坦层30上设有公共电极层110，所述公共电极层110上设有钝化层120，所述钝化层120覆盖所述公共电极层110以及所述第一通孔201的侧壁。具体为，所述钝化层120包括第一子钝化层1201以及与所述第一子钝化层1201相连的第二子钝化层1202，所述第二子钝化层1202覆盖所述公共电极层110，所述第一子钝化层1201延伸至所述第一通孔301中，并覆盖所述第一通孔301的侧壁。所述钝化层120上设有所述像素电极层40，所述像素电极层40覆盖所述钝化层120，且所述像素电极层40通过所述第一通孔201与所述漏极201接触。在本实施例中，第二子像素电极层402覆盖所述钝化层120。
请参阅图2，本发明提供一种显示面板，包括上述的阵列基板、彩膜基板130及液晶分子层140，所述彩膜基板130设于所述光阻柱60上，所述阵列基板、所述光阻柱60以及所述彩膜基板130形成一填充空间，所述液晶分子层140置于所述填充空间中。所述液晶分子层140通过扭转可以控制射出显示面板的光线亮度。所述彩膜基板130结合所述液晶分子层140可以调节三原色的光亮，得到需要的彩色显示。本发明所述的显示面板将所述彩膜基板130中的所述光阻柱60转移到所述阵列基板中，不会增加所述显示面板的成本。一起制成的所述光阻柱60与所述光阻层50不仅实现了对所述阵列基板的平坦化，解决了由于产品高度差距明显所导致的在后续的成盒制程中对液晶的配向造成影响的技术问题，提升了产品的良率与竞争力，而且实现对后续的成盒制程提供空间以及支撑所述显示面板。
本发明提供一种阵列基板的制作方法，包括：
步骤1，提供一基板10。
步骤2，在所述基板10上形成薄膜晶体管20。
步骤3，在所述基板10和所述薄膜晶体管20上形成平坦层30。
步骤4，在所述平坦层30中形成露出所述薄膜晶体管20的漏极201的第一通孔301。
步骤5，在所述平坦层30远离所述基板10的表面上形成像素电极层40。其中，所述像素电极层40覆盖所述第一通孔201与所述漏极201接触。
步骤6，在所述像素电极层40上形成覆盖所述像素电极层40的光阻层50。其中，所述光阻层50填充覆盖有所述像素电极层40的所述第一通孔301。
进一步地，在所述基板10上形成薄膜晶体管20的步骤还包括：
在所述基板10上形成遮光层70；
在所述遮光层70上形成覆盖所述遮光层70的缓冲层80；
在所述缓冲层80上形成多晶硅层90；
在所述多晶硅层90上形成覆盖所述多晶硅层90的介电绝缘层100，在所述介电绝缘层100中形成两个间隔设置的且露出所述多晶硅层90部分表面的第二通孔1001与第三通孔1002；其中，所述介电绝缘层100包括绝缘层1003以及层叠于所述绝缘层1003上的介电层1004，所述薄膜晶体管20的栅极203设于所述绝缘层1003上，所述介电层1004覆盖所述栅极203。
在所述介电绝缘层100上形成源极202与漏极201，其中，所述漏极201通过所述第二通孔1002与所述多晶硅层90接触，所述源极201通过所述第三通孔1002与所述多晶硅层90接触，所述平坦层30设于所述漏极201、所述源极202以及所述介电绝缘层100上。
进一步地，在所述平坦层30远离所述基板10的表面上形成像素电极层40的步骤包括：
在所述平坦层30上形成公共电极层110；
在所述公共电极层110上形成覆盖所述公共电极层110以及所述第一通孔301侧壁的钝化层120；
在所述钝化层120上形成覆盖所述钝化层120的像素电极层40，其中，所述像素电极层40通过所述第一通孔301与所述漏极201连接。
进一步地，在所述像素电极层40上形成覆盖所述像素电极层40的光阻层50的步骤之后还包括：在所述光阻层50上形成光阻柱60。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (14)

  1. 一种阵列基板，用于形成显示面板，其中，包括基板，设于所述基板上的薄膜晶体管以及设于所述基板和所述薄膜晶体管上的平坦层，所述平坦层中设有露出所述薄膜晶体管的漏极的第一通孔，所述平坦层远离所述基板的表面上设有像素电极层，所述像素电极层覆盖所述第一通孔并与所述漏极接触，所述像素电极层上覆盖有光阻层，且所述光阻层填充覆盖有所述像素电极层的所述第一通孔。
  2. 根据权利要求1所述的阵列基板，其中，所述光阻层上设有光阻柱，所述光阻柱用于支撑所述显示面板。
  3. 根据权利要求2所述的阵列基板，其中，所述基板上设有遮光层，所述遮光层上设有覆盖所述遮光层的缓冲层，所述缓冲层上设有多晶硅层，所述多晶硅层上覆盖有介电绝缘层，所述介电绝缘层中形成有两个间隔设置的且露出所述多晶硅层部分表面的第二通孔与第三通孔，所述薄膜晶体管的所述漏极与源极设于所述介电绝缘层上，且所述漏极通过所述第二通孔与所述多晶硅层接触，所述源极通过所述第三通孔与所述多晶硅层接触，所述平坦层设于所述漏极、所述源极以及所述介电绝缘层上。
  4. 根据权利要求3所述的阵列基板，其中，所述介电绝缘层包括绝缘层以及层叠于所述绝缘层上的介电层，所述薄膜晶体管的栅极设于所述绝缘层上，所述介电层覆盖所述栅极。
  5. 根据权利要求4所述的阵列基板，其中，所述平坦层上设有公共电极层，所述公共电极层上设有钝化层，所述钝化层覆盖所述公共电极层以及所述第一通孔的侧壁；所述钝化层上设有所述像素电极层，所述像素电极层覆盖所述钝化层，且所述像素电极层通过所述第一通孔与所述漏极接触。
  6. 一种显示面板，其中，包括如权利要求1所述的阵列基板。
  7. 根据权利要求6所述的显示面板，其中，所述光阻层上设有光阻柱，所述光阻柱用于支撑所述显示面板。
  8. 根据权利要求7所述的显示面板，其中，所述基板上设有遮光层，所述遮光层上设有覆盖所述遮光层的缓冲层，所述缓冲层上设有多晶硅层，所述 多晶硅层上覆盖有介电绝缘层，所述介电绝缘层中形成有两个间隔设置的且露出所述多晶硅层部分表面的第二通孔与第三通孔，所述薄膜晶体管的所述漏极与源极设于所述介电绝缘层上，且所述漏极通过所述第二通孔与所述多晶硅层接触，所述源极通过所述第三通孔与所述多晶硅层接触，所述平坦层设于所述漏极、所述源极以及所述介电绝缘层上。
  9. 根据权利要求8所述的显示面板，其中，所述介电绝缘层包括绝缘层以及层叠于所述绝缘层上的介电层，所述薄膜晶体管的栅极设于所述绝缘层上，所述介电层覆盖所述栅极。
  10. 根据权利要求9所述的显示面板，其中，所述平坦层上设有公共电极层，所述公共电极层上设有钝化层，所述钝化层覆盖所述公共电极层以及所述第一通孔的侧壁；所述钝化层上设有所述像素电极层，所述像素电极层覆盖所述钝化层，且所述像素电极层通过所述第一通孔与所述漏极接触。
  11. 一种阵列基板的制作方法，其中，包括：
    提供一基板；
    在所述基板上形成薄膜晶体管；
    在所述基板和所述薄膜晶体管上形成平坦层；
    在所述平坦层中形成露出所述薄膜晶体管的漏极的第一通孔；
    在所述平坦层远离所述基板的表面上形成像素电极层，其中，所述像素电极层覆盖所述第一通孔并与所述漏极接触；
    在所述像素电极层上形成覆盖所述像素电极层的光阻层，其中，所述光阻层填充覆盖有所述像素电极层的所述第一通孔。
  12. 根据权利要求11所述的阵列基板的制作方法，其中，在所述基板上形成薄膜晶体管的步骤还包括：
    在所述基板上形成遮光层；
    在所述遮光层上形成覆盖所述遮光层的缓冲层；
    在所述缓冲层上形成多晶硅层；
    在所述多晶硅层上形成覆盖所述多晶硅层的介电绝缘层，在所述介电绝缘层中形成两个间隔设置的且露出所述多晶硅层部分表面的第二通孔与第三通孔；
    在所述介电绝缘层上形成源极与漏极，其中，所述漏极通过所述第二通孔与所述多晶硅层接触，所述源极通过所述第三通孔与所述多晶硅层接触。
  13. 根据权利要求12所述的阵列基板的制作方法，其中，在所述平坦层远离所述基板的表面上形成像素电极层的步骤包括：
    在所述平坦层上形成公共电极层；
    在所述公共电极层上形成覆盖所述公共电极层以及所述第一通孔侧壁的钝化层；
    在所述钝化层上形成覆盖所述钝化层的像素电极层，其中，所述像素电极层通过所述第一通孔与所述漏极连接。
  14. 根据权利要求13所述的阵列基板的制作方法，其中，在所述像素电极层上形成覆盖所述像素电极层的光阻层的步骤之后还包括：在所述光阻层上形成光阻柱。
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