WO2018205524A1 - 一种阵列基板及其制作方法、显示装置 - Google Patents

一种阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2018205524A1
WO2018205524A1 PCT/CN2017/110125 CN2017110125W WO2018205524A1 WO 2018205524 A1 WO2018205524 A1 WO 2018205524A1 CN 2017110125 W CN2017110125 W CN 2017110125W WO 2018205524 A1 WO2018205524 A1 WO 2018205524A1
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Prior art keywords
insulating layer
array substrate
layer
hollow
gate
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PCT/CN2017/110125
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English (en)
French (fr)
Inventor
张洁
杨璐
史大为
樊君
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US15/777,178 priority Critical patent/US20200257176A1/en
Publication of WO2018205524A1 publication Critical patent/WO2018205524A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • an ADS (Advanced Super-Dimensional Field Conversion Technology) mode liquid crystal display panel the array substrate of the liquid crystal display panel includes a plurality of insulating layers, such as a gate insulating layer, between the source/drain metal layer and the first transparent electrode layer.
  • the array substrate further includes an insulating layer between the gate metal layer and the source/drain metal layer. It can be seen that the array substrate has a plurality of insulating layers, and the multilayer insulating layer causes loss of transmittance of the array substrate and affects display quality.
  • the present disclosure provides an array substrate, a method for fabricating the same, and a display device for solving the problem of affecting transmittance of an array substrate due to a plurality of insulating layers.
  • an array substrate including a gate line and a data line, the gate line and the data line define a plurality of pixel areas, and the array substrate further includes a layer of insulating layer, the plurality of insulating layers including at least one layer of hollow insulating layer, The portion of the hollow insulating layer located in the pixel region has a hollowed out region.
  • the array substrate includes a gate insulating layer, and the hollow insulating layer includes the gate insulating layer.
  • the array substrate includes a source/drain metal layer, a first transparent electrode layer, and a second insulating layer between the source/drain metal layer and the first transparent electrode layer, the hollow
  • the insulating layer includes the second insulating layer.
  • the array substrate is a top gate type array substrate, and the array substrate includes a source/drain metal layer, a gate metal layer, and a first layer between the gate metal layer and the source/drain metal layer.
  • An insulating layer, the hollow insulating layer comprising the first insulating layer.
  • the array substrate further includes: an active layer having a hollow region at an overlapping position of the source/drain metal layer and the active layer.
  • the hollow insulating layer is completely hollowed out in the pixel region.
  • the portion of the hollow insulating layer located in the pixel region having the hollow region means that the hollow insulating layer has a hollow region in each pixel region.
  • the portion of the hollow insulating layer located in the pixel region having the hollowed out region means that in the partial pixel region, the hollow insulating layer has a hollow region, and in another portion of the pixel region, the hollow insulating layer is not Has a hollowed out area.
  • the hollow region of the first insulating layer at the overlapping position of the source/drain metal layer and the active layer and the hollow region at other locations in the pixel region are formed by one patterning process.
  • the hollow region of the first insulating layer at the overlapping position of the source/drain metal layer and the active layer is in communication with the hollow region at other locations in the pixel region.
  • a display device comprising the above array substrate.
  • a method for fabricating an array substrate including:
  • a gate metal layer Forming a gate metal layer, a source/drain metal layer, and a plurality of insulating layers, wherein the gate metal layer includes a gate line, the source/drain metal layer includes a data line, and the gate line and the data line define a plurality of pixel regions; And, at least one hollow insulating layer is disposed in the plurality of insulating layers, wherein a portion of the hollow insulating layer located in the pixel region has a hollowed out region.
  • the step of forming a plurality of insulating layers comprises:
  • a gate insulating layer is formed, the hollow insulating layer including the gate insulating layer.
  • the manufacturing method further includes: forming a first transparent electrode layer;
  • the step of forming a plurality of insulating layers includes:
  • the hollow insulating layer including the second insulating layer.
  • the step of forming a plurality of insulating layers includes:
  • At least one insulating layer is provided to be hollowed out, thereby reducing the influence of the insulating layer in the pixel region on the light transmittance and improving the display quality.
  • FIG. 1 is a schematic structural view of an array substrate of an ADS mode in the related art
  • FIG. 2 is a schematic structural diagram of an array substrate of an ADS mode according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of an array substrate of another ADS mode according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flow chart of a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide an array substrate including a gate line and a data line, the gate line and the data line defining a plurality of pixel regions, the array substrate further including a plurality of insulating layers, wherein the plurality of layers of insulation
  • the layer includes at least one hollow insulating layer, and a portion of the hollow insulating layer located in the pixel region has a hollowed out region.
  • At least one insulating layer is disposed in the pixel region of the array substrate, thereby reducing the influence of the insulating layer in the pixel region on the light transmittance and improving the display quality.
  • the portion of the hollow insulating layer located in the pixel region having the hollow region may mean that the hollow insulating layer has a hollow region in each pixel region.
  • the hollow insulating layer has a hollowed out area, and in another part of the pixel area, the hollowed out insulating layer does not have a hollowed out area.
  • the array substrate in the embodiment of the present disclosure includes a gate insulating layer.
  • the hollow insulating layer may include the gate insulating layer, that is, a portion of the gate insulating layer located in the pixel region has a hollow region, thereby The effect of the gate insulating layer on the light transmittance in the pixel region is reduced, and the display quality is improved.
  • the array substrate in the embodiment of the present disclosure includes a source/drain metal layer, a first transparent electrode layer, and a second insulating layer between the source/drain metal layer and the first transparent electrode layer, and the source/drain metal layer may include Source electrode, drain electrode, and data line.
  • the first transparent electrode layer may be a pixel electrode layer or a common electrode layer.
  • the hollow insulating layer may include the second insulating layer, that is, a portion of the second insulating layer located in the pixel region has a hollow region, thereby reducing light transmission through the second insulating layer in the pixel region. The effect of the rate improves the display quality.
  • the drain electrode overlaps the pixel electrode layer through the hollow region of the second insulating layer located in the pixel region, that is, the via hole for connecting the drain electrode and the pixel electrode layer is not separately formed on the second insulating layer. Therefore, it is not necessary to increase the number of masks, and the implementation cost is low.
  • the hollow insulating layer may simultaneously include the gate insulating layer and the second insulating layer, thereby further reducing the influence of the insulating layer on the light transmittance in the pixel region, and improving the display. quality.
  • the array substrate of the embodiment of the present disclosure is a top gate type array substrate
  • the array substrate includes a source/drain metal layer, a gate metal layer, and a first insulating layer between the gate metal layer and the source/drain metal layer.
  • the source/drain metal layer may include a source electrode, a drain electrode, and a data line
  • the gate metal layer may include a gate electrode and a gate line.
  • the hollow insulating layer includes the first insulating layer, that is, The portion of the first insulating layer located in the pixel region has a hollow region, thereby reducing the influence of the first insulating layer on the light transmittance in the pixel region, and improving the display quality.
  • the hollow insulating layer may further include any two or three of the foregoing gate insulating layer, the first insulating layer, and the second insulating layer, thereby further reducing the pixel area.
  • the effect of the inner insulating layer on the light transmittance improves the display quality.
  • the array substrate in the above embodiment further includes an active layer.
  • the first insulating layer has a hollow region at a overlapping position of the source/drain metal layer and the active layer, thereby realizing a source/drain metal layer.
  • the connection with the active layer, the hollow region of the first insulating layer at the overlapping position of the source/drain metal layer and the active layer and the hollow region at other positions in the pixel region may be formed by one patterning process, thereby eliminating the need Via holes for connecting the source/drain metal layer and the active layer are separately formed on the first insulating layer.
  • the hollow region of the first insulating layer at the overlapping position of the source/drain metal layer and the active layer is in communication with the hollow region at other locations in the pixel region.
  • the hollow insulating layer is completely hollowed out in the pixel region, thereby maximally reducing the influence of the hollow insulating layer on the transmittance and improving the display quality.
  • Embodiments of the present disclosure also provide a display device including the above array substrate.
  • the display device may be a display panel or a display device including a display panel and a driving circuit.
  • the display device is a liquid crystal display device.
  • the embodiment of the present disclosure further provides a method for fabricating an array substrate, including:
  • the multilayer insulating layer includes at least one hollow insulating layer, and a portion of the hollow insulating layer located in the pixel region has a hollowed out region.
  • the step of forming a plurality of insulating layers includes: forming a gate insulating layer, the hollow insulating layer including the gate insulating layer.
  • the method of fabricating the array substrate further includes: forming a first transparent electrode layer;
  • the step of forming a plurality of insulating layers includes: forming a second insulating layer between the source/drain metal layer and the first transparent electrode layer, the hollow insulating layer including the second insulating layer.
  • the array substrate is a top gate type array substrate
  • the step of forming a plurality of insulating layers includes: forming a first insulation between the gate metal layer and the source/drain metal layer a layer, the hollow insulating layer comprising the first insulating layer.
  • FIG. 1 is a schematic structural diagram of an array substrate of an ADS mode in the related art.
  • the array substrate includes: a base substrate 101, an active layer 102, a gate insulating layer 103, a gate metal layer 104, a first insulating layer 105, a source/drain metal layer 106, a second insulating layer 107, a common electrode layer 108, and a third The insulating layer 109 and the pixel electrode layer 110.
  • FIG. 1 is a schematic structural diagram of an array substrate of an ADS mode in the related art.
  • the array substrate includes: a base substrate 101, an active layer 102, a gate insulating layer 103, a gate metal layer 104, a first insulating layer 105, a source/drain metal layer 106, a second insulating layer 107, a common electrode layer 108, and a third The insulating layer 109 and the pixel electrode layer 110.
  • the array substrate includes a plurality of insulating layers (the gate insulating layer 103, the first insulating layer 105, the second insulating layer 107, and the third insulating layer 109), thereby affecting the transmittance of the array substrate. .
  • FIG. 2 is a schematic structural diagram of an array substrate of an ADS mode according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of another ADS mode array substrate in the embodiment of the present disclosure.
  • the array substrate includes: a base substrate 101, an active layer 102, a gate insulating layer 103, a gate metal layer, a first insulating layer 105, a source/drain metal layer, a second insulating layer 107, and a common electrode.
  • the gate metal layer includes a gate electrode 104 and a gate line 1042.
  • the source/drain metal layer includes a source electrode 1061, a drain electrode 1062, and a data line 1063.
  • the gate line 1042 and the data line 1063 define a plurality of pixel regions.
  • the portion of the first insulating layer 105 located in the pixel region has a hollowed out region.
  • the first insulating layer 105 is disposed in the pixel region of the array substrate. By placing the cutout region, the influence of the first insulating layer 105 in the pixel region on the light transmittance can be reduced, and the display quality can be improved.
  • the first insulating layer 105 also has a hollowed-out region at the overlapping position of the drain electrode 1062 and the active layer 102 (the position shown by the dotted line in FIG. 3). Thereby, the connection of the source/drain metal layer and the active layer is achieved.
  • the first insulating layer 105 between the gate metal layer and the source/drain metal layer is provided with a hollow region in the pixel region.
  • the second insulating layer 107 between the source/drain metal layer and the common electrode layer 108 may be provided with a hollow region in the pixel region.
  • the first insulating layer 105 and the second insulating layer 107 are simultaneously provided with a cutout region in the pixel region.
  • the positions of the common electrode layer 108 and the pixel electrode layer 110 may be interchanged.
  • a display device comprising any one of the array substrates as described above.
  • the array substrate included in the display device reference may be made to the specific description of the array substrate as described above, and details are not described herein again.
  • FIG. 4 is a schematic flow chart of a method of fabricating an array substrate according to an embodiment of the present disclosure. As shown in FIG. 4, the method for fabricating the array substrate includes the following steps:
  • Step S410 sequentially forming a gate metal layer, a source/drain metal layer, and a plurality of insulating layers, wherein the gate metal layer includes a gate line, the source/drain metal layer includes a data line, and the gate line and the data line define a plurality of Pixel regions;
  • Step S420 providing at least one hollow insulating layer in the plurality of insulating layers, wherein a portion of the hollow insulating layer located in the pixel region has a hollowed out region.
  • the step of forming a plurality of insulating layers comprises:
  • a gate insulating layer is formed, the hollow insulating layer including the gate insulating layer.
  • the method for fabricating the array substrate may further include:
  • the step of forming a plurality of insulating layers includes:
  • the step of forming a plurality of insulating layers comprises:

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Abstract

一种阵列基板及其制作方法、显示装置。该阵列基板包括：栅线（1042）和数据线（1063），所述栅线（1042）和数据线（1063）限定出多个像素区域，所述阵列基板还包括多层绝缘层，所述多层绝缘层中包括至少一层镂空绝缘层，所述镂空绝缘层位于所述像素区域内的部分具有镂空区域，从而可减少像素区域内的绝缘层对光线透过率的影响，提高显示品质。

Description

一种阵列基板及其制作方法、显示装置
相关申请的交叉参考
本申请主张在2017年5月11日在中国提交的中国专利申请号No.201710331516.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
随着液晶显示面板产业的日益成熟和发展，高品质液晶显示面板的需求越来越迫切，包括亮度、对比度以及分辨率等方面。而就目前的工艺制程来看，较低透过率成了高分辨率产品提高显示品质的瓶颈所在。
尤其是ADS(高级超维场转换技术)模式的液晶显示面板，该种液晶显示面板的阵列基板中，包括多层绝缘层，例如栅绝缘层，源漏金属层与第一透明电极层之间的绝缘层，第一透明电极层与第二透明电极层之间的绝缘层。此外，当该阵列基板中的薄膜晶体管为顶栅型薄膜晶体管时，阵列基板还包括栅金属层与源漏金属层之间的绝缘层。可见，阵列基板上具有多层绝缘层，多层绝缘层会造成阵列基板的透过率损失，影响显示品质。
发明内容
(一)要解决的技术问题
有鉴于此，本公开文本提供一种阵列基板及其制作方法、显示装置，用于解决阵列基板上因多层绝缘层影响透过率的问题。
(二)技术方案
为解决上述技术问题，根据本公开文本的第一方面，提供了一种阵列基板，包括栅线和数据线，所述栅线和数据线限定出多个像素区域，所述阵列基板还包括多层绝缘层，所述多层绝缘层中包括至少一层镂空绝缘层，所述 镂空绝缘层位于所述像素区域内的部分具有镂空区域。
根据本公开文本的一个可行实施例，所述阵列基板包括栅绝缘层，所述镂空绝缘层包括所述栅绝缘层。
根据本公开文本的一个可行实施例，所述阵列基板包括源漏金属层、第一透明电极层和位于所述源漏金属层和第一透明电极层之间的第二绝缘层，所述镂空绝缘层包括所述第二绝缘层。
根据本公开文本的一个可行实施例，所述阵列基板为顶栅型阵列基板，所述阵列基板包括源漏金属层、栅金属层和位于所述栅金属层和源漏金属层之间的第一绝缘层，所述镂空绝缘层包括所述第一绝缘层。
根据本公开文本的一个可行实施例，所述阵列基板还包括：有源层，所述第一绝缘层在所述源漏金属层与所述有源层的搭接位置处具有镂空区域。
根据本公开文本的一个可行实施例，所述镂空绝缘层在所述像素区域内全部镂空。
根据本公开文本的一个可行实施例，所述镂空绝缘层位于像素区域内的部分具有镂空区域是指在每一像素区域内，镂空绝缘层均具有镂空区域。
根据本公开文本的一个可行实施例，所述镂空绝缘层位于像素区域内的部分具有镂空区域是指在部分像素区域内，镂空绝缘层具有镂空区域，在另一部分像素区域内，镂空绝缘层不具有镂空区域。
根据本公开文本的一个可行实施例，所述第一绝缘层的在源漏金属层与有源层的搭接位置处的镂空区域与像素区域内其他位置处的镂空区域采用一次构图工艺形成。
根据本公开文本的一个可行实施例，所述第一绝缘层的在源漏金属层与有源层的搭接位置处的镂空区域与像素区域内其他位置处的镂空区域连通在一起。
根据本公开文本的第二方面，还提供了一种显示装置，包括上述阵列基板。
根据本公开文本的第三方面，还提供了一种阵列基板的制作方法，包括：
形成栅金属层、源漏金属层和多层绝缘层，其中，所述栅金属层包括栅线，所述源漏金属层包括数据线，所述栅线和数据线限定出多个像素区域； 以及，在所述多层绝缘层中设置至少一层镂空绝缘层，其中，所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
根据本公开文本的一个可行实施例，所述形成多层绝缘层的步骤包括：
形成栅绝缘层，所述镂空绝缘层包括所述栅绝缘层。
根据本公开文本的一个可行实施例，所述制作方法还包括：形成第一透明电极层；
所述形成多层绝缘层的步骤包括：
形成位于源漏金属层和第一透明电极层之间的第二绝缘层，所述镂空绝缘层包括所述第二绝缘层。
根据本公开文本的一个可行实施例，当所述阵列基板为顶栅型阵列基板时，所述形成多层绝缘层的步骤包括：
形成位于所述栅金属层和源漏金属层之间的第一绝缘层，所述镂空绝缘层包括所述第一绝缘层。
(三)有益效果
本公开文本实施例所提供的上述技术方案的有益效果如下：
在阵列基板的像素区域内，将至少一层绝缘层设置为镂空，从而可减少像素区域内的绝缘层对光线透过率的影响，提高显示品质。
附图说明
为了更清楚地说明本公开文本实施例或相关技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中的一ADS模式的阵列基板的结构示意图；
图2为根据本公开文本实施例的一ADS模式的阵列基板的结构示意图；
图3为根据本公开文本实施例的另一ADS模式的阵列基板的结构示意图；以及
图4为根据本公开文本实施例的阵列基板的制作方法的流程示意图。
具体实施方式
下面结合附图和实施例，对本公开文本的具体实施方式做进一步描述。以下实施例仅用于说明本公开文本，但不用来限制本公开文本的范围。
为使本公开文本实施例的目的、技术方案和优点更加清楚，下面将结合本公开文本实施例的附图，对本公开文本实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开文本保护的范围。
本公开文本实施例提供一种阵列基板，包括栅线和数据线，所述栅线和数据线限定出多个像素区域，所述阵列基板还包括多层绝缘层，其中，所述多层绝缘层中包括至少一层镂空绝缘层，所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
本公开文本实施例中，在阵列基板的像素区域内，将至少一层绝缘层设置为镂空，从而可减少像素区域内的绝缘层对光线透过率的影响，提高显示品质。
本公开文本实施例中，镂空绝缘层位于像素区域内的部分具有镂空区域可以是指在每一像素区域内，镂空绝缘层均具有镂空区域。当然，也不排除以下情况，即，在部分像素区域内，镂空绝缘层具有镂空区域，在另一部分像素区域内，镂空绝缘层不具有镂空区域。
本公开文本实施例中的阵列基板包括栅绝缘层，优选地，所述镂空绝缘层可以包括所述栅绝缘层，也就是说，所述栅绝缘层位于像素区域内的部分具有镂空区域，从而减少像素区域内栅绝缘层对光线透过率的影响，提高显示品质。
本公开文本实施例中的阵列基板包括源漏金属层、第一透明电极层和位于所述源漏金属层和第一透明电极层之间的第二绝缘层，所述源漏金属层可以包括源电极、漏电极和数据线。所述第一透明电极层可以是像素电极层，也可以是公共电极层。优选地，所述镂空绝缘层可以包括所述第二绝缘层，也就是说，所述第二绝缘层位于像素区域内的部分具有镂空区域，从而减少像素区域内第二绝缘层对光线透过率的影响，提高显示品质。
优选地，所述漏电极通过所述第二绝缘层位于像素区域内的镂空区域与像素电极层搭接，即无需在第二绝缘层上单独制作用于连接漏电极和像素电极层的过孔，从而不需要增加掩膜版的数量，实现成本低。
当然，在本公开文本的其他一些实施例中，所述镂空绝缘层可以同时包括上述栅绝缘层和第二绝缘层，从而可进一步减少像素区域内绝缘层对光线透过率的影响，提高显示品质。
当本公开文本实施例的阵列基板为顶栅型阵列基板时，所述阵列基板包括源漏金属层、栅金属层和位于所述栅金属层和源漏金属层之间的第一绝缘层，所述源漏金属层可以包括源电极、漏电极和数据线，所述栅金属层可以包括栅电极和栅线，优选地，所述镂空绝缘层包括所述第一绝缘层，也就是说，所述第一绝缘层位于像素区域内的部分具有镂空区域，从而减少像素区域内第一绝缘层对光线透过率的影响，提高显示品质。
当然，在本公开文本的其他一些实施例中，所述镂空绝缘层还可以包括上述栅绝缘层、第一绝缘层和第二绝缘层中的任意两个或三个，从而可进一步减少像素区域内绝缘层对光线透过率的影响，提高显示品质。
上实施例中的阵列基板还包括有源层，优选地，所述第一绝缘层在所述源漏金属层与所述有源层的搭接位置处具有镂空区域，从而实现源漏金属层与有源层的连接，所述第一绝缘层的在源漏金属层与有源层的搭接位置处的镂空区域与像素区域内其他位置处的镂空区域可采用一次构图工艺形成，从而无需在第一绝缘层上单独制作用于连接源漏金属层与有源层的过孔。
优选地，所述第一绝缘层的在源漏金属层与有源层的搭接位置处的镂空区域与像素区域内其他位置处的镂空区域连通在一起。
本公开文本实施例中，优选地，所述镂空绝缘层在所述像素区域内全部镂空，从而可最大化的减少镂空绝缘层对透过率的影响，提高显示品质。
本公开文本实施例还提供一种显示装置，包括上述阵列基板。
所述显示装置可以为显示面板，或者包括显示面板和驱动电路的显示器件。
优选地，所述显示装置为液晶显示装置。
本公开文本实施例还提供一种阵列基板的制作方法，包括：
形成栅金属层、源漏金属层和多层绝缘层，其中，所述栅金属层包括栅线，所述源漏金属层包括数据线，所述栅线和数据线限定出多个像素区域，所述多层绝缘层中包括至少一层镂空绝缘层，所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
在本公开文本的一些实施例中，所述形成多层绝缘层的步骤包括：形成栅绝缘层，所述镂空绝缘层包括所述栅绝缘层。
在本公开文本的一些实施例中，所述阵列基板的制作方法还包括：形成第一透明电极层；
所述形成多层绝缘层的步骤包括：形成位于源漏金属层和第一透明电极层之间的第二绝缘层，所述镂空绝缘层包括所述第二绝缘层。
在本公开文本的一些实施例中，所述阵列基板为顶栅型阵列基板，所述形成多层绝缘层的步骤包括：形成位于所述栅金属层和源漏金属层之间的第一绝缘层，所述镂空绝缘层包括所述第一绝缘层。
下面结合具体实施例对本公开文本实施例的阵列基板的结构进行说明。
请参考图1，图1为相关技术中的一ADS模式的阵列基板的结构示意图。该阵列基板包括：衬底基板101，有源层102，栅绝缘层103，栅金属层104，第一绝缘层105，源漏金属层106，第二绝缘层107，公共电极层108，第三绝缘层109和像素电极层110。从图1中可以看出，该阵列基板包括多个绝缘层(栅绝缘层103，第一绝缘层105，第二绝缘层107，和第三绝缘层109)，从而影响阵列基板的透过率。
请参考图2和图3，图2为本公开文本实施例中的一ADS模式的阵列基板的结构示意图。而图3为本公开文本实施例中的另一ADS模式的阵列基板的结构示意图。作为非限定性的示例，该阵列基板包括：衬底基板101，有源层102，栅绝缘层103，栅金属层，第一绝缘层105，源漏金属层，第二绝缘层107，公共电极层108，第三绝缘层109和像素电极层110。栅金属层包括栅电极104和栅线1042。源漏金属层包括源电极1061、漏电极1062和数据线1063。所述栅线1042和数据线1063限定出多个像素区域。所述第一绝缘层105位于像素区域内的部分具有镂空区域。
本公开文本实施例中，在阵列基板的像素区域内，将第一绝缘层105设 置镂空区域，从而可减少像素区域内的第一绝缘层105对光线透过率的影响，提高显示品质。
同时，请参考图3，上述实施例中，第一绝缘层105在所述漏电极1062与所述有源层102的搭接位置处(图3中虚线框所示位置)也具有镂空区域，从而实现源漏金属层与有源层的连接。
上述实施例中，是将位于栅金属层和源漏金属层之间的第一绝缘层105，在像素区域内，设置镂空区域。当然，在本公开文本的其他一些实施例中，也可以将源漏金属层和公共电极层108之间的第二绝缘层107，在像素区域内，设置镂空区域。或者，同时将第一绝缘层105和第二绝缘层107在像素区域内设置镂空区域。
上述实施例中，公共电极层108和像素电极层110的位置可以互换。
根据本公开文本的另一方面，提供了一种显示装置，其包括如上所述的任何一个阵列基板。关于该显示装置所包含的阵列基板的具体设置可以参考如上关于阵列基板的具体描述，在此不再赘述。
根据本公开文本的另一方面，提供了一种阵列基板的制作方法。图4为根据本公开文本实施例的阵列基板的制作方法的流程示意图。如图4所示，该阵列基板的制作方法例如包括如下步骤：
步骤S410，依次形成栅金属层、源漏金属层和多层绝缘层，其中，所述栅金属层包括栅线，所述源漏金属层包括数据线，所述栅线和数据线限定出多个像素区域；以及
步骤S420，在所述多层绝缘层中设置至少一层镂空绝缘层，其中，所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
可选的，所述形成多层绝缘层的步骤包括：
形成栅绝缘层，所述镂空绝缘层包括所述栅绝缘层。
可选的，该阵列基板的制作方法还可以包括：
形成第一透明电极层；
所述形成多层绝缘层的步骤包括：
形成位于源漏金属层和第一透明电极层之间的第二绝缘层，其中，所述镂空绝缘层包括所述第二绝缘层。
可选的，当所述阵列基板为顶栅型阵列基板时，所述形成多层绝缘层的步骤包括：
形成位于所述栅金属层和源漏金属层之间的第一绝缘层，其中，所述镂空绝缘层包括所述第一绝缘层。
除非另作定义，本公开文本使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开文本中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
以上所述是本公开文本的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开文本所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开文本的保护范围。

Claims (15)

  1. 一种阵列基板，包括栅线和数据线，所述栅线和数据线限定出多个像素区域，所述阵列基板还包括多层绝缘层，所述多层绝缘层中包括至少一层镂空绝缘层，所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括栅绝缘层，所述镂空绝缘层包括所述栅绝缘层。
  3. 根据权利要求1或2所述的阵列基板，其中，所述阵列基板包括源漏金属层、第一透明电极层和位于所述源漏金属层和第一透明电极层之间的第二绝缘层，所述镂空绝缘层包括所述第二绝缘层。
  4. 根据权利要求1至3中任一项所述的阵列基板，其中，所述阵列基板为顶栅型阵列基板，所述阵列基板包括源漏金属层、栅金属层和位于所述栅金属层和源漏金属层之间的第一绝缘层，所述镂空绝缘层包括所述第一绝缘层。
  5. 根据权利要求4所述的阵列基板，还包括：有源层，所述第一绝缘层在所述源漏金属层与所述有源层的搭接位置处具有镂空区域。
  6. 根据权利要求1至5中任一项所述的阵列基板，其中，所述镂空绝缘层在所述像素区域内全部镂空。
  7. 根据权利要求1至6中任一项所述的阵列基板，其中，所述镂空绝缘层位于像素区域内的部分具有镂空区域是指在每一像素区域内，镂空绝缘层均具有镂空区域。
  8. 根据权利要求1至6中任一项所述的阵列基板，其中，所述镂空绝缘层位于像素区域内的部分具有镂空区域是指在部分像素区域内，镂空绝缘层具有镂空区域，在另一部分像素区域内，镂空绝缘层不具有镂空区域。
  9. 根据权利要求5所述的阵列基板，其中，所述第一绝缘层的在源漏金属层与有源层的搭接位置处的镂空区域与像素区域内其他位置处的镂空区域采用一次构图工艺形成。
  10. 根据权利要求5或9所述的阵列基板，其中，所述第一绝缘层的在源漏金属层与有源层的搭接位置处的镂空区域与像素区域内其他位置处的镂 空区域连通在一起。
  11. 一种显示装置，其包括如权利要求1至10中任一项所述的阵列基板。
  12. 一种阵列基板的制作方法，包括：
    依次形成栅金属层、源漏金属层和多层绝缘层，其中，所述栅金属层包括栅线，所述源漏金属层包括数据线，所述栅线和数据线限定出多个像素区域；以及
    在所述多层绝缘层中设置至少一层镂空绝缘层，其中，所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
  13. 根据权利要求12所述的阵列基板的制作方法，其中，所述形成多层绝缘层的步骤包括：
    形成栅绝缘层，所述镂空绝缘层包括所述栅绝缘层。
  14. 根据权利要求12所述的阵列基板的制作方法，还包括：
    形成第一透明电极层；
    所述形成多层绝缘层的步骤包括：
    形成位于源漏金属层和第一透明电极层之间的第二绝缘层，其中，所述镂空绝缘层包括所述第二绝缘层。
  15. 根据权利要求12所述的阵列基板的制作方法，其中，当所述阵列基板为顶栅型阵列基板时，所述形成多层绝缘层的步骤包括：
    形成位于所述栅金属层和源漏金属层之间的第一绝缘层，其中，所述镂空绝缘层包括所述第一绝缘层。
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CN110517595A (zh) * 2019-08-30 2019-11-29 京东方科技集团股份有限公司 一种透明显示面板及透明显示器
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