CN106932989A - 一种阵列基板及其制作方法、显示装置 - Google Patents

一种阵列基板及其制作方法、显示装置 Download PDF

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CN106932989A
CN106932989A CN201710331516.8A CN201710331516A CN106932989A CN 106932989 A CN106932989 A CN 106932989A CN 201710331516 A CN201710331516 A CN 201710331516A CN 106932989 A CN106932989 A CN 106932989A
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insulating barrier
array base
base palte
layer
hollow out
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张洁
杨璐
史大为
樊君
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Publication of CN106932989A publication Critical patent/CN106932989A/zh
Priority to PCT/CN2017/110125 priority patent/WO2018205524A1/zh
Priority to US15/777,178 priority patent/US20200257176A1/en
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    • GPHYSICS
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1248Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
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Abstract

本发明提供一种阵列基板及其制作方法、显示装置,该阵列基板包括:栅线和数据线,所述栅线和数据线限定出多个像素区域,所述阵列基板还包括多层绝缘层,所述多层绝缘层中包括至少一层镂空绝缘层,所述镂空绝缘层位于所述像素区域内的部分具有镂空区域,从而可减少像素区域内的绝缘层对光线透过率的影响,提高显示品质。

Description

一种阵列基板及其制作方法、显示装置
技术领域
本发明涉及显示技术领域,尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
随着液晶显示面板产业的日益成熟和发展,高品质液晶显示面板的需求越来越迫切,包括亮度、对比度以及分辨率等方面。而就目前的工艺制程来看,较低透过率成了高分辨率产品提高显示品质的瓶颈所在。
尤其是ADS(高级超维场转换技术)模式的液晶显示面板,该种液晶显示面板的阵列基板中,包括多层绝缘层,例如栅绝缘层,源漏金属层与第一透明电极层之间的绝缘层,第一透明电极层与第二透明电极层之间的绝缘层,当该阵列基板中的薄膜晶体管为顶栅型薄膜晶体管时,阵列基板还包括栅金属层与源漏金属层之间的绝缘层,可见,阵列基板上具有多层绝缘层,多层绝缘层会造成阵列基板的透过率损失,影响显示品质。
发明内容
有鉴于此,本发明提供一种阵列基板及其制作方法、显示装置,用于解决阵列基板上因多层绝缘层影响透过率的问题。
为解决上述技术问题,本发明提供一种阵列基板,包括栅线和数据线,所述栅线和数据线限定出多个像素区域,所述阵列基板还包括多层绝缘层,所述多层绝缘层中包括至少一层镂空绝缘层,所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
优选地,所述阵列基板包括栅绝缘层,所述镂空绝缘层包括所述栅绝缘层。
优选地,所述阵列基板包括源漏金属层、第一透明电极层和位于所述源漏金属层和第一透明电极层之间的第二绝缘层,所述镂空绝缘层包括所述第二绝缘层。
优选地,所述阵列基板为顶栅型阵列基板,所述阵列基板包括源漏金属层、栅金属层和位于所述栅金属层和源漏金属层之间的第一绝缘层,所述镂空绝缘层包括所述第一绝缘层。
优选地,所述阵列基板还包括:有源层,所述第一绝缘层在所述源漏金属层与所述有源层的搭接位置处具有镂空区域。
优选地,所述镂空绝缘层在所述像素区域内全部镂空。
本发明还提供一种显示装置,包括上述阵列基板。
本发明还提供一种阵列基板的制作方法,包括:
形成栅金属层、源漏金属层和多层绝缘层,其中,所述栅金属层包括栅线,所述源漏金属层包括数据线,所述栅线和数据线限定出多个像素区域,所述多层绝缘层中包括至少一层镂空绝缘层,所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
优选地,形成多层绝缘层的步骤包括:
形成栅绝缘层,所述镂空绝缘层包括所述栅绝缘层。
优选地,所述制作方法还包括:形成第一透明电极层;
形成多层绝缘层的步骤包括:
形成位于源漏金属层和第一透明电极层之间的第二绝缘层,所述镂空绝缘层包括所述第二绝缘层。
优选地,所述阵列基板为顶栅型阵列基板,形成多层绝缘层的步骤包括:
形成位于所述栅金属层和源漏金属层之间的第一绝缘层,所述镂空绝缘层包括所述第一绝缘层。
本发明的上述技术方案的有益效果如下:
在阵列基板的像素区域内,将至少一层绝缘层设置为镂空,从而可减少像素区域内的绝缘层对光线透过率的影响,提高显示品质。
附图说明
图1为现有技术中的一ADS模式的阵列基板的结构示意图;
图2和图3为本发明实施例中的一ADS模式的阵列基板的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例的附图,对本发明实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于所描述的本发明的实施例,本领域普通技术人员所获得的所有其他实施例,都属于本发明保护的范围。
本发明实施例提供一种阵列基板,包括栅线和数据线,所述栅线和数据线限定出多个像素区域,所述阵列基板还包括多层绝缘层,其中,所述多层绝缘层中包括至少一层镂空绝缘层,所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
本发明实施例中,在阵列基板的像素区域内,将至少一层绝缘层设置为镂空,从而可减少像素区域内的绝缘层对光线透过率的影响,提高显示品质。
本发明实施例中,镂空绝缘层位于像素区域内的部分具有镂空区域可以是指在每一像素区域内,镂空绝缘层均具有镂空区域。当然,也不排除以下情况,即,在部分像素区域内,镂空绝缘层具有镂空区域,在另一部分像素区域内,镂空绝缘层不具有镂空区域。
本发明实施例中的阵列基板包括栅绝缘层,优选地,所述镂空绝缘层可以包括所述栅绝缘层,也就是说,所述栅绝缘层位于像素区域内的部分具有镂空区域,从而减少像素区域内栅绝缘层对光线透过率的影响,提高显示品质。
本发明实施例中的阵列基板包括源漏金属层、第一透明电极层和位于所述源漏金属层和第一透明电极层之间的第二绝缘层,所述源漏金属层可以包括源电极、漏电极和数据线。所述第一透明电极层可以是像素电极层,也可以是公共电极层。优选地,所述镂空绝缘层可以包括所述第二绝缘层,也就是说,所述第二绝缘层位于像素区域内的部分具有镂空区域,从而减少像素区域内第二绝缘层对光线透过率的影响,提高显示品质。
优选地,所述漏电极通过所述第二绝缘层位于像素区域内的镂空区域与像素电极层搭接,即无需在第二绝缘层上单独制作用于连接漏电极和像素电极层的过孔,从而不需要增加掩膜版的数量,实现成本低。
当然,在本发明的其他一些实施例中,所述镂空绝缘层可以同时包括上述栅绝缘层和第二绝缘层,从而可进一步减少像素区域内绝缘层对光线透过率的影响,提高显示品质。
当本发明实施例的阵列基板为顶栅型阵列基板时,所述阵列基板包括源漏金属层、栅金属层和位于所述栅金属层和源漏金属层之间的第一绝缘层,所述源漏金属层可以包括源电极、漏电极和数据线,所述栅金属层可以包括栅电极和栅线,优选地,所述镂空绝缘层包括所述第一绝缘层,也就是说,所述第一绝缘层位于像素区域内的部分具有镂空区域,从而减少像素区域内第一绝缘层对光线透过率的影响,提高显示品质。
当然,在本发明的其他一些实施例中,所述镂空绝缘层还可以包括上述栅绝缘层、第一绝缘层和第二绝缘层中的任意两个或三个,从而可进一步减少像素区域内绝缘层对光线透过率的影响,提高显示品质。
上实施例中的阵列基板还包括有源层,优选地,所述第一绝缘层在所述源漏金属层与所述有源层的搭接位置处具有镂空区域,从而实现源漏金属层与有源层的连接,所述第一绝缘层的在源漏金属层与有源层的搭接位置处的镂空区域与像素区域内其他位置处的镂空区域可采用一次构图工艺形成,从而无需在第一绝缘层上单独制作用于连接源漏金属层与有源层的过孔。
优选地,所述第一绝缘层的在源漏金属层与有源层的搭接位置处的镂空区域与像素区域内其他位置处的镂空区域连通在一起。
本发明实施例中,优选地,所述镂空绝缘层在所述像素区域内全部镂空,从而可最大化的减少镂空绝缘层对透过率的影响,提高显示品质。
本发明实施例还提供一种显示装置,包括上述阵列基板。
所述显示装置可以为显示面板,或者包括显示面板和驱动电路的显示器件。
优选地,所述显示装置为液晶显示装置。
本发明实施例还提供一种阵列基板的制作方法,包括:
形成栅金属层、源漏金属层和多层绝缘层,其中,所述栅金属层包括栅线,所述源漏金属层包括数据线,所述栅线和数据线限定出多个像素区域,所述多层绝缘层中包括至少一层镂空绝缘层,所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
在本发明的一些实施例中,所述形成多层绝缘层的步骤包括:形成栅绝缘层,所述镂空绝缘层包括所述栅绝缘层。
在本发明的一些实施例中,所述阵列基板的制作方法还包括:形成第一透明电极层;
所述形成多层绝缘层的步骤包括:形成位于源漏金属层和第一透明电极层之间的第二绝缘层,所述镂空绝缘层包括所述第二绝缘层。
在本发明的一些实施例中,所述阵列基板为顶栅型阵列基板,所述形成多层绝缘层的步骤包括:形成位于所述栅金属层和源漏金属层之间的第一绝缘层,所述镂空绝缘层包括所述第一绝缘层。
下面结合具体实施例对本发明实施例的阵列基板的结构进行说明。
请参考图1,图1为现有技术中的一ADS模式的阵列基板的结构示意图,该阵列基板包括:衬底基板101,有源层102,栅绝缘层103,栅金属层104,第一绝缘层105,源漏金属层106,第二绝缘层107,公共电极层108,第三绝缘层109和像素电极层110。从图1中可以看出,该阵列基板包括多个绝缘层(栅绝缘层103,第一绝缘层105,第二绝缘层107,和第三绝缘层109),从而影响阵列基板的透过率。
请参考图2和图3,图2和图3为本发明实施例中的一ADS模式的阵列基板的结构示意图,该阵列基板包括:衬底基板101,有源层102,栅绝缘层103,栅金属层,第一绝缘层105,源漏金属层,第二绝缘层107,公共电极层108,第三绝缘层109和像素电极层110。栅金属层包括栅电极1041和栅线1042,源漏金属层包括源电极1061、漏电极1062和数据线1063。所述栅线1042和数据线1063限定出多个像素区域,所述第一绝缘层105位于像素区域内的部分具有镂空区域。
本发明实施例中,在阵列基板的像素区域内,将第一绝缘层105设置镂空区域,从而可减少像素区域内的第一绝缘层105对光线透过率的影响,提高显示品质。
同时,请参考图3,上述实施例中,第一绝缘层105在所述漏电极1062与所述有源层102的搭接位置处(图中虚线框所示位置)也具有镂空区域,从而实现源漏金属层与有源层的连接。
上述实施例中,是将位于栅金属层和源漏金属层之间的第一绝缘层105,在像素区域内,设置镂空区域,当然,在本发明的其他一些实施例中,也可以将源漏金属层和公共电极层108之间的第二绝缘层107,在像素区域内,设置镂空区域,或者,同时将第一绝缘层105和第二绝缘层107在像素区域内设置镂空区域。
上述实施例中,公共电极层108和像素电极层110的位置可以互换。
除非另作定义,本发明使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。同样,“一个”或者“一”等类似词语也不表示数量限制,而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也相应地改变。
以上所述是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明所述原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。

Claims (11)

1.一种阵列基板,包括栅线和数据线,所述栅线和数据线限定出多个像素区域,所述阵列基板还包括多层绝缘层,其特征在于,所述多层绝缘层中包括至少一层镂空绝缘层,所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
2.根据权利要求1所述的阵列基板,其特征在于,所述阵列基板包括栅绝缘层,所述镂空绝缘层包括所述栅绝缘层。
3.根据权利要求1所述的阵列基板,其特征在于,所述阵列基板包括源漏金属层、第一透明电极层和位于所述源漏金属层和第一透明电极层之间的第二绝缘层,所述镂空绝缘层包括所述第二绝缘层。
4.根据权利要求1所述的阵列基板,其特征在于,所述阵列基板为顶栅型阵列基板,所述阵列基板包括源漏金属层、栅金属层和位于所述栅金属层和源漏金属层之间的第一绝缘层,所述镂空绝缘层包括所述第一绝缘层。
5.根据权利要求4所述的阵列基板,其特征在于,还包括:有源层,所述第一绝缘层在所述源漏金属层与所述有源层的搭接位置处具有镂空区域。
6.根据权利要求1-5任一项所述的阵列基板,其特征在于,所述镂空绝缘层在所述像素区域内全部镂空。
7.一种显示装置,其特征在于,包括如权利要求1-6任一项所述的阵列基板。
8.一种阵列基板的制作方法,其特征在于,包括:
形成栅金属层、源漏金属层和多层绝缘层,其中,所述栅金属层包括栅线,所述源漏金属层包括数据线,所述栅线和数据线限定出多个像素区域,所述多层绝缘层中包括至少一层镂空绝缘层,所述镂空绝缘层位于所述像素区域内的部分具有镂空区域。
9.根据权利要求8所述的阵列基板的制作方法,其特征在于,形成多层绝缘层的步骤包括:
形成栅绝缘层,所述镂空绝缘层包括所述栅绝缘层。
10.根据权利要求8所述的阵列基板的制作方法,其特征在于,还包括:形成第一透明电极层;
形成多层绝缘层的步骤包括:
形成位于源漏金属层和第一透明电极层之间的第二绝缘层,所述镂空绝缘层包括所述第二绝缘层。
11.根据权利要求8所述的阵列基板的制作方法,其特征在于,所述阵列基板为顶栅型阵列基板,形成多层绝缘层的步骤包括:
形成位于所述栅金属层和源漏金属层之间的第一绝缘层,所述镂空绝缘层包括所述第一绝缘层。
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