CN104360557B - 阵列基板及其制造方法,以及显示装置 - Google Patents
阵列基板及其制造方法,以及显示装置 Download PDFInfo
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- CN104360557B CN104360557B CN201410697709.1A CN201410697709A CN104360557B CN 104360557 B CN104360557 B CN 104360557B CN 201410697709 A CN201410697709 A CN 201410697709A CN 104360557 B CN104360557 B CN 104360557B
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Abstract
本发明的实施例提供阵列基板及其制造方法,以及显示装置。该阵列基板的制造方法,包括:形成薄膜晶体管;形成覆盖所述薄膜晶体管的钝化层,该钝化层具有过孔并且该过孔露出所述薄膜晶体管的漏极的至少一部分;形成过孔导电层,该过孔导电层覆盖所述漏极于所述过孔处露出的部分并连接所述漏极;对所述过孔导电层进行处理,以使所述过孔导电层的反射率低于所述漏极的反射率;以及形成像素电极,该像素电极通过所述过孔导电层连接所述漏极。
Description
技术领域
本发明的实施例涉及阵列基板及其制造方法,以及显示装置。
背景技术
薄膜晶体管液晶显示装置主要包括阵列基板、彩膜基板以及夹置在阵列基板和彩膜基板之间的液晶层。阵列基板包括栅线、数据线以及由栅线和数据线彼此交叉而限定的多个像素区域。在每个像素区域内形成有薄膜晶体管和像素电极。像素电极经由于覆盖薄膜晶体管的钝化层中形成的过孔而与薄膜晶体管的漏极连接。彩膜基板上形成有红、绿、蓝(R、G、B)三种彩膜组成的彩膜层和黑矩阵。黑矩阵与薄膜晶体管对应设置,防止漏光。
在实际工艺中,阵列基板和彩膜基板对盒时往往会存在偏差,因此需要增大黑矩阵的宽度,以避免对盒偏差造成漏光。然而,增大黑矩阵的宽度会降低像素区域的开口率,影响显示效果。为了解决上述问题,将彩膜层及黑矩阵直接形成在阵列基板上的COA(Colorfilter On Array)技术应用而生。在COA技术中,彩膜层和黑矩阵与薄膜晶体管一起形成在阵列基板上,如此不仅可以提升显示装置的开口率,增加显示装置的亮度,而且避免了将彩膜层和薄膜晶体管形成在不同基板上所衍生的各种问题。
然而,在COA技术中,黑矩阵形成在阵列基板上,此时尽管黑矩阵可以遮挡薄膜晶体管及大面积的金属线(例如,栅线、数据线),然而由于位于钝化层过孔处的漏极需要与像素电极连接,因此位于过孔处的漏极是不能被黑矩阵遮挡的。在此情形下,过孔处的漏极将反射环境光,造成显示装置的对比度和色纯度下降,从而严重影响显示装置的显示效果。
发明内容
根据本发明的实施例,提供一种阵列基板的制造方法。例如,该阵列基板的制造方法可以包括:形成薄膜晶体管;形成覆盖所述薄膜晶体管的钝化层,该钝化层具有过孔并且该过孔露出所述薄膜晶体管的漏极的至少一部分;形成过孔导电层,该过孔导电层覆盖所述漏极于所述过孔处露出的部分并连接所述漏极;对所述过孔导电层进行处理,以使所述过孔导电层的反射率低于所述漏极的反射率;以及形成像素电极,该像素电极通过所述过孔导电层连接所述漏极。
例如,所述方法还可以包括:形成公共电极。所述过孔导电层与所述公共电极同时形成,并且所述过孔导电层与所述公共电极彼此断开。
例如,所述方法还可以包括:在所述过孔导电层和所述公共电极上形成电极间绝缘层;对所述电极间绝缘层进行构图工艺,以露出所述过孔导电层;以及对所述过孔导电层进行处理,以使所述过孔导电层的反射率低于所述漏极的反射率。
例如,所述方法还可以包括:在所述电极间绝缘层上形成所述像素电极。
例如,所述过孔导电层可以与所述像素电极一体形成。
例如,所述方法还可以包括:形成像素电极层;在像素电极层上涂覆光刻胶,采用双色调掩模板对光刻胶进行曝光、显影,以形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶完全去除区域,该光刻胶完全保留区域对应于要形成所述像素电极的区域,该光刻胶部分保留区域对应于要形成所述过孔导电层的区域,该光刻胶完全去除区域对应于其他区域;蚀刻去除光刻胶完全去除区域的像素电极层;灰化去除光刻胶部分保留区域的光刻胶,以形成所述过孔导电层;以剩余的光刻胶作为掩模,对所述过孔导电层进行处理以使过孔导电层的反射率低于漏极的反射率;以及去除剩余的光刻胶,得到像素电极。
例如,所述方法还可以包括:形成像素电极层;采用第一单色调掩模板对所述像素电极层进行构图工艺以形成所述像素电极和过孔导电层;以及采用第二单色调掩模板对所述过孔导电层进行处理,以使所述过孔导电层的反射率低于所述漏极的反射率。
例如,对所述过孔导电层进行处理可以包括:对所述过孔导电层进行氢化处理。
例如,所述氢化处理可以采用氢等离子体。
例如,所述方法还可以包括:形成黑矩阵和彩膜层,其中所述黑矩阵形成为对应于所述薄膜晶体管,并且所述彩膜层形成为对应于所述像素电极。
例如,所述方法还可以包括:形成有机绝缘层,其中所述有机绝缘层形成为位于所述像素电极所在层与所述漏极所在的层之间。
例如,所述方法还可以包括:形成隔垫物,其中所述隔垫物位于所述阵列基板的最上层。
根据本发明的实施例,提供一种阵列基板。例如,该阵列基板可以包括:薄膜晶体管;钝化层,覆盖所述薄膜晶体管,该钝化层具有过孔并且该过孔露出所述薄膜晶体管的漏极的至少一部分;过孔导电层,覆盖所述漏极于所述过孔处露出的部分并连接所述漏极,并且所述过孔导电层的反射率低于所述漏极的反射率;以及像素电极,该像素电极通过所述过孔导电层连接所述漏极。
例如,所述阵列基板还可以包括公共电极。所述过孔导电层与所述公共电极同层设置,并且所述过孔导电层与所述公共电极彼此断开。
例如,所述过孔导电层与所述像素电极同层设置,并且所述过孔导电层与所述像素电极彼此连接。
例如,所述阵列基板还可以包括黑矩阵和彩膜层,其中所述黑矩阵对应于所述薄膜晶体管,并且所述彩膜层对应于所述像素电极。
例如,所述阵列基板还可以包括有机绝缘层,其中所述有机绝缘层位于所述像素电极所在层与所述漏极所在的层之间。
例如,所述阵列基板还可以包括隔垫物,其中所述隔垫物位于所述阵列基板的最上层。
根据本发明的实施例,提供一种显示装置。例如,该显示装置可以包括如上所述的阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案,下面将对实施例的附图作简单地介绍,显而易见地,下面描述中的附图仅仅涉及本发明的一些实施例,而非对本发明的限制。
图1是示出在根据本发明实施例的阵列基板的制造方法中形成薄膜晶体管的示意图;
图2是示出在根据本发明实施例的阵列基板的制造方法中形成钝化层及过孔的示意图;
图3是示出在根据本发明实施例的阵列基板的制造方法中形成黑矩阵的示意图;
图4是示出在根据本发明实施例的阵列基板的制造方法中形成彩膜层的示意图;
图5是示出在根据本发明实施例的阵列基板的制造方法中形成公共电极和过孔导电层的示意图;
图6是示出在根据本发明实施例的阵列基板的制造方法中形成电极间绝缘层的示意图;
图7是示出在根据本发明实施例的阵列基板的制造方法中对过孔导电层进行处理以降低其反射率的示意图;
图8是示出在根据本发明实施例的阵列基板的制造方法中形成像素电极的示意图;
图9是示出在根据本发明实施例的阵列基板的制造方法中形成隔垫物的示意图;
图10示出在根据本发明实施例的阵列基板的制造方法中形成有机绝缘层的示意图;以及
图11是示出在根据本发明实施例的阵列基板的制造方法中形成像素电极和过孔导电层的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例的附图,对本发明实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于所描述的本发明的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。
除非另作定义,此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。同样,“一个”、“一”或者“该”等类似词语也不表示数量限制,而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同,并不排除其他元件或者物件。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
根据本发明的实施例,提供一种阵列基板的制造方法。该阵列基板的制造方法包括:形成薄膜晶体管;形成覆盖所述薄膜晶体管的钝化层,该钝化层具有过孔并且该过孔露出所述薄膜晶体管的漏极的至少一部分;形成过孔导电层,该过孔导电层覆盖所述漏极于所述过孔处露出的部分并连接所述漏极;对所述过孔导电层进行处理,以使所述过孔导电层的反射率低于所述漏极的反射率;以及形成像素电极,该像素电极通过所述过孔导电层连接所述漏极。
在根据本发明实施例的阵列基板的制造方法中,由于过孔导电层覆盖漏极于钝化层过孔处露出的部分且经处理后的过孔导电层的反射率低于漏极的反射率,因此能够避免漏极反光并能够提高显示装置的显示质量。
在根据本发明实施例的阵列基板的制造方法中,可以采用单独的工艺形成过孔导电层并采用单独的工艺对过孔导电层进行处理以降低其反射率。然而,为了简化制造工艺并降低制造成本,希望形成过孔导电层的步骤及对过孔导电层进行处理以降低其反射率的步骤能与形成阵列基板的其他部件的步骤同时进行。例如,一种情形下:过孔导电层与公共电极同时形成;以及另一种情形下:过孔导电层与像素电极同时形成。下面,作为示例,将结合附图对上述两种情形下的阵列基板的制造方法进行详细的描述。
[过孔导电层与公共电极同时形成]
图1至图10是示出根据本发明实施例的阵列基板的制造方法的示意图。如图1至图10所示,根据本发明实施例的阵列基板的制造方法包括以下步骤。
首先,在基底基板1上形成薄膜晶体管,如图1所示。薄膜晶体管可以是底栅型或顶栅型。作为示例,图中示出了底栅型的薄膜晶体管。
薄膜晶体管包括栅极2、栅绝缘层5、有源层6、源极7和漏极8。在形成栅极2的同时,还可以形成栅线(未示出)、公共电极线3和接口区焊垫4。在形成源极7和漏极8的同时还可以形成数据线(未示出)。所述栅线和数据线彼此交叉以限定矩阵形式的多个像素单元。在图中,作为示例,仅示出了一个像素单元,但是其他像素单元可以相似地形成。
接着,形成钝化层9,并对钝化层9进行构图工艺以在钝化层9中形成过孔10,如图2所示。过孔10位于薄膜晶体管的漏极8处,以露出漏极8的至少一部分。在形成过孔10的同时,还可以形成附加过孔10’。附加过孔10’位于公共电极线3处并延伸穿过栅绝缘层5以露出公共电极线3的一部分。
接着,形成黑矩阵11和彩膜层12,如图3和图4所示。黑矩阵11形成为对应于薄膜晶体管,彩膜层12形成为对应于像素电极。
例如,阵列基板包括红色像素单元、绿色像素单元和蓝色像素单元,相应地,彩膜层12包括位于红色像素单元中的红色彩膜、位于绿色像素单元中的绿色彩膜和位于蓝色像素单元中的蓝色彩膜。红色彩膜、绿色彩膜和蓝色彩膜分别通过不同的构图工艺形成。
接着,形成公共电极13和过孔导电层14,如图5所示。具体而言,首先沉积一层公共电极层,然后对公共电极层进行构图工艺以同时形成公共电极13和过孔导电层14。公共电极13和过孔导电层14彼此断开。公共电极13经由附加过孔10’连接到公共电极线3。过孔导电层14位于过孔10处。更进一步地,过孔导电层14覆盖漏极8于过孔10处露出的部分并连接漏极8。例如,公共电极13和过孔导电层14由ITO(Indium Tin Oxide)、IZO(Indium ZincOxide)、氧化锡等透明导电氧化物形成。
接着,形成电极间绝缘层15并对电极间绝缘层15进行构图工艺以露出过孔导电层14,如图6所示。电极间绝缘层15覆盖整个基板而仅露出过孔导电层14。
接着,对露出的过孔导电层14进行处理,以使其反射率降低,如图7所示。例如,所述处理为氢化处理,并且进一步地,该氢化处理采用氢等离子体。例如,在40-200mtorr的压强下对过孔导电层14进行10-300秒的氢化处理。更进一步地,例如,在60mtorr的压强下对过孔导电层14进行60秒的氢化处理。如上所述过孔导电层可以由ITO形成,ITO通常包含90%的In2O3和10%的SnO2,当进行氢化处理时,氢可以将SnO2中的Sn还原,被还原的Sn从ITO的表面析出形成雾状的黑点,从而可使得过孔导电层14的反射率显著降低并低于由金属形成的漏极8的反射率。由于过孔导电层14覆盖漏极8于过孔10处露出的部分并且经处理后的过孔导电层14的反射率低于漏极8的反射率,因此能够避免漏极8反射环境光的情形,从而提高显示装置的显示效果。
另外,在上述对露出的过孔导电层14进行处理以降低其反射率的步骤中,电极间绝缘层15可以保护整个基板不受影响,所以在该步骤中不需要设置专门的掩模板来保护基板,从而进一步简化了制造工艺并降低了制造成本。
最后,形成像素电极16,如图8所示。例如,像素电极16由ITO(Indium Tin Oxide)、IZO(Indium Zinc Oxide)、氧化锡等透明导电氧化物形成,并且像素电极16为具有多个狭缝的狭缝电极。像素电极16通过过孔导电层14与薄膜晶体管的漏极8连接。
[过孔导电层与像素电极同时形成]
下面,将参照图11对过孔导电层与像素电极同时形成的情形进行描述。在下面的描述中,将仅描述与过孔导电层和公共电极同时形成的情形不同的特征,而相同的特征将不再重复描述。
在根据本发明实施例的阵列基板的制造方法中,过孔导电层14和像素电极16可以同时形成并相互连接。如图11所示,过孔导电层14和像素电极16可以一体形成。
例如,在形成过孔导电层14和像素电极16并对过孔导电层14进行处理以降低其反射率的过程中,可以采用双色调掩模板(诸如,灰色调掩模板和半色调掩模板)。首先,形成像素电极层;然后在像素电极层上涂覆光刻胶,采用双色调掩模板对光刻胶进行曝光、显影,以形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶完全去除区域,该光刻胶完全保留区域对应于要形成像素电极的区域,该光刻胶部分保留区域对应于要形成过孔导电层的区域,该光刻胶完全去除区域对应于其他区域;蚀刻去除光刻胶完全去除区域的像素电极层;灰化去除光刻胶部分保留区域的光刻胶,以形成过孔导电层;以剩余的光刻胶作为掩模,对所述过孔导电层进行处理以使过孔导电层的反射率低于漏极的反射率;以及去除剩余的光刻胶,得到像素电极。由于在形成过孔导电层14和像素电极16并对过孔导电层14进行处理以降低其反射率的过程中仅采用了一块双色调掩模板,因此可以进一步简化制造工艺并降低制造成本。
例如,像素电极16和过孔导电层14由ITO(Indium Tin Oxide)、IZO(Indium ZincOxide)、氧化锡等透明导电氧化物形成。
例如,所述处理为氢化处理,并且进一步地,该氢化处理采用氢等离子体。例如,在40-200mtorr的压强下对过孔导电层14进行10-300秒的氢化处理。更进一步地,例如,在60mtorr的压强下对过孔导电层14进行60秒的氢化处理。如上所述过孔导电层可以由ITO形成,ITO通常包含90%的In2O3和10%的SnO2,当进行氢化处理时,氢可以将SnO2中的Sn还原,被还原的Sn从ITO的表面析出形成雾状的黑点,从而可使得过孔导电层14的反射率显著降低并低于由金属形成的漏极8的反射率。由于过孔导电层14覆盖漏极8于过孔10处露出的部分并且经处理后的过孔导电层14的反射率低于漏极8的反射率,因此能够避免漏极8反射环境光的情形,从而提高显示装置的显示效果。
当然,在形成过孔导电层14和像素电极16并对过孔导电层14进行处理以降低其反射率的过程中,也可以采用两次单色调掩模板。首先,形成像素电极层;然后采用第一单色调掩模板对像素电极层进行构图工艺以得到一体形成的像素电极和过孔导电层;最后再采用第二单色调掩模板对过孔导电层14进行处理,以使其反射率低于漏极的反射率。
例如,采用第二单色调掩模板对过孔导电层14进行处理以使其反射率低于漏极的反射率可以包括:涂覆光刻胶,以覆盖整个基板;采用所述第二单色调掩模板对所述光刻胶进行曝光、显影,以形成光刻胶完全去除区域和光刻胶完全保留区域,该光刻胶完全去除区域对应于所述过孔导电层,该光刻胶完全保留区域对应于其他区域;对光刻胶完全去除区域的过孔导电层进行处理,以使其反射率低于漏极的反射率;以及去除光刻胶完全保留区域的光刻胶。
需要说明的是,尽管图11中示出的是ADS模式的显示装置的阵列基板,但是上面描述的过孔导电层与像素电极同时形成的技术方案也同样适用于VA模式、IPS模式等的显示装置的阵列基板。
需要说明的是,在根据本发明实施例的阵列基板的制造方法中,除了上述步骤之外,还可以形成隔垫物17,如图9所示。在将阵列基板与对向基板对盒之后,隔垫物17用于维持阵列基板和对向基板之间的盒厚。例如,隔垫物17位于阵列基板的最上层。
需要说明的是,在根据本发明实施例的阵列基板的制造方法中,除了上述步骤之外,还可以形成有机绝缘层18,如图10所示。该有机绝缘层18位于像素电极16所在层与漏极8所在的层之间,以降低像素电极16与漏极8所在的层之间的寄生电容,例如像素电极16与数据线之间的寄生电容Cpd。例如,该有机绝缘层18由聚酰亚胺、环氧树脂等形成。
需要说明的是,在根据本发明实施例的阵列基板的制造方法中,基底基板1、栅极2、栅绝缘层5、有源层6、源极7和漏极8、钝化层9、黑矩阵11、彩膜层12、电极间绝缘层15以及隔垫物17可以由本领域已知的材料和工艺形成,在此不再赘述。
根据本发明的实施例,还提供一种阵列基板。该阵列基板包括:薄膜晶体管;钝化层,覆盖所述薄膜晶体管,该钝化层具有过孔并且该过孔露出所述薄膜晶体管的漏极的至少一部分;过孔导电层,覆盖所述漏极于所述过孔处露出的部分并连接所述漏极,并且所述过孔导电层的反射率低于所述漏极的反射率;以及像素电极,该像素电极通过所述过孔导电层连接所述漏极。
在根据本发明实施例的阵列基板中,由于过孔导电层覆盖漏极于钝化层过孔处露出的部分且过孔导电层的反射率低于漏极的反射率,因此能够避免漏极反光并能够提高显示装置的显示质量。
根据本发明的实施例,还提供一种显示装置,其包括上述任一实施例的阵列基板。该显示装置包括阵列基板与对向基板,该阵列基板与对向基板彼此对置以形成液晶盒,在液晶盒中填充有液晶材料。该对向基板例如为彩膜基板。在一些示例中,该液晶显示装置还包括为阵列基板提供背光的背光源。所述液晶显示装置例如可以实现为:液晶面板、电子纸、有机发光二极管(OLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、手表等任何具有显示功能的产品或部件。
由于根据本发明实施例的阵列基板包括如上所述的阵列基板,因此能够避免漏极反光并能够提高显示装置的显示质量。
以上所述仅是本发明的示范性实施例,而非用于限制本发明的保护范围,本发明的保护范围由权利要求确定。
Claims (19)
1.一种阵列基板的制造方法,该阵列基板包括栅线、数据线以及栅线和数据线彼此交叉所限定的像素单元,
其中,所述方法包括:
形成薄膜晶体管;
形成覆盖所述薄膜晶体管的钝化层,该钝化层具有过孔并且该过孔露出所述薄膜晶体管的漏极的至少一部分;
形成过孔导电层,该过孔导电层覆盖所述漏极于所述过孔处露出的部分并连接所述漏极;
对所述过孔导电层进行处理,以使所述过孔导电层的反射率低于所述漏极的反射率;以及
形成像素电极,该像素电极通过所述过孔导电层连接所述漏极,
其中所述过孔导电层设置在所述过孔处且不延伸进入所述像素单元的显示区域。
2.根据权利要求1所述的阵列基板的制造方法,还包括:形成公共电极,其中所述过孔导电层与所述公共电极同时形成,并且所述过孔导电层与所述公共电极彼此断开。
3.根据权利要求2所述的阵列基板的制造方法,还包括:
在所述过孔导电层和所述公共电极上形成电极间绝缘层;
对所述电极间绝缘层进行构图工艺,以露出所述过孔导电层;以及
对所述过孔导电层进行处理,以使所述过孔导电层的反射率低于所述漏极的反射率。
4.根据权利要求3所述的阵列基板的制造方法,还包括:在所述电极间绝缘层上形成所述像素电极。
5.根据权利要求1所述的阵列基板的制造方法,其中所述过孔导电层与所述像素电极一体形成。
6.根据权利要求5所述的阵列基板的制造方法,还包括:
形成像素电极层;
在像素电极层上涂覆光刻胶,采用双色调掩模板对光刻胶进行曝光、显影,以形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶完全去除区域,该光刻胶完全保留区域对应于要形成所述像素电极的区域,该光刻胶部分保留区域对应于要形成所述过孔导电层的区域,该光刻胶完全去除区域对应于其他区域;
蚀刻去除光刻胶完全去除区域的像素电极层;
灰化去除光刻胶部分保留区域的光刻胶,以形成所述过孔导电层;
以剩余的光刻胶作为掩模,对所述过孔导电层进行处理以使过孔导电层的反射率低于漏极的反射率;以及
去除剩余的光刻胶,得到像素电极。
7.根据权利要求5所述的阵列基板的制造方法,还包括:
形成像素电极层;
采用第一单色调掩模板对所述像素电极层进行构图工艺以形成所述像素电极和过孔导电层;以及
采用第二单色调掩模板对所述过孔导电层进行处理,以使所述过孔导电层的反射率低于所述漏极的反射率。
8.根据权利要求1-7任一项所述的阵列基板的制造方法,其中对所述过孔导电层进行处理包括:对所述过孔导电层进行氢化处理。
9.根据权利要求8所述的阵列基板的制造方法,其中所述氢化处理采用氢等离子体。
10.根据权利要求1-7任一项所述的阵列基板的制造方法,还包括:形成黑矩阵和彩膜层,其中所述黑矩阵形成为对应于所述薄膜晶体管,并且所述彩膜层形成为对应于所述像素电极。
11.根据权利要求1-7任一项所述的阵列基板的制造方法,还包括:形成有机绝缘层,其中所述有机绝缘层形成为位于所述像素电极所在层与所述漏极所在的层之间。
12.根据权利要求1-7任一项所述的阵列基板的制造方法,还包括:形成隔垫物,其中所述隔垫物位于所述阵列基板的最上层。
13.一种阵列基板,包括:
薄膜晶体管;
钝化层,覆盖所述薄膜晶体管,该钝化层具有过孔并且该过孔露出所述薄膜晶体管的漏极的至少一部分;
过孔导电层,覆盖所述漏极于所述过孔处露出的部分并连接所述漏极,并且所述过孔导电层的反射率低于所述漏极的反射率;以及
像素电极,该像素电极通过所述过孔导电层连接所述漏极,
其中所述阵列基板还包括栅线、数据线以及栅线和数据线彼此交叉所限定的像素单元,并且
其中所述过孔导电层设置在所述过孔处且不延伸进入所述像素单元的显示区域。
14.根据权利要求13所述的阵列基板,还包括公共电极,其中所述过孔导电层与所述公共电极同层设置,并且所述过孔导电层与所述公共电极彼此断开。
15.根据权利要求13所述的阵列基板,其中所述过孔导电层与所述像素电极同层设置,并且所述过孔导电层与所述像素电极彼此连接。
16.根据权利要求13-15任一项所述的阵列基板,还包括黑矩阵和彩膜层,其中所述黑矩阵对应于所述薄膜晶体管,并且所述彩膜层对应于所述像素电极。
17.根据权利要求13-15任一项所述的阵列基板,还包括有机绝缘层,其中所述有机绝缘层位于所述像素电极所在层与所述漏极所在的层之间。
18.根据权利要求13-15任一项所述的阵列基板,还包括隔垫物,其中所述隔垫物位于所述阵列基板的最上层。
19.一种显示装置,包括如权利要求13所述的阵列基板。
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CN105304648A (zh) * | 2015-10-23 | 2016-02-03 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN105278193B (zh) * | 2015-11-19 | 2018-09-18 | 深圳市华星光电技术有限公司 | 阵列基板及其制造方法、液晶显示面板 |
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CN105742293A (zh) * | 2016-03-01 | 2016-07-06 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法 |
CN108666218A (zh) * | 2017-03-29 | 2018-10-16 | 京东方科技集团股份有限公司 | 薄膜晶体管和显示基板及其制作方法、显示装置 |
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US9437487B2 (en) | 2016-09-06 |
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