WO2016078272A1 - 一种基板及其制造方法、显示装置 - Google Patents

一种基板及其制造方法、显示装置 Download PDF

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Publication number
WO2016078272A1
WO2016078272A1 PCT/CN2015/074856 CN2015074856W WO2016078272A1 WO 2016078272 A1 WO2016078272 A1 WO 2016078272A1 CN 2015074856 W CN2015074856 W CN 2015074856W WO 2016078272 A1 WO2016078272 A1 WO 2016078272A1
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WIPO (PCT)
Prior art keywords
auxiliary
insulating layer
data line
line
gate line
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PCT/CN2015/074856
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English (en)
French (fr)
Inventor
张翔燕
武延兵
李文波
李盼
贾倩
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/785,808 priority Critical patent/US9703162B2/en
Priority to EP15778189.9A priority patent/EP3223311B1/en
Publication of WO2016078272A1 publication Critical patent/WO2016078272A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133528—Polarisers
    • G02F1/133548—Wire-grid polarisers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/136295—Materials; Compositions; Manufacture processes
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Definitions

  • the present invention relates to the field of display manufacturing, and in particular to a substrate, a method of manufacturing the same, and a display device.
  • Liquid crystal display has the advantages of light weight, thin thickness and low power consumption, and is widely used in electronic products such as televisions, mobile phones, and displays.
  • the liquid crystal display is composed of a matrix of pixels in both horizontal and vertical directions.
  • the drive circuit outputs a drive signal to scan each pixel unit line by line.
  • the driving circuit of the liquid crystal display mainly comprises a gate driving circuit and a source driving circuit, and the source driving circuit sequentially latches the input display data and the clock signal, and converts the source driving signal into the data line of the liquid crystal panel; the gate The driving circuit converts the input clock signal into a gate driving signal through a shift register, and applies it to the gate line of the liquid crystal panel row by row, and each pixel unit in the pixel matrix is under the control of the gate driving circuit and the source driving circuit. Show grayscale.
  • the gate driving circuit needs to input the gate driving signal into the pixel unit through the gate line, and the source driving circuit also needs to input the converted source driving signal into the pixel unit through the data line, so the resistance in the gate line or the data line is coming. A larger one will cause an increase in the delay of the gate drive signal or the source drive signal, which in turn causes the display gray scale to be abnormal.
  • Embodiments of the present invention provide a substrate, a method of fabricating the same, and a display device for reducing resistance of a gate line or a data line, thereby reducing signal delay caused by gate line resistance or data line resistance in a display device, and the present invention
  • the embodiment adopts the following technical solutions:
  • a substrate including: a substrate substrate on which a plurality of gate lines are disposed in parallel, and a first insulating layer covering the gate lines is disposed on the first insulating layer a plurality of data lines perpendicular to the gate line covering a second insulating layer of the data line, And a pixel electrode located in the sub-pixel region formed by the data line and the gate line;
  • the substrate further includes:
  • a polarizing film covering the pixel electrode, the projection of the polarizing film being opposite to the pixel electrode;
  • a first auxiliary gate line disposed on the second insulating layer parallel to the gate line, a projection of the first auxiliary gate line being opposite to the gate line, and at least two on each of the first auxiliary gate lines At least two positions opposite to the gate line are electrically connected by via holes penetrating the first insulating layer and the second insulating layer, wherein the first auxiliary gate line and the polarizing film are passed through The same patterning process of the same layer of transparent conductive material is formed;
  • the substrate further includes:
  • a polarizing film covering the pixel electrode, the projection of the polarizing film being opposite to the pixel electrode;
  • a first auxiliary data line disposed on the second insulating layer parallel to the data line, a projection of the first auxiliary data line is opposite to the data line, and at least two of each of the first auxiliary data lines At least two locations opposite the data line are electrically connected by vias penetrating the second insulating layer, wherein the first auxiliary data line and the polarizing film are the same through the same layer of transparent conductive material The sub-patterning process is formed.
  • the substrate includes the polarizing film and the first auxiliary gate line, between adjacent two data lines, between each of the gate lines and the corresponding first auxiliary gate line A via hole penetrating the first insulating layer and the second insulating layer is disposed.
  • the substrate includes the polarizing film and the first auxiliary data line, between each adjacent two gate lines, between each of the data lines and the corresponding first auxiliary data line A via hole penetrating the second insulating layer is provided.
  • the substrate when the substrate includes: the polarizing film and the first auxiliary gate line, the substrate further includes: a second auxiliary data line;
  • the second auxiliary data line is disposed on the second insulating layer, the second auxiliary data line is parallel to the data line, and the projection of the second auxiliary data line is opposite to the data line,
  • the second auxiliary data line is partitioned into the plurality of auxiliary data line segments by the first auxiliary gate line, and at least two positions on the auxiliary data line segment and at least two positions opposite to the data line pass through the second insulating layer
  • the via electrical connection wherein the first auxiliary gate line, the polarizing film, and the second auxiliary data line are formed by the same patterning process of the same layer of transparent conductive material.
  • the substrate when the substrate includes the polarizing film and the first auxiliary data line, the substrate further includes: a second auxiliary gate line;
  • the second auxiliary gate line is disposed on the second insulating layer, the second auxiliary gate line is parallel to the gate line, and a projection of the second auxiliary gate line is opposite to the gate line, the first Separating the second auxiliary gate lines by the first auxiliary data lines into a plurality of auxiliary gate line segments, at least two positions on each of the auxiliary gate line segments and at least two positions opposite to the gate lines passing through the first
  • the via is electrically connected to the via of the second insulating layer; wherein the first auxiliary data line, the polarizing film, and the second auxiliary gate line are formed by the same patterning process of the same layer of transparent conductive material.
  • the transparent conductive material is a wire grid polarizing material.
  • a display device comprising the substrate of any of the above is provided.
  • a substrate manufacturing method including:
  • Forming the polarizing film and the first auxiliary gate line comprising: forming at least two via holes penetrating the first insulating layer and the second insulating layer at positions corresponding to each of the gate lines by a first patterning process; a transparent conductive material layer covering the pixel electrode and the second insulating layer; performing a second patterning process on the transparent conductive material layer to form a polarizing film and a first auxiliary gate line, each of the gate lines and a corresponding first An auxiliary gate line is electrically connected through a via hole penetrating the first insulating layer and the second insulating layer;
  • Forming the polarizing film and the first auxiliary data line comprising: forming at least two via holes penetrating the second insulating layer at positions corresponding to each of the data lines by a first patterning process; forming a covering of the pixel electrodes and the a transparent conductive material layer of the second insulating layer; performing a second patterning process on the transparent conductive material layer to form a polarizing film and a first auxiliary data line, each of the data lines and the corresponding first auxiliary data line passing through At least two vias on the second insulating layer are electrically connected.
  • the method when the method includes the steps of: forming a polarizing film and a first auxiliary gate line, the method further includes:
  • At least two via holes penetrating the second insulating layer are formed at positions corresponding to each of the data lines by the first patterning process;
  • Performing the second patterning process on the transparent conductive material layer to form a second auxiliary data line the second auxiliary data line being partitioned by the first auxiliary gate line into a plurality of auxiliary data line segments, each of the auxiliary data lines At least two locations on the line segment opposite the data line are electrically connected by vias extending through the second insulating layer.
  • the method when the method includes the steps of: forming a polarizing film and a first auxiliary data line, the method further includes:
  • At least two via holes penetrating the first insulating layer and the second insulating layer are formed at positions corresponding to each of the gate lines by the first patterning process ;
  • Performing the second patterning process on the transparent conductive material layer to form a second auxiliary gate line the second auxiliary gate line being separated by the first auxiliary data line into a plurality of auxiliary gate line segments, each of the auxiliary gate lines At least two locations on the line segment opposite the gate line are electrically connected by vias extending through the first insulating layer and the second insulating layer.
  • the transparent conductive material is a wire grid polarizing material.
  • the first auxiliary gate line is disposed on the second insulating layer, and the first auxiliary gate line and the gate line are passed through at least two through the first insulating layer and the second
  • the via holes of the insulating layer are connected in parallel, thereby reducing the resistance of the gate line, or providing a first auxiliary data line on the second insulating layer, and passing the first auxiliary data line and the data line through at least two through the second insulating layer
  • the vias are connected in parallel, thereby reducing the resistance of the data lines, thereby reducing the signal delay caused by the gate line resistance or the data line resistance in the display device.
  • FIG. 1 is a schematic structural view of a substrate according to an embodiment of the present invention.
  • Figure 2 is a cross-sectional view showing a cross section of the substrate A-A' of Figure 1 according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of another substrate according to an embodiment of the present invention.
  • Figure 4 is a cross-sectional view showing a cross section of the substrate B-B' of Figure 3 according to an embodiment of the present invention
  • Figure 5 is a cross-sectional view showing a cross section of the substrate C-C' of Figure 3 according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of still another substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of still another substrate according to an embodiment of the present invention.
  • FIG. 8 is a flow chart showing steps of a method for manufacturing a substrate according to an embodiment of the present invention.
  • FIG. 9 is a flow chart showing the steps of a method for manufacturing another substrate according to an embodiment of the present invention.
  • upper and lower are based on the order in which the substrate is manufactured.
  • the upper pattern refers to a pattern formed later
  • the lower pattern refers to a pattern formed earlier.
  • FIG. 1 is a top view of the substrate, and FIG. 2 is a cross-sectional view taken along line AA' of the top view of FIG. 1;
  • the substrate substrate 101 includes a plurality of parallel gate lines 103 disposed on the substrate substrate 101, and a first insulating layer 102 covering the gate lines 103, located on the first insulating layer 102 and the gate a plurality of data lines 104 perpendicular to the line 103, a second insulating layer 105 covering the data lines; and a pixel electrode 106 located in the sub-pixel region formed around the data line 104 and the gate line 103; Also includes:
  • the projection of the polarizing film 107 is opposite to the pixel electrode 106;
  • the auxiliary gate line 108, the projection of the first auxiliary gate line 108 is opposite to the gate line 103, and at least two locations on each of the first auxiliary gate lines 108 are opposite to the gate line 103. At least two locations are electrically connected by vias 109 penetrating the first insulating layer 102 and the second insulating layer 105, wherein the first auxiliary gate line 108 and the polarizing film 107 are transparent conductive materials through the same layer The same patterning process is formed.
  • a first auxiliary gate line is disposed on the second insulating layer, and the first auxiliary gate line and the gate line are connected in parallel through the via hole penetrating the first insulating layer and the second insulating layer, thereby reducing The resistance of the gate line further reduces the delay of the signal due to the gate line resistance in the display device.
  • the transparent conductive material is a wire grid polarizing material, for example, a WGP (Wire Grid Polarizer).
  • WGP Wireless Grid Polarizer
  • the polarizing film in the embodiment of the present invention is formed by a WGP deposited directly on the pixel electrode, wherein the thickness of the polarizing film can be controlled by a deposition process; and the polarizer of the conventional display device is compounded by a multilayer polymer material. The polarizer is then fixed to the substrate by an adhesive.
  • the embodiment of the present invention can more easily control the thickness of the module of the display device, thereby further reducing the thickness of the module of the display device;
  • An auxiliary gate line and a polarizing film are formed by the same patterning process for the same layer of material.
  • the embodiment of the present invention does not require an additional process flow.
  • FIGS. 3, 4, and 5 An embodiment of the present invention provides a substrate, which is shown in FIGS. 3, 4, and 5, wherein FIG. 3 is a plan view of the substrate, and FIG. 4 is a cross-sectional view taken along line BB' of the top view of FIG. A cross-sectional view taken along the line C-C' of the top view shown in FIG.
  • the specific substrate includes: a substrate 101 on which a plurality of gate lines 103 arranged in parallel are disposed to cover the gate lines a first insulating layer 102 of 103, a plurality of data lines 104 on the first insulating layer 102 perpendicular to the gate lines 103, a second insulating layer 105 covering the data lines; and the data lines 104 And the gate line 103 encloses the pixel electrode 106 of the formed sub-pixel region; the substrate further includes:
  • the projection of the polarizing film 107 is opposite to the pixel electrode 106;
  • a first auxiliary data line 110 disposed on the second insulating layer 105 in parallel with the data line 104, the projection of the first auxiliary data line 110 is opposite to the data line 104, each of the first At least two locations on the auxiliary data line 110 and the data line 104 The upper opposite at least two locations are electrically connected by a via 111 extending through the second insulating layer 105, wherein the first auxiliary data line and the polarizing film are the same patterning process through the same layer of transparent conductive material form.
  • the first auxiliary data line is disposed on the second insulating layer, and the first auxiliary data line and the data line are connected in parallel through the via hole penetrating the second insulating layer, thereby reducing the data line.
  • the resistance which in turn reduces the delay of the signal due to the resistance of the data line in the display device.
  • the transparent conductive material is a wire grid polarizing material, for example, may be WGP.
  • the polarizing film in the embodiment of the present invention is formed by a WGP deposited directly on the pixel electrode, wherein the thickness of the polarizing film can be controlled by a deposition process; and the polarizer of the conventional display device is compounded by a multilayer polymer material. The polarizer is then fixed to the substrate by an adhesive.
  • the embodiment of the present invention can more easily control the thickness of the module of the display device, thereby further reducing the thickness of the module of the display device;
  • An auxiliary data line and a polarizing film are formed by the same patterning process for the same layer of material.
  • the embodiment of the present invention does not require an additional process flow.
  • each of the gate lines 103 A via 109 penetrating the first insulating layer 102 and the second insulating layer 105 is disposed between the corresponding first auxiliary gate lines 108.
  • a via hole penetrating the first insulating layer and the second insulating layer is disposed between each of the gate lines and the corresponding first auxiliary gate line, so that Between two adjacent data lines, each of the gate lines and the corresponding first auxiliary gate line are connected in parallel through a via hole penetrating the first insulating layer and the second insulating layer. Since the gate driving circuit supplies a gate driving signal to the gate of the switching transistor in each pixel unit through the gate line, the above connection manner can cause the signal source of the gate driving circuit to be between the gates of each stage switching transistor.
  • the gate line and the first auxiliary gate line are connected in parallel, so the above embodiment can further reduce the resistance between the gate-to-gate drive signal source of the switching transistor in each pixel unit, thereby reducing the gate line in the display device.
  • the signal delay caused by the resistor caused by the resistor.
  • each of the data lines 104 And a corresponding second auxiliary data line 110 is disposed between the second insulation Via 111 of layer 105.
  • a via hole penetrating the second insulating layer is disposed between each of the data lines and the corresponding first auxiliary data line, so that adjacent Between the two gate lines, each of the data lines and the corresponding first auxiliary data line are connected in parallel through a via hole penetrating the second insulating layer. Since the source driving circuit supplies the source driving signal to the source of the switching transistor in each pixel unit through the data line, the connection manner may be such that the signal source of the source driving circuit is between the sources of each stage switching transistor.
  • the data line is connected in parallel with the first auxiliary data line, so the above embodiment can further reduce the resistance between the source of the source-to-source drive signal of the switching transistor in each pixel unit, thereby reducing the data line in the display device.
  • the signal delay caused by the resistor caused by the resistor.
  • the substrate when the substrate includes the first auxiliary gate line 108 and the polarizing film 107, the substrate further includes: a second auxiliary data line 112;
  • the second auxiliary data line 112 is disposed on the second insulating layer 105, the second auxiliary data line 112 is parallel to the data line 104, and the projection of the second auxiliary data line 112 and the data line 104, the second auxiliary data line 112 is partitioned by the first auxiliary gate line 108 into a plurality of auxiliary data line segments 112-1, at least two positions on the auxiliary data line segment 112-1 and the data. At least two opposite positions on the line are electrically connected by a via 109 penetrating the second insulating layer; wherein the first auxiliary gate line 108 and the polarizing film 107 and the second auxiliary data line 112 pass The same patterning process is formed for the same layer of transparent conductive material.
  • the first auxiliary gate line and the second auxiliary data line are formed by the same patterning process of the same layer of transparent conductive material, and the first auxiliary gate line blocks the second auxiliary data line into a plurality of auxiliary data line segments. And at least two positions on each of the auxiliary data line segments and at least two positions opposite to the data line are electrically connected through the via holes penetrating the second insulating layer, so that each auxiliary data line segment is connected in parallel with the corresponding data line, thereby The resistance of the data line is reduced, thereby reducing the signal delay caused by the data line resistance in the display device; further, only the portion of the auxiliary data line segment between the two via holes can be connected in parallel with the corresponding data line.
  • each of the auxiliary data line segments has a via hole at each end thereof, and the auxiliary data line segment is connected to the corresponding data line in parallel through the via holes at both ends to minimize the resistance of the data line, thereby maximizing the resistance of the data line. Reduce the signal delay caused by the data line resistance in the display device.
  • the first auxiliary gate line blocks the second auxiliary data line into a plurality of auxiliary data line segments, thereby avoiding electrical connection between the first auxiliary gate line and the second auxiliary data line. The electrical connection between the gate line and the data line ensures that the display including the above substrate can work normally.
  • the substrate when the substrate includes the first auxiliary data line 110 and the polarizing film 107, the substrate further includes: a second auxiliary gate line 113;
  • the second auxiliary gate line 113 is disposed on the second insulating layer 105, the second auxiliary gate line 113 is parallel to the gate line 103, and the projection of the second auxiliary gate line 113 and the gate line Opposite to 103, the second auxiliary gate line 113 is partitioned by the first auxiliary data line into a plurality of auxiliary gate line segments 113-1, at least two positions on the auxiliary gate line segment 113-1 and the gate lines
  • the opposite at least two positions on the 103 are electrically connected by a via 109 penetrating the first insulating layer and the second insulating layer; wherein the first auxiliary data line 110, the polarizing film 107, and the second auxiliary The gate line 113 is formed by the same patterning process for the same layer of transparent conductive material.
  • the first auxiliary data line and the second auxiliary gate line are formed by the same patterning process of the same layer of transparent conductive material, and the first auxiliary data line blocks the second auxiliary gate line into a plurality of auxiliary gate line segments. And at least two positions on the auxiliary gate line segment at least two positions opposite to the gate line are electrically connected through the via holes penetrating the first insulating layer and the second insulating layer, so that each auxiliary gate line segment and the corresponding The gate lines are connected in parallel, thereby reducing the resistance of the gate line, thereby reducing the signal delay caused by the gate line resistance in the display device; further, the auxiliary gate line segment can only correspond to the portion between the two via holes.
  • the gate lines are connected in parallel, so a preferred way is to have a via hole at each end of the auxiliary gate line segment, and the auxiliary gate line segment can reduce the resistance of the gate line to the greatest extent by connecting the via holes at both ends in parallel with the corresponding gate line. Thereby, the signal delay caused by the gate line resistance in the display device is minimized.
  • the first auxiliary data line blocks the second auxiliary gate line into a plurality of auxiliary gate line segments, thereby avoiding electrical connection between the gate line and the data line caused by electrical connection between the first auxiliary data line and the second auxiliary gate line, thereby ensuring
  • the display including the above substrate can work normally.
  • An embodiment of the present invention provides a substrate manufacturing method for manufacturing the substrate shown in FIGS. 1 and 2.
  • the substrate manufacturing method includes the following steps:
  • the gate line is formed in the above step S801, the first insulating layer is formed in step S802, and the step
  • the method of fabricating the data line in S803 and the second insulating layer in S804 is the same as the method of fabricating the gate line, the first insulating layer, the data line and the second insulating layer in the prior art, and is not limited herein.
  • the first insulating layer and the second insulating layer are both separate layers.
  • the meaning of "layer” may refer to a film formed by a deposition process or the like on a substrate by using a certain material; for example, the first insulating layer may be formed by depositing SiNx (silicon nitride) on a substrate. Got it.
  • the insulating layer may be formed by depositing an insulating film on the substrate by depositing SiNx according to actual needs, and then removing portions on the insulating film by a patterning process to obtain an insulating layer.
  • step S805 in addition to the via holes penetrating the first insulating layer and the second insulating layer by the first patterning process, the pixel electrode and the pixel unit should be formed on the second insulating layer by the first patterning process.
  • the patterning process used in the method of manufacturing the substrate generally includes processes such as cleaning, film formation, photoresist coating, exposure, development, etching, photoresist stripping, etc.; physical vapor deposition is usually used for the metal layer ( For example, magnetron sputtering method forms a film, and a pattern is formed by wet etching, while for a non-metal layer, a film is formed by chemical vapor deposition, and a pattern is formed by dry etching.
  • the polarizing film and the first auxiliary gate line may be formed by the above-mentioned patterning process, and may be formed by a patterning process such as nanoimprinting, light diffraction dry etching, or electron beam direct writing, which is not limited herein.
  • a method of manufacturing a substrate provided by an embodiment of the present invention by disposing a first auxiliary gate line on a second insulating layer, and passing the first auxiliary gate line and the gate line through at least two through the first insulating layer and the second insulating layer
  • the vias are connected in parallel, thereby reducing the resistance of the gate lines, thereby reducing the signal delay of the gate line resistance in the display device.
  • the transparent conductive material is a wire grid polarizing material, for example, may be WGP.
  • the polarizing film in the embodiment of the present invention is formed by a WGP deposited directly on the pixel electrode, wherein the thickness of the polarizing film can be controlled by a deposition process, and the polarizer of the conventional display device is compounded by a multilayer polymer material. Therefore, the polarizer is fixed on the substrate by an adhesive.
  • the embodiment of the present invention can more easily control the thickness of the module of the display device, thereby making it easier.
  • the thickness of the module of the display device is reduced.
  • the first auxiliary data line and the polarizing film are formed by the same patterning process for the same layer of material. Compared with the manufacturing process of the polarizer in the prior art, the embodiment of the present invention No additional process is required.
  • the substrate manufacturing method in the corresponding embodiment of FIG. 8 further includes:
  • step S805 the method further includes: forming, between the two adjacent gate lines, at least two through the second insulating layer at positions corresponding to each of the data lines by the first patterning process hole.
  • step S808 the method further includes: performing the second patterning process on the transparent conductive material layer to form a second auxiliary data line, wherein the second auxiliary data line is partitioned into multiple auxiliary data by the first auxiliary gate line a line segment, at least two locations on each of the auxiliary data line segments and at least two locations opposite the data line are electrically connected by vias extending through the second insulating layer.
  • the second auxiliary data line formed in step S808 in the above embodiment is electrically connected to the data line through the via hole formed in step S805 through the second insulating layer, so that each second auxiliary data line segment is connected in parallel with the corresponding data line, thereby reducing The resistance of the data line is reduced, thereby reducing the signal delay caused by the resistance of the data line in the display device.
  • An embodiment of the present invention provides a substrate manufacturing method for manufacturing the substrate shown in FIGS. 3, 4, and 5.
  • the substrate manufacturing method includes the following steps:
  • the gate line is formed
  • the first insulating layer is formed in step S902
  • the data line is formed in step S903
  • the second insulating layer is formed in S904.
  • the gate line, the first insulating layer, the data line and the prior art are formed.
  • the second insulating layer is of the same manner and is not limited herein; wherein the first insulating layer and the second insulating layer are separate layers.
  • "Floor" The meaning may refer to a film formed by a deposition process or the like on a substrate by using a certain material; for example, the first insulating layer may be formed by depositing SiNx (silicon nitride) on a substrate. Specifically, for example, the insulating layer may be formed by depositing an insulating film on the substrate by depositing SiNx according to actual needs, and then removing portions on the insulating film by a patterning process to obtain an insulating layer.
  • step S905 in addition to forming at least two via holes on the second insulating layer corresponding to the position corresponding to each of the data lines by the first patterning process, the second patterning process should be formed on the second insulating layer.
  • the patterning process used in the method of manufacturing the substrate generally includes processes such as cleaning, film formation, photoresist coating, exposure, development, etching, photoresist stripping, etc.; physical vapor deposition is usually used for the metal layer ( For example, magnetron sputtering method forms a film, and a pattern is formed by wet etching, while for a non-metal layer, a film is formed by chemical vapor deposition, and a pattern is formed by dry etching.
  • the polarizing film and the first auxiliary data line may be formed by using the above-mentioned patterning process, and may be formed by a patterning process such as nanoimprinting, light diffraction dry etching, or electron beam direct writing, which is not limited herein.
  • the method for manufacturing a substrate provided by the embodiment of the present invention, by disposing a first auxiliary data line on the second insulating layer, and connecting the first auxiliary data line and the data line through at least two via holes penetrating the second insulating layer, thereby The resistance of the data line is reduced, thereby reducing the signal delay of the arrival of the data line resistance in the display device.
  • the transparent conductive material is a wire grid polarizing material, for example, may be WGP.
  • the transparent conductive material is WGP
  • the polarizing film in the embodiment of the present invention is formed by WGP directly deposited on the pixel electrode, wherein the thickness of the polarizing film can be controlled by a deposition process, and the polarizer of the conventional display device is composed of a multilayer polymer. The material is composited, and the polarizer is fixed on the substrate by an adhesive.
  • the embodiment of the present invention can more easily control the thickness of the module of the display device.
  • the first auxiliary data line and the polarizing film are formed by the same patterning process for the same layer of material, compared to the manufacturing process of the polarizer in the prior art.
  • Embodiments of the invention do not require additional process flow.
  • the substrate manufacturing method in the corresponding embodiment of FIG. 9 further includes:
  • step 905 the method further includes: forming, between the two adjacent data lines, at least two through the first insulating layer and at a position corresponding to each of the gate lines by the first patterning process Two vias of insulating layer.
  • step S908 the method further includes: performing a second patterning process on the transparent conductive material layer to form a second auxiliary gate line, wherein the second auxiliary gate line is separated by the first auxiliary data line into a plurality of auxiliary gate lines And a line segment, at least two positions on each of the auxiliary gate line segments and at least two positions opposite to the gate line are electrically connected by via holes penetrating the first insulating layer and the second insulating layer.
  • the second auxiliary gate line formed in step S908 in the above embodiment is electrically connected to the gate line through the via hole penetrating through the first insulating layer and the second insulating layer formed in step S905, thereby reducing the resistance of the gate line and further reducing the display.
  • the signal delay caused by the gate line resistance in the device is electrically connected to the gate line through the via hole penetrating through the first insulating layer and the second insulating layer formed in step S905, thereby reducing the resistance of the gate line and further reducing the display.
  • the embodiment of the present invention further provides a display device, which includes any substrate provided by the embodiment of the present invention, and the substrate can be obtained by the manufacturing method provided by the embodiment of the present invention.
  • the display device may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital camera, a mobile phone, a tablet computer, or the like.

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Abstract

一种基板及其制造方法、显示装置。该基板包括：衬底基板（101），多条平行设置的栅线（103），覆盖栅线（103）的第一绝缘层（102），位于第一绝缘层（102）上与栅线（103）垂直的多条数据线（104），覆盖数据线（104）的第二绝缘层（105），以及数据线（104）和栅线（103）围设形成的子像素区域的像素电极（106）；覆盖像素电极（106）的偏光膜（107）；以及，设置在第二绝缘层（105）上与栅线（103）平行的第一辅助栅线（108），每一条第一辅助栅线（108）上至少两个位置与栅线（103）上相对的至少两个位置通过贯穿第一绝缘层（102）和第二绝缘层（105）的过孔（109）电连接，第一辅助栅线（108）与偏光膜（107）为通过对同一层透明导电材料的同一次构图工艺形成。可以减小显示装置中的信号延迟，用于显示器的制造。

Description

一种基板及其制造方法、显示装置 技术领域
本发明涉及显示器制造领域，尤其涉及一种基板及其制造方法、显示装置。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有重量轻、厚度薄、低功耗等优点，广泛应用于电视、手机、显示器等电子产品中。液晶显示器是由水平和垂直两个方向的像素矩阵构成的。液晶显示器进行显示时，驱动电路输出驱动信号，逐行对各像素单元进行扫描。液晶显示器的驱动电路主要包括栅极驱动电路和源极驱动电路，源极驱动电路将输入的显示数据及时钟信号定时顺序锁存，转换成源极驱动信号输入到液晶面板的数据线；栅极驱动电路将输入的时钟信号经过移位寄存器转换成栅极驱动信号，逐行施加到液晶面板的栅线中，像素矩阵中的各像素单元则在栅极驱动电路和源极驱动电路的控制下显示灰阶。
目前显示设备正在向着尺寸更大和厚度更薄的方向发展，但是显示装置尺寸越大或者分辨率越高就要求数据线和栅线越长，进而导致显示装置的栅线和数据线的电阻越大。而栅极驱动电路需将栅极驱动信号通过栅线输入像素单元，源极驱动电路也需将转换后的源极驱动信号通过数据线输入像素单元，因此栅线或数据线中的电阻越来越大将导致栅极驱动信号或源极驱动信号的延迟越来越大，进而导致显示灰阶不正常。
发明内容
本发明的实施例提供一种基板及其制造方法、显示装置，用于减小栅线或数据线的电阻，进而减小显示装置中栅线电阻或数据线电阻带来的信号延迟，本发明的实施例采用如下技术方案：
第一方面，提供一种基板，包括：衬底基板，位于所述衬底基板上多条平行设置的栅线，覆盖所述栅线的第一绝缘层，位于所述第一绝缘层上与所述栅线垂直的多条数据线，覆盖所述数据线的第二绝缘层， 以及位于所述数据线和所述栅线围设形成的子像素区域的像素电极；
所述基板还包括：
覆盖所述像素电极的偏光膜，所述偏光膜的投影与所述像素电极相对；以及，
设置在所述第二绝缘层上与所述栅线平行的第一辅助栅线，所述第一辅助栅线的投影与所述栅线相对，每一条所述第一辅助栅线上至少两个位置与所述栅线上相对的至少两个位置通过贯穿所述第一绝缘层和第二绝缘层的过孔电连接，其中，所述第一辅助栅线与所述偏光膜为通过对同一层透明导电材料的同一次构图工艺形成；
或者，所述基板还包括：
覆盖所述像素电极的偏光膜，所述偏光膜的投影与所述像素电极相对；以及，
设置在所述第二绝缘层上与所述数据线平行的第一辅助数据线，所述第一辅助数据线的投影与所述数据线相对，每一条所述第一辅助数据线上至少两个位置与所述数据线上相对的至少两个位置通过贯穿第二绝缘层的过孔电连接，其中，所述第一辅助数据线与所述偏光膜为通过对同一层透明导电材料的同一次构图工艺形成。
可选的，当所述基板包括所述偏光膜和所述第一辅助栅线时，在相邻的两条数据线之间，每一条所述栅线和对应的第一辅助栅线之间设置有一个贯穿所述第一绝缘层和第二绝缘层的过孔。
可选的，当所述基板包括所述偏光膜和所述第一辅助数据线时，在相邻的两条栅线之间，每一条所述数据线和对应的第一辅助数据线之间设置有一个贯穿所述第二绝缘层的过孔。
可选的，当所述基板包括：所述偏光膜和所述第一辅助栅线时，所述基板还包括：第二辅助数据线；
所述第二辅助数据线设置在所述第二绝缘层上，所述第二辅助数据线与所述数据线平行，所述第二辅助数据线的投影与所述数据线相对，所述第二辅助数据线被所述第一辅助栅线隔断成多个辅助数据线段，每个所述辅助数据线段上至少两个位置与所述数据线上相对的至少两个位置通过贯穿第二绝缘层的过孔电连接；其中，所述第一辅助栅线、所述偏光膜和所述第二辅助数据线为通过对同一层透明导电材料的同一次构图工艺形成。
可选的，当所述基板包括所述偏光膜和所述第一辅助数据线时，所述基板还包括：第二辅助栅线；
所述第二辅助栅线设置在所述第二绝缘层上，所述第二辅助栅线与所述栅线平行，所述第二辅助栅线的投影与所述栅线相对，所述第二辅助栅线被所述第一辅助数据线隔断成多个辅助栅线段，每个所述辅助栅线段上至少两个位置与所述栅线上相对的至少两个位置通过贯穿所述第一绝缘层和第二绝缘层的过孔电连接；其中，所述第一辅助数据线、所述偏光膜和所述第二辅助栅线为通过对同一层透明导电材料的同一次构图工艺形成。
可选的，所述透明导电材料为线栅起偏材料。
第二方面，提供一种显示装置，包括上述任一项所述的基板。
第三方面，提供一种基板制造方法，包括：
在衬底基板上制作多条平行设置的栅线；
制作覆盖所述栅线的第一绝缘层；
制作位于所述第一绝缘层上与所述栅线垂直的多条数据线；
制作覆盖所述数据线的第二绝缘层；
在所述栅线与所述数据线围设形成的子像素区域形成像素电极；
制作偏光膜和第一辅助栅线，包括：通过第一构图工艺在每一条所述栅线对应的位置形成至少两个贯穿所述第一绝缘层和所述第二绝缘层的过孔；形成覆盖所述像素电极和所述第二绝缘层的透明导电材料层；对所述透明导电材料层进行第二构图工艺形成偏光膜和第一辅助栅线，每一条所述栅线与对应的第一辅助栅线通过贯穿所述第一绝缘层和所述第二绝缘层的过孔电连接；
或者，
制作偏光膜和第一辅助数据线，包括：通过第一构图工艺在每一条所述数据线对应的位置形成至少两个贯穿所述第二绝缘层的过孔；形成覆盖所述像素电极和所述第二绝缘层的透明导电材料层；对所述透明导电材料层进行第二构图工艺形成偏光膜和第一辅助数据线，每一条所述数据线与对应的第一辅助数据线通过所述第二绝缘层上的至少两个过孔电连接。
可选的，当所述方法包括制作偏光膜和第一辅助栅线的步骤时，所述方法还包括：
在相邻的两条栅线之间，通过所述第一构图工艺在每一条所述数据线对应的位置上形成至少两个贯穿所述第二绝缘层的过孔；
对所述透明导电材料层进行所述第二构图工艺形成第二辅助数据线，所述第二辅助数据线被所述第一辅助栅线隔断成多个辅助数据线段，每个所述辅助数据线段上至少两个位置与所述数据线上相对的至少两个位置通过贯穿所述第二绝缘层的过孔电连接。
可选的，当所述方法包括制作偏光膜和第一辅助数据线的步骤时，所述方法还包括：
在相邻的两条数据线之间，通过所述第一构图工艺在每一条所述栅线对应的位置上形成至少两个贯穿所述第一绝缘层和所述第二绝缘层的过孔；
对所述透明导电材料层进行所述第二构图工艺形成第二辅助栅线，所述第二辅助栅线被所述第一辅助数据线隔断成多个辅助栅线段，每个所述辅助栅线段上至少两个位置与所述栅线上相对的至少两个位置通过贯穿所述第一绝缘层和第二绝缘层的过孔电连接。
可选的，所述透明导电材料为线栅起偏材料。
本发明实施例提供的基板及其制造方法、显示装置，在第二绝缘层上设置第一辅助栅线，并将第一辅助栅线与栅线通过至少两个贯穿第一绝缘层和第二绝缘层的过孔并联，从而减小了栅线的电阻，或者在第二绝缘层上设置第一辅助数据线，并将第一辅助数据线与数据线通过至少两个贯穿第二绝缘层的过孔并联，从而减小了数据线的电阻，进而减小了显示装置中栅线电阻或数据线电阻带来的信号延迟。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明的实施例提供的一种基板示意性结构图；
图2为本发明的实施例提供的图1所示基板A-A’截面的剖面图；
图3为本发明的实施例提供的另一种基板示意性结构图；
图4为本发明的实施例提供的图3所示基板B-B’截面的剖面图；
图5为本发明的实施例提供的图3所示基板C-C’截面的剖面图；
图6为本发明的实施例提供的又一种基板示意性结构图；
图7为本发明的实施例提供的再一种基板示意性结构图；
图8为本发明的实施例提供的一种基板的制造方法步骤流程图；
图9为本发明的实施例提供的另一种基板的制造方法步骤流程图。
附图标记：
衬底基板-101；第一绝缘层--102；栅线--103；数据线--104；第二绝缘层--105；像素电极--106；偏光膜--107；第一辅助栅线--108；贯穿第一绝缘层及第二绝缘层的过孔--109；第一辅助数据线--110；贯穿第二绝缘层的过孔--111；第二辅助数据线--112；辅助数据线段--112-1；第二辅助栅线-113；辅助栅线段-113-1。
具体实施方式
下面结合附图对本发明实施例提供的基板及其制造方法、显示装置进行详细描述，其中用相同的附图标记指示本文中的相同元件。在下面的描述中，为便于解释，给出了大量具体细节，以便提供对一个或多个实施例的全面理解。然而，很明显，也可以不用这些具体细节来实现所述实施例。在其它例子中，以方框图形式示出公知结构和设备，以便于描述一个或多个实施例。
本发明实施例中的“上”、“下”以制造基板时的先后顺序为准，例如，在上的图案是指相对在后形成的图案，在下的图案是指相对在先形成的图案。
本发明一实施例提供一种基板，参照图1、2所示，其中图1为该基板的俯视图，图2为沿图1所示俯视图的A-A’截面的剖面图；具体的该基板包括：衬底基板101，位于所述衬底基板101上多条平行设置的栅线103，覆盖所述栅线103的第一绝缘层102，位于所述第一绝缘层102上与所述栅线103垂直的多条数据线104，覆盖所述数据线的第二绝缘层105；以及位于所述数据线104和所述栅线103围设形成的子像素区域的像素电极106；所述基板还包括：
覆盖所述像素电极106的偏光膜107，所述偏光膜107的投影与所述像素电极106相对；
以及，设置在所述第二绝缘层105上与所述栅线103平行的第一 辅助栅线108，所述第一辅助栅线108的投影与所述栅线103相对，每一条所述第一辅助栅线108上至少两个位置(portion)与所述栅线103上相对的至少两个位置通过贯穿所述第一绝缘层102和第二绝缘层105的过孔109电连接，其中，所述第一辅助栅线108与所述偏光膜107为通过对同一层透明导电材料的同一次构图工艺形成。
本发明实施例提供的基板，在第二绝缘层上设置第一辅助栅线，并将第一辅助栅线与栅线通过贯穿第一绝缘层和第二绝缘层的过孔并联，从而减小了栅线的电阻，进而减小了显示装置中栅线电阻带来的信号的延迟。
可选的，所述透明导电材料为线栅起偏材料，例如：可以为WGP(Wire Grid Polarizer，线栅起偏器)。当采用WGP时，本发明实施例中的偏光膜由直接沉积在像素电极上的WGP形成，其中偏光膜的厚度可以通过沉积工艺控制；而传统显示装置的偏光片由多层高分子材料复合而成，再通过粘着剂将偏光片固定于基板上。相比于现有技术，由于偏光膜的厚度可以通过沉积工艺控制，所以本发明实施例更容易控制显示装置的模组厚度，进而更容易实现显示装置的模组厚度的降低；而且上述的第一辅助栅线与偏光膜为对同一层材料通过同一次构图工艺形成，相比于现有技术中偏光片的制造工艺，本发明实施例不用增加额外的工艺流程。
本发明一实施例提供一种基板，参照图3、4、5所示，其中图3为该基板的俯视图，图4为沿图3所示俯视图的B-B’截面的剖面图，图5为沿图3所示俯视图的C-C’截面的剖面图；具体的该基板包括：衬底基板101，位于所述衬底基板101上多条平行设置的栅线103，覆盖所述栅线103的第一绝缘层102，位于所述第一绝缘层102上与所述栅线103垂直的多条数据线104，覆盖所述数据线的第二绝缘层105；以及位于所述数据线104和所述栅线103围设形成的子像素区域的像素电极106；所述基板还包括：
覆盖所述像素电极106的偏光膜107，所述偏光膜107的投影与所述像素电极106相对；
以及设置在所述第二绝缘层105上与所述数据线104平行的第一辅助数据线110，所述第一辅助数据线110的投影与所述数据线104相对，每一条所述第一辅助数据线110上至少两个位置与所述数据线104 上相对的至少两个位置通过贯穿所述第二绝缘层105的过孔111电连接，其中，所述第一辅助数据线与所述偏光膜为通过对同一层透明导电材料的同一次构图工艺形成。
本发明实施例提供的基板，在第二绝缘层上设置第一辅助数据线，并将第一辅助数据线与数据线通过贯穿第二绝缘层的过孔并联，所以可以从而减小了数据线的电阻，进而减小了显示装置中数据线电阻带来的信号的延迟。
可选的，所述透明导电材料为线栅起偏材料，例如：可以为WGP。当采用WGP时，本发明实施例中的偏光膜由直接沉积在像素电极上的WGP形成，其中偏光膜的厚度可以通过沉积工艺控制；而传统显示装置的偏光片由多层高分子材料复合而成，再通过粘着剂将偏光片固定于基板上。相比于现有技术，由于偏光膜的厚度可以通过沉积工艺控制，所以本发明实施例更容易控制显示装置的模组厚度，进而更容易实现显示装置的模组厚度的降低；而且上述的第一辅助数据线与偏光膜为对同一层材料通过同一次构图工艺形成，相比于现有技术中偏光片的制造工艺，本发明实施例不用增加额外的工艺流程。
可选的，参照图1所示，当所述基板包括所述偏光膜107和所述第一辅助栅线108时，在相邻的两条数据线104之间，每一条所述栅线103和对应的第一辅助栅线108之间设置有一个贯穿所述第一绝缘层102和第二绝缘层105的过孔109。
上述实施例中在相邻的两条数据线之间，每一条所述栅线和对应的第一辅助栅线之间设置有一个贯穿第一绝缘层和第二绝缘层的过孔，使得在相邻的两条数据线之间，每一条栅线和对应的第一辅助栅线通过贯穿第一绝缘层和第二绝缘层的过孔并联。由于栅极驱动电路通过栅线向每一级像素单元中开关晶体管的栅极提供栅极驱动信号，因此上述连接方式可以使栅极驱动电路的信号源到每一级开关晶体管的栅极之间的栅线和第一辅助栅线并联，所以上述实施例可以进一步减小每一个像素单元中开关晶体管的栅极到栅极驱动信号的信号源之间的电阻，进而减小显示装置中栅线电阻带来的信号延迟。
可选的，参照图3所示，当所述基板包括所述偏光膜107和所述第一辅助数据线110时，在相邻的两条栅线103之间，每一条所述数据线104和对应的第一辅助数据线110之间设置有一个贯穿第二绝缘 层105的过孔111。
上述实施例中在相邻的两条栅线之间，每一条所述数据线和对应的第一辅助数据线之间上设置有一个贯穿所述第二绝缘层的过孔，使得在相邻的两条栅线之间，每一条数据线和对应的第一辅助数据线通过贯穿第二绝缘层的过孔并联。由于源极驱动电路通过数据线向每一级像素单元中开关晶体管的源极提供源极驱动信号，因此上述连接方式可以使得源极驱动电路的信号源到每一级开关晶体管的源极之间的数据线和第一辅助数据线并联，所以上述实施例可以进一步减小每一个像素单元中开关晶体管的源极到源极驱动信号的信号源之间的电阻，进而减小显示装置中数据线电阻带来的信号延迟。
进一步的，参照图6所示，当所述基板包括所述第一辅助栅线108和所述偏光膜107时，所述基板还包括：第二辅助数据线112；
所述第二辅助数据线112设置在所述第二绝缘层105上，所述第二辅助数据线112与所述数据线104平行，所述第二辅助数据线112的投影与所述数据线104相对，所述第二辅助数据线112被所述第一辅助栅线108隔断成多个辅助数据线段112-1，每个所述辅助数据线段112-1上至少两个位置与所述数据线上相对的至少两个位置通过贯穿所述第二绝缘层的过孔109电连接；其中，所述第一辅助栅线108和所述偏光膜107与所述第二辅助数据线112为通过对同一层透明导电材料的同一次构图工艺形成。
上述实施例中，第一辅助栅线和第二辅助数据线为通过对同一层透明导电材料的同一次构图工艺形成，第一辅助栅线将第二辅助数据线隔断成多个辅助数据线段，而每一个辅助数据线段上至少两个位置与所述数据线上相对的至少两个位置通过贯穿第二绝缘层的过孔电连接，使得每一个辅助数据线段都和对应的数据线并联，从而减小了数据线的电阻，进而减小了显示装置中数据线电阻带来的信号延迟；进一步的，上述辅助数据线段只有在两个过孔之间的部分才可以和对应的数据线并联，所以一种优选的方式是，辅助数据线段的两端各有一个过孔，辅助数据线段通过两端的过孔与对应的数据线并联则可以最大程度的减小数据线的电阻，进而最大程度的减小显示装置中数据线电阻带来的信号延迟。此外第一辅助栅线将第二辅助数据线隔断成多个辅助数据线段，避免了第一辅助栅线和第二辅助数据线电连接而引 起的栅线和数据线的电连接，从而保证了包含上述基板的显示器能够正常工作。
进一步的，参照图7所示，当所述基板包括所述第一辅助数据线110和所述偏光膜107时，所述基板还包括：第二辅助栅线113；
所述第二辅助栅线113设置在所述第二绝缘层105上，所述第二辅助栅线113与所述栅线103平行，所述第二辅助栅线113的投影与所述栅线103相对，所述第二辅助栅线113被所述第一辅助数据线隔断成多个辅助栅线段113-1，每个所述辅助栅线段113-1上至少两个位置与所述栅线103上相对的至少两个位置通过贯穿所述第一绝缘层和第二绝缘层的过孔109电连接；其中，所述第一辅助数据线110、所述偏光膜107和所述第二辅助栅线113为通过对同一层透明导电材料的同一次构图工艺形成。
上述实施例中，第一辅助数据线和第二辅助栅线为通过对同一层透明导电材料的同一次构图工艺形成，第一辅助数据线将第二辅助栅线隔断成多个辅助栅线段，而每个辅栅线段上至少两个位置与栅线上相对的至少两个位置通过贯穿所述第一绝缘层和第二绝缘层的过孔电连接，使得每一个辅助栅线段都和对应的栅线并联，从而减小了栅线的电阻，进而减小了显示装置中栅线电阻带来的信号延迟；进一步的，上述辅助栅线段只有在两个过孔之间的部分才可以和对应的栅线并联，所以一种优选的方式是，辅助栅线段的两端各有一个过孔，辅助栅线段通过两端的过孔与对应的栅线并联则可以最大程度的减小栅线的电阻，进而最大程度的减小显示装置中栅线电阻带来的信号延迟。此外第一辅助数据线将第二辅助栅线隔断成多个辅助栅线段，避免了第一辅助数据线和第二辅助栅线电连接而引起的栅线和数据线的电连接，从而保证了包含上述基板的显示器能够正常工作。
本发明的实施例提供一种基板制造方法，用于制造图1、2所示的基板，参照图8所示，该基板制造方法包括如下步骤：
S801、在衬底基板上制作多条平行设置的栅线。
S802、制作覆盖所述栅线的第一绝缘层。
S803、制作位于所述第一绝缘层上与所述栅线垂直的多条数据线。
S804、制作覆盖所述数据线的第二绝缘层。
上述步骤S801中制作栅线、步骤S802中制作第一绝缘层、步骤 S803中制作数据线及S804中制作第二绝缘层的方式与现有技术中制作栅线、第一绝缘层、数据线及第二绝缘层的方式相同，在此本文不做限定。其中，上述的第一绝缘层和第二绝缘层均为单独的层。“层”的含义可以是指利用某一种材料在基板上利用沉积等工艺制作出的一层薄膜；例如上述的第一绝缘层可以是在衬底基板上沉积SiNx(氮化硅)所制得的。具体的，上述的绝缘层可以根据实际需要，先在衬底基板上沉积SiNx制作绝缘薄膜，再通过构图工艺在绝缘薄膜上去除部分，制得绝缘层。
S805、通过第一构图工艺在每一条所述栅线对应的位置形成至少两个贯穿所述第一绝缘层和所述第二绝缘层的过孔。
上述步骤S805中，除了通过第一构图工艺形成贯穿所述第一绝缘层和所述第二绝缘层的过孔外，还应通过第一构图工艺在第二绝缘层上形成像素电极与像素单元中晶体管的漏极连接的过孔。
S806、在所述栅线与所述数据线围设形成的子像素区域形成像素电极。
S807、形成覆盖所述像素电极和所述第二绝缘层的透明导电材料层。
S808、对所述透明导电材料层进行第二构图工艺形成偏光膜和第一辅助栅线，每一条所述栅线与对应的第一辅助栅线通过贯穿所述第一绝缘层和所述第二绝缘层的过孔电连接。
需要说明的是，上述步骤中，对各个层的具体形貌及电路连接参照图1、2对应的装置实施例。此外，该基板的制造方法中用到的构图工艺通常包括清洗、成膜、光刻胶涂覆、曝光、显影、刻蚀、光刻胶剥离等工序；对于金属层通常采用物理气相沉积方式(例如：磁控溅射法)成膜，通过湿法刻蚀形成图形，而对于非金属层通常采用化学气相沉积方式成膜，通过干法刻蚀形成图形。当然步骤S808中，除了可采用上述构图工艺形成偏光膜、第一辅助栅线外还可以通过纳米压印、光衍射干刻、电子束直写等构图工艺形成，本文在此不作限定。
本发明实施例提供的基板的制造方法，通过在第二绝缘层上设置第一辅助栅线，并将第一辅助栅线与栅线通过至少两个贯穿第一绝缘层和第二绝缘层的过孔并联，从而减小了栅线的电阻，进而减小显示装置中栅线电阻到来的信号延迟。
可选的，上述透明导电材料为线栅起偏材料，例如：可以为WGP。当采用WGP时，本发明实施例中的偏光膜由直接沉积在像素电极上的WGP形成，其中偏光膜的厚度可以通过沉积工艺控制，而传统显示装置的偏光片由多层高分子材料复合而成，再通过粘着剂将偏光片固定于基板上，相比于现有技术，由于偏光膜的厚度可以通过沉积工艺控制，所以本发明实施例更容易控制显示装置的模组厚度，进而更容易实现显示装置的模组厚度的降低；而且上述的第一辅助数据线与偏光膜为对同一层材料通过同一次构图工艺形成，相比于现有技术中偏光片的制造工艺，本发明实施例不用增加额外的工艺流程。
可选的，图8对应实施例中基板制造方法还包括：
在步骤S805中，还包括：在相邻的两条栅线之间，通过所述第一构图工艺在每一条所述数据线对应的位置上形成至少两个贯穿所述第二绝缘层的过孔。
在步骤S808中，还包括：对所述透明导电材料层进行所述第二构图工艺形成第二辅助数据线，所述第二辅助数据线被所述第一辅助栅线隔断成多个辅助数据线段，每个所述辅助数据线段上至少两个位置与所述数据线上相对的至少两个位置通过贯穿所述第二绝缘层的过孔电连接。
上述实施例中步骤S808形成的第二辅助数据线通过步骤S805形成的贯穿第二绝缘层的过孔与数据线电连接，使得每一个第二辅助数据线段都和对应的数据线并联，从而减小了数据线的电阻，进而减小显示装置中数据线电阻带来的信号延迟。
本发明一实施例提供一种基板制造方法，用于制造图3、4、5所示的基板，参照图9所示，该基板制造方法包括如下步骤：
S901、在衬底基板上制作多条平行设置的栅线。
S902、制作覆盖所述栅线的第一绝缘层。
S903、制作位于所述第一绝缘层上与所述栅线垂直的多条数据线。
S904、制作覆盖所述数据线的第二绝缘层。
上述步骤S901中制作栅线、步骤S902中制作第一绝缘层、步骤S903中制作数据线及S904中制作第二绝缘层的方式与现有技术中制作栅线、第一绝缘层、数据线及第二绝缘层的方式相同，在此本文不做限定；其中，上述的第一绝缘层和第二绝缘层均为单独的层。“层” 的含义可以是指利用某一种材料在基板上利用沉积等工艺制作出的一层薄膜；例如上述的第一绝缘层可以是在衬底基板上沉积SiNx(氮化硅)所制得的。具体的，又如，上述的绝缘层可以根据实际需要，先在衬底基板上沉积SiNx制作绝缘薄膜，再通过构图工艺在绝缘薄膜上去除部分，制得绝缘层。
S905、通过第一构图工艺在每一条所述数据线对应的位置对应的第二绝缘层上形成至少两个过孔；
上述步骤S905中，除了通过第一构图工艺在每一条所述数据线对应的位置对应的第二绝缘层上形成至少两个过孔外，还应通过第一构图工艺在第二绝缘层上形成像素电极与像素单元中晶体管的漏极连接的过孔。
S906、在所述栅线与所述数据线围设形成的子像素区域形成像素电极。
S907、形成覆盖所述像素电极和所述第二绝缘层的透明导电材料层。
S908、对所述透明导电材料层进行第二构图工艺形成偏光膜和第一辅助数据线，每一条所述数据线与对应的第一辅助数据线通过所述第二绝缘层上的至少两个过孔电连接。
需要说明的是，上述步骤中，对各个层的具体形貌及电路连接参照图3、4、5对应的装置实施例。此外，该基板的制造方法中用到的构图工艺通常包括清洗、成膜、光刻胶涂覆、曝光、显影、刻蚀、光刻胶剥离等工序；对于金属层通常采用物理气相沉积方式(例如：磁控溅射法)成膜，通过湿法刻蚀形成图形，而对于非金属层通常采用化学气相沉积方式成膜，通过干法刻蚀形成图形。当然在步骤S908中，除了可采用上述构图工艺形成偏光膜、第一辅助数据线外还可以通过纳米压印、光衍射干刻、电子束直写等构图工艺形成，本文在此不作限定。
本发明实施例提供的基板的制造方法，通过在第二绝缘层上设置第一辅助数据线，并将第一辅助数据线与数据线通过至少两个贯穿第二绝缘层的过孔并联，从而减小了数据线的电阻，进而减小显示装置中数据线电阻到来的信号延迟。
可选的，上述透明导电材料为线栅起偏材料，例如：可以为WGP。 当透明导电材料为WGP时，本发明实施例中的偏光膜由直接沉积在像素电极上的WGP形成，其中偏光膜的厚度可以通过沉积工艺控制，而传统显示装置的偏光片由多层高分子材料复合而成，再通过粘着剂将偏光片固定于基板上，相比于现有技术，由于偏光膜的厚度可以通过沉积工艺控制，所以本发明实施例更容易控制显示装置的模组厚度，进而更容易实现显示装置的模组厚度的降低；而且上述的第一辅助数据线与偏光膜为对同一层材料通过同一次构图工艺形成，相比于现有技术中偏光片的制造工艺，本发明实施例不用增加额外的工艺流程。
可选的，图9对应实施例中基板制造方法还包括：
在步骤905中，还包括：在相邻的两条数据线之间，通过所述第一构图工艺在每一条所述栅线对应的位置上形成至少两个贯穿所述第一绝缘层和第二绝缘层的过孔。
在步骤S908中，还包括：对所述透明导电材料层进行所述第二构图工艺形成第二辅助栅线，所述第二辅助栅线被所述第一辅助数据线隔断成多个辅助栅线段，每个所述辅助栅线段上至少两个位置与所述栅线上相对的至少两个位置通过贯穿所述第一绝缘层和第二绝缘层的过孔电连接。
上述实施例中步骤S908形成的第二辅助栅线通过步骤S905形成的贯穿第一绝缘层和第二绝缘层的过孔与栅线电连接，从而减小了栅线的电阻，进而减小显示装置中栅线电阻带来的信号延迟。
本发明实施例还提供了一种显示装置，包括：本发明实施例提供的任一种基板，所述基板可以由本发明实施例提供的制作方法获得。所述显示装置可以为液晶显示器、液晶电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (11)

  1. 一种基板，包括：衬底基板，位于所述衬底基板上多条平行设置的栅线，覆盖所述栅线的第一绝缘层，位于所述第一绝缘层上与所述栅线垂直的多条数据线，覆盖所述数据线的第二绝缘层，以及位于所述数据线和所述栅线围设形成的子像素区域的像素电极；
    其特征在于，所述基板还包括：覆盖所述像素电极的偏光膜，所述偏光膜的投影与所述像素电极相对；以及设置在所述第二绝缘层上与所述栅线平行的第一辅助栅线，所述第一辅助栅线的投影与所述栅线相对，每一条所述第一辅助栅线上至少两个位置与所述栅线上相对的至少两个位置通过贯穿所述第一绝缘层和所述第二绝缘层的过孔电连接；其中，所述第一辅助栅线与所述偏光膜为通过对同一层透明导电材料的同一次构图工艺形成；
    或者，
    所述基板还包括：覆盖所述像素电极的偏光膜，所述偏光膜的投影与所述像素电极相对；以及设置在所述第二绝缘层上与所述数据线平行的第一辅助数据线，所述第一辅助数据线的投影与所述数据线相对，每一条所述第一辅助数据线上至少两个位置与所述数据线上相对的至少两个位置通过贯穿所述第二绝缘层的过孔电连接；其中，所述第一辅助数据线与所述偏光膜为通过对同一层透明导电材料的同一次构图工艺形成。
  2. 根据权利要求1所述的基板，其特征在于，当所述基板包括所述偏光膜和所述第一辅助栅线时，在相邻的两条数据线之间，每一条所述栅线和对应的第一辅助栅线之间设置有一个贯穿所述第一绝缘层和所述第二绝缘层的过孔。
  3. 根据权利要求1所述的基板，其特征在于，当所述基板包括所述偏光膜和所述第一辅助数据线时，在相邻的两条栅线之间，每一条所述数据线和对应的第一辅助数据线之间设置有一个贯穿所述第二绝缘层的过孔。
  4. 根据权利要求1所述的基板，其特征在于，当所述基板包括所述偏光膜和所述第一辅助栅线时，所述基板还包括：第二辅助数据线；
    所述第二辅助数据线设置在所述第二绝缘层上，所述第二辅助数 据线与所述数据线平行，所述第二辅助数据线的投影与所述数据线相对，所述第二辅助数据线被所述第一辅助栅线隔断成多个辅助数据线段，每个所述辅助数据线段上至少两个位置与所述数据线上相对的至少两个位置通过贯穿所述第二绝缘层的过孔电连接；其中，所述第一辅助栅线、所述偏光膜和所述第二辅助数据线为通过对同一层透明导电材料的同一次构图工艺形成。
  5. 根据权利要求1所述的基板，其特征在于，当所述基板包括所述偏光膜和所述第一辅助数据线时，所述基板还包括：第二辅助栅线；
    所述第二辅助栅线设置在所述第二绝缘层上，所述第二辅助栅线与所述栅线平行，所述第二辅助栅线的投影与所述栅线相对，所述第二辅助栅线被所述第一辅助数据线隔断成多个辅助栅线段，每个所述辅助栅线段上至少两个位置与所述栅线上相对的至少两个位置通过贯穿所述第一绝缘层和所述第二绝缘层的过孔电连接；其中，所述第一辅助数据线、所述偏光膜和所述第二辅助栅线为通过对同一层透明导电材料的同一次构图工艺形成。
  6. 根据权利要求1-5任一项所述的基板，其特征在于，所述透明导电材料为线栅起偏材料。
  7. 一种显示装置，其特征在于，包括权利要求1-6任一项所述的基板。
  8. 一种基板制造方法，其特征在于，包括：
    在衬底基板上制作多条平行设置的栅线；
    制作覆盖所述栅线的第一绝缘层；
    制作位于所述第一绝缘层上与所述栅线垂直的多条数据线；
    制作覆盖所述数据线的第二绝缘层；
    在所述栅线与所述数据线围设形成的子像素区域形成像素电极；以及
    制作偏光膜和第一辅助栅线，包括：通过第一构图工艺在每一条所述栅线对应的位置形成至少两个贯穿所述第一绝缘层和所述第二绝缘层的过孔；形成覆盖所述像素电极和所述第二绝缘层的透明导电材料层；对所述透明导电材料层进行第二构图工艺形成偏光膜和第一辅助栅线，每一条所述栅线与对应的第一辅助栅线通过贯穿所述第一绝缘层和所述第二绝缘层的过孔电连接；
    或者，
    制作偏光膜和第一辅助数据线，包括：通过第一构图工艺在每一条所述数据线对应的位置形成至少两个贯穿所述第二绝缘层的过孔；形成覆盖所述像素电极和所述第二绝缘层的透明导电材料层；对所述透明导电材料层进行第二构图工艺形成偏光膜和第一辅助数据线，每一条所述数据线与对应的第一辅助数据线通过所述第二绝缘层上的至少两个过孔电连接。
  9. 根据权利要求8所述的方法，其特征在于，当所述方法包括制作偏光膜和第一辅助栅线的步骤时，所述方法还包括：
    在相邻的两条栅线之间，通过所述第一构图工艺在每一条所述数据线对应的位置上形成至少两个贯穿所述第二绝缘层的过孔；
    对所述透明导电材料层进行所述第二构图工艺形成第二辅助数据线，所述第二辅助数据线被所述第一辅助栅线隔断成多个辅助数据线段，每个所述辅助数据线段上至少两个位置与所述数据线上相对的至少两个位置通过贯穿所述第二绝缘层的过孔电连接。
  10. 根据权利要求8所述的方法，其特征在于，当所述方法包括制作偏光膜和第一辅助数据线的步骤时，所述方法还包括：
    在相邻的两条数据线之间，通过所述第一构图工艺在每一条所述栅线对应的位置上形成至少两个贯穿所述第一绝缘层和所述第二绝缘层的过孔；
    对所述透明导电材料层进行所述第二构图工艺形成第二辅助栅线，所述第二辅助栅线被所述第一辅助数据线隔断成多个辅助栅线段，每个所述辅助栅线段上至少两个位置与所述栅线上相对的至少两个位置通过贯穿所述第一绝缘层和第二绝缘层的过孔电连接。
  11. 根据权利要求8-10任一项所述的方法，其特征在于，所述透明导电材料为线栅起偏材料。
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