WO2017193710A1 - 阵列基板及其制作方法、显示面板、显示装置 - Google Patents

阵列基板及其制作方法、显示面板、显示装置 Download PDF

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WO2017193710A1
WO2017193710A1 PCT/CN2017/077847 CN2017077847W WO2017193710A1 WO 2017193710 A1 WO2017193710 A1 WO 2017193710A1 CN 2017077847 W CN2017077847 W CN 2017077847W WO 2017193710 A1 WO2017193710 A1 WO 2017193710A1
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layer
etching
electrode
electrode layer
pattern
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PCT/CN2017/077847
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English (en)
French (fr)
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刘琨
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/575,421 priority Critical patent/US20180151591A1/en
Publication of WO2017193710A1 publication Critical patent/WO2017193710A1/zh

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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, a display panel, and a display device.
  • TFTs Thin Film Transistors
  • the process of forming a passivation layer and forming a peripheral circuit gate insulating layer is generally combined into one step process, so that only 7 times of masking is required.
  • the membrane process shortens the production cycle.
  • An object of the present invention is to solve the problem of poor adhesion between a pixel electrode and a source/drain metal layer caused by lateral etching of an etch barrier layer.
  • the present invention provides an array substrate, a method of fabricating the same, a display panel, and a display device.
  • an array substrate including: a gate layer, a gate insulating layer, an active layer, a source/drain electrode layer, an etch barrier layer, a flat layer, a first electrode layer, and a passivation sequentially formed on a substrate a layer and a second electrode layer; wherein, in the via region, a via hole is formed in the etch stop layer, the flat layer, and the passivation layer;
  • the first electrode layer includes a common electrode pattern and an anti-etching pattern;
  • the anti-etching pattern includes a plurality of anti-etching structures, and each of the anti-etching structures is correspondingly filled into a via hole for preventing the via hole
  • the etch stop layer is etched;
  • the second electrode layer includes a pixel electrode pattern, and the pixel electrode in the pixel electrode pattern is electrically connected to the source/drain electrode layer through an anti-etching structure in the via hole.
  • the material of the flat layer comprises a resin.
  • the material of the first electrode layer and the second electrode layer comprises ITO.
  • the material of the passivation layer comprises silicon nitride.
  • the material of the etch barrier layer comprises silicon nitride.
  • a display panel including the above array substrate.
  • a display panel including the above array substrate.
  • a fourth aspect provides a method for fabricating an array substrate, comprising: a gate layer, a gate insulating layer, an active layer, a source/drain electrode layer, an etch barrier layer, and a planar layer sequentially formed on the substrate; wherein a via hole region, a via hole formed in the etch stop layer and the flat layer;
  • the first common electrode layer includes a common electrode pattern and an anti-etching pattern
  • the anti-etching pattern includes a plurality of anti-etching structures, and each anti-etching structure corresponds to Filled into a via to prevent the etch stop layer at the via from being etched
  • a second electrode layer is formed on the passivation layer, and the second electrode layer includes a pixel electrode pattern, and the pixel electrode in the pixel electrode pattern is electrically connected to the source/drain electrode layer through an anti-etching structure in the via hole.
  • the step of forming the first electrode layer includes: forming the first electrode layer with ITO; and/or, forming the second electrode layer comprises: forming the second electrode layer with ITO.
  • the step of forming a planar layer includes forming a planar layer using a resin.
  • an anti-etching pattern for preventing etching of the etching stopper layer in the same layer as the common electrode is formed inside the via hole, so that the passivation layer is engraved later.
  • the etch barrier layer can be effectively protected from lateral etching, so that the subsequently formed pixel electrode and the source/drain electrode layer can be well overlapped.
  • FIG. 1 The feature information and advantages of the present invention will be more clearly understood from the following description of the accompanying drawings.
  • FIG. 1 is a schematic cross-sectional view showing a prior art array substrate
  • FIG. 2 is a schematic cross-sectional view showing a prior art array substrate
  • FIG. 3 is a schematic structural view of an array substrate provided by an embodiment of the present invention.
  • FIG. 4 is a schematic structural view showing a flat layer formed by an embodiment of the present invention.
  • FIG. 5 is a schematic view showing a method of coating a photoresist when forming a first electrode layer according to an embodiment of the present invention
  • FIG. 6 is a schematic view showing a method of performing exposure and development processes when forming a first electrode layer according to an embodiment of the present invention
  • FIG. 7 is a schematic structural view showing a first electrode layer formed by an embodiment of the present invention.
  • FIG. 8 is a schematic view showing a method of forming a passivation layer provided by an embodiment of the present invention.
  • FIG. 1 shows an intermediate structure in an array substrate obtained by etching a passivation layer and a gate insulating layer in a prior art when a thin film transistor array product is formed by a mask process, including: a substrate 1' and sequentially formed a gate 2a' on the substrate 1' and another gate layer structure 2b' formed in the same layer as the gate 2a', a gate insulating layer 3', an active layer 4', a source/drain electrode layer 5', etching a barrier layer 6', a flat layer 7', a first electrode layer (common electrode layer) 8', a passivation layer 9'; wherein, in the display region A, the etching barrier layer 6', the flat layer 7' and the blunt layer A via hole 11' is also formed in the layer 9'; when the via hole 12' located in the peripheral circuit region B is etched, the etching time is too long, resulting in the via region 11' in the display region A.
  • the etch stop layer 6' is laterally etched such that the planar layer 7' has an undercut problem as shown in FIG. Referring to FIG. 2, such a design may result in a subsequently formed second electrode layer (including the pixel electrode 10a' located in the display region A and the structure 10b' located in the peripheral circuit region B) and the source and drain metal Layer 5' is poorly bonded.
  • the first aspect of the present invention provides an array substrate, see FIG. 3, including a substrate 1; and a display region A, further including a gate electrode 2a formed on the substrate and formed on the gate electrode 2a a gate insulating layer 3; an active layer 4 formed on the gate insulating layer 3, a source/drain electrode layer 5 formed on the active layer 4, and an etch stop layer 6 formed on the source/drain electrode layer 5, forming a flat layer 7 on the etch barrier layer 6, a first electrode layer formed on the flat layer 7, a passivation layer 9 formed on the first electrode layer, and a pixel electrode 10a formed on the passivation layer 9; , in the via region, the etch stop layer 6, the flat layer 7 and the passivation layer 9 are formed with vias 11;
  • a gate layer structure 2b formed in the same layer as the gate electrode 2a, a gate insulating layer 3 formed over the gate layer structure 2b, and a passivation layer 9 formed on the gate insulating layer 3 are further included.
  • a pixel electrode layer structure 10b formed on the passivation layer 9 in the same layer as the pixel electrode 10a is formed, in which a via hole 12 is further formed in the passivation layer 9 and the gate insulating layer 3.
  • the first electrode layer includes a common electrode pattern and an anti-etching pattern; wherein the common electrode pattern includes a plurality of common electrodes 8a, and the anti-etching pattern includes a plurality of anti-etching structures 8b, see FIG. 3, each of which is protected from etching
  • the structure 8b is correspondingly filled in each of the via holes 11, and the etching prevention structure 8b completely covers the etching resistance at the position of the via hole 11.
  • the barrier layer 6 is configured to prevent the etch stop layer 6 at the via hole 11 from being laterally etched due to a long etching time when the peripheral line gate insulating layer is etched;
  • the second electrode layer 10a includes a pixel electrode pattern, and the pixel electrode The pixel electrode in the pattern is electrically connected to the source/drain electrode layer 5 through an anti-etching structure in the via hole 11.
  • an anti-etching structure 8b for preventing etching of the etching stopper layer 6 in the same layer as the common electrode 8a is formed inside the via hole 11, so that the passivation layer 9 is etched and located later.
  • the gate insulating layer 3 of the peripheral line region B is etched, the etch barrier layer 6 can be effectively protected from lateral etching, and the subsequent formation of the pixel electrode 10a and the source/drain electrode layer 5 can be ensured.
  • the material of the flat layer 7 herein may include a resin; and the materials of the first electrode layer and the second electrode layer 10 may include ITO or the like; the material of the passivation layer 9 may include silicon nitride; The material of the layer 6 may include silicon nitride.
  • the material used in the above-mentioned respective layer structures is not limited herein.
  • the embodiment of the present invention further provides a method for fabricating an array substrate, which can be used to fabricate the above array substrate, and the method can include:
  • Step S1 in the display area A, the gate 2a, the gate insulating layer 3, the active layer 4, the source/drain electrode layer 5, the etch stop layer 6, and the flat layer 7 are sequentially formed on the substrate 1; a via hole 11 is formed in the hole region, the etch stop layer 6 and the flat layer 7; and at the same time, the peripheral line region B further includes a gate layer structure 2b formed in the same layer as the gate electrode 2a, formed in the gate layer structure The gate insulating layer 3 above 2b. See Figure 4 for the structure obtained after step S1.
  • the steps of forming the gate electrode 2a and the gate layer structure 2b, the gate insulating layer 3, the active layer 4, the source/drain electrode layer 5, the etch barrier layer 6, and the planar layer 7 on the substrate can be referred to the prior art. No longer detailed.
  • step S2 in the display area A, a first electrode layer material is formed on the structure obtained in step S1 (this layer is represented as 8 for convenience of explanation), and the structure obtained after step S2 can be referred to FIG.
  • Step S3 forming a layer of photoresist on the structure obtained in step S2, and performing exposure development to obtain a photoresist pattern 13;
  • the photoresist pattern 13 includes a photoresist retention region and a photoresist removal region, wherein the light
  • the glue-retained area includes a portion where the etching prevention structure needs to be formed (located in the via hole 11) and a portion located in a region where the common electrode needs to be formed. See Figure 6 for the structure obtained after step S3.
  • Step S4 etching is performed using the photoresist pattern 13 formed in step S3 as a mask to obtain a common electrode pattern and an anti-etching pattern;
  • the common electrode pattern includes a plurality of common electrode blocks 8a, and the anti-etching pattern includes a plurality of anti-etching patterns.
  • Etching structure 8b, each of the anti-etching structures 8b is correspondingly filled into a via hole 11 for preventing the etching stopper layer 6 at the via hole 11 from being laterally etched, and the structure obtained after the step S4 can be referred to FIG. .
  • a whole layer of electrode material may be deposited on the substrate in step S1. Since the via hole 11 is formed in step S1, the deposited electrode material layer covers the flat layer 7 in the via hole 11; The electrode material is patterned to obtain a corresponding anti-etching pattern and a common electrode pattern is obtained.
  • the patterning process may specifically include: forming a photoresist on the electrode material layer, and exposing and developing the photoresist using a mask to obtain a corresponding photoresist pattern, and then using the photoresist pattern as a mask counter electrode Material layer Row etching is performed to obtain an anti-etching pattern and a common electrode pattern.
  • Step S5 forming a passivation layer material on the structure obtained in step S4; etching the substrate on which the passivation layer material is formed, etching away the blunt area of the via 11 and the periphery in the display area A
  • the layer material is etched and the passivation layer material and the gate insulating layer material in a specific region in the peripheral circuit region B are etched to obtain the via hole 12 in the specific region.
  • the structure obtained after the step S5 can be referred to FIG. .
  • step S2 since it is also necessary to etch the gate insulating layer material in the peripheral circuit region B, etching is required for a relatively long time; since in step S2, the gate insulating layer 3 is formed in the via hole 11 By etching the structure 8b, in this step, the etch stop layer 6 at the position of the via hole 11 can be effectively protected.
  • Step S6 forming a second electrode layer over the structure obtained in step S5; the second electrode layer includes a pixel electrode 10a located in the display area A and a second electrode layer structure 10b located in the peripheral circuit area B.
  • the structure obtained after the step S6 can be referred to FIG. Since the etch stop layer 6 at the position of the via hole 11 is not laterally etched in the step S3, the pixel electrode 10a can be well overlapped with the source/drain metal layer 5.
  • the step of forming the first electrode layer includes: forming the first electrode layer by using ITO; and/or, forming the second electrode layer comprises: forming the second electrode layer by using ITO, it being understood that The first electrode layer and the second electrode layer are formed by using other transparent conductive metal materials, which is not specifically limited in the present invention.
  • the step of forming a flat layer includes: forming a flat layer using a resin.
  • an embodiment of the present invention further provides a display panel, including the array substrate described above.
  • an embodiment of the present invention further provides a display device, which includes the above display panel.
  • the display device herein may be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc., any product or component having display function.

Abstract

一种阵列基板及其制作方法、显示面板、显示装置。该阵列基板包括基底（1）以及依次形成在基底上的栅极层（2a）、栅绝缘层（3）、有源层（4）、源漏电极层（5）、刻蚀阻挡层（6）、平坦层（7）、第一电极层（8）、钝化层（9）和第二电极层（10）；其中，在过孔区域，刻蚀阻挡层、平坦层和钝化层中形成有过孔（11）；第一电极层包括公共电极图形（8a）和防刻蚀图形；防刻蚀图形包括多个防刻蚀结构（8b），每一个防刻蚀结构对应填充到一个过孔中；第二电极层包括像素电极图形，像素电极图形中的像素电极（10a）通过过孔中的防刻蚀结构与源漏电极层导电连接。通过在过孔内部形成防刻蚀图形，可以在过孔过刻时对平坦层下的刻蚀阻挡层进行保护，使其不会发生横向化学反应刻蚀，保证第二电极层与源漏电极层的能够良好搭接。

Description

阵列基板及其制作方法、显示面板、显示装置
交叉引用
本申请要求于2016年5月12日提交的申请号为201610317785.4、名称为“阵列基板及其制作方法、显示面板、显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本发明涉及显示技术领域，尤其是涉及一种阵列基板及其制作方法、显示面板、显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)作为开关器件在显示技术领域发挥着重要的作用。制作出低成本高性能的TFT一直是人们追求的目标。
原有的薄膜晶体管阵列产品需要进行8次掩膜技术，现在为了节约成本，一般采用将形成钝化层以及形成外围电路栅绝缘层工艺合并到一步工艺中来制作，从而只需要进行7次掩膜工艺，缩短了生产周期。在形成钝化层以及形成外围电路栅绝缘层的过程中，在外围电路区域需要刻蚀钝化层和栅绝缘层已得到贯穿钝化层和栅绝缘层的过孔，该刻蚀过程的时间较长，会使位于显示区域的刻蚀阻挡层被横向刻蚀，最终导致像素电极与源漏金属层搭接不良。
发明内容
本发明的一个目的在于解决刻蚀阻挡层的横向刻蚀导致的像素电极与源漏金属层搭接不良的问题。
为了达到上述目的，本发明提供了一种阵列基板及其制作方法、显示面板、显示装置。
一方面，提供了一种阵列基板，包括：在基底上依次形成的栅极层、栅绝缘层、有源层、源漏电极层、刻蚀阻挡层、平坦层、第一电极层、钝化层和第二电极层；其中，在过孔区域，所述刻蚀阻挡层、平坦层和钝化层中形成有过孔；
所述第一电极层包括公共电极图形和防刻蚀图形；所述防刻蚀图形包括多个防刻蚀结构，每一个防刻蚀结构对应填充到一个过孔中，用于防止过孔处的刻蚀阻挡层被刻蚀；
所述第二电极层包括像素电极图形，所述像素电极图形中的像素电极通过过孔中的防刻蚀结构与源漏电极层导电连接。
在一实施例中，所述平坦层的材料包括树脂。
在一实施例中，所述第一电极层以及第二电极层的材料包括ITO。
在一实施例中，所述钝化层的材料包括氮化硅。
在一实施例中，所述刻蚀阻挡层的材料包括氮化硅。
第二方面，提供了一种显示面板，包括上述阵列基板。
第三方面，提供了一种显示面板，包括上述阵列基板。
第四方面，提供了一种阵列基板的制作方法，包括：在基底上依次形成的栅极层、栅绝缘层、有源层、源漏电极层、刻蚀阻挡层以及平坦层；其中，在过孔区域，所述刻蚀阻挡层以及所述平坦层中形成有过孔；
在所述平坦层上形成第一电极层；所述第一公共电极层包括公共电极图形和防刻蚀图形；所述防刻蚀图形包括多个防刻蚀结构，每一个防刻蚀结构对应填充到一个过孔中，用于防止过孔处的刻蚀阻挡层被刻蚀；
在所述第一电极层上形成钝化材料；并通过图案化工艺刻蚀掉过孔处的钝化材料得到钝化层；
在所述钝化层上形成第二电极层，所述第二电极层包括像素电极图形，所述像素电极图形中的像素电极通过过孔中的防刻蚀结构与源漏电极层导电连接。
在一实施例中，形成第一电极层的步骤包括：利用ITO形成第一电极层；和/或，形成第二电极层的步骤包括：利用ITO形成第二电极层。
在一实施例中，形成平坦层的步骤包括：利用树脂形成平坦层。
本发明提供的阵列基板中，在制作公共电极图形时，在过孔内部形成与公共电极同层的、用于防止刻蚀阻挡层刻蚀的防刻蚀图形，这样在后续进行钝化层刻蚀以及栅绝缘层刻蚀时，可以对刻蚀阻挡层进行有效的保护，使其不会发生横向刻蚀，保证后续形成的像素电极与源漏电极层的能够良好搭接。
附图说明
通过参考附图会更加清楚的理解本发明的特征信息和优点，附图是示意性的而不应理解为对本发明进行任何限制，在附图中：
图1示出了现有技术的阵列基板剖面结构示意图；
图2示出了现有技术的阵列基板剖面结构示意图；
图3示出了本发明实施方式提供的阵列基板结构示意图；
图4示出了本发明实施方式提供的形成平坦层后的结构示意图；
图5示出了本发明实施方式提供的形成第一电极层时涂覆光刻胶方法示意图；
图6示出了本发明实施方式提供的形成第一电极层时进行曝光显影工艺方法示意图；
图7示出了本发明实施方式提供的形成第一电极层后的结构示意图；
图8示出了本发明实施方式提供的形成钝化层的方法示意图。
具体实施方式
为了能够更清楚地理解本发明的上述目的、特征和优点，下面结合附图和具体实施方式对本发明进行进一步的详细描述。需要说明的是，在不冲突的情况下，本申请的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是，本发明还可以采用其他不同于在此描述的其他方式来实施，因此，本发明的保护范围并不受下面公开的具体实施例的限制。
下面对现有技术中薄膜晶体管阵列产品通过7次掩膜工艺形成的过程进行具体说明：
图1示出了现有技术中在利用掩膜工艺形成薄膜晶体管阵列产品时，对钝化层和栅绝缘层进行刻蚀后得到的阵列基板中的中间结构，包括：基底1’以及依次形成在基底1’上的栅极2a’以及与栅极2a’同层形成的另一栅极层结构2b’、栅绝缘层3’、有源层4’、源漏电极层5’、刻蚀阻挡层6’、平坦层7’、第一电极层(公共电极层)8’、钝化层9’；其中，在显示区域A内，在刻蚀阻挡层6’、平坦层7’和钝化层9’中还形成有过孔11’；在刻蚀位于外围电路区域B内的过孔12’时，由于刻蚀的时间过长，导致在显示区域A内的过孔区域11’内的刻蚀阻挡层6’被横向刻蚀，使得平坦层7’如图1所示的底切问题。参见图2，这样的设计可能导致后续形成的第二电极层(包括位于显示区域A内的像素电极10a’以及位于外围电路区域B内的结构10b’)中的像素电极10a’与源漏金属层5’搭接不良。
为了解决上述问题，第一方面，本发明实施方式提供了一种阵列基板，参见图3，包括基底1；在显示区域A，还包括形成在基底上形成的栅极2a、形成在栅极2a上的栅绝缘层3；形成在栅绝缘层3上的有源层4、形成在有源层4上的源漏电极层5和形成在源漏电极层5上的刻蚀阻挡层6、形成在刻蚀阻挡层6上的平坦层7、形成在平坦层7上的第一电极层、形成在第一电极层上的钝化层9和形成在钝化层9上的像素电极10a；其中，在过孔区域，刻蚀阻挡层6、平坦层7和钝化层9中形成有过孔11；
在外围线路区域B，还包括形成与栅极2a同层形成的栅极层结构2b，形成在栅极层结构2b上方的栅绝缘层3，以及形成在栅绝缘层3上的钝化层9，形成在钝化层9上与像素电极10a同层形成的像素电极层结构10b，其中，在钝化层9和栅绝缘层3中还形成有过孔12。
上述的第一电极层包括公共电极图形和防刻蚀图形；其中，公共电极图形包括多个公共电极8a，防刻蚀图形包括多个防刻蚀结构8b，参见图3，每一个防刻蚀结构8b对应填充到每一个过孔11中，该防刻蚀结构8b完全覆盖过孔11位置处的刻蚀阻 挡层6，用于防止过孔11处的刻蚀阻挡层6在外围线路栅绝缘层进行刻蚀时由于过刻时间较长发生横向刻蚀；第二电极层10a包括像素电极图形，像素电极图形中的像素电极通过过孔11中的防刻蚀结构与源漏电极层5导电连接。
本发明实施方式中，在过孔11内部形成有与公共电极8a同层的、用于防止刻蚀阻挡层6刻蚀的防刻蚀结构8b，这样在后续进行钝化层9刻蚀以及位于外围线路区域B的栅绝缘层3刻蚀时，可以对刻蚀阻挡层6进行有效的保护，使其不会发生横向刻蚀，保证后续形成的像素电极10a与源漏电极层5的能够良好搭接。
在具体实施时，这里的平坦层7的材料可以包括树脂；而第一电极层以及第二电极层10的材料则可以包括ITO等；钝化层9的材料可以包括氮化硅；刻蚀阻挡层6的材料可以包括氮化硅，在能够实现对应的功能的前提下，上述的各个层结构具体采用何种材料本发明在此不做限定。
第二方面，本发明实施方式还提供了一种阵列基板的制作方法，可以用以制作上述的阵列基板，该方法可以包括：
步骤S1，在显示区域A内，在基底1上依次形成的栅极2a、栅绝缘层3、有源层4、源漏电极层5、刻蚀阻挡层6以及平坦层7；其中，在过孔区域，刻蚀阻挡层6以及平坦层7中形成有过孔11；同时，在外围线路区域B，还包括形成与栅极2a同层形成的栅极层结构2b，形成在栅极层结构2b上方的栅绝缘层3。经步骤S1之后得到的结构可以参见图4。
在基底上形成栅极2a以及栅极层结构2b、栅绝缘层3、有源层4、源漏电极层5、刻蚀阻挡层6以及平坦层7的步骤均可以参见现有技术，在此不再详细说明。
步骤S2，在显示区域A内，在步骤S1得到的结构上形成一层第一电极层材料(为了方便说明，该层表示为8)，经步骤S2之后得到的结构可以参见图5。
步骤S3，在步骤S2得到的结构之上形成一层光刻胶，并进行曝光显影得到光刻胶图形13；该光刻胶图形13包括光刻胶保留区域和光刻胶去除区域，其中光刻胶保留区域包括需要形成防刻蚀结构的部分(位于过孔11中)以及位于需要形成公共电极的区域的部分。经步骤S3之后得到的结构可以参见图6。
步骤S4，利用步骤S3中形成的光刻胶图形13为掩膜进行刻蚀，得到公共电极图形和防刻蚀图形；公共电极图形包括多个公共电极块8a，防刻蚀图形包括多个防刻蚀结构8b，每一个防刻蚀结构8b对应填充到一个过孔11中，用于防止过孔11处的刻蚀阻挡层6被横向刻蚀，经步骤S4之后得到的结构可以参见图7。
具体来说，可以在步骤S1中的基板上沉积一整层电极材料，由于步骤S1中形成有过孔11，则所沉积的电极材料层会覆盖过孔11内的平坦层7；通过该层电极材料进行图案化，可以得到对应的防刻蚀图形，并得到公共电极图形。
图案化的过程可以具体包括：在电极材料层上形成光刻胶，并使用掩膜版对光刻胶进行曝光显影得到对应的光刻胶图形，之后对以光刻胶图形为掩膜对电极材料层进 行刻蚀，得到防刻蚀图形和公共电极图形。
步骤S5，在步骤S4得到的结构之上形成一层钝化层材料；并对形成有钝化层材料的基板进行刻蚀，刻蚀掉位于显示区域A内的过孔11区域及周边的钝化层材料；并刻蚀位于外围电路区域B内的特定区域内的钝化层材料以及栅绝缘层材料，得到位于该特定区域内的过孔12，经步骤S5之后得到的结构可以参见图8。
在这个步骤中，由于还需要刻蚀外围电路区域B内的栅绝缘层材料，需要刻蚀相对比较长的时间；由于在步骤S2中，在过孔11中形成了覆盖栅绝缘层3的防刻蚀结构8b，则本步骤中，过孔11位置处的刻蚀阻挡层6可以得到有效的防护。
步骤S6，在步骤S5得到的结构之上形成第二电极层；该第二电极层包括位于显示区域A内的像素电极10a以及位于外围电路区域B内的第二电极层结构10b。经步骤S6之后得到的结构可以参考图3。由于在步骤S3中，过孔11位置处的刻蚀阻挡层6没有发生横向刻蚀，像素电极10a能够较好的与源漏金属层5进行良好搭接。
在具体实施时，形成第一电极层的步骤包括：可以利用ITO形成第一电极层；和/或，形成第二电极层的步骤包括：利用ITO形成第二电极层，可以理解的是也可以利用其它透明导电金属材料形成第一电极层以及第二电极层，本发明对此不作具体限定。
在具体实施时，形成平坦层的步骤包括：可以利用树脂形成平坦层。
第三方面，本发明实施方式还提供了一种显示面板，包括上述所述的阵列基板。
第四方面，本发明实施方式还提供了一种显示装置，该显示装置包括上述的显示面板。
在具体实施时，这里的显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然结合附图描述了本发明的实施方式，但是本领域技术人员可以在不脱离本发明的精神和范围的情况下做出各种修改和变型，这样的修改和变型均落入由所附权利要求所限定的范围之内。

Claims (10)

  1. 一种阵列基板，其特征在于，包括基底、依次形成在基底上的栅极层、栅绝缘层、有源层、源漏电极层、刻蚀阻挡层、平坦层、第一电极层、钝化层和第二电极层；其中，所述刻蚀阻挡层、平坦层和钝化层中形成有过孔；
    所述第一电极层包括公共电极图形和防刻蚀图形；所述防刻蚀图形包括多个防刻蚀结构，每一个防刻蚀结构对应填充到一个过孔中；
    所述第二电极层包括像素电极图形，所述像素电极图形中的像素电极通过过孔中的防刻蚀结构与源漏电极层导电连接。
  2. 如权利要求1所述的阵列基板，其中，所述平坦层的材料包括树脂。
  3. 如权利要求1或2所述的阵列基板，其中，所述第一电极层以及第二电极层的材料包括ITO。
  4. 如权利要求1至3中任一所述的阵列基板，其中，所述钝化层的材料包括氮化硅。
  5. 如权利要求1至4中任一所述的阵列基板，其中，所述刻蚀阻挡层的材料包括氮化硅。
  6. 一种显示面板，包括如权利要求1-5任一所述的阵列基板。
  7. 一种显示装置，包括如权利要求6所述的显示面板。
  8. 一种阵列基板的制作方法，包括：
    在基底上依次形成栅极层、栅绝缘层、有源层、源漏电极层、刻蚀阻挡层以及平坦层；其中，所述刻蚀阻挡层以及所述平坦层中形成有过孔；
    在所述平坦层上形成第一电极层；所述第一电极层包括公共电极图形和防刻蚀图形；所述防刻蚀图形包括多个防刻蚀结构，每一个防刻蚀结构对应填充到一个过孔中；
    在所述第一电极层上形成钝化材料；并通过图案化工艺刻蚀掉过孔处的钝化材料得到钝化层；
    在所述钝化层上形成第二电极层，所述第二电极层包括像素电极图形，所述像素电极图形中的像素电极通过过孔中的防刻蚀结构与源漏电极层导电连接。
  9. 如权利要求8所述的方法，其中，形成第一电极层的步骤包括：利用ITO形成第一电极层；和/或，形成第二电极层的步骤包括：利用ITO形成第二电极层。
  10. 如权利要求8或9所述的方法，其中，形成平坦层的步骤包括：利用树脂形成平坦层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114326231A (zh) * 2021-12-14 2022-04-12 广州华星光电半导体显示技术有限公司 显示面板及其制备方法与显示装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105826330A (zh) * 2016-05-12 2016-08-03 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置
CN106876411A (zh) * 2017-03-10 2017-06-20 京东方科技集团股份有限公司 显示基板的制作方法、显示基板和显示装置
CN109427689A (zh) * 2017-08-31 2019-03-05 昆山国显光电有限公司 一种显示面板及其制造方法
CN109192701B (zh) * 2018-08-31 2020-12-08 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN110299385B (zh) * 2019-06-17 2021-09-28 云谷（固安）科技有限公司 显示装置及其显示面板、显示面板的制作方法
CN111312921A (zh) * 2020-02-20 2020-06-19 京东方科技集团股份有限公司 显示面板以及其制造方法、显示装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102445802A (zh) * 2010-10-12 2012-05-09 乐金显示有限公司 用于液晶显示装置的阵列基板及其制造方法
CN105826330A (zh) * 2016-05-12 2016-08-03 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100766318B1 (ko) * 2005-11-29 2007-10-11 엘지.필립스 엘시디 주식회사 유기 반도체 물질을 이용한 박막트랜지스터와 이를 구비한액정표시장치용 어레이 기판 및 그 제조방법
JP4487318B2 (ja) * 2007-07-26 2010-06-23 エプソンイメージングデバイス株式会社 液晶表示装置及びその製造方法
CN104685635B (zh) * 2012-10-01 2017-05-17 夏普株式会社 半导体装置
CN104656332B (zh) * 2015-01-28 2018-11-06 上海天马微电子有限公司 阵列基板及其制备方法和显示装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102445802A (zh) * 2010-10-12 2012-05-09 乐金显示有限公司 用于液晶显示装置的阵列基板及其制造方法
CN105826330A (zh) * 2016-05-12 2016-08-03 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114326231A (zh) * 2021-12-14 2022-04-12 广州华星光电半导体显示技术有限公司 显示面板及其制备方法与显示装置
CN114326231B (zh) * 2021-12-14 2023-10-13 广州华星光电半导体显示技术有限公司 显示面板及其制备方法与显示装置

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