WO2014206015A1 - 阵列基板、其制备方法及显示装置 - Google Patents

阵列基板、其制备方法及显示装置 Download PDF

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Publication number
WO2014206015A1
WO2014206015A1 PCT/CN2013/088658 CN2013088658W WO2014206015A1 WO 2014206015 A1 WO2014206015 A1 WO 2014206015A1 CN 2013088658 W CN2013088658 W CN 2013088658W WO 2014206015 A1 WO2014206015 A1 WO 2014206015A1
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WO
WIPO (PCT)
Prior art keywords
common electrode
black matrix
thin film
photoresist
electrode
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Application number
PCT/CN2013/088658
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English (en)
French (fr)
Inventor
牛菁
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/357,725 priority Critical patent/US9589834B2/en
Publication of WO2014206015A1 publication Critical patent/WO2014206015A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • the liquid crystal display panel is mainly composed of an array substrate, a counter substrate, and liquid crystal molecules located between the two substrates.
  • the array substrate is provided with sub-pixel units arranged in a matrix, and each sub-pixel unit is provided with a thin film transistor (TFT) and a pixel electrode connected to the thin film transistor.
  • TFT thin film transistor
  • a common electrode and a color filter corresponding to each sub-pixel unit are disposed on the opposite substrate.
  • the structure on the array substrate includes: a gate electrode 102 and a common electrode which are sequentially disposed on the substrate substrate 101.
  • the common electrode 113 is electrically connected to the common electrode line 103 through a via a penetrating through the gate insulating layer 104, the first insulating layer 108, the color filter 110, and the second insulating layer 112.
  • the array substrate of the above structure needs to be patterned by using 10 masks during preparation, and the steps of patterning using Mask are specifically as follows: preparing the pattern of the gate electrode 102 and the common electrode line 103, the active layer 105, the source electrode a pattern of 106 and drain 107, a pattern of gate insulating layer 104 and first insulating layer 108, a pattern of black matrix 109, a pattern of color filter 110, a pattern of pixel electrode 111, a pattern of second insulating layer 112, A pattern of the common electrode 113. Since the color filter 110 is generally composed of a monochromatic filter in which three primary colors (red, green, and blue) are arranged in a cross-cord, it is necessary to use a three-channel mask composition for patterning.
  • the opaque common electrode line 103 is disposed in the same layer as the gate electrode 102, on the one hand The opening area of each sub-pixel unit is occupied, which affects the aperture ratio; on the other hand, the common electrode 113 needs to be electrically connected to the common electrode line 103 through the deep via hole a, because the gate insulating layer penetrates through the via hole a 104.
  • the materials of the first insulating layer 108, the color filter 110, and the second insulating layer 112 are different, and multiple patterns are required to be formed in the preparation process, which also increases the difficulty of the overall preparation process.
  • the ADS mode array substrate of the existing COA structure has a problem that the preparation process is difficult and the aperture ratio is low.
  • Embodiments of the present invention provide an array substrate, a preparation method thereof, and a display device, which can improve
  • the aperture ratio of the COA structure can reduce the difficulty of preparation.
  • Embodiments of the present invention provide an array substrate including a substrate, a thin film transistor thin film transistor on the substrate, and an electrode structure on the thin film transistor, the electrode structure including pixel electrodes insulated from each other And the common electrode, also includes:
  • a black matrix located above the thin film transistor, and an orthographic projection of the thin film transistor on the base substrate is located within an orthographic projection of the black matrix on the substrate;
  • the black matrix is electrically connected to the common electrode for providing a common electrode signal to the common electrode.
  • a display device includes the above array substrate provided by the embodiment of the present invention.
  • the electrode structure includes mutually insulated pixel electrodes and a common electrode; forming a black matrix, an orthographic projection of the thin film transistor on the substrate is located in the black matrix on the substrate Within the orthographic projection on the substrate, and the black matrix is directly electrically connected to the common electrode for providing a common electrode signal to the common electrode.
  • the array substrate comprises a thin film transistor thin film transistor on a substrate substrate, and an electrode structure on the thin film transistor, wherein the electrode structure comprises mutually insulated pixel electrodes
  • the common electrode also includes: located in thin An orthographic projection over the film transistor and on the substrate of the substrate covers the black matrix of the thin film transistor; the black matrix is electrically connected to the common electrode for providing a common electrode signal to the common electrode. Since the function of the black matrix multiplexing common electrode line is used, the common electrode signal is electrically connected to the common electrode, and the sub-pixel unit opening can be reduced compared with the common electrode line in the same layer in the prior art. The occupation of the area increases the aperture ratio of the array substrate. Moreover, since the black matrix as the common electrode line is disposed above the thin film transistor, the film layer through which the via holes are required when the black matrix is connected to the common electrode can be reduced, and the difficulty in the fabrication process is also reduced.
  • FIG. 1 is a schematic structural view of an ADS mode array substrate of a conventional COA structure
  • FIGS. 3a to 3f are steps of forming a pattern of a common electrode and a black matrix by one patterning process in a preparation method according to an embodiment of the present invention; Schematic diagram of the structure. detailed description
  • An embodiment of the present invention provides an array substrate, as shown in FIG. 2a to FIG. 2c, including a substrate substrate 201, a thin film transistor 202 on the substrate substrate 201, and an electrode structure 203 on the thin film transistor 202.
  • the structure 203 includes a pixel electrode 2031 and a common electrode 2032 which are insulated from each other.
  • the array substrate further includes a front projection over the thin film transistor 202 and on the substrate substrate 201.
  • the shadow covers the black matrix 204 of the thin film transistor 202. That is, the orthographic projection of the thin film transistor 202 on the base substrate 201 is located within the orthographic projection of the black matrix 204 on the base substrate 201.
  • the black matrix 204 is electrically connected to the common electrode 2032 for providing a common electrode signal to the common electrode 2032.
  • the above array substrate provided by the embodiment of the present invention can be applied to a liquid crystal display such as an in-plane switch (IPS, In-Plane Switch) and an advanced super-dimension switch (ADS) capable of realizing a wide viewing angle.
  • a liquid crystal display such as an in-plane switch (IPS, In-Plane Switch) and an advanced super-dimension switch (ADS) capable of realizing a wide viewing angle.
  • IPS in-plane switch
  • ADS advanced super-dimension switch
  • the black matrix is electrically connected to the common electrode, and is used for providing a common electrode signal to the common electrode. Since the function of the black matrix multiplexing common electrode line is used, the common electrode signal is electrically connected to the common electrode, and the sub-pixel unit opening can be reduced compared with the common electrode line in the same layer in the prior art. The occupation of the area increases the aperture ratio of the array substrate. Moreover, since the black matrix as the common electrode line is disposed above the thin film transistor, the film layer through which the via holes are required when the black matrix is connected to the common electrode can be reduced, and the difficulty in the fabrication process is also reduced.
  • the thin film transistor in the array substrate provided by the embodiment of the present invention may adopt a bottom gate structure, as shown in FIG. 2a to FIG. 2c, a gate electrode 2021 and a gate electrode sequentially disposed on the substrate substrate 201.
  • the insulating layer 2022, the active layer 2023, the source 2024, and the drain 2025 are formed.
  • the thin film transistor 202 in the array substrate may adopt other structures, which are not limited herein.
  • the black matrix 204 as a common electrode line may be directly electrically connected to the common electrode 2032, that is, in the black matrix.
  • the other electrode layer is not disposed between the common electrode and the common electrode 2032.
  • the common electrode needs to be connected to the common electrode line through the via hole penetrating the plurality of film layers, which can be avoided. The setting of the holes reduces the difficulty of the preparation process.
  • the black matrix 204 directly connected to the common electrode 2032 may be directly disposed on the film layer of the common electrode 2032.
  • the black matrix 204 may be disposed directly below the film layer of the common electrode 2032, which is not limited herein.
  • the black matrix 204 in the above array substrate provided by the embodiment of the present invention, when the black matrix 204 is directly located on the common electrode 2032, the common electrode 2032 and the black matrix can be used.
  • the 204 is formed by one patterning process, that is, a gray mask or a halftone mask is used to simultaneously prepare the patterns of the two layers, so that the composition of the mask is reduced by using 10 masks compared with the prior art, which can reduce the use of the Mask. The number of times, thereby improving the manufacturing efficiency of the product and reducing the production cost.
  • a metal material or an opaque organic layer may be used.
  • the conductive material acts as a material for the black matrix.
  • a first insulating layer 206 for insulating protection of the source electrode 2024 and the drain electrode 2025 is disposed on the thin film transistor 202, and is in the first insulation.
  • a color filter 205 is disposed on the layer 206, and the color filter 205 is generally composed of a monochromatic filter in which three primary colors (red, green, and blue) are arranged in a cross.
  • a second insulating layer 207 is disposed between the pixel electrode 2031 and the common electrode 2032.
  • the first insulating layer 206 in the structure shown in FIG. 2a may be omitted between the thin film transistor 202 and the electrode structure 203, and the color is
  • the filter 205 multiplexes the insulating layer, that is, a color filter 205 as an insulating layer is directly disposed between the thin film transistor 202 and the electrode structure 203.
  • the color filter 205 is generally composed of three primary colors (red, green, Blue) A cross-arranged monochromatic filter.
  • a color filter 205 may be used between the pixel electrode 2031 and the common electrode 2032 instead of the structure shown in FIG. 2a.
  • the second insulating layer 207, the color filter 205 multiplexes the insulating layer, that is, a color filter 205 as an insulating layer is disposed between the pixel electrode 2031 and the common electrode 2032.
  • the color filter 205 is generally A monochromatic filter consisting of three primary colors (red, green, blue) arranged in a cross. Compared with the structure shown in FIG.
  • the array substrate according to an embodiment of the present invention may include a plurality of pixel units each including the above-described thin film transistor, an electrode structure, and a black matrix.
  • the color filter in addition to the non-display area corresponding to the thin film transistor, it is also located outside the thin film transistor.
  • the color filter 205 in the display area, in the case where the color filter 205 is substituted for the first insulating layer 206 in FIG. 2a (as shown in FIG. 2b), the color filter may be disposed under the electrode structure; in the color filter In the case of 205 instead of the second insulating layer 207 in FIG. 2a (as shown in FIG. 2c), a color filter may be disposed between the pixel electrode and the common electrode in the electrode structure.
  • Each of the pixel units includes a color filter of one color, and a plurality of pixel units include color filters of different colors, thereby enabling color display.
  • an embodiment of the present invention further provides a display device, which is provided by the embodiment of the present invention.
  • the display device may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, Any product or part that has a display function, such as a navigator.
  • a display device refer to the embodiment of the above array substrate, and the repeated description is omitted.
  • an embodiment of the present invention further provides a method for preparing an array substrate, which specifically includes the following steps:
  • the electrode structure comprises mutually insulated pixel electrodes and a common electrode; forming a black matrix; the orthographic projection of the black matrix on the substrate substrate covers the thin film transistor; and the black matrix is directly electrically connected to the common electrode , for providing a common electrode signal to the common electrode.
  • the black matrix may be located above the common electrode, that is, the black matrix may be formed after the common electrode is formed.
  • the common electrode may be located above the black matrix, that is, the black matrix is formed first, and then the common electrode is formed, which is not limited herein.
  • the method for preparing the array substrate may include the following steps:
  • Step S101 forming a thin film transistor on the base substrate
  • Step S102 forming a pixel electrode on the thin film transistor
  • Step S103 forming a common electrode insulated from the pixel electrode on the pixel electrode;
  • Step S104 forming a black matrix on the common electrode; the orthographic projection of the black matrix on the substrate substrate covers the thin film transistor; and the black matrix is directly electrically connected to the common electrode for providing the common electrode signal to the common electrode.
  • the above step S103 forms a common electrode insulated from the pixel electrode on the pixel electrode and the step S104 forms a black matrix on the common electrode, which can be realized by a Mask, that is, the pattern of the common electrode and the black matrix can be formed by one patterning process, so that The prior art can reduce the number of uses of the Mask, improve the manufacturing efficiency of the product, and reduce the production cost.
  • the pattern of the common electrode and the black matrix formed by one patterning process can be realized by the following means:
  • a thin film of the common electrode 2032 and a thin film of the black matrix 204 are sequentially formed as shown in Fig. 3a;
  • a photoresist 208 is coated on the film of the black matrix, and the photoresist 208 is exposed and developed using a mask, as shown in FIG. 3b, a photoresist completely removed region a, a photoresist portion reserved region b, and The photoresist completely retains the region c;
  • the mask may be a halftone mask or a gray tone mask;
  • the photoresist portion remaining region b corresponds to the pattern region where the common electrode 2032 is formed, and the photoresist completely reserved region c corresponds to the pattern region where the black matrix 204 is formed;
  • the photoresist completely removed region &, the photoresist portion remaining region b, and the photoresist completely reserved region c are etched to form a pattern of the common electrode 2032 and the black matrix 204.
  • the process of etching the photoresist completely removed region &, the photoresist portion remaining region b, and the photoresist completely remaining region c to form a pattern of the common electrode 2032 and the black matrix 204 can be realized, for example, by:
  • the film of the common electrode 2032 of the region a and the film of the black matrix 204 are completely removed by an etching process, and a pattern of the common electrode 2032 is obtained, as shown in FIG. 3c;
  • an etch process is used to remove the film of the black matrix 204 of the photoresist portion retention region b, as shown in FIG. 3e;
  • the photoresist 208 is completely stripped of the photoresist to obtain a pattern of the black matrix 204, as shown in Fig. 3f.
  • a metal material or an opaque organic conductive material may be used as the material of the black matrix.
  • a color filter as an insulating layer is formed on the thin film transistor, and the color filter is generally arranged by three primary colors (red, green, blue). Color filter composition.
  • a color filter as an insulating layer is formed on the pixel electrode, and the color filter is generally composed of three primary colors (red, green) , blue) consisting of crossed monochromatic filters.
  • the structure and method of the above array substrate have been described by way of example only in which the thin film transistor, the electrode structure, and the black matrix are disposed in this order from the substrate substrate side.
  • embodiments according to the present invention are not limited thereto.
  • the stacking order of the above-mentioned thin film transistor, electrode structure and black matrix can be changed according to actual needs, except that the black matrix and the common electrode are electrically connected, thereby avoiding the provision of a common electrode line.
  • the array substrate comprises a thin film transistor thin film transistor on a substrate substrate, and an electrode structure on the thin film transistor, wherein the electrode structure comprises mutually insulated pixel electrodes
  • the common electrode further comprising: a black matrix of the orthographic projection over the thin film transistor and on the substrate substrate covering the thin film transistor; the black matrix is electrically connected to the common electrode for providing the common electrode signal to the common electrode. Since the function of the black matrix multiplexing common electrode line is used, the common electrode signal is electrically connected to the common electrode, and the sub-pixel unit opening can be reduced compared with the common electrode line in the same layer in the prior art. The occupation of the area increases the aperture ratio of the array substrate. Moreover, since the black matrix as the common electrode line is disposed above the thin film transistor, the film layer through which the via holes are required when the black matrix is connected to the common electrode can be reduced, and the difficulty in the fabrication process is also reduced.

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Abstract

提供了一种阵列基板、其制备方法及显示装置。阵列基板包括位于衬底基板（201）上的薄膜晶体管（202），位于薄膜晶体管（202）上的电极结构（203），电极结构（203）包括相互绝缘的像素电极（2031）和公共电极（2032）。阵列基板还包括：位于薄膜晶体管（202）上方的黑矩阵（204），且薄膜晶体管（202）在衬底基板（201）上的正投影位于黑矩阵（204）在衬底基板（201）上的正投影之内；黑矩阵（204）与公共电极（2032）电性相连，用于向公共电极（2032）提供公共电极信号。

Description

阵列基板、 其制备方法及显示装置 技术领域
本发明的实施例涉及一种阵列基板、 其制备方法及显示装置。 背景技术
液晶显示面板主要由阵列基板、 对向基板以及位于该两基板之间的液晶 分子组成。 阵列基板上设置有呈矩阵排列的亚像素单元， 每个亚像素单元都 设置有薄膜晶体管 （TFT ) 以及与薄膜晶体管相连的像素电极。 对向基板上 设置有公共电极和与各亚像素单元——对应的彩色滤光片。 液晶显示面板在 对盒时需要将对向基板上的各彩色滤光片与阵列基板上的各亚像素单元进行 对位。 在对位时容易出现对位误差， 为了避免对位误差的产生， 出现了将彩 色滤光片直接设置在阵列基板上的结构 （COA, CF on Array ) 。
目前， 现有的 COA结构大多是将彩色滤光片直接筒单的叠加在阵列基 板上。 以高级超维场开关（ADS, Advanced Super Dimension Switch )模式的 COA结构为例， 如图 1所示， 其阵列基板上的结构包括： 依次设置在衬底基 板 101上的栅极 102和公共电极线 103 ,栅绝缘层 104,有源层 105,源极 106 和漏极 107, 第一绝缘层 108, 黑矩阵 109, 彩色滤光片 110, 像素电极 111 , 第二绝缘层 112,以及公共电极 113。公共电极 113通过贯穿栅极绝缘层 104、 第一绝缘层 108、 彩色滤光片 110以及第二绝缘层 112的过孔 a与公共电极 线 103电性相连。
上述结构的阵列基板在制备时需要使用 10道掩膜板 ( Mask )进行构图， 需要使用 Mask进行构图的步骤具体为： 制备栅极 102和公共电极线 103的 图形， 有源层 105、 源极 106和漏极 107的图形， 栅极绝缘层 104和第一绝 缘层 108的图形，黑矩阵 109的图形，彩色滤光片 110的图形，像素电极 111 的图形，第二绝缘层 112的图形，公共电极 113的图形。 由于彩色滤光片 110 一般是由三原色（红， 绿， 蓝） 交叉排列的单色滤光片组成的， 因此需要分 别使用 3道 Mask构图进行构图。
在上述结构中， 不透光的公共电极线 103与栅极 102同层设置， 一方面 会占用各亚像素单元的开口区域， 影响了开口率； 另一方面， 公共电极 113 需要通过较深的过孔 a与公共电极线 103电性相连， 由于该过孔 a贯穿的栅 极绝缘层 104、第一绝缘层 108、彩色滤光片 110以及第二绝缘层 112的材料 不尽相同， 在制备过程需要多次构图才能形成， 这也增加了整体制备工艺的 难度。
综上所述,现有 COA结构的 ADS模式阵列基板存在制备工艺难度较大， 开口率较低的问题。 发明内容
本发明实施例提供一种阵列基板、 其制备方法及显示装置， 可以提高
COA结构的开口率且可以降低制备难度。
本发明实施例提供了一种阵列基板， 包括衬底基板， 位于所述衬底基板 上的薄膜晶体管薄膜晶体管， 以及位于所述薄膜晶体管上的电极结构， 所述 电极结构包括相互绝缘的像素电极和公共电极， 还包括：
位于所述薄膜晶体管上方的黑矩阵， 且所述薄膜晶体管在所述衬底基板 上的正投影位于所述黑矩阵在所述衬底基板上的正投影之内；
所述黑矩阵与所述公共电极电性相连， 用于向所述公共电极提供公共电 极信号。
本发明实施例提供的一种显示装置， 包括本发明实施例提供的上述阵列 基板。
本发明实施例提供的一种阵列基板的制备方法， 包括：
在衬底基板上形成薄膜晶体管的步骤；
形成电极结构的步骤；所述电极结构包括互绝缘的像素电极和公共电极； 形成黑矩阵的步骤， 所述薄膜晶体管在所述衬底基板上的正投影位于所 述黑矩阵在所述衬底基板上的正投影之内， 且所述黑矩阵与所述公共电极直 接电性相连， 用于向所述公共电极提供公共电极信号。
本发明实施例的有益效果包括：
本发明实施例提供的一种阵列基板、 其制备方法及显示装置， 该阵列基 板包括位于衬底基板上的薄膜晶体管薄膜晶体管， 以及位于薄膜晶体管上的 电极结构， 电极结构包括相互绝缘的像素电极和公共电极， 还包括： 位于薄 膜晶体管上方且在村底基板上的正投影覆盖薄膜晶体管的黑矩阵； 黑矩阵与 公共电极电性相连， 用于向公共电极提供公共电极信号。 由于采用黑矩阵复 用公共电极线的功能， 与公共电极电性相连向其提供公共电极信号， 相对于 现有技术中单独设置与栅极同层的公共电极线， 可以减少各亚像素单元开口 区域的占用， 提高阵列基板的开口率。 并且， 由于将作为公共电极线的黑矩 阵设置在薄膜晶体管的上方， 还可以减少黑矩阵与公共电极连接时所需过孔 所贯穿的膜层， 也降低了制备工艺的难度。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有 COA结构的 ADS模式阵列基板的结构示意图；
图 2a至图 2c分别为本发明实施例提供的阵列基板的结构示意意图； 图 3a至图 3f为本发明实施例提供的制备方法中通过一次构图工艺形成 公共电极和黑矩阵的图形的各步骤的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
附图中各层薄膜厚度和形状不反映阵列基板的真实比例， 目的只是示意 说明本发明内容。
本发明实施例提供了一种阵列基板， 如图 2a至图 2c所示， 包括村底基 板 201 , 位于村底基板 201上的薄膜晶体管 202, 以及位于薄膜晶体管 202 上的电极结构 203 ,该电极结构 203包括相互绝缘的像素电极 2031和公共电 极 2032。
该阵列基板还包括位于薄膜晶体管 202上方且在村底基板 201上的正投 影覆盖薄膜晶体管 202的黑矩阵 204。 也就是说， 薄膜晶体管 202在衬底基 板 201上的正投影位于黑矩阵 204在衬底基板 201上的正投影之内。 黑矩阵 204与公共电极 2032电性相连， 用于向公共电极 2032提供公共电极信号。
具体地， 本发明实施例提供的上述阵列基板可以适用于能够实现宽视角 的平面内开关（IPS, In-Plane Switch )和高级超维场开关（ ADS, Advanced Super Dimension Switch )型等液晶显示屏， 在此不做限定。 以下描述都是以应用于 ADS型液晶显示面板为例进行说明。
本发明实施例提供的上述阵列基板中， 黑矩阵与公共电极电性相连， 且 用于向公共电极提供公共电极信号。由于采用黑矩阵复用公共电极线的功能， 与公共电极电性相连向其提供公共电极信号， 相对于现有技术中单独设置与 栅极同层的公共电极线， 可以减少各亚像素单元开口区域的占用， 提高阵列 基板的开口率。 并且， 由于将作为公共电极线的黑矩阵设置在薄膜晶体管的 上方， 还可以减少黑矩阵与公共电极连接时所需过孔所贯穿的膜层， 也降低 了制备工艺的难度。
在具体实施时， 本发明实施例提供的上述阵列基板中的薄膜晶体管可以 采用底栅型结构， 如图 2a至图 2c所示， 由依次设置在衬底基板 201上的栅 极 2021、 栅极绝缘层 2022、 有源层 2023、 源极 2024和漏极 2025组成， 当 然在具体实施时阵列基板中的薄膜晶体管 202也可以采用其他结构， 在此不 做限定。
下面以底栅型结构的薄膜晶体管为例对本发明实施例提供的上述阵列基 板进行说明。
较佳地，在本发明实施例提供的上述阵列基板中，如图 2a至图 2c所示， 可以将作为公共电极线的黑矩阵 204设置为与公共电极 2032直接电性相连， 即在黑矩阵 204与公共电极 2032之间不设置其他膜层，相对于现有技术中公 共电极线与栅极同层设置， 公共电极需要通过贯穿多个膜层的过孔与公共电 极线相连， 可以避免过孔的设置， 降低了制备工艺的难度。
在具体实施时， 在本发明实施例提供的上述阵列基板中， 如图 2a至图 2c所示， 直接与公共电极 2032电性相连的黑矩阵 204可以直接设置在公共 电极 2032的膜层之上， 当然也可以将黑矩阵 204直接设置在公共电极 2032 的膜层以下， 在此不作限定。 较佳地，如图 2a至图 2c所示，在本发明实施例提供的上述阵列基板中， 采用黑矩阵 204直接位于所述公共电极 2032之上的结构时，可以将公共电极 2032和黑矩阵 204通过一次构图工艺制成， 即采用一块灰色调掩膜板或半色 调掩膜板同时制备两个膜层的图形， 这样相对于现有技术需要采用 10 道 Mask进行构图， 可以减少 Mask的使用次数， 从而提高产品的制造效率， 降 低生产成本。
例如， 在本发明实施例提供的上述阵列基板中， 为了保证黑矩阵既具有 对薄膜晶体管进行遮光保护的不透光性，又具有传递公共电极信号的导电性， 可以采用金属材料或不透明的有机导电材料作为黑矩阵的材料。
例如， 在本发明实施例提供的上述阵列基板中， 如图 2a所示， 在薄膜晶 体管 202上设置对源极 2024和漏极 2025起绝缘保护作用的第一绝缘层 206, 并在第一绝缘层 206上设置彩色滤光片 205, 该彩色滤光片 205—般由三原 色（红， 绿， 蓝）交叉排列的单色滤光片组成。 并在像素电极 2031与公共电 极 2032之间设置第二绝缘层 207。
进一步地， 在本发明实施例提供的上述阵列基板中， 如图 2b所示，还可 以在薄膜晶体管 202与电极结构 203之间省去图 2a所示结构中的第一绝缘层 206,将彩色滤光片 205复用绝缘层的作用， 即在薄膜晶体管 202与电极结构 203 之间直接设置作为绝缘层的彩色滤光片 205 , 同样， 该彩色滤光片 205 一般由三原色 （红， 绿， 蓝） 交叉排列的单色滤光片组成。 相对于如图 2a 所示的结构， 利用彩色滤光片复用绝缘层的功能， 可以省去在源极漏极与像 素电极之间另外设置绝缘层， 这样， 在制备时可以减少一道 Mask进行构图， 进一步提高产品的制造效率， 降低生产成本。
或者，进一步地，在本发明实施例提供的上述阵列基板中，如图 2c所示， 还可以在像素电极 2031与公共电极 2032之间采用彩色滤光片 205代替图 2a 所示结构中的第二绝缘层 207, 彩色滤光片 205复用绝缘层的作用， 即在像 素电极 2031与公共电极 2032之间设置作为绝缘层的彩色滤光片 205, 同样， 该彩色滤光片 205—般由三原色（红， 绿， 蓝）交叉排列的单色滤光片组成。 相对于如图 2a所示的结构，在像素电极与公共电极之间利用彩色滤光片复用 绝缘层的功能， 省去另外设置的绝缘层， 这样， 在制备时可以减少一道 Mask 进行构图， 进一步提高产品的制造效率， 降低生产成本。 在图 2a-2c中仅仅示出了薄膜晶体管部分的结构。 根据本发明实施例的 阵列基板可以包括多个像素单元， 每个像素单元包括上述薄膜晶体管、 电极 结构和黑矩阵。 对于彩色滤光片， 除了位于与薄膜晶体管相对应的非显示区 夕卜，还位于薄膜晶体管之外的显示区。例如，在显示区内，在彩色滤光片 205 代替图 2a中的第一绝缘层 206的情况下 （如图 2b所示） ， 彩色滤光片可以 设置在电极结构下方；在彩色滤光片 205代替图 2a中的第二绝缘层 207的情 况下（如图 2c所示）， 彩色滤光片可以设置在电极结构中的像素电极和公共 电极之间。 每个像素单元包括一种颜色的彩色滤光片， 多个像素单元中包括 不同颜色的彩色滤光片， 从而能够实现彩色显示。
基于同一发明构思， 本发明实施例还提供了一种显示装置， 包括本发明 实施例提供的上述阵列基板， 该显示装置可以为： 手机、 平板电脑、 电视机、 显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。 该显示装置的实施可以参见上述阵列基板的实施例， 重复之处不再赘述。
基于同一发明构思， 本发明实施例还提供了一种阵列基板的制备方法， 具体包括以下步骤：
在衬底基板上形成薄膜晶体管的步骤；
形成电极结构的步骤； 该电极结构包括互绝缘的像素电极和公共电极； 形成黑矩阵的步骤； 该黑矩阵在衬底基板上的正投影覆盖薄膜晶体管； 且黑矩阵与公共电极直接电性相连， 用于向公共电极提供公共电极信号。
例如， 黑矩阵可以位于公共电极的上方， 即先形成公共电极之后再形成 黑矩阵， 当然公共电极也可以位于黑矩阵的上方， 即先形成黑矩阵之后再形 成公共电极， 在此不做限定。
例如， 当黑矩位于公共电极上方时， 本发明实施例提供的阵列基板的制 备方法可以包括以下步骤：
步骤 S101、 在衬底基板上形成薄膜晶体管；
步骤 S102、 在薄膜晶体管上形成像素电极；
步骤 S103、 在像素电极上形成与像素电极绝缘的公共电极；
步骤 S104、在公共电极上形成黑矩阵； 该黑矩阵在衬底基板上的正投影 覆盖薄膜晶体管； 且黑矩阵与公共电极直接电性相连， 用于向公共电极提供 公共电极信号。 上述步骤 S103在像素电极上形成与像素电极相互绝缘的公共电极和步 骤 S104在公共电极上形成黑矩阵， 可以采用一道 Mask实现， 即可以通过一 次构图工艺形成公共电极和黑矩阵的图形， 这样相对于现有技术能够减少 Mask的使用次数， 提高产品的制造效率， 降低生产成本。
例如， 通过一次构图工艺形成公共电极和黑矩阵的图形， 可以通过下述 方式实现：
首先， 依次形成公共电极 2032的薄膜和黑矩阵 204的薄膜， 如图 3a所 示；
然后， 在黑矩阵的薄膜上涂覆光刻胶 208, 使用掩膜板对光刻胶 208曝 光显影， 如图 3b所示， 得到光刻胶完全去除区域 a、 光刻胶部分保留区域 b 以及光刻胶完全保留区域 c; 例如， 掩模板可以为半色调掩模板或灰色调掩 模板；
光刻胶部分保留区域 b对应于形成公共电极 2032的图形区域，光刻胶完 全保留区域 c对应于形成黑矩阵 204的图形区域；
最后， 对光刻胶完全去除区域&、 光刻胶部分保留区域 b以及光刻胶完 全保留区域 c进行刻蚀， 形成公共电极 2032和黑矩阵 204的图形。
对光刻胶完全去除区域&、 光刻胶部分保留区域 b以及光刻胶完全保留 区域 c进行刻蚀，形成公共电极 2032和黑矩阵 204的图形的过程，例如可以 通过以下方式实现：
首先，采用刻蚀工艺去掉光刻胶完全去除区域 a的公共电极 2032的薄膜 和黑矩阵 204的薄膜， 得到公共电极 2032的图形， 如图 3c所示；
然后， 灰化光刻胶 208, 去除掉光刻胶部分保留区域 b的光刻胶 208, 如 图 3d所示；
接着， 采用刻蚀工艺去掉光刻胶部分保留区域 b的黑矩阵 204的薄膜， 如图 3e所示；
最后， 剥离光刻胶完全保留区域 c的光刻胶 208, 得到黑矩阵 204的图 形， 如图 3f所示。
较佳地， 例如， 为了保证黑矩阵既具有对薄膜晶体管进行遮光保护的不 透光性， 又具有传递公共电极信号的导电性， 可以采用金属材料或不透明的 有机导电材料作为黑矩阵的材料。 进一步地， 在薄膜晶体管上形成像素电极的步骤 S102之前， 在薄膜晶 体管上先形成作为绝缘层的彩色滤光片，且该彩色滤光片一般由三原色（红， 绿， 蓝） 交叉排列的单色滤光片组成。 相对于现有结构的制备方法， 利用彩 色滤光片复用绝缘层的功能， 可以省去在源极漏极与像素电极之间另外设置 绝缘层， 这样， 在制备时可以减少一道 Mask进行构图， 进一步提高产品的 制造效率， 降低生产成本。
或者， 进一步地， 在像素电极上形成与像素电极绝缘的公共电极的步骤 S103之前， 在像素电极上先形成作为绝缘层的彩色滤光片， 且该彩色滤光片 一般由三原色（红， 绿， 蓝） 交叉排列的单色滤光片组成。 相对于现有结构 的制备方法， 利用彩色滤光片复用绝缘层的功能， 可以省去在像素电极与公 共电极之间另外设置绝缘层， 这样， 在制备时可以减少一道 Mask进行构图， 进一步提高产品的制造效率， 降低生产成本。
以上阵列基板的结构和方法虽然仅仅以从衬底基板侧依次设置薄膜晶体 管、 电极结构和黑矩阵的设置方式为例进行了描述。 然而， 根据本发明的实 施例并不限制于此。 上述薄膜晶体管、 电极结构和黑矩阵的叠置次序可以根 据实际需要而改变， 只是要黑矩阵和公共电极电性连接， 从而避免另外设置 公共电极线。
本发明实施例提供的一种阵列基板、 其制作方法及显示装置， 该阵列基 板包括位于衬底基板上的薄膜晶体管薄膜晶体管， 以及位于薄膜晶体管上的 电极结构， 电极结构包括相互绝缘的像素电极和公共电极， 还包括： 位于薄 膜晶体管上方且在衬底基板上的正投影覆盖薄膜晶体管的黑矩阵； 黑矩阵与 公共电极电性相连， 用于向公共电极提供公共电极信号。 由于采用黑矩阵复 用公共电极线的功能， 与公共电极电性相连向其提供公共电极信号， 相对于 现有技术中单独设置与栅极同层的公共电极线， 可以减少各亚像素单元开口 区域的占用， 提高阵列基板的开口率。 并且， 由于将作为公共电极线的黑矩 阵设置在薄膜晶体管的上方， 还可以减少黑矩阵与公共电极连接时所需过孔 所贯穿的膜层， 也降低了制备工艺的难度。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括衬底基板， 位于所述衬底基板上的薄膜晶体管， 以及位于所述薄膜晶体管上的电极结构， 所述电极结构包括相互绝缘的像素 电极和公共电极， 该阵列基板还包括：
位于所述薄膜晶体管上方的黑矩阵， 且所述薄膜晶体管在所述衬底基板 上的正投影位于所述黑矩阵在所述衬底基板上的正投影之内；
所述黑矩阵与所述公共电极电性相连， 用于向所述公共电极提供公共电 极信号。
2、如权利要求 1所述的阵列基板， 其中， 所述黑矩阵与所述公共电极直 接电性相连。
3、如权利要求 2所述的阵列基板， 其中， 所述黑矩阵直接位于所述公共 电极之上。
4、 如权利要求 1-3任一项所述的阵列基板， 其中， 所述黑矩阵为金属材 料或不透明的有机导电材料。
5、 如权利要求 1-4任一项所述的阵列基板， 其中， 所述阵列基板包括多 个像素单元， 且每个像素单元包括所述薄膜晶体管、 所述电极结构和所述黑 矩阵； 每个像素单元包括显示区和非显示区， 所述薄膜晶体管位于所述非显 示区， 所述电极结构的一部分位于所述薄膜晶体管上方， 所述电极结构的另 一部分位于所述显示区。
6、 如权利要求 1-5任一项所述的阵列基板， 还包括： 位于所述薄膜晶体 管与所述电极结构之间且作为绝缘层的彩色滤光片。
7、 如权利要求 1-5任一项所述的阵列基板， 还包括： 位于所述像素电极 与所述公共电极之间且作为绝缘层的彩色滤光片。
8、 一种显示装置， 包括如权利要求 1-7任一项所述的阵列基板。
9、 一种阵列基板的制备方法， 包括：
在衬底基板上形成薄膜晶体管的步骤；
形成电极结构的步骤， 所述电极结构包括相互绝缘的像素电极和公共电 极；
形成黑矩阵的步骤， 所述薄膜晶体管在所述衬底基板上的正投影位于所 述黑矩阵在所述村底基板上的正投影之内， 且所述黑矩阵与所述公共电极直 接电性相连， 用于向所述公共电极提供公共电极信号。
10、 如权利要求 9所述的制备方法， 其中， 所述形成电极结构的步骤和 形成黑矩阵的步骤包括：
在所述薄膜晶体管上形成像素电极；
在所述像素电极上形成与所述像素电极绝缘的公共电极；
在所述公共电极上形成黑矩阵。
11、如权利要求 10所述的制备方法， 其中， 所述在所述像素电极上形成 与所述像素电极绝缘的公共电极以及在所述公共电极上形成黑矩阵包括： 通过一次构图工艺形成所述公共电极和黑矩阵。
12、如权利要求 11所述的制备方法， 其中， 所述通过一次构图工艺形成 公共电极和黑矩阵包括：
依次形成公共电极的薄膜和黑矩阵的薄膜；
在所述黑矩阵的薄膜上涂覆光刻胶， 使用掩膜板对光刻胶曝光显影， 得 到光刻胶完全去除区域、 光刻胶部分保留区域以及光刻胶完全保留区域； 所 述光刻胶部分保留区域对应于形成所述公共电极的区域， 所述光刻胶完全保 留区域对应于形成所述黑矩阵的区域；
对光刻胶完全去除区域、 光刻胶部分保留区域以及光刻胶完全保留区域 进行刻蚀， 形成公共电极和黑矩阵。
13、如权利要求 12所述的制备方法， 其中， 所述掩模板为半色调掩模板 或灰色调掩模板。
14、 如权利要求 12或 13所述的制备方法， 其中， 所述对光刻胶完全去 除区域、 光刻胶部分保留区域以及光刻胶完全保留区域进行刻蚀， 形成公共 电极和黑矩阵包括： 的薄膜， 得到公共电极；
灰化光刻胶， 去除掉所述光刻胶部分保留区域的光刻胶；
采用刻蚀工艺去掉所述光刻胶部分保留区域的黑矩阵的薄膜， 剥离所述 光刻胶完全保留区域的光刻胶， 得到黑矩阵。
15、 如权利要求 9-14任一项所述的制备方法， 其中， 所述黑矩阵由金属 材料或不透明的有机导电材料形成。
16、如权利要求 10所述的制备方法， 其中，在形成所述薄膜晶体管之后 且在所述形成所述像素电极之前， 还包括： 在所述薄膜晶体管上形成作为绝 缘层的彩色滤光片。
17、 如权利要求 9所述的制备方法， 其中， 在形成所述像素电极之后且 在所述形成所述公共电极之前， 还包括： 在所述像素电极上形成作为绝缘层 的彩色滤光片。
PCT/CN2013/088658 2013-06-24 2013-12-05 阵列基板、其制备方法及显示装置 WO2014206015A1 (zh)

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