1299573 九、發明說明： 【發明所屬之技術領域】 本發明疋有關於一種液晶顯示器，特別是薄膜電晶體 液晶顯示器陣列之結構及製造方法。 【先前技術】 隨著液晶顯示器技術的進步和市場對大尺寸顯示器的 需求，不僅液晶顯示器的尺寸愈來愈大，顯示器的解析度 也愈來愈高，使得導線的阻抗和電容也跟著提高。導線之 阻抗和電容的提高會使得顯示器中電阻電容延遲的問題愈 來愈嚴重，除了影響到顯示器中訊號的傳輸，也降低了顯 示器的顯示品質。 習知降低顯示器中電阻電容延遲的方法，主要為導入 銅製釭及增加導線線寬。雖然在液晶顯示器製程中導入製 作銅導線的銅製程，可降低導線的阻抗而增加訊號的傳導 速度，因而可望降低電阻電容延遲，但銅製程本身卻有許 多問題有待解決。增加導線線寬因為可增加導線的截面 積，降低導線的阻抗，故可降低電阻電容延遲的影響。但 導線加寬部會影響到畫素顯示的面積，降低顯示器的開口 率及顯示器的亮度。 另外，由於顯示器的晝素區域是由多個不同功能的薄 層組成’各薄層的反射率差異很大，以致於光在通過薄層 和薄層間的界面時，造成部分的光容易反射而降低光的穿 透度。如此一來，會使得顯示器亮度下降，或顯示器需要 5 •1299573 用較高亮度的背光源才能達到想要的亮度。 【發明内容】 因此本發明的目的之一就是在提供一種液晶顯示器陣 列基板，能降低其導線之電阻電容延遲，並且不會影響到 顯示器的開口率。 本發明的另一目的是在提供一種液晶顯示器陣列基板 之製造方法，能增加穿透晝素區域的光量，提升顯示器的 亮度。 根據本發明之上述目的，提出一種液晶顯示器陣列基 板。此陣列基板包含第一導線、第二導線、訊號絕緣層、 第三導線、第四導線、電晶體和晝素電極。第一導線，位 於基板上並且具有交叉區域。第二導線於基板上，分別垂 直排列於第一導線之交叉區域之兩侧。訊號絕緣層，位於 第二導線與交叉區域之上，其中位於第二導線上之訊號絕 緣層具有第一開口，以暴露出第二導線。第三導線，覆蓋 父叉區域兩側之第一導線以複合成一掃描線。第四導線， 覆蓋第一導線與交叉區域以複合成一訊號線，第三導線與 第四導線沒有相接。電晶體的源極與第四導線電性相連， 電晶體的閘極與第一導線電性相連。畫素電極與電晶體之 汲極電性相接。 根據本發明之上述目的，提出一種液晶顯示器陣列基 板之製造方法。首先，以圖案化之第一金屬層於基板上分 別形成第一導線、第二導線及閘極，第一導線具有交叉區 6 1299573 域且與閘極電性相連，第二導線分別垂直排列於第一導線 之交叉區域之兩側。之後，依序形成圖案化之介電層及半 ‘體層於弟一導線、父叉區域與閘極上方，其中位於第二 導線上之介電層與半導體層具有第一開口以曝露出第二導 線，位於閘極上方之介電層與半導體層分別作為介電層與 通道層之用。之後，以圖案化之第二金屬層於基板上分別 幵成弟二導線來覆蓋位於交叉區域兩側之第一導線以形成 掃描線，形成第四導線來覆蓋位於第二導線與交叉區域上 之半導體層以开> 成訊號線，以及形成源極及汲極於通道層 上之兩側以形成薄膜電晶體，其中第三導線與第四導線沒 有相接。之後，形成圖案化之保護層覆蓋於薄膜電晶體、 掃描線與訊號線之上。最後，形成晝素電極於基板上方， 晝素電極與薄膜電晶體電性相接。 由上述可知，在本發明的薄膜電晶體液晶顯示器陣列 基板之結構中，因為掃描線和訊號線的厚度增加了，截面 積變大了，阻抗因而降低了，故可改善電阻電容延遲對書 素品質的影響。而且，因為掃描線和訊號線在基板上佔據 的面積依然一樣，故不會影響畫素面積的大小。此外，因 為晝素區域上無介電層，故光所需通過的層數減少，使得 晝素區域的透光率增加，以增加顯示器的亮度。 【實施方式】 以下將以圖示及詳細說明清楚說明本發明之精神，如 熟悉此技術之人員在瞭解本發明之較佳實施例後，當可由 7 1299573 本發明所教示之技術，加以改變及修飾，其並不脫離本發 明之精神與範圍。 實施例一 請同時參見第1A圖與第2A圖，第1A圖為第2A圖中 訊號線的AA切線、掃描線的BB切線、電容線的cc切線 和閘極的DD切線的剖面結構示意圖。首先，在透明基板（未 繪示於圖中）上形成第一金屬層，然後定義第一金屬層以形 成第一掃描線112、第一訊號線114、電容線116及閘極 118。在第2A圖中，第一掃描線112與電容線116互相平 行，第一掃描線112與電容線116分別具有複數個交叉區 域119。第一訊號線114垂直於第一掃描線112和電容線 116，且第一訊號線丨14間斷排列於第一掃描線丨丨2和電容 線116之父叉區域119之兩側，不與交叉區域119相接。 第一掃描線112與第一訊號線114所定義出之區域為基板 上的畫素區域。 η月參見第1B圖’在第一掃描線ι12、第一訊號線114、 電容線116及閘極118上依序形成一層介電層12〇和一層 半導體層130。在較佳的實施例中，半導體層13〇由非晶矽 層和位於其上的Ν型摻雜非晶矽層共同組成。 印同時參照第1C圖與第2Β圖，第2Β圖為第1C圖的 俯視圖。在第ic圖與第2Β圖中，定義半導體層13〇和介 電層120’以分別在第一訊號線U4和交叉區域η9上形成 訊號絕緣層134，在電容線116上形成電容介電層136，在 1299573 閘極118上形成通道層138。在第一訊號線114之中央部分 的讯號絕緣層134具有開口 139，以暴露出第一訊號線 114。而且訊號絕緣層134和電容介電層136各自獨立不相 接。在此’由第一掃描線丨丨2與第一訊號線丨14所定義出 - 之晝素區域之上的介電層和半導體層全被移除，以減少光 通過晝素區域所需經過的薄膜層數，讓晝素區域的透光率 增加。 參 請同時參考第1D圖與第2C圖，第2C圖為第id圖的 俯視圖在疋義元半導體層和介電層後，在其上形成一層 第二金屬層。然後定義第二金屬層，以分別在暴露出的第 - 一掃描線112上形成第二掃描線142，在訊號絕緣層134 * 上及開口 I39之中形成第二訊號線144，在電容介電層136 上形成上電極146,在通道層138之兩側分別形成源極148 和汲極149,以及形成連接線147用以連接上電極146與汲 極 149。 _ 上述之第二掃描線142和第一掃描線Π2直接接觸， 形成了具有雙層金屬結構之掃描線。而第二訊號線144和 第一訊號線114在開口 139處直接接觸，亦形成具有雙層 金屬結構之訊號線。在交叉區域119上的訊號絕緣層134 用來使第二訊號線144分別與第一掃描線112以及電容線 ^ U6互相絕緣。上述之閘極118、源極148和汲極149構成 電晶體之三個電極。上述之電容線116、電容介電層136、 上電極146三者構成完整的儲存電容器。 最後，請同時參考第1E圖與第2D圖，第2D圖為第 9 1299573 1E圖的俯視圖。在第1E圖與第2D圖中，先沉積一層保護 層150，然後疋義保護層15〇，以移除位於畫素區域與上電 極146的保護層，並使其覆蓋在第二掃描線142、第二訊號 線144、源極148和汲極149之上，以保護上述之導線與電 極，使其不易被氧化。 ^ 接著，在基板上形成平坦層160，再定義平坦層16〇， 以暴露出上電極146。 最後，形成透明導電層，再定義透明導電層，以在晝 素區域上形成與上電極146相接之畫素電極17卜在此，= 素電極是透過上電極146與沒極149相接。畫素電極⑺ 彼此獨立不相接。在本發明的液晶顯示器陣列基板中，掃 描線和訊號㈣由兩層金屬層所構成。在先前所述中，掃 描線由第-掃描線和第二掃描線所構成，訊號線由第一訊 號線和第二訊號線所構成。如此，掃描線和訊號線的厚度 增=了，截面積變大了，阻抗因而降低了，故可改善電阻 電合延遲對畫素品質的影響。此外，因為掃描線和訊號線 在基板上佔據的面積依然—樣，故不會影響每個畫素之 口率的大小。 一 此外，原本光經過畫素區域時，需要穿過基板、介電 f、平坦層和透明導電。因為各層之間的折射率不同，使 仔光在穿透界面時，部分光會因為折射與/或反射而損耗。 在本實施例中，移除了折射率最大的介電層，不僅各層之 間的折射率差異縮小，光通過界面間的反射率也減少了。 “斤而、、工過的層數由五層降低到三層，需經過的界面數由 1299573 四個減少到兩個，使得光在界面的反射機率大幅降低。光 通過畫素區域的損耗減少了，故最終的顯示器產品的亮度 可望獲得明顯的提升。 實施例二 在實施例二中，省略了實施例一之平坦層，因此也對 液^顯示器陣列基板的部分結構做出—些相對應的調整。 在實施例二中，除了在定義第二金屬層時，在電容介電層 上不形成上電極外，從第一金屬層之沉積至保護層之沉積 的製程步驟與實施例—的製程步驟相同，故在此不再贊述。 請同時參考第3A圖與第3B圖，第3B圖為第3A圖的 俯視圖。。 在沉積保護層之後，定義保護層15G使其覆蓋於第二 掃描線142、苐一讯號線144、源極}48和沒極149之上。 之後，形成透明導電層，再定義透明導電層，以在畫素區 域上形成晝素電極171，晝素電極171是經由接點181與電 晶體的沒極149相接。 在如述定義保護層的步驟中，因為在電容介電層上無 上電極，故可繼續往下蝕刻以去除電容線116上之半導體 層130，只留下介電層12〇。因此在第3A圖中，儲存電容 益是由電容線116、介電層丨2〇與晝素電極ι71所構成，其 分別為儲存電容器之下電極、介電層與上電極。相較於實 施例一中，儲存電容器之介電層是由介電層和半導體層兩 者構成，在本實施例中，儲存電容器之介電層僅由介電層 11 1299573 稱成，囚此 容器整體的儲存電容量因而可以增加 因為在這個實施例之畫素區域中，_ 進一步省略掉平土曰 層，使得光通過畫素區域時，僅需經過基板和透― 不僅光所需經過的薄膜層數減少，所需經過的界面曰 少了，故可以進一步降低光在通過界面的損耗量。减 實施例三1299573 IX. Description of the Invention: [Technical Field] The present invention relates to a structure and a manufacturing method of a liquid crystal display, particularly a thin film transistor liquid crystal display array. [Prior Art] With the advancement of liquid crystal display technology and the market demand for large-sized displays, not only the size of liquid crystal displays has become larger, but also the resolution of displays has become higher and higher, so that the impedance and capacitance of wires have also increased. The increase in impedance and capacitance of the wire can make the delay of the resistor and capacitor in the display more and more serious, which not only affects the transmission of the signal in the display, but also reduces the display quality of the display. Conventionally, the method of reducing the delay of the resistor and capacitor in the display is mainly to introduce a copper crucible and increase the wire width. Although the copper process for fabricating copper wires is introduced into the liquid crystal display process, the impedance of the wires can be reduced and the conduction speed of the signals can be increased, so that the delay of the resistors and capacitors can be expected, but the copper process itself has many problems to be solved. Increasing the wire width increases the cross-sectional area of the wire and reduces the impedance of the wire, thus reducing the effects of resistor-capacitance delay. However, the wire widening affects the area of the pixel display, reducing the aperture ratio of the display and the brightness of the display. In addition, since the pixel region of the display is composed of a plurality of thin layers of different functions, the reflectance of each thin layer varies greatly, so that when light passes through the interface between the thin layer and the thin layer, part of the light is easily reflected. And reduce the penetration of light. As a result, the brightness of the display may be degraded, or the display may require 5 • 12995573 to achieve the desired brightness with a higher brightness backlight. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a liquid crystal display array substrate which can reduce the resistance-capacitance delay of its wires without affecting the aperture ratio of the display. Another object of the present invention is to provide a method of fabricating a liquid crystal display array substrate which can increase the amount of light penetrating the pixel region and enhance the brightness of the display. According to the above object of the present invention, a liquid crystal display array substrate is proposed. The array substrate includes a first wire, a second wire, a signal insulating layer, a third wire, a fourth wire, a transistor, and a halogen electrode. The first wire is on the substrate and has an intersection area. The second wires are arranged on the substrate and are vertically arranged on opposite sides of the intersection of the first wires. The signal insulating layer is located above the second wire and the intersection region, wherein the signal insulating layer on the second wire has a first opening to expose the second wire. The third wire covers the first wires on both sides of the parent fork area to be combined into one scan line. The fourth wire covers the first wire and the intersection area to be combined into a signal line, and the third wire and the fourth wire are not connected. The source of the transistor is electrically connected to the fourth wire, and the gate of the transistor is electrically connected to the first wire. The pixel electrode is electrically connected to the anode of the transistor. According to the above object of the present invention, a method of manufacturing a liquid crystal display array substrate is proposed. First, a first conductive line, a second conductive line and a gate are respectively formed on the substrate by the patterned first metal layer. The first conductive line has an intersection region 6 1299573 domain and is electrically connected to the gate, and the second conductive lines are vertically arranged respectively. Both sides of the intersection of the first wires. Thereafter, the patterned dielectric layer and the semi-body layer are sequentially formed on the first conductor, the parent fork region and the gate, wherein the dielectric layer and the semiconductor layer on the second conductor have a first opening to expose the second The wire, the dielectric layer and the semiconductor layer above the gate are used as the dielectric layer and the channel layer, respectively. Then, the patterned second metal layer is respectively formed on the substrate to cover the first wires on both sides of the intersection region to form a scan line, and the fourth wire is formed to cover the second wire and the intersection region. The semiconductor layer is formed into a signal line, and a source and a drain are formed on both sides of the channel layer to form a thin film transistor, wherein the third wire is not connected to the fourth wire. Thereafter, a patterned protective layer is formed overlying the thin film transistor, the scan lines, and the signal lines. Finally, a halogen electrode is formed on the substrate, and the halogen electrode is electrically connected to the thin film transistor. It can be seen from the above that in the structure of the thin film transistor liquid crystal display array substrate of the present invention, since the thickness of the scanning line and the signal line is increased, the cross-sectional area is increased, and the impedance is lowered, so that the resistance-capacitance delay can be improved. The impact of quality. Moreover, since the area occupied by the scan lines and the signal lines on the substrate remains the same, it does not affect the size of the pixel area. In addition, since there is no dielectric layer on the halogen region, the number of layers that light needs to pass is reduced, so that the transmittance of the halogen region is increased to increase the brightness of the display. The embodiments of the present invention will be apparent from the following description of the preferred embodiments of the present invention. Modifications do not depart from the spirit and scope of the invention. Embodiment 1 Please refer to FIG. 1A and FIG. 2A simultaneously. FIG. 1A is a cross-sectional structural diagram of the AA tangent line of the signal line, the BB tangent line of the scan line, the cc tangent line of the capacitor line, and the DD tangent line of the gate in FIG. 2A. First, a first metal layer is formed on a transparent substrate (not shown), and then a first metal layer is defined to form a first scan line 112, a first signal line 114, a capacitance line 116, and a gate 118. In Fig. 2A, the first scan line 112 and the capacitance line 116 are parallel to each other, and the first scan line 112 and the capacitance line 116 have a plurality of intersecting regions 119, respectively. The first signal line 114 is perpendicular to the first scan line 112 and the capacitor line 116, and the first signal line 丨 14 is intermittently arranged on both sides of the parent scan area 119 of the first scan line 丨丨2 and the capacitor line 116, not intersecting Area 119 is connected. The area defined by the first scan line 112 and the first signal line 114 is a pixel area on the substrate. Referring to FIG. 1B, a dielectric layer 12A and a semiconductor layer 130 are sequentially formed on the first scanning line ι12, the first signal line 114, the capacitance line 116, and the gate 118. In a preferred embodiment, the semiconductor layer 13 is composed of an amorphous germanium layer and a germanium-doped amorphous germanium layer thereon. The same applies to the first and second drawings, and the second is a plan view of the first. In the ic diagram and the second diagram, the semiconductor layer 13A and the dielectric layer 120' are defined to form a signal insulating layer 134 on the first signal line U4 and the intersection region η9, respectively, and a capacitor dielectric layer is formed on the capacitor line 116. 136, a channel layer 138 is formed on the 1929573 gate 118. The signal insulating layer 134 at the central portion of the first signal line 114 has an opening 139 to expose the first signal line 114. Moreover, the signal insulating layer 134 and the capacitor dielectric layer 136 are each independently non-contiguous. The dielectric layer and the semiconductor layer above the 'different region defined by the first scanning line 丨丨2 and the first signal line 丨14' are all removed to reduce the passage of light through the pixel region. The number of layers of the film increases the light transmittance of the halogen region. Referring to both the 1D and 2C drawings, the 2C is a top view of the id diagram after forming a second metal layer on the semiconductor layer and the dielectric layer. A second metal layer is then formed to form a second scan line 142 on the exposed first scan line 112, and a second signal line 144 is formed on the signal insulating layer 134* and the opening I39. An upper electrode 146 is formed on the layer 136, a source 148 and a drain 149 are formed on both sides of the channel layer 138, and a connection line 147 is formed to connect the upper electrode 146 and the drain 149. The second scan line 142 and the first scan line Π2 are in direct contact with each other to form a scan line having a two-layer metal structure. The second signal line 144 and the first signal line 114 are in direct contact at the opening 139, and a signal line having a double-layer metal structure is also formed. The signal insulating layer 134 on the intersection region 119 is used to insulate the second signal line 144 from the first scan line 112 and the capacitance line ^ U6, respectively. The gate 118, the source 148 and the drain 149 described above constitute the three electrodes of the transistor. The capacitor line 116, the capacitor dielectric layer 136, and the upper electrode 146 described above constitute a complete storage capacitor. Finally, please refer to both the 1E and 2D drawings, and the 2D is a top view of the 9 1299573 1E. In FIGS. 1E and 2D, a protective layer 150 is deposited first, and then the protective layer 15 is removed to remove the protective layer located in the pixel region and the upper electrode 146, and is covered on the second scan line 142. The second signal line 144, the source 148 and the drain 149 are disposed to protect the wires and the electrodes from being oxidized. ^ Next, a flat layer 160 is formed on the substrate, and a flat layer 16A is defined to expose the upper electrode 146. Finally, a transparent conductive layer is formed, and a transparent conductive layer is further defined to form a pixel electrode 17 connected to the upper electrode 146 on the pixel region. Here, the electrode is connected to the gate 149 through the upper electrode 146. The pixel electrodes (7) are independent of each other. In the liquid crystal display array substrate of the present invention, the scanning line and the signal (4) are composed of two metal layers. In the foregoing, the scan line is composed of a first scan line and a second scan line, and the signal line is composed of a first signal line and a second signal line. Thus, the thickness of the scanning line and the signal line is increased, the cross-sectional area is increased, and the impedance is lowered, so that the influence of the resistance-integration delay on the pixel quality can be improved. In addition, since the area occupied by the scan lines and the signal lines on the substrate remains the same, it does not affect the size of each pixel. In addition, when the original light passes through the pixel region, it needs to pass through the substrate, the dielectric f, the flat layer, and the transparent conductive. Because of the different refractive indices between the layers, some of the light is lost due to refraction and/or reflection as it passes through the interface. In this embodiment, the dielectric layer having the largest refractive index is removed, and not only the refractive index difference between the layers is reduced, but also the reflectance between the light passing interfaces is reduced. The number of layers that have been used has been reduced from five to three, and the number of interfaces to be passed has been reduced from four to 1,295,573 to two, so that the probability of light reflection at the interface is greatly reduced. The loss of light through the pixel region is reduced. Therefore, the brightness of the final display product is expected to be significantly improved. Embodiment 2 In the second embodiment, the flat layer of the first embodiment is omitted, so that some phases of the liquid crystal display array substrate are also made. Corresponding adjustments. In the second embodiment, in addition to the formation of the second metal layer, the process steps and embodiments from the deposition of the first metal layer to the deposition of the protective layer are performed without forming an upper electrode on the capacitor dielectric layer. The process steps are the same, so I won't comment here. Please refer to Figures 3A and 3B at the same time, and Figure 3B is a top view of Figure 3A. After depositing the protective layer, define the protective layer 15G to cover the The second scan line 142, the first signal line 144, the source terminal 48 and the gate 149 are formed. Thereafter, a transparent conductive layer is formed, and a transparent conductive layer is defined to form a halogen electrode 171 on the pixel region. Electrode 171 is The contact 181 is connected to the transistor 149. In the step of defining the protective layer as described above, since there is no upper electrode on the capacitor dielectric layer, the etching can be continued downward to remove the semiconductor layer 130 on the capacitor line 116. Only the dielectric layer 12〇 is left. Therefore, in FIG. 3A, the storage capacitor is composed of a capacitor line 116, a dielectric layer 丨2〇 and a halogen electrode ι71, which are respectively the lower electrodes of the storage capacitor and the dielectric layer. In the first embodiment, the dielectric layer of the storage capacitor is composed of both a dielectric layer and a semiconductor layer. In this embodiment, the dielectric layer of the storage capacitor is only composed of the dielectric layer 11. 1299573 It is said that the storage capacity of the whole container can be increased because in the pixel area of this embodiment, _ further omits the flat layer of soil, so that when the light passes through the pixel area, it only needs to pass through the substrate and through - Not only the number of thin layers that the light needs to pass is reduced, but also the required interface is reduced, so that the amount of light lost through the interface can be further reduced.
因為透明導電層本身有導體的性質，故實施例二中之 第二金屬層與透明導電層，可以僅由透明導電層來代替 之。因此，在實施例三中，除了省略平坦層之外，還省略 了弟-金屬層。在這個實施例中，透明導電層除了可做為 畫素電極之外，還兼做為導線。因為，省略了平括層和第 二金屬層，故製程所需的光罩數可減少，製程的成本也可 望降低。在實施例三中’從第一金屬層的沈積至定義半導 體層和介電層的製程步驟與實施例—的製程步驟相同，故 在此不再贊述。 請同時參考第4A圖與第4B圖，第4B圖為第4A圖的 俯視圖。。在沉積一層透明導電層之後，定義透明導電層， 以在第一知描線112上形成第二掃描線M2,在第一訊號線 114上形成第二訊號線144，在通道層…兩側形成源極w ♦汲極149’以及在晝素區域形成畫素電極i7i。其中，位 於電容介電層136上之畫素電極m可兼做為儲存電容器 之上電極。 12 1299573 之後，沉積一層保護層，再定義保護層丨5〇，使其覆蓋 在弟一知描線142、第二訊號線144、源極148和汲極149 之上，以保護上述之導線與電極。 由上述本發明較佳實施例可知，應用本發明具有下列 優點。 (1) 可降低知描線和訊號線的阻抗，以降低電阻電容 延遲對畫素品質的影響。 (2) 可增加晝素區域的透光率，以增加顯示器的亮 度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 ^為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之詳細說明如下： 第1A-1E圖係繪示依照本發明一較佳實施例液晶顯示 器陣列基板的製造流程剖面示意圖。 抑第2Α-2Γ)圖係繪不依照本發明一較佳實施例液晶顯示 器陣列基板的製造流程俯視示意圖。 第圖係繪不依照本發明另一較佳實施例液晶顯示 器陣列基板的製造流程剖面示意圖。 第3Β目係、縿不依照本發明另一較佳實施例液晶顯示 13 1299573 器陣列基板的掃描線俯視示意圖。 第4A圖係繪示依照本發明又一較佳實施例液晶顯示 器陣列基板的製造流程剖面示意圖。 第4B圖係繪示依照本發明又一較佳實施例液晶顯示 器陣列基板的掃描線俯視示意圖。 【主要元件符號說明】 112 :第一掃描線 114 :第一訊號線 116 :電容線 118 :閘極 Π9 :交叉區域 120 :介電層 130 :半導體層 13 4 ·成就絕緣層 136 :電容介電層 138 :通道層 139 :開口 142 :第二掃描線 144 :第二訊號線 146 :電容之上電極 147 :連接線 148 :源極 149 :汲極 1299573 150 :保護層 16 0 :平坦層 171 :畫素電極 181 :接點Since the transparent conductive layer itself has the property of a conductor, the second metal layer and the transparent conductive layer in the second embodiment can be replaced only by the transparent conductive layer. Therefore, in the third embodiment, the brother-metal layer is omitted except that the flat layer is omitted. In this embodiment, the transparent conductive layer serves as a wire in addition to the pixel electrode. Since the flat layer and the second metal layer are omitted, the number of masks required for the process can be reduced, and the cost of the process can be expected to be lowered. In the third embodiment, the process from the deposition of the first metal layer to the process of defining the semiconductor layer and the dielectric layer is the same as that of the embodiment, and therefore will not be described here. Please refer to FIG. 4A and FIG. 4B at the same time, and FIG. 4B is a plan view of FIG. 4A. . After depositing a transparent conductive layer, a transparent conductive layer is defined to form a second scan line M2 on the first trace 112, a second signal line 144 on the first signal line 114, and a source on both sides of the channel layer. The pole w ♦ the drain 149' and the pixel electrode i7i are formed in the halogen region. The pixel electrode m on the capacitor dielectric layer 136 can also serve as the upper electrode of the storage capacitor. 12 1299573, after depositing a protective layer, and then defining a protective layer 丨5〇, covering the line 142, the second signal line 144, the source 148 and the drain 149 to protect the above-mentioned wires and electrodes . It will be apparent from the above-described preferred embodiments of the present invention that the application of the present invention has the following advantages. (1) The impedance of the sense line and the signal line can be reduced to reduce the influence of the resistance and capacitance delay on the pixel quality. (2) Increase the light transmittance of the halogen region to increase the brightness of the display. While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. A schematic cross-sectional view showing a manufacturing process of a liquid crystal display array substrate. 2 is a schematic plan view showing a manufacturing process of a liquid crystal display array substrate according to a preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing the manufacturing process of a liquid crystal display array substrate in accordance with another preferred embodiment of the present invention. The third item is a schematic view of a scanning line of a liquid crystal display 13 according to another preferred embodiment of the present invention. Figure 4A is a cross-sectional view showing the manufacturing process of a liquid crystal display array substrate in accordance with still another preferred embodiment of the present invention. 4B is a top plan view showing a scanning line of a liquid crystal display array substrate according to still another preferred embodiment of the present invention. [Main component symbol description] 112: First scan line 114: First signal line 116: Capacitor line 118: Gate Π 9: Intersection region 120: Dielectric layer 130: Semiconductor layer 13 4 • Achievement insulating layer 136: Capacitance dielectric Layer 138: channel layer 139: opening 142: second scan line 144: second signal line 146: capacitor upper electrode 147: connection line 148: source 149: drain 1299573 150: protective layer 16 0 : flat layer 171: Pixel electrode 181: contact