CN100419559C - Liquid crystal display array substrate and mfg. method thereof - Google Patents
Liquid crystal display array substrate and mfg. method thereof Download PDFInfo
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- CN100419559C CN100419559C CNB2006101528640A CN200610152864A CN100419559C CN 100419559 C CN100419559 C CN 100419559C CN B2006101528640 A CNB2006101528640 A CN B2006101528640A CN 200610152864 A CN200610152864 A CN 200610152864A CN 100419559 C CN100419559 C CN 100419559C
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Abstract
The invention discloses liquid crystal display array base plate and its manufacturing method. Its scanning line and signal line are formed by double conducting layers to reduce capacitance resistance delay. In addition, the pixel area marked off by the scanning line and signal line is removed dielectric layer, even the flat layer to increase its light transmittance.
Description
Technical field
The present invention relates to a kind of LCD, particularly relate to a kind of structure and manufacture method of thin-film transistor liquid crystal display array.
Background technology
Along with the progress of LCD Technology and the market demand to large-sized monitor, not only the size of LCD is increasing, and exploration on display resolution ratio is also more and more higher, makes the impedance of lead and electric capacity also and then improve.The impedance of lead and the raising of electric capacity can make the problem that resistance capacitance postpones in the display more and more serious, except having influence on the transmission of signal in the display, have also reduced the display quality of display.
The method that resistance capacitance postpones in the known reduction display is mainly and imports copper processing and increase lead live width.Though make to import the copper processing procedure of making copper conductor in the flow process in LCD, increase the conduction of velocity of signal can reduce the impedance of lead, postpone thereby can reduce resistance capacitance, but that the copper processing procedure itself has many problems to have is to be solved.Increase the lead live width because can increase the sectional area of lead, reduce the impedance of lead, so can reduce the influence that resistance capacitance postpones.The area that pixel shows be can have influence on but lead is widened, the aperture opening ratio of display and the brightness of display reduced.
In addition, because the pixel region of display is made up of the thin layer of a plurality of difference in functionalitys, the difference in reflectivity of each thin layer is very big, reduces the penetration of light so that light by the interface between thin layer and thin layer the time, causes the light of part to reflect easily.Thus, can make display brightness descend, or display need just can reach the brightness of wanting with the backlight of higher brightness.
Summary of the invention
The object of the present invention is to provide a kind of LCD (Liquid Crystal Display) array substrate, the resistance capacitance that can reduce its lead postpones, and can not have influence on the aperture opening ratio of display.
Another object of the present invention is to provide a kind of manufacture method of LCD (Liquid Crystal Display) array substrate, can increase the light quantity that penetrates pixel region, promote the brightness of display.
To achieve these goals, the invention provides a kind of LCD (Liquid Crystal Display) array substrate.This array base palte comprises first lead, second lead, signal isolation layer, privates, privates, transistor and pixel electrode.First lead is positioned on the substrate and has the intersection region.Second lead is vertically arranged in the both sides of the intersection region of first lead respectively on substrate.The signal isolation layer is positioned on second lead and the intersection region, and the signal isolation layer that wherein is positioned on second lead has first opening, to expose second lead.Privates, first lead that covers the both sides, intersection region is to be combined into the one scan line.Privates cover second lead and intersection region to be combined into a signal wire, and privates and privates do not join.Transistorized source electrode and privates are electrical connected, and the transistorized grid and first lead are electrical connected.Pixel electrode and transistor drain are electrically connected.
To achieve these goals, the invention provides a kind of manufacture method of LCD (Liquid Crystal Display) array substrate.At first, form first lead, second lead and grid respectively with the first metal layer of patterning on substrate, first lead has the intersection region and is electrical connected with grid, and second lead is vertically arranged in the both sides of the intersection region of first lead respectively.Afterwards, form the dielectric layer of patterning and semiconductor layer in regular turn in second lead, intersection region and grid top, the dielectric layer and the semiconductor layer that wherein are positioned on second lead have first opening to expose second lead, are positioned at the dielectric layer of grid top and semiconductor layer respectively as dielectric layer and channel layer.Afterwards, with second metal level of patterning on substrate, form respectively privates cover be positioned at the both sides, intersection region first lead to form sweep trace, form privates and cover the semiconductor layer that is positioned on second lead and the intersection region with the formation signal wire, and form source electrode and the both sides on channel layer of draining to form thin film transistor (TFT), wherein privates and privates do not join.Afterwards, forming patterned protective layer is covered on thin film transistor (TFT), sweep trace and the signal wire.At last, form pixel electrode in the substrate top, pixel electrode and thin film transistor (TFT) are electrically connected.
From the above, in the structure of thin-film transistor LCD device array substrate of the present invention, because the thickness of sweep trace and signal wire has increased, it is big that sectional area becomes, and impedance thereby reduced is so can improve the influence of resistance capacitance delay to the pixel quality.And, because sweep trace is still the same with the area that signal wire occupies on substrate, so can not influence the size of elemental area.In addition, because there is not dielectric layer on the pixel region,, make the transmittance of pixel region increase, to increase the brightness of display so the required number of plies of passing through of light reduces.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Figure 1A to Fig. 1 E is the manufacturing process diagrammatic cross-section according to a preferred embodiment of the present invention LCD (Liquid Crystal Display) array substrate;
Fig. 2 A to Fig. 2 D is the manufacturing process schematic top plan view according to a preferred embodiment of the present invention LCD (Liquid Crystal Display) array substrate;
Fig. 3 A is the manufacturing process diagrammatic cross-section according to another preferred embodiment LCD (Liquid Crystal Display) array substrate of the present invention;
Fig. 3 B is the sweep trace schematic top plan view according to another preferred embodiment LCD (Liquid Crystal Display) array substrate of the present invention;
Fig. 4 A is the manufacturing process diagrammatic cross-section according to the another preferred embodiment LCD (Liquid Crystal Display) array substrate of the present invention;
Fig. 4 B is the sweep trace schematic top plan view according to the another preferred embodiment LCD (Liquid Crystal Display) array substrate of the present invention.
Wherein, Reference numeral:
112 first sweep traces
114 first signal wires
116 electric capacity lines
118 grids
119 intersection regions
120 dielectric layers
130 semiconductor layers
134 signal isolation layers
136 capacitance dielectric layers
138 channel layers
139 openings
142 second sweep traces
144 secondary signal lines
The top electrode of 146 electric capacity
147 connecting lines
148 source electrodes
149 drain electrodes
150 protective seams
160 flatness layers
171 pixel electrodes
181 contacts
Embodiment
Embodiment one, please also refer to Figure 1A and Fig. 2 A, and Figure 1A is the cross-sectional view of the DD tangent line of the CC tangent line of BB tangent line, electric capacity line of AA tangent line, the sweep trace of signal wire among Fig. 2 A and grid.At first, on the transparency carrier (not shown), form the first metal layer, define the first metal layer then to form first sweep trace 112, first signal wire 114, electric capacity line 116 and grid 118.In Fig. 2 A, first sweep trace 112 is parallel to each other with electric capacity line 116, and first sweep trace 112 has several intersection regions 119 respectively with electric capacity line 116.First signal wire 114 is perpendicular to first sweep trace 112 and electric capacity line 116, and first signal wire 114 is interrupted the both sides of the intersection region 119 that is arranged in first sweep trace 112 and electric capacity line 116, do not join with intersection region 119.The zone that first sweep trace 112 and first signal wire 114 are defined is the pixel region on the substrate.
Please refer to Figure 1B, on first sweep trace 112, first signal wire 114, electric capacity line 116 and grid 118, form one dielectric layer 120 and one semiconductor layer 130 in regular turn.In preferred embodiment, semiconductor layer 130 is made of jointly amorphous silicon layer and position N type doped amorphous silicon layer thereon.
Please also refer to Fig. 1 C and Fig. 2 B, Fig. 2 B is the vertical view of Fig. 1 C.In Fig. 1 C and Fig. 2 B, definition semiconductor layer 130 and dielectric layer 120 to form signal isolation layer 134 respectively on first signal wire 114 and intersection region 119, form capacitance dielectric layer 136 on electric capacity line 116, form channel layer 138 on grid 118.Signal isolation layer 134 at the middle body of first signal wire 114 has opening 139, to expose first signal wire 114.And signal isolation layer 134 and capacitance dielectric layer 136 are independent does not separately join.At this, dielectric layer and semiconductor layer on the pixel region that is defined by first sweep trace 112 and first signal wire 114 are removed entirely, to reduce the film number of plies of light by the required process of pixel region, allow the transmittance of pixel region increase.
Please also refer to Fig. 1 D and Fig. 2 C, Fig. 2 C is the vertical view of Fig. 1 D.After having defined semiconductor layer and dielectric layer, form one deck second metal level thereon.Define second metal level then, on first sweep trace 112 that exposes, to form second sweep trace 142 respectively, forming secondary signal line 144 on the signal isolation layer 134 and among the opening 139, on capacitance dielectric layer 136, form top electrode 146, form source electrode 148 and drain electrode 149 in the both sides of channel layer 138 respectively, and form connecting line 147 in order to the utmost point 146 and the drain electrode 149 of Connecting Power.
The second above-mentioned sweep trace 142 directly contacts with first sweep trace 112, has formed the sweep trace with double-level-metal structure.And secondary signal line 144 directly contacts at opening 139 places with first signal wire 114, also forms the signal wire with double-level-metal structure.Signal isolation layer 134 on intersection region 119 be used for making secondary signal line 144 respectively with first sweep trace 112 and electric capacity line 116 mutual insulatings.Three electrodes of above-mentioned grid 118, source electrode 148 and 149 transistor formeds that drain.Above-mentioned electric capacity line 116, capacitance dielectric layer 136, top electrode 146 threes constitute complete reservior capacitor.
At last, please also refer to Fig. 1 E and Fig. 2 D, Fig. 2 D is the vertical view of Fig. 1 E.In Fig. 1 E and Fig. 2 D; deposit layer protective layer 150 earlier; define protective seam 150 then; to remove the protective seam that is positioned at pixel region and top electrode 146; and make it cover second sweep trace 142, secondary signal line 144, source electrode 148 and drain on 149; to protect above-mentioned lead and electrode, it is oxidized that it is difficult for.
Then, on substrate, form flatness layer 160, define flatness layer 160 again, to expose top electrode 146.
At last, form transparency conducting layer, define transparency conducting layer again, on pixel region, form the pixel electrode 171 that joins with top electrode 146.At this, pixel electrode is to join by top electrode 146 and drain electrode 149.Pixel electrode 171 does not join independently of one another.In LCD (Liquid Crystal Display) array substrate of the present invention, sweep trace and signal wire all are made of two metal layers.In the above, sweep trace is made of first sweep trace and second sweep trace, and signal wire is made of first signal wire and secondary signal line.Like this, the thickness of sweep trace and signal wire has increased, and it is big that sectional area becomes, thereby impedance has reduced, so can improve the influence of resistance capacitance delay to the pixel quality.In addition, because sweep trace is still the same with the area that signal wire occupies on substrate, so can not influence the size of each aperture ratio of pixels.
In addition, when light is through pixel region originally, need pass substrate, dielectric layer, flatness layer and transparency conducting layer.Because the refractive index difference between each layer makes light when penetrating the interface, part light can be because refraction and reflection and loss.In the present embodiment, removed the dielectric layer of refractive index maximum, not only the refractive index difference between each layer dwindles, and light has also reduced by the reflectivity between the interface.The number of plies of the required process of light is reduced to three layers by five layers, needs the interface number of process to reduce to two by four, makes light significantly reduce in the reflection probability at interface.Light has reduced by the loss of pixel region, so the brightness of final display product can obtain tangible lifting.
Embodiment two, in the present embodiment, omitted the flatness layer of embodiment one, therefore also the part-structure of LCD (Liquid Crystal Display) array substrate made some corresponding adjustment.In embodiment two, identical from the making process step of the deposition that is deposited into protective seam of the first metal layer except during second metal level, on capacitance dielectric layer, not forming outside the top electrode with the making process step of embodiment one in definition, so do not repeat them here.
Please also refer to Fig. 3 A and Fig. 3 B, 3B figure is the vertical view of 3A figure.
After the deposition protective seam, definition protective seam 150 makes it be covered in second sweep trace 142, secondary signal line 144, source electrode 148 and drains on 149.Afterwards, form transparency conducting layer, define transparency conducting layer again, to form pixel electrode 171 on pixel region, pixel electrode 171 is to join through contact 181 and transistor drain 149.
In the step of above-mentioned definition protective seam,,, only stay dielectric layer 120 so can continue down to be etched with the semiconductor layer of removing on the electric capacity line 116 130 because on capacitance dielectric layer, there is not top electrode.Therefore in Fig. 3 A, reservior capacitor is made of with pixel electrode 171 electric capacity line 116, dielectric layer 120, and it is respectively bottom electrode, dielectric layer and the top electrode of reservior capacitor.In embodiment one, the dielectric layer of reservior capacitor is to be made of dielectric layer and semiconductor layer, in the present embodiment, the dielectric layer of reservior capacitor only is made of dielectric layer, therefore, the thickness attenuation of the dielectric layer of reservior capacitor, thus the storage capacitors amount of reservior capacitor integral body can increase.
Because in the pixel region of this embodiment, further dispense flatness layer, make when light passes through pixel region, only need pass through substrate and transparency conducting layer.Not only the film number of plies of the required process of light reduces, and the interface number of required process has also reduced, so can further reduce the waste of light by the interface time.
Because itself has property of conductor transparency conducting layer, so second metal level and transparency conducting layer among the embodiment two can only be replaced by transparency conducting layer.Therefore, in embodiment three, except omitting flatness layer, also omitted second metal level.In this embodiment, transparency conducting layer is except can also holding concurrently as lead as the pixel electrode.Because omitted the flatness layer and second metal level, so the required light shield number of manufacturing process can reduce, the cost of manufacturing process also can reduce.In embodiment three, identical from the processing step that is deposited into definition semiconductor layer and dielectric layer of the first metal layer with the processing step of embodiment one, so do not repeat them here.
Please also refer to Fig. 4 A and Fig. 4 B, Fig. 4 B is the vertical view of Fig. 4 A.After deposition layer of transparent conductive layer, the definition transparency conducting layer to form second sweep trace 142 on first sweep trace 112, forms secondary signal line 144 on first signal wire 114, form source electrode 148 and drain electrode 149 in channel layer 138 both sides, and form pixel electrode 171 at pixel region.Wherein, the pixel electrode 171 that is positioned on the capacitance dielectric layer 136 can be held concurrently as the top electrode of holding capacitor.
Afterwards, the deposition layer protective layer defines protective seam 150 again, makes it cover second sweep trace 142, secondary signal line 144, source electrode 148 and drains on 149, to protect above-mentioned lead and electrode.
By the invention described above preferred embodiment as can be known, use the present invention and have following advantage:
(1) can reduce the impedance of sweep trace and signal wire, postpone influence the pixel quality to reduce resistance capacitance.
(2) can increase the transmittance of pixel region, to increase the brightness of display.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (17)
1. the manufacture method of a LCD (Liquid Crystal Display) array substrate is characterized in that, comprises:
Form a patterning the first metal layer on a substrate, to form at least one first lead, at least two second leads and at least one grid respectively, this first lead has at least one intersection region and is electrical connected with this grid, and this second lead is vertically arranged in the both sides of this intersection region of this first lead respectively;
Formation and patterning one dielectric layer and semi-conductor layer are in this second lead, this intersection region and this grid top successively, this dielectric layer and this semiconductor layer that wherein are positioned on this second lead have one first opening to expose this second lead, and this semiconductor layer that is positioned at this grid top is as channel layer;
Form a patterning second metal level on this substrate, with form respectively at least two privates cover be positioned at these both sides, intersection region this first lead to form the one scan line, form privates and cover this semiconductor layer of being positioned on this second lead and this intersection region to form a signal wire, and form one source pole at least and at least one both sides on this channel layer of draining to form at least one thin film transistor (TFT), wherein this privates and this privates do not join;
Form a patterning protective seam to be covered on this thin film transistor (TFT), this sweep trace and this signal wire; And
Form at least one pixel electrode in this substrate top, this pixel electrode and this thin film transistor (TFT) are electrically connected.
2. the manufacture method of LCD (Liquid Crystal Display) array substrate according to claim 1 is characterized in that, this semiconductor layer comprises an amorphous silicon layer and a position doped amorphous silicon layer thereon.
3. the manufacture method of LCD (Liquid Crystal Display) array substrate according to claim 1 is characterized in that, also comprises:
Form this patterning the first metal layer and also comprise a formation electric capacity line parallel with this first lead, this electric capacity line is positioned at the homonymy of this first lead with this grid and does not link to each other with this second lead;
Form this dielectric layer on this electric capacity line as a capacitance dielectric layer; And
Form this pixel electrode on this capacitance dielectric layer as a top electrode.
4. the manufacture method of LCD (Liquid Crystal Display) array substrate according to claim 1 is characterized in that, at this protective seam that forms patterning and form between this pixel electrode, also comprise form patterning a flatness layer on this substrate.
5. the manufacture method of LCD (Liquid Crystal Display) array substrate according to claim 4 is characterized in that, also comprises:
Form this patterning the first metal layer and also comprise a formation electric capacity line parallel with this first lead, this electric capacity line is positioned at the homonymy of this first lead with this grid and does not link to each other with this second lead;
Form this dielectric layer and this semiconductor layer on this electric capacity line as a capacitance dielectric layer; And
Form this patterning second metal level on this capacitance dielectric layer as a top electrode, this top electrode and this pixel electrode are electrically connected, wherein this flatness layer has one second opening to expose this top electrode.
6. the manufacture method of a LCD (Liquid Crystal Display) array substrate is characterized in that, comprises:
Form a patterning the first metal layer on a substrate, to form at least one first lead, at least two second leads and at least one grid respectively, this first lead has at least one intersection region and is electrical connected with this grid, and this second lead is vertically arranged in the both sides of this intersection region of this first lead respectively;
Formation and patterning one dielectric layer and semi-conductor layer are in this second lead, this intersection region and this grid top in regular turn, this dielectric layer and this semiconductor layer that wherein are positioned on this second lead have one first opening to expose this second lead, are positioned at the usefulness of this semiconductor layer of this grid top as channel layer;
Form a patterned transparent conductive layer on this substrate, with form respectively at least two privates cover be positioned at these both sides, intersection region this first lead to form the one scan line, form privates and cover this semiconductor layer of being positioned on those second leads and this intersection region to form a signal wire, form one source pole at least and at least one both sides on this channel layer of draining to form at least one thin film transistor (TFT), and form at least one pixel electrode between this sweep trace and this signal wire, wherein this privates and this privates do not join; And
Form a patterning protective seam to be covered on this thin film transistor (TFT), this sweep trace and this signal wire.
7. the manufacture method of LCD (Liquid Crystal Display) array substrate according to claim 6 is characterized in that, this semiconductor layer comprises an amorphous silicon layer and a position doped amorphous silicon layer thereon.
8. the manufacture method of LCD (Liquid Crystal Display) array substrate according to claim 6 is characterized in that, also comprises:
Form this first metal layer and also comprise a formation electric capacity line parallel with this first lead, this electric capacity line is positioned at the homonymy of this first lead with this grid and does not link to each other with this second lead;
Form this dielectric layer on this electric capacity line as a capacitance dielectric layer; And
As a top electrode, this top electrode and this pixel electrode are electrically connected this transparency conducting layer that forms this patterning on this capacitance dielectric layer.
9. a LCD (Liquid Crystal Display) array substrate is characterized in that, comprises:
At least one first lead is positioned on the substrate, and this first lead has at least one intersection region;
Article at least two, second lead is positioned on this substrate, and this second lead is vertically arranged in the both sides of this intersection region of this first lead respectively;
At least one signal isolation layer is positioned on this second lead and this intersection region, and this signal isolation layer that wherein is positioned on this second lead has at least one first opening, to expose this second lead;
Article at least two, privates, this first lead that covers these both sides, intersection region is to be combined into the one scan line;
At least one privates cover this signal isolation layer and this first opening to be combined into a signal wire, and this privates and this privates do not join;
At least one transistor, this transistorized one source pole and this privates are electrical connected, and this transistorized grid and this first lead are electrical connected; And
At least one pixel electrode, this pixel electrode is electrically connected with this transistorized drain electrode.
10. LCD (Liquid Crystal Display) array substrate according to claim 9 is characterized in that, also comprises:
One electric capacity line is positioned on this substrate, and is parallel with this first lead, is positioned at the homonymy of this first lead with this transistor and do not link to each other with this second lead;
One capacitance dielectric layer is positioned on this electric capacity line; And
One top electrode is positioned on this capacitance dielectric layer, is electrically connected with this transistorized this drain electrode and this pixel electrode.
11. LCD (Liquid Crystal Display) array substrate according to claim 10 is characterized in that, also comprises:
One flatness layer of patterning is positioned on privates, privates, transistor, the top electrode and covers this substrate and directly is exposed to outer part, and this flatness layer has one second opening with this top electrode of exposed portions serve.
12. LCD (Liquid Crystal Display) array substrate according to claim 10 is characterized in that, this capacitance dielectric layer comprises a dielectric layer and semi-conductor layer.
13. LCD (Liquid Crystal Display) array substrate according to claim 10 is characterized in that, this capacitance dielectric layer comprises a dielectric layer.
14. LCD (Liquid Crystal Display) array substrate according to claim 10 is characterized in that, the material of this top electrode is metal or transparent conductive material.
15. LCD (Liquid Crystal Display) array substrate according to claim 9 is characterized in that, the material of this first lead and this second lead is a metal.
16. LCD (Liquid Crystal Display) array substrate according to claim 9 is characterized in that, the material of this privates, these privates and this transistorized source electrode and drain electrode is metal or transparent conductive material.
17. LCD (Liquid Crystal Display) array substrate according to claim 9 is characterized in that, also comprises a protective seam, is positioned on this privates, these privates and this transistor.
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101236953B (en) * | 2008-04-15 | 2010-10-06 | 上海广电光电子有限公司 | Thin film transistor array base plate and its making method |
| KR101527971B1 (en) * | 2008-07-21 | 2015-06-10 | 삼성디스플레이 주식회사 | Organic light emitting display device |
| CN102809859B (en) * | 2012-08-01 | 2014-12-31 | 深圳市华星光电技术有限公司 | Liquid crystal display device, array substrate and manufacture method thereof |
| US20140036188A1 (en) * | 2012-08-01 | 2014-02-06 | Cheng-Hung Chen | Liquid Crystal Display Device, Array Substrate and Manufacturing Method Thereof |
| CN110780497A (en) * | 2019-10-22 | 2020-02-11 | 深圳市华星光电技术有限公司 | Wiring structure of display panel, wiring method of display panel and display panel |
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| JPH0954342A (en) * | 1995-08-11 | 1997-02-25 | Nec Corp | Active matrix type liquid crystal display panel and its production |
| JP2000214475A (en) * | 1999-01-21 | 2000-08-04 | Sharp Corp | Liquid crystal display device |
| US20020168788A1 (en) * | 2001-05-11 | 2002-11-14 | Mong-Yueh Wu | Method of fabricating a thin film transistor liquid crystal display |
| CN1542528A (en) * | 2003-04-29 | 2004-11-03 | 友达光电股份有限公司 | Fabrication method of thin film transistor liquid crystal display panel |
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| JPH0954342A (en) * | 1995-08-11 | 1997-02-25 | Nec Corp | Active matrix type liquid crystal display panel and its production |
| JP2000214475A (en) * | 1999-01-21 | 2000-08-04 | Sharp Corp | Liquid crystal display device |
| US20020168788A1 (en) * | 2001-05-11 | 2002-11-14 | Mong-Yueh Wu | Method of fabricating a thin film transistor liquid crystal display |
| CN1542528A (en) * | 2003-04-29 | 2004-11-03 | 友达光电股份有限公司 | Fabrication method of thin film transistor liquid crystal display panel |
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