CN1327480C - Pixel structure, film transistor and mfg. method thereof - Google Patents
Pixel structure, film transistor and mfg. method thereof Download PDFInfo
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- CN1327480C CN1327480C CNB200510002765XA CN200510002765A CN1327480C CN 1327480 C CN1327480 C CN 1327480C CN B200510002765X A CNB200510002765X A CN B200510002765XA CN 200510002765 A CN200510002765 A CN 200510002765A CN 1327480 C CN1327480 C CN 1327480C
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Abstract
The present invention relates to a method for manufacturing a pixel structure, which comprises the following steps that a base plate is provided; a color light filtering layer is formed on the base plate; a polarized light layer is covered on the color light filtering layer; subsequently, a first metal layer is formed on the polarized light layer, and the first metal layer is patterned; a source electrode and a drain electrode are defined; a trench material layer, a grid insulating layer and a second metal layer are orderly formed on the base plate for covering the source electrode and the drain electrode; the second metal layer, the grid insulating layer and the trench material layer are patterned, and a grid electrode and a channel layer can be defined; a protective layer is formed on the upper part of the base plate for covering the grid electrode; the protective layer is patterned, and a part of the drain electrode is exposed; subsequently, a transparent conducting layer is formed on the upper part of the base plate, and the transparent conducting layer is electrically connected with the exposed drain electrode; the transparent conducting layer is patterned, and a pixel electrode is formed.
Description
Technical field
The invention relates to a kind of dot structure and a kind of thin-film transistor and manufacture method thereof, and particularly thin film transistor (TFT) array is produced on (Arrayon color filter, AOC) dot structure of technology and manufacture method thereof on the colorful filter array substrate relevant for a kind of.
Background technology
General liquid crystal display panel of thin film transistor is made of thin-film transistor array base-plate, colorful filter array substrate and the liquid crystal layer that is sandwiched between the two substrates.In addition, other has a kind of manufacture method of display panels, be that thin film transistor (TFT) array is produced on (Array on colorfilter on the colorful filter array substrate, AOC), in other words, it forms after the color filter film on substrate earlier, forms thin film transistor (TFT) array again on color filter film.
Generally speaking, thin-film transistor array base-plate is made of a plurality of dot structure, and each pixel comprised a thin-film transistor and a pixel electrode (Pixel Electrode), and its manufacture method five road mask fabrication operations more commonly.The first road mask fabrication operation is to be used for defining the first metal layer, to form the members such as grid of scan wiring and thin-film transistor.The second road mask fabrication operation is channel layer and the ohmic contact layer that defines thin-film transistor.The 3rd road mask fabrication operation is to be used for defining second metal level, to form the members such as source/drain of data wiring and thin-film transistor.The 4th road mask fabrication operation is to be used for passivation layer patternization.And the 5th road mask fabrication operation is to be used for the transparency conducting layer patterning, to form pixel electrode.
Yet, along with the development trend of Thin Film Transistor-LCD, and will face many problems and challenge towards the large scale making, for example rate of finished products reduces and production capacity descends or the like.If therefore can reduce the mask number of thin-film transistor production process, promptly reduce the exposure engineering number of times that thin-film transistor component is made, just can reduce manufacturing time, increase production capacity, and then reduce manufacturing cost.
And using the technology of four road mask fabrication operations also to be suggested at present, it is the design of using semi-transparent (halftone) on mask mostly, to reduce the mask number one.But, on mask, use the mode of semi-transparent pattern but to have some problems, for example the mask layout design difficulty improves and whether the photoresist selectivity is enough or the like.And, the common technology of on mask, using semi-transparent pattern, the uniformity of the photoresist pattern after exposure often is unfavorable.
Summary of the invention
Therefore purpose of the present invention just provides a kind of one pixel structure process method, the method is that thin film transistor (TFT) array is produced on technology on the colorful filter array substrate, and only need use four road masks and do not need to use the technology of semi-transparent pattern (halftone) on mask.
Purpose of the present invention just provides a kind of dot structure, utilize the made dot structure of four road mask fabrication operations, and the thin-film transistor in this dot structure is produced on the chromatic filter layer.
Purpose of the present invention just provides a kind of method of manufacturing thin film transistor, and this manufacture method is different from existing method for fabricating thin film transistor.
Purpose of the present invention just provides a kind of thin-film transistor, and the structure of this thin-film transistor is different from existing thin-film transistor.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of one pixel structure process method, and the method at first provides a substrate, and has been formed with a chromatic filter layer on this substrate, and is coated with a polarizing layer (polarizing layer) on this chromatic filter layer.Then on polarizing layer, form a first metal layer, and carry out the first road mask fabrication operation,, and define an one source pole and a drain electrode with the patterning the first metal layer.Then, above substrate, form a raceway groove material layers, a gate insulation layer and one second metal level in regular turn, to cover source electrode and drain electrode, and carry out one second road mask fabrication operation, with patterning second metal level, gate insulation layer and raceway groove material layers, and define a grid and a channel layer.Subsequently, above substrate, form a passivation layer,, and carry out one the 3rd road mask fabrication operation,, and the part drain electrode is come out with patterned passivation layer with cover gate.Then form a transparency conducting layer above substrate, this transparency conducting layer is electrically connected with the drain electrode that exposes.Afterwards, transparency conducting layer is carried out one the 4th road mask fabrication operation, to define a pixel electrode.
The present invention proposes a kind of dot structure again, and it comprises a chromatic filter layer, a polarizing layer, a thin-film transistor, a passivation layer and a pixel electrode.Wherein, chromatic filter layer is configured on the substrate, and polarizing layer covers on the chromatic filter layer.Above-mentioned thin-film transistor is configured on the polarizing layer, and this thin-film transistor by an one source pole and a drain electrode, be covered in a channel layer in source electrode and the drain electrode, be disposed at the gate insulation layer on the channel layer and the grid that is disposed on the gate insulation layer is constituted, and above-mentioned passivation layer covers on the thin-film transistor, and the part drain electrode is come out.Pixel electrode is disposed on the polarizing layer, and pixel electrode is electrically connected with the drain electrode that exposes.
The present invention proposes a kind of method of manufacturing thin film transistor in addition, and the method at first provides a substrate, then forms a first metal layer on substrate, and the patterning the first metal layer, to define an one source pole and a drain electrode.Afterwards, above substrate, form a raceway groove material layers, a gate insulation layer and one second metal level in regular turn, with covering source electrode and drain electrode, and patterning second metal level, gate insulation layer and raceway groove material layers, to define a grid and a channel layer.
The present invention reintroduces a kind of thin-film transistor, and this thin-film transistor comprises one source pole and a drain electrode, a channel layer, a gate insulation layer and a grid, and wherein source electrode and drain configuration are on a substrate, and channel layer covers source electrode and drain electrode.In addition, gate insulation layer is disposed on the channel layer.In addition, gate configuration is on gate insulation layer.
AOC technology of the present invention is different from prior art, and its practice is that thin-film transistor is produced on the chromatic filter layer.In addition, the present invention only need carry out the making that four road mask fabrication operations promptly can be finished dot structure, and its more traditional five road mask fabrication operations can reduce the mask number one, therefore has the advantage that increases production capacity and reduce cost.In addition, on mask, do not use the technology of semi-transparent pattern (halftone) in the four road mask fabrication operations of the present invention, therefore do not have the problem of mask layout design and photoresist selectivity aspect, nor have the uneven problem of exposure back pattern.
The structure and the manufacture method thereof of thin-film transistor of the present invention are different from prior art, with grid in formed order of thin-film transistor and position thereof, the grid of existing thin-film transistor be define out in the first road mask fabrication operation and its source electrode and drain electrode be positioned at grid and channel layer above, and the grid of thin-film transistor of the present invention is in the second road mask fabrication operation to define out and source electrode and draining be formed at grid and channel layer below.
Description of drawings
Fig. 1 is the schematic top plan view according to a kind of dot structure of the first embodiment of the present invention;
Fig. 2 is the schematic top plan view according to the another kind of dot structure of the Thin Film Transistor-LCD of the first embodiment of the present invention;
Fig. 3 is the schematic top plan view according to a kind of dot structure of the second embodiment of the present invention;
Fig. 4 A to Fig. 4 I is the manufacturing process generalized section according to the first embodiment of the invention dot structure;
Fig. 5 A to Fig. 5 I is the manufacturing process generalized section according to the second embodiment of the invention dot structure.
Symbol description:
Second weld pad, 116 polarizing layers 120
Ohmic contact material layers 140,140a data wiring 150
Raceway groove material layers 160 channel layer 160a
Passivation layer 180,180a transparency conducting layer 182,182a
Thin-film transistor T pixel electrode P
Reservior capacitor C weld pad B, B '
Embodiment
One pixel structure process method proposed by the invention need not used semi-transparent pattern (halftone) technology fully on mask, promptly can finish the making of dot structure with four road masks.And, owing to be formed with chromatic filter layer on the substrate, thus with the made substrate of four road masks with a plurality of dot structures can be directly and another substrate arrange in pairs or groups, to constitute a liquid crystal display panel of thin film transistor.Below be illustrated as the present invention's preferred embodiment, but be not in order to limit the present invention.
First embodiment of four road mask fabrication operations:
Fig. 1 is the schematic top plan view according to a kind of dot structure of first embodiment of the invention, and Fig. 4 A to Fig. 4 I is the manufacturing process generalized section according to the first embodiment of the invention dot structure.
With reference to Fig. 1 and Fig. 4 A, one substrate 100 at first is provided, and zone, the preboarding that can include the predetermined thin-film transistor T of formation (thin film transistor) on this substrate 100 becomes zone and the predetermined zone that forms weld pad B, B ' (bonding pad) of the zone of pixel electrode P (pixel electrode), the predetermined reservior capacitor C of formation (storage capacitor).In a preferred embodiment, substrate 100 can be transparent glass substrate or transparent plastic substrate, and has been formed with a chromatic filter layer 110 on this substrate 100, and is coated with a polarizing layer 120 on the chromatic filter layer 110.What deserves to be mentioned is that the method that forms chromatic filter layer 110 on substrate 100 can comprise and form a black matrix 112, its material comprises black resin, metal or is made of red, green, blue look filter pattern storehouse.Form a plurality of color filter patterns 113 afterwards in black matrix 112, it can be red filter pattern, green filter pattern and blue filter pattern.Then, shown in Fig. 4 B, on polarizing layer 120, form a first metal layer 130.In a preferred embodiment, after forming the first metal layer 130, also be included in and form an ohmic contact material layers 140 on the first metal layer 130.
Above-mentioned the first metal layer 130 can be a single-layer metal layer or multiple layer metal layer structure, if the first metal layer 130 is single-layer metal layers, then its material can be selected from chromium (Cr) layer, tungsten (W) layer, tantalum (Ta) layer, titanium (Ti) layer, molybdenum (Mo) layer, aluminium (Al) layer with and alloy-layer.If the first metal layer 130 is multiple layer metal layer structure, it can be Al/Cr/Al three-decker, Mo/Al/Mo three-decker or Cr/Al double-layer structure or the like combination.And above-mentioned ohmic contact material layers 140 can be a doped amorphous silicon.
Referring again to Fig. 4 B, and then, carry out the first road mask fabrication operation, on ohmic contact material layers 140, to form a patterning photoresist layer 102.And, carry out an etching production process with photoresist layer 102 as an etching photomask, with patterning ohmic contact material layers 140 and the first metal layer 130, and the ohmic contact material layers 140a of patterning can have identical pattern with the first metal layer 132/134 of patterning, shown in Fig. 4 C.In a preferred embodiment, the first road mask fabrication operation defines an one source pole 132 and a drain electrode 134 predetermined formation in the thin-film transistor T zone.In addition, in the first road mask fabrication operation, also comprise and define a data wiring 150 (as shown in Figure 1) that is connected with source electrode 132.In another preferred embodiment, also be included in predetermined the formation in the weld pad B zone of substrate frontside edge in the first road mask fabrication operation and define one first weld pad 114 that is electrically connected with data wiring 150.
Please refer to Fig. 1 and Fig. 4 D, above substrate 100, form a raceway groove material layers 160, a gate insulation layer 162 and one second metal level 164 in regular turn, cover above-mentioned formed structure.In addition, the second above-mentioned metal level 164 can be a single-layer metal layer or multiple layer metal layer structure, if second metal level 164 is single-layer metal layers, then its material can be selected from chromium (Cr) layer, tungsten (W) layer, tantalum (Ta) layer, titanium (Ti) layer, molybdenum (Mo) layer, aluminium (Al) layer with and alloy-layer.If second metal level 164 is multiple layer metal layer structure, it can be Al/Cr/Al three-decker, Mo/Al/Mo three-decker or Cr/Al double-layer structure or the like combination.
In a preferred embodiment, the material of raceway groove material layers 160 can be an amorphous silicon.The material of gate insulation layer 162 can be silicon nitride, silica or silicon oxynitride.And then, carry out one second road mask fabrication operation, on second metal level 164, to form the photoresist layer 104 of a patterning, and carry out an etching production process as an etching photomask with photoresist layer 104, shown in Fig. 4 E, with patterning second metal level 164, gate insulation layer 162 and raceway groove material layers 160.In a preferred embodiment, the second road mask fabrication operation defines a grid 164a and a channel layer 160a predetermined formation in the thin-film transistor T zone.In addition, in the second road mask fabrication operation, also comprise define be electrically connected with grid 164a scan distribution 170 (as shown in Figure 1).
In another preferred embodiment, the second road mask fabrication operation also is included in predetermined formation in the storage pad container C zone and defines bottom electrode 122, and reservior capacitor C can be the reservior capacitor (Cst on gate) of grid layer top.In another preferred embodiment, another edge preboarding that the second road mask fabrication operation also is included in substrate 100 becomes to define in the weld pad B` zone and scan one second weld pad 116 that distribution 170 is electrically connected (as shown in Figure 1, section is similar to weld pad B), and in weld pad B zone, retain second metal level 164 partly.
Please refer to Fig. 1 and Fig. 4 F, deposition one passivation layer 180 covers above-mentioned formed structure above substrate 100.In a preferred embodiment, the material of passivation layer 180 can be silica, silicon nitride, silicon oxynitride or organic material.And then, carry out one the 3rd road mask fabrication operation, on passivation layer 180, to form the photoresist layer 106 of a patterning, and carry out an etching production process as an etching photomask with photoresist layer 106, with patterned passivation layer 180, and the passivation layer 180a of formation patterning, shown in Fig. 4 G.
In a preferred embodiment, the passivation layer 180a of patterning comes out part drain electrode 134.In another preferred embodiment, the 3rd road mask fabrication operation comprises that also reservation is positioned at the passivation layer 180a on the bottom electrode 122, with the usefulness as capacitance dielectric layer.In another preferred embodiment, the 3rd road mask fabrication operation also comprises first weld pad 114 and second weld pad 116 that exposes part.
Please refer to Fig. 1 and Fig. 4 H, above substrate 100, form a transparency conducting layer 182, and this transparency conducting layer 182 is electrically connected with the drain electrode 134 that exposes.In a preferred embodiment, the material of transparency conducting layer 182 can be to adopt ITO or IZO.And then, transparency conducting layer 182 is carried out one the 4th road mask fabrication operation, on transparency conducting layer 182, to form a patterning photoresist layer 108, and carry out an etching production process as an etching photomask with photoresist layer 108, with patterned transparent conductive layer 182, and the transparency conducting layer 182a of formation patterning, shown in Fig. 4 I.In a preferred embodiment, the 4th road mask fabrication operation becomes to define a pixel electrode 184 in the pixel electrode P zone in preboarding.
In another preferred embodiment, also comprise the transparency conducting layer that keeps on the passivation layer 180a be positioned at bottom electrode 122 tops in the 4th road mask fabrication operation, with as a top electrode 186.Dielectric material between above-mentioned top electrode 186, bottom electrode 122 and two electrodes (passivation layer 180a) can constitute a pixel storage capacitor device.It should be noted that above-mentioned reservior capacitor C does not limit to the reservior capacitor that is positioned at the grid layer top, it also can be formed in the reservior capacitor (Cst on common) (as shown in Figure 2) of common lines top.
In another preferred embodiment, also comprise in the 4th road mask fabrication operation keeping the transparency conducting layer 182a be positioned at above first weld pad 114 and second weld pad 116.For forming weld pad B zone, this transparency conducting layer 182a makes first weld pad 114 be electrically connected with second metal level 164 that is formed at first weld pad, 114 tops.Same, for forming weld pad B ' zone, this transparency conducting layer makes second weld pad be electrically connected (not showing) with the first metal layer that is formed at second weld pad below.
Describe dot structure with reference to Fig. 1 and Fig. 4 I, comprise a chromatic filter layer 110, a polarizing layer 120, a thin-film transistor T, a passivation layer 180a and a pixel electrode P by the above-mentioned four road formed dot structures of mask fabrication operation.Wherein, chromatic filter layer 110 is configured on the substrate 100, and polarizing layer 120 covers on the chromatic filter layer 110.Wherein, chromatic filter layer 110 can comprise a black matrix 112 and be disposed at a plurality of color filter patterns 113 of deceiving in the matrix 112 that it can be red filter pattern, a plurality of green filter pattern and a plurality of blue filter pattern.
Above-mentioned thin-film transistor T is configured on the polarizing layer 120, and this thin-film transistor T by an one source pole 132 and a drain electrode 134, be covered in a channel layer 160a in source electrode 132 and the drain electrode 134, be disposed at the gate insulation layer 162 on the channel layer 160a and the grid 164a that is disposed on the gate insulation layer 162 is constituted.In addition, the material of above-mentioned channel layer 160a can comprise amorphous silicon.
In another preferred embodiment, dot structure of the present invention also comprises an ohmic contact layer 140a, and it is disposed between source electrode 132/ drain electrode 134 and the channel layer 160a.In addition, passivation layer 180a cover film transistor T, and part drain electrode 134 is come out.In addition, pixel electrode P is disposed on the polarizing layer 120, and pixel electrode P is electrically connected with the drain electrode 134 that exposes.
In a preferred embodiment, dot structure of the present invention also comprises a reservior capacitor C, it is disposed at polarizing layer 120 tops, and this reservior capacitor C is made of a bottom electrode 122, a top electrode 186 (transparency conducting layer) and a capacitance dielectric layer (passivation layer 180a), and top electrode 186 is electrically connected with pixel electrode P.
In a preferred embodiment, dot structure of the present invention also comprises first weld pad 114 and one second weld pad 116, and it is configured in two edges of substrate 100, and first weld pad 114 is electrically connected with data wiring 150.In a preferred embodiment, this first weld pad 114 more is electrically connected with second metal level 164 that is positioned at the weld pad area B by a transparency conducting layer 182a.In addition, second weld pad 116 with scan distribution 170 and be electrically connected.In a preferred embodiment, this second weld pad more by a transparency conducting layer be positioned at the weld pad area B ' the first metal layer be electrically connected (not showing).
Second embodiment of four road mask fabrication operations:
Fig. 3 is the schematic top plan view according to a kind of dot structure of second embodiment of the invention, and Fig. 5 A to Fig. 5 I is the manufacturing process generalized section according to the second embodiment of the invention dot structure.It should be noted that therefore second embodiment only explains at part inequality because the manufacturing process of the second embodiment dot structure is similar to above-mentioned first embodiment.
At first, carry out the step of Fig. 5 A, its step with Fig. 4 A is identical.Afterwards, please refer to Fig. 5 B, carry out the first road mask fabrication operation, on ohmic contact material layers 140, to form the photoresist layer 102 of a patterning.Then, with photoresist layer 102 is that the etching photomask carries out an etching production process, to define source electrode 132 and drain electrode 134, shown in Fig. 3 and Fig. 5 C, and in the first road mask fabrication operation, also be included in preboarding and become to define a bottom electrode 122 in the pixel electrode P zone.In another preferred embodiment, define one first weld pad 114 that is electrically connected with data wiring 150 predetermined the formation in the weld pad B zone of substrate frontside edge in the first road mask fabrication operation.
Then, carry out Fig. 5 D to Fig. 5 E step, it is similar to Fig. 4 D to Fig. 4 E step, in this step, except defining grid 164a and channel layer 162, also comprise and keep the gate insulation layer 162 that is positioned at bottom electrode 122 tops, the raceway groove material layers 160 and the second metal level 164a, gate insulation layer 162 that wherein remains and raceway groove material layers 160 are as a capacitance dielectric layer, and the second metal level 164a that remains is a common lines, it is as the top electrode 186 of reservior capacitor C, so reservior capacitor C can be formed in the reservior capacitor (Cs on common) of common lines top.Can constitute a pixel storage capacitor device by bottom electrode 122, top electrode 186 and capacitance dielectric layer.In another preferred embodiment, this step also comprises and defines second weld pad 116.
Then, carry out Fig. 5 F to Fig. 5 I, it is similar to Fig. 4 F to Fig. 4 I step, comprises deposit passivation layer and patterned passivation layer, deposit transparent conductive layer and patterned transparent conductive layer.Special one carry be, the pixel electrode 184 that is defined after the patterned transparent conductive layer can be passivated the bottom electrode 122 that layer 180a expose and be electrically connected.
Similar with the dot structure that the production process of second embodiment is produced to above-mentioned first embodiment, difference is that reservior capacitor C is a kind of capacitor (Cst oncommon) that is formed on the common lines top, and reservior capacitor C is made of a bottom electrode 122, a top electrode 186 (common lines) and a capacitance dielectric layer (gate insulation layer 162 and raceway groove material layers 160), and bottom electrode 122 is electrically connected with pixel electrode P.
By the explanation of above two embodiment as can be known, COA technology of the present invention is different from prior art, and its practice is that thin-film transistor is produced on the chromatic filter layer.In addition, the present invention only need carry out the making that four road mask fabrication operations promptly can be finished dot structure, and its more traditional five road mask fabrication operations can reduce the mask number one, therefore has the advantage that increases production capacity and reduce cost.And, on mask, do not use the technology of semi-transparent pattern (halftone) in the present invention's four road mask fabrication operations, so do not have the problem of mask layout design and photoresist selectivity aspect, nor have the uneven problem of exposure back pattern.
What deserves to be mentioned is that no matter be in the dot structure of first embodiment or second embodiment, thin-film transistor T makes flow process and structure all is identical.Therefore thin-film transistor T manufacture method and structure for convenience of description below explain with the accompanying drawing of second embodiment.Please refer to Fig. 5 I, this thin-film transistor T manufacture method at first defines an one source pole 132 and a drain electrode 134.Afterwards, use with the mask fabrication operation with source electrode 132 and drain 134 above formation define a channel layer 160a, a gate insulation layer 162 and a grid 164a simultaneously, to form a thin-film transistor.Therefore be configured in the bottom of total with the source electrode 132 of the formed thin-film transistor of the method and drain electrode 134, and channel layer 160a covers source electrode 132 and drain electrode 134.In addition, gate insulation layer 162 is disposed on the channel layer 160a.In addition, grid 164a is disposed on the gate insulation layer 162.In a preferred embodiment, thin-film transistor T also comprises an ohmic contact material layers 140a, and it is disposed between source electrode 132/ drain electrode 134 and the channel layer 160a.Particularly, the material of channel layer 160a can be an amorphous silicon.
The structure and the manufacture method thereof of thin-film transistor of the present invention are different from prior art, with grid in formed order of thin-film transistor and position thereof, the grid of prior art thin-film transistor is formed on the substrate in the first road mask fabrication operation, and the grid of thin-film transistor of the present invention is formed on the gate insulation layer in the second road mask fabrication operation.
Though the present invention has done explanation as above with preferred embodiment; but it is not in order to limit the present invention; any those skilled in the art; in not breaking away from method of the present invention and scope; can do various replacements and modification, so protection range of the present invention being as the criterion with defined in claims.
Claims (12)
1. one pixel structure process method is characterized in that comprising:
One substrate is provided, and has been formed with a chromatic filter layer on this substrate, and be coated with a polarizing layer on this chromatic filter layer;
On this polarizing layer, form a first metal layer;
Carry out the first road mask fabrication operation,, and define an one source pole and a drain electrode with this first metal layer of patterning;
Above substrate, form a raceway groove material layers, a gate insulation layer and one second metal level in regular turn, cover this source electrode and this drain electrode;
Carry out one second road mask fabrication operation, with this second metal level of patterning, this gate insulation layer and this raceway groove material layers, to define a grid and a channel layer;
Above this substrate, form a passivation layer, cover this grid;
Carry out one the 3rd road mask fabrication operation,, and this drain electrode part is come out with this passivation layer of patterning;
Form a transparency conducting layer above this substrate, this transparency conducting layer is electrically connected with this drain electrode that exposes; And
This transparency conducting layer is carried out one the 4th road mask fabrication operation, to define a pixel electrode.
2. a kind of one pixel structure process method according to claim 1 is characterized in that, wherein:
In the described second road mask fabrication operation, also comprise defining a bottom electrode;
In the 3rd road mask fabrication operation, also comprise keeping the passivation layer that is positioned on this bottom electrode; And
In described the 4th road mask fabrication operation, also comprise keeping this transparency conducting layer be positioned on this passivation layer, with as a top electrode.
3. a kind of one pixel structure process method according to claim 1 is characterized in that, wherein:
In the described first road mask fabrication operation, also comprise defining a bottom electrode;
In the described second road mask fabrication operation, also comprise keeping this gate insulation layer and this second metal level be positioned at this bottom electrode top, with as a capacitance dielectric layer and a top electrode;
In described the 3rd road mask fabrication operation, also comprise the bottom electrode that exposes part; And
The pixel electrode that is defined in described the 4th road mask fabrication operation is electrically connected with this bottom electrode that exposes.
4. a kind of one pixel structure process method according to claim 1 is characterized in that, wherein:
In the described first road mask fabrication operation, also comprise defining one first weld pad;
In the described second road mask fabrication operation, also comprise defining one second weld pad;
In described the 3rd road mask fabrication operation, also comprise exposing this first weld pad of part and this second weld pad; And
In described the 4th road mask fabrication operation, also comprise keeping this transparency conducting layer that is positioned at this first weld pad and this second weld pad top.
5. a kind of one pixel structure process method according to claim 1, it is characterized in that, after forming this first metal layer on this substrate, also be included in and form an ohmic contact material layers on this first metal layer, and in this first road mask fabrication operation, also comprise this ohmic contact material layers of patterning.
6. a kind of one pixel structure process method according to claim 1 is characterized in that, the method that forms this chromatic filter layer on described substrate comprises:
On this substrate, form a black matrix; And
In this black matrix, form a plurality of red filter pattern, a plurality of green filter pattern and a plurality of blue filter pattern.
7. dot structure is characterized in that comprising:
One chromatic filter layer is configured on the substrate;
One polarizing layer covers on this chromatic filter layer;
One thin-film transistor, be configured on this polarizing layer, this thin-film transistor is covered in a channel layer in this source electrode and this drain electrode, is disposed at the gate insulation layer on this channel layer and the grid that is disposed on this gate insulation layer is constituted by one source pole and a drain electrode, part;
One passivation layer covers this thin-film transistor, and the part drain electrode is come out; And
One pixel electrode is disposed on this polarizing layer, and this pixel electrode is electrically connected with this drain electrode that exposes.
8. a kind of dot structure according to claim 7, it is characterized in that also comprising a reservior capacitor, be disposed on this polarizing layer, and this reservior capacitor is made of a bottom electrode, a top electrode and a capacitance dielectric layer, and this top electrode is electrically connected with this pixel electrode.
9. a kind of dot structure according to claim 7, it is characterized in that also comprising a reservior capacitor, be disposed between this polarizing layer and this pixel electrode, this reservior capacitor is made of a bottom electrode, a top electrode and a capacitance dielectric layer, and this bottom electrode is electrically connected with this pixel electrode.
10. a kind of dot structure according to claim 7 is characterized in that also comprising one first weld pad and one second weld pad, is configured on the surface of two neighboring edges of described substrate.
11. a kind of dot structure according to claim 7 is characterized in that also comprising an ohmic contact layer, it is disposed between described source electrode and the channel layer, and between described drain and the channel layer.
12. a kind of dot structure according to claim 7 is characterized in that, described chromatic filter layer comprises a black matrix and is disposed at this black matrix interior a plurality of red filter pattern, a plurality of green filter pattern and a plurality of blue filter pattern.
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| CN102244009A (en) * | 2011-07-30 | 2011-11-16 | 华映光电股份有限公司 | Thin film transistor and manufacturing method thereof |
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| CN100456139C (en) * | 2006-04-20 | 2009-01-28 | 友达光电股份有限公司 | Method of mfg. lower substrate of LCD device by using three masks |
| WO2010024035A1 (en) | 2008-08-27 | 2010-03-04 | シャープ株式会社 | Electrode contact structure, liquid crystal display device provided with electrode contact structure, and electrode contact structure manufacturing method |
| CN103257499A (en) * | 2013-05-28 | 2013-08-21 | 南京中电熊猫液晶显示科技有限公司 | Thin film transistor liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof |
| US9599865B2 (en) | 2015-01-21 | 2017-03-21 | Apple Inc. | Low-flicker liquid crystal display |
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| CN1652296A (en) | 2005-08-10 |
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