CN101136376A - Pixel structure and manufacturing method therefor - Google Patents
Pixel structure and manufacturing method therefor Download PDFInfo
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- CN101136376A CN101136376A CNA2007101619428A CN200710161942A CN101136376A CN 101136376 A CN101136376 A CN 101136376A CN A2007101619428 A CNA2007101619428 A CN A2007101619428A CN 200710161942 A CN200710161942 A CN 200710161942A CN 101136376 A CN101136376 A CN 101136376A
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Abstract
This invention relates to a manufacturing method for pixel structure, which provides a base board with a shading layer and a flatness layer formed orderly, forms a semiconductor layer and a first metal layer on the flatness layer, processes a first mask to define a source, a drain, a channel layer, data lines and a first weld pad with the patternized first metal layer and the semiconductor layer, in which, the channel layer is connected with the source and the drain, and the data lines are connected with the first weld pad, then a door dielectric layer, a second metal layer and a protection layer are formed on the base board, then a second mask is processed to define a grid, scan lines and a second weld pad with the patternized protection layer, the second metal layer and the door dielectric layer, and part of the drain is exposed, in which, the grid is stacked with the channel layer and the scan lines are connected with the grid and the second weld pad, and a transparent conduction layer is formed on the base board, then a third mask is manufactured and the transparent conduction layer is patternized to define the pixel electrode connected with the exposed drain.
Description
Technical field
The invention relates to a kind of dot structure and manufacture method thereof, and particularly can reduce dot structure (Pixel Structure) and the manufacture method thereof that light shield uses number relevant for a kind of.
Background technology
Thin Film Transistor-LCD (thin film transistor liquid crystal display, TFT-LCD) mainly constituted by thin-film transistor array base-plate, colored optical filtering substrates and liquid crystal layer, wherein thin-film transistor array base-plate is by a plurality of thin-film transistors with arrayed, and forms with the pixel electrode (pixel electrode) of the corresponding configuration of each thin-film transistor.And above-mentioned thin-film transistor comprises grid, channel layer, drain electrode and source electrode, and thin-film transistor and pixel electrode formation dot structure.Wherein, thin-film transistor is used as the switch element of liquid crystal display.
When making thin-film transistor, one of most important consideration is exactly to reduce manufacturing technology steps, and then reduces the cost of making.Particularly, employed light shield cost is higher in manufacturing process, therefore if can reduce the required light shield number of manufacturing process, then can effectively reduce cost of manufacture.
Generally speaking, the light shield of making thin-film transistor at present is generally four to seven roads.In order to promote manufacturing process efficient, be to use four road light shield manufacturing process at present mostly.But along with the development trend of large size panel, the size of light shield must can improve the light shield cost thereupon increasing.Therefore, each tame manufacturer needs to think deeply the possible technology of further reduction light shield number especially.
Summary of the invention
In view of this, the invention provides a kind of one pixel structure process method, utilize three road light shields can carry out the making of dot structure.
The present invention also provides a kind of dot structure, utilizes three road light shields just can make this dot structure.
Based on above-mentioned, the present invention proposes a kind of one pixel structure process method.At first, provide substrate, be formed with light shield layer on this substrate, and be coated with a flatness layer on the light shield layer.Then, on flatness layer, form semiconductor layer and the first metal layer in regular turn.Come again, this first metal layer of patterning and semiconductor layer, and define source electrode, drain electrode, channel layer, data wire and first weld pad, and wherein channel layer links source electrode and drain electrode, and data wire links the source electrode and first weld pad.Continue it, on substrate, form door dielectric layer, second metal level and protective layer in regular turn.Then, this protective layer of patterning, second metal level and door dielectric layer, and define grid, scan line and second weld pad, and expose the part drain electrode, wherein grid and channel layer are overlapping, and scan line links the grid and second weld pad.Continue it, on substrate, form transparency conducting layer.Afterwards, this transparency conducting layer of patterning, to define pixel electrode, wherein pixel electrode electrically connects with the drain electrode that exposes.
In one embodiment of this invention, in this first metal layer of above-mentioned patterning and this semiconductor layer step, more comprise defining a bottom electrode, and this bottom electrode is positioned at the predetermined position that forms scan line; In this protective layer of patterning, this second metal level and this dielectric layer step, more comprise and keep door dielectric layer, second metal level and the protective layer that is positioned at the bottom electrode top, wherein, the door dielectric layer is that second metal level as a capacitance dielectric layer, reservation is scan line and as a top electrode, and the side of bottom electrode is to come out; The pixel electrode that is defined in this transparency conducting layer step of patterning electrically connects at the side and the bottom electrode of bottom electrode.
In one embodiment of this invention, in this first metal layer of above-mentioned patterning and this semiconductor layer step, more comprise defining a bottom electrode, and this bottom electrode is positioned at the position that preboarding becomes pixel electrode; In this protective layer of patterning, this second metal level and this dielectric layer step, more comprise and keep door dielectric layer, second metal level and the protective layer that is positioned at the bottom electrode top, wherein, the door dielectric layer is as a capacitance dielectric layer, second metal level that keeps is a bridging line and as a top electrode, and the side of bottom electrode is to come out; The pixel electrode that is defined in this transparency conducting layer step of patterning electrically connects at the side and the bottom electrode of bottom electrode.
In one embodiment of this invention, above-mentioned semiconductor layer comprises a passage material layers and an ohmic contact material layers, and this ohmic contact material layers is between passage material layers and the first metal layer.
In one embodiment of this invention, this first metal layer of above-mentioned patterning and this semiconductor layer step comprise: at first, utilize the first half mode light shields to form the first patterning photoresist layer on the first metal layer.Afterwards, serve as the cover curtain with the first patterning photoresist layer, when defining source electrode, drain electrode, channel layer, data wire and first weld pad, remove the first metal layer between source electrode and drain electrode.
In one embodiment of this invention, this protective layer of above-mentioned patterning, this second metal level and this dielectric layer step comprise: at first, utilize the second half mode light shields to form the second patterning photoresist layer on protective layer.Afterwards, serve as cover curtain with the second patterning photoresist layer, define grid, scan line, with second weld pad in, remove the protective layer that is positioned at above first weld pad and second weld pad.
In one embodiment of this invention; in this protective layer of above-mentioned patterning, this second metal level and this dielectric layer step; more comprise second metal level was carried out etching, so that the width of formed grid and scan line is less than the width of patterned protective layer.
In one embodiment of this invention, in this transparency conducting layer step of above-mentioned patterning, more comprise keeping the transparency conducting layer that is positioned at first weld pad and second weld pad top.
In one embodiment of this invention, the above-mentioned method that forms light shield layer on substrate comprises the following steps.At first, on substrate, form black matrix.Continue it, in black matrix, form most color filter patterns.These color filter patterns comprise most red filter pattern, most green filter pattern and most blue filter pattern.
Based on above-mentioned, the present invention also proposes a kind of dot structure, comprises light shield layer, flatness layer, thin-film transistor, protective layer, pixel electrode and reservior capacitor.Light shield layer is configured on the substrate.Flatness layer covers on the light shield layer.Thin-film transistor is configured on the flatness layer, and this thin-film transistor is to be covered in source electrode and drain electrode on the channel layer, to be disposed at the dielectric layer in source electrode and the drain electrode and the grid that is disposed on the dielectric layer is constituted by channel layer, part.Protective layer cover film transistor, and part source electrode and drain electrode are come out.Pixel electrode is disposed on the flatness layer, and pixel electrode covering source electrode and drain electrode, and electrically connects with the drain electrode that exposes.Reservior capacitor is disposed on the flatness layer, and reservior capacitor is made of bottom electrode, top electrode and capacitance dielectric layer, wherein, bottom electrode is positioned at the predetermined position that forms scan line, and the side of bottom electrode is to come out, top electrode is scan line, and capacitance dielectric layer is between bottom electrode and scan line, and pixel electrode electrically connects at the side and the bottom electrode of bottom electrode.
In one embodiment of this invention, above-mentioned dot structure more comprises an ohmic contact material layers, and it is disposed between source/drain and the channel layer.
In one embodiment of this invention, the width of above-mentioned grid and scan line is less than the width of protective layer.
In one embodiment of this invention, above-mentioned dot structure more comprises one first weld pad and one second weld pad, is configured in two edges of substrate.
In one embodiment of this invention, above-mentioned dot structure more comprises a transparency conducting layer, is positioned at first weld pad and second weld pad top.
In one embodiment of this invention, above-mentioned light shield layer comprises a black matrix and is disposed at most interior color filter patterns of black matrix.These color filter patterns comprise most red filter pattern, most green filter pattern and most blue filter pattern.
Based on above-mentioned, the present invention reintroduces a kind of dot structure, comprises light shield layer, flatness layer, thin-film transistor, protective layer, pixel electrode and reservior capacitor.Light shield layer is configured on the substrate.Flatness layer covers on the light shield layer.Thin-film transistor is configured on the flatness layer, and this thin-film transistor is to be covered in source electrode and drain electrode on the channel layer, to be disposed at the dielectric layer in source electrode and the drain electrode and the grid that is disposed on the dielectric layer is constituted by channel layer, part.Protective layer cover film transistor, and part source electrode and drain electrode are come out.Pixel electrode is disposed on the flatness layer, and pixel electrode covering source electrode and drain electrode, and electrically connects with the drain electrode that exposes.Reservior capacitor is disposed on the flatness layer, and reservior capacitor is made of bottom electrode, top electrode and capacitance dielectric layer, wherein, bottom electrode is positioned at the position that preboarding becomes pixel electrode, and the side of bottom electrode is to come out, top electrode is a bridging line, and capacitance dielectric layer is between bottom electrode and bridging line, and pixel electrode electrically connects at the side and the bottom electrode of bottom electrode.
In one embodiment of this invention, above-mentioned dot structure more comprises an ohmic contact material layers, and it is disposed between source/drain and the channel layer.
In one embodiment of this invention, the width of above-mentioned grid and bridging line is less than the width of protective layer.
In one embodiment of this invention, above-mentioned dot structure more comprises one first weld pad and one second weld pad, is configured in two edges of substrate.
In one embodiment of this invention, above-mentioned dot structure more comprises a transparency conducting layer, is positioned at first weld pad and second weld pad top.
In one embodiment of this invention, above-mentioned light shield layer comprises a black matrix and is disposed at most interior color filter patterns of black matrix.These color filter patterns comprise most red filter pattern, most green filter pattern and most blue filter pattern.
One pixel structure process method of the present invention adopts half mode light shield, and can utilize three road light shields promptly to finish the making of dot structure, so, can reduce the use number of light shield, and reduce cost of manufacture.In addition, when forming dot structure, can form reservior capacitor in the lump, help promoting the demonstration usefulness of dot structure.Moreover the side direction at the bottom electrode of reservior capacitor electrically connects pixel electrode and bottom electrode.So, when charging, can charge for reservior capacitor simultaneously for pixel electrode.In addition; utilize overetched mode to make grid and scan line compared to the protective layer of its top distance that inwardly contracts; therefore, formed pixel electrode can electrically not contact with grid, scan line, can avoid the yield of dot structure inefficacy and then lifting dot structure.Moreover this dot structure is that array is positioned at structure on the colored optical filtering substrates (Array On Color Filter Substrate AOC), therefore can simplify the structure of this dot structure effectively, and can avoid channel layer to produce leakage current because of shining light.
Description of drawings
Fig. 1 is the schematic top plan view of the dot structure of first embodiment of the invention.
Fig. 2 A-Fig. 2 F is the step schematic diagram of the one pixel structure process method of first embodiment of the invention.
Fig. 3 is the schematic top plan view of the dot structure of second embodiment of the invention.
Fig. 4 A-Fig. 4 F is the step schematic diagram of the one pixel structure process method of second embodiment of the invention.
Drawing reference numeral:
100,300: dot structure
110,310: substrate
120,320: light shield layer
122,322: black matrix
124,324: color filter patterns
130,330: flatness layer
140,340: semiconductor layer
142,342: the passage material layers
144,344: the ohmic contact material layers
140a, 340a: channel layer
150,350: the first metal layer
152,352: source electrode
154,354: drain electrode
156,356: data wire
157,357: bottom electrode
158,358: the first weld pads
160,360: the first patterning photoresist layers
162,362: the second patterning photoresist layers
170,370: door dielectric layer (capacitance dielectric layer)
180,380: the second metal levels
180 ', 380 ': top electrode
182,382: grid
184,384: scan line
186,386: the second weld pads
190,390: protective layer
192,392: transparency conducting layer
192 ', 392 ': pixel electrode
200,400: the first half mode light shields
202,402: the second half mode light shields
388: bridging line
Cst: reservior capacitor
D1, d2: width
TFT: thin-film transistor
A-A ', B-B ', C-C ', D-D ': hatching
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
First embodiment
Fig. 1 illustrates the schematic top plan view into the dot structure of first embodiment of the invention.Fig. 2 A～Fig. 2 F illustrates the step schematic diagram into the one pixel structure process method of first embodiment of the invention.Please jointly with reference to Fig. 1 and Fig. 2 A～Fig. 2 F, wherein, the A-A ' of Fig. 2 A～Fig. 2 F district is the section of the A-A ' line in Fig. 1, and B-B ' district is the section of the B-B ' line in Fig. 1.
At first, please provide substrate 110, be formed with light shield layer 120 on this substrate 110, and be coated with a flatness layer 130 on the light shield layer 120 simultaneously with reference to Fig. 1 and Fig. 2 A.The above-mentioned method that forms light shield layer 120 on substrate 110 for example is as described below.At first, on substrate 110, form black matrix 122.The method that forms black matrix 122 for example is transfer printing or ink-jet method.Continue it, form most color filter patterns 124 in black matrix 122, the method that forms color filter patterns 124 can be an ink-jet method.These color filter patterns 124 can be most red filter pattern, most green filter pattern and most blue filter pattern (only illustrating among Fig. 2 A).In addition, the method that forms flatness layer 130 for example is low temperature chemical vapor deposition method or method of spin coating, and the material of flatness layer 130 for example is silicon nitride or transparent resin, does not limit the formation method and the material of flatness layer 130 at this.
Then, please refer to Fig. 2 B, on flatness layer 130, form semiconductor layer 140 and the first metal layer 150 in regular turn.The method that forms this semiconductor layer 140 for example is a chemical vapour deposition technique, and the method that forms the first metal layer 150 for example is a sputtering method.In one embodiment, semiconductor layer 140 can comprise a passage material layers 142 and an ohmic contact material layers 144, and this ohmic contact material layers 144 is between passage material layers 142 and the first metal layer 150.The material of passage material layers 142 for example is amorphous silicon or polysilicon, and the material of ohmic contact material layers 144 for example is through doped amorphous silicon.Certainly, in a further embodiment, also can not form ohmic contact material layers 144.
Come again, please be simultaneously with reference to Fig. 1, Fig. 2 B and Fig. 2 C, carry out the first road light shield manufacturing process, with patterning the first metal layer 150 and semiconductor layer 140, and define source electrode 152, drain electrode 154, channel layer 140a, data wire 156 and first weld pad 158, wherein channel layer 140a links source electrode 152 and drain electrode 154, and data wire 156 links the source electrode 152 and first weld pad 158.At this, one light shield manufacturing process is that general designation is used one mask pattern, carries out little shadow manufacturing process and follow-up etching manufacturing process.
Illustrate as Fig. 2 B, the first above-mentioned road light shield manufacturing process for example is to utilize the first half mode light shields 200 to form the first patterning photoresist layer 160 on the first metal layer 150.Afterwards, serve as the cover curtain with the first patterning photoresist layer 160, when defining source electrode 152, drain electrode 154, channel layer 140a, data wire 156 and first weld pad 158, remove the first metal layer 150 between source electrode 152 and drain electrode 154.In addition, when being formed with the situation of ohmic contact material layers 144, also can this ohmic contact material layers 144 of patterning.In addition, in the first above-mentioned road light shield manufacturing process, more comprise defining a bottom electrode 157, and this bottom electrode 157 is arranged in the predetermined position that forms scan line 184 (being illustrated in Fig. 1 and Fig. 2 E).After etching is finished, remove the first patterning photoresist layer 160.
Continue it, please on substrate 110, form door dielectric layer 170, second metal level 180 and protective layer 190 in regular turn simultaneously with reference to Fig. 1 and Fig. 2 D.Similarly, the method that forms door dielectric layer 170 and protective layer 190 for example is a chemical vapour deposition technique, and the method that forms second metal level 180 for example is a sputtering method.
Then; please continue with reference to Fig. 1, Fig. 2 D and Fig. 2 E; carry out the second road light shield manufacturing process; with this protective layer 190 of patterning, second metal level 180 and door dielectric layer 170; and define grid 182, scan line 184 and second weld pad 186; and expose part drain electrode 154, wherein grid 182 is overlapping with channel layer 140a, and scan line 184 links the grid 182 and second weld pad 186.
The second above-mentioned road light shield manufacturing process for example is to utilize the second half mode light shields 202 to form the second patterning photoresist layer 162 on protective layer 190.Afterwards, serve as cover curtain with the second patterning photoresist layer 162, define grid 182, scan line 184, with second weld pad 186 in, remove the protective layer 190 that is positioned at first weld pad 158 and second weld pad, 186 tops.It should be noted that in the second above-mentioned road light shield manufacturing process, more comprise second metal level 180 was carried out etching, for example is Wet-type etching, so that the width d1 of formed grid 182 and scan line 184 is less than the width d2 of patterned protective layer 190.
In addition; in the second road light shield manufacturing process; more comprise and keep door dielectric layer 170, second metal level 180 and protective layer 190 that is positioned at bottom electrode 157 tops; wherein; door dielectric layer 170 is that second metal level 180 as a capacitance dielectric layer, reservation is scan line 184 and as a top electrode 180 ', and the side of bottom electrode 157 is to come out.
Continue it, please refer to Fig. 1 and Fig. 2 F, on substrate 110, form transparency conducting layer 192.And, carry out the 3rd road light shield manufacturing process, this transparency conducting layer 192 of patterning, to define pixel electrode 192 ', wherein pixel electrode 192 ' electrically connects with the drain electrode 154 that exposes.Shown in Fig. 1 and Fig. 2 F, in the 3rd above-mentioned road light shield manufacturing process, more comprise keeping the transparency conducting layer 192 that is positioned at first weld pad 158 and second weld pad, 186 tops.Particularly, the pixel electrode 192 ' that is defined in the 3rd road light shield manufacturing process electrically connects at the side and the bottom electrode 157 of bottom electrode 157.
In sum, this one pixel structure process method is passed through to adopt half mode light shield, and then can only utilize three road light shields promptly to finish the making of dot structure 100.Therefore, can reduce the use number of light shield, and reduce cost of manufacture.In addition; at the defined bottom electrode 157 of the first road light shield manufacturing process, with the defined door of second road light shield manufacturing process dielectric layer 170, form the reservior capacitor Cst of dot structure 100 as second metal level 180 and each rete of protective layer 190 of top electrode 180 ', and this reservior capacitor Cst is arranged on the predetermined position that forms scan line 184.Moreover, utilize pixel electrode 192 ' and drain electrode 154 to electrically connect, and pixel electrode 192 ' electrically connects in side direction with bottom electrode 157, by this, when charging, can charge simultaneously for reservior capacitor Cst (bottom electrode 157, the door dielectric layer 170 and top electrode 180 ' that are illustrated as Fig. 2 F) for pixel electrode 192 '.
Please refer to Fig. 1 and Fig. 2 F, via above-mentioned manufacture method made dot structure 100, it comprises light shield layer 120, flatness layer 130, thin-film transistor TFT, protective layer 190, pixel electrode 192 ' and reservior capacitor Cst.Light shield layer 120 is configured on the substrate 110.Flatness layer 130 covers on the light shield layer 120.Thin-film transistor TFT is configured on the flatness layer 130, and this thin-film transistor TFT is covered in source electrode 152 and drain electrode 154 on the channel layer 140a, is disposed at the door dielectric layer 170 in source electrode 152 and the drain electrode 154 and the grid 182 that is disposed on the dielectric layer 170 is constituted by channel layer 140a, part.Protective layer 190 cover film transistor T FT, and part source electrode 152 and drain electrode 154 are come out.Pixel electrode 192 ' is disposed on the flatness layer 130, and pixel electrode 192 ' covering source electrode 152 and drain electrode 154, and electrically connects with the drain electrode 154 that exposes.Reservior capacitor Cst is disposed on the flatness layer 130, and reservior capacitor Cst is made of bottom electrode 157, top electrode 180 ' and capacitance dielectric layer 170, wherein, bottom electrode 157 is positioned at the predetermined position that forms scan line 184, and the side of bottom electrode 157 is to come out, top electrode 180 ' is scan line 184, and capacitance dielectric layer 170 is between bottom electrode 157 and scan line 184, and pixel electrode 192 ' electrically connects at the side and the bottom electrode 157 of bottom electrode 157.
Please continue with reference to Fig. 1 and Fig. 2 F, dot structure 100 can more comprise an ohmic contact material layers 144, and it is disposed between source electrode 152/ drain electrode 154 and the channel layer 140a.Therefore, can reduce channel layer 140a and source electrode 152, the drain electrode 154 and between electrical resistance.
In addition, shown in Fig. 2 F, the width d1 of grid 182 and scan line 184 is less than the width d2 of protective layer 190.That is, utilized the mode of etching (overetching), make grid 182 and scan line 184 compared to the protective layer 190 of its top distance that inwardly contracts.Therefore, formed pixel electrode 192 can electrically not contact with grid 182, scan line 184, and can avoid dot structure 100 to lose efficacy, and then promotes the making yield of dot structure 100.
As shown in Figure 1, this dot structure 100 can have one first weld pad 158 and one second weld pad 186, is configured in two edges of substrate 110.Particularly, transparency conducting layer 192 can be positioned at first weld pad 158 and second weld pad, 186 tops, and helps the electric connection of other circuit element.
In addition, light shield layer 120 can comprise a black matrix 122 and be disposed at most the color filter patterns 124 of deceiving in the matrix 122.These color filter patterns 124 comprise most red filter pattern, most green filter pattern and most blue filter pattern.By this, can utilize light shield layer 120 to avoid channel layer 140a to be subjected to irradiate light, and can reduce the leakage current that causes because of light.And this array is positioned at structure on the colored optical filtering substrates, and (Array On Color Filter Substrate AOC) can simplify this dot structure 100 effectively.
Second embodiment
Fig. 3 illustrates the schematic top plan view into the dot structure of second embodiment of the invention.Fig. 4 A～Fig. 4 F illustrates the step schematic diagram into the one pixel structure process method of second embodiment of the invention.Please jointly with reference to Fig. 3 and Fig. 4 A～Fig. 4 F, wherein, the C-C ' of Fig. 4 A～Fig. 4 F district is the section of the C-C ' line in Fig. 3, and D-D ' district is the section of the D-D ' line in Fig. 3.
At first, please provide substrate 310, be formed with light shield layer 320 on this substrate 310, and be coated with a flatness layer 330 on the light shield layer 320 simultaneously with reference to Fig. 3 and Fig. 4 A.The above-mentioned method that forms light shield layer 320 on substrate 310 for example is as described below.At first, on substrate 310, form black matrix 322.The method that forms black matrix 322 for example is transfer printing or ink-jet method.Continue it, form most color filter patterns 324 in black matrix 322, the method that forms color filter patterns 324 can be an ink-jet method.These color filter patterns 324 can be most red filter pattern, most green filter pattern and most blue filter pattern (only illustrating among Fig. 4 A).In addition, the method that forms flatness layer 330 for example is low temperature chemical vapor deposition method or method of spin coating etc., and the material of flatness layer 330 for example is silicon nitride or transparent resin, and the present invention does not limit the formation method and the material of flatness layer 330.
Then, please refer to Fig. 4 B, on flatness layer 330, form semiconductor layer 340 and the first metal layer 350 in regular turn.The method that forms this semiconductor layer 340 for example is a chemical vapour deposition technique, and the method that forms the first metal layer 350 for example is a sputtering method.In one embodiment, semiconductor layer 340 can comprise a passage material layers 342 and an ohmic contact material layers 344, and this ohmic contact material layers 344 is between passage material layers 342 and the first metal layer 350.The material of passage material layers 342 for example is amorphous silicon or polysilicon, and the material of ohmic contact material layers 344 for example is through doped amorphous silicon.Certainly, in a further embodiment, also can not form ohmic contact material layers 344.
Come again, please be simultaneously with reference to Fig. 3, Fig. 4 B and Fig. 4 C, carry out the first road light shield manufacturing process, with patterning the first metal layer 350 and semiconductor layer 340, and define source electrode 352, drain electrode 354, channel layer 340a, data wire 356 and first weld pad 358, wherein channel layer 340a links source electrode 352 and drain electrode 354, and data wire 356 links the source electrode 352 and first weld pad 358.The first above-mentioned road light shield manufacturing process for example is to utilize the first half mode light shields 400 to form the first patterning photoresist layer 360 on the first metal layer 350.Afterwards, serve as the cover curtain with the first patterning photoresist layer 360, when defining source electrode 352, drain electrode 354, channel layer 340a, data wire 356 and first weld pad 358, remove the first metal layer 350 between source electrode 352 and drain electrode 354.In addition, when being formed with the situation of ohmic contact material layers 344, also can this ohmic contact material layers 344 of patterning.In addition, in the first above-mentioned road light shield manufacturing process, more comprise defining a bottom electrode 357, and this bottom electrode 357 is arranged in the position that preboarding becomes pixel electrode 392 (being illustrated in Fig. 4 F).And, after etching is finished, remove photoresist pattern 360.
Continue it, please on substrate 310, form door dielectric layer 370, second metal level 380 and protective layer 390 in regular turn simultaneously with reference to Fig. 3 and Fig. 4 D.Similarly, the method that forms door dielectric layer 370 and protective layer 390 for example is a chemical vapour deposition technique, and the method that forms second metal level 380 for example is a sputtering method.
Then; please continue with reference to Fig. 3, Fig. 4 D and Fig. 4 E; carry out the second road light shield manufacturing process; with this protective layer 390 of patterning, second metal level 380 and door dielectric layer 370; and define grid 382, scan line 384 and second weld pad 386; and expose part drain electrode 354, wherein grid 382 is overlapping with channel layer 340a, and scan line 384 links the grid 382 and second weld pad 386.
The second above-mentioned road light shield manufacturing process for example is to utilize the second half mode light shields 402 to form the second patterning photoresist layer 362 on protective layer 390.Afterwards, serve as cover curtain with the second patterning photoresist layer 362, define grid 382, scan line 384, with second weld pad 386 in, remove the protective layer 390 that is positioned at first weld pad 358 and second weld pad, 386 tops.It should be noted that in the second above-mentioned road light shield manufacturing process, more comprise second metal level 380 was carried out etching, so that the width d1 of formed grid 382 and scan line 384 is less than the width d2 of patterned protective layer 390.
Particularly; in the second road light shield manufacturing process; more comprise and keep door dielectric layer 370, second metal level 380 and protective layer 390 that is positioned at bottom electrode 357 tops; wherein; door dielectric layer 370 is as a capacitance dielectric layer; second metal level 380 that keeps is a bridging line 388 and as a top electrode 380 ', and the side of bottom electrode 357 is to come out.
Continue it, please refer to Fig. 3 and Fig. 4 F, on substrate 310, form transparency conducting layer 392.And, carry out the 3rd road light shield manufacturing process, this transparency conducting layer 392 of patterning, to define pixel electrode 392 ', wherein pixel electrode 392 ' electrically connects with the drain electrode 354 that exposes.As shown in Figure 3, in the 3rd above-mentioned road light shield manufacturing process, more comprise keeping the transparency conducting layer 392 that is positioned at first weld pad 358 and second weld pad, 386 tops.Particularly, the pixel electrode 392 ' that is defined in the 3rd road light shield manufacturing process electrically connects at the side and the bottom electrode 357 of bottom electrode 357.
In sum, this one pixel structure process method is passed through to adopt half mode light shield, and then can only utilize three road light shields promptly to finish the making of dot structure 300.Therefore, can reduce the use number of light shield, and reduce cost of manufacture.In addition; at the defined bottom electrode 357 of the first road light shield manufacturing process, with the defined door of second road light shield manufacturing process dielectric layer 370, form the reservior capacitor Cst of dot structure 300 as second metal level 380 and each rete of protective layer 390 of top electrode 380 ', and this reservior capacitor Cst is arranged on the predetermined position that forms bridging line 386.Moreover, utilize pixel electrode 392 ' and drain electrode 354 to electrically connect, and pixel electrode 392 ' electrically connects in side direction with bottom electrode 357, by this, when charging, can charge simultaneously for reservior capacitor Cst (bottom electrode 357, the door dielectric layer 370 and top electrode 380 ' that are illustrated as Fig. 4 F) for pixel electrode 392 '.
Please refer to Fig. 3 and Fig. 4 F, via the dot structure 300 of above-mentioned manufacture method made, it comprises light shield layer 320, flatness layer 330, thin-film transistor TFT, protective layer 390, pixel electrode 392 ' and reservior capacitor Cst.Light shield layer 320 is configured on the substrate 310.Flatness layer 330 covers on the light shield layer 320.Thin-film transistor TFT is configured on the flatness layer 330, and this thin-film transistor TFT is covered in source electrode 352 and drain electrode 354 on the channel layer 340a, is disposed at the door dielectric layer 370 in source electrode 352 and the drain electrode 354 and the grid 382 that is disposed on the dielectric layer 370 is constituted by channel layer 340a, part.Protective layer 390 cover film transistor T FT, and part source electrode 352 and drain electrode 354 are come out.Pixel electrode 392 ' is disposed on the flatness layer 330, and pixel electrode 392 ' covering source electrode 352 and drain electrode 354, and electrically connects with the drain electrode 354 that exposes.Reservior capacitor Cst is disposed on the flatness layer 330, and reservior capacitor Cst is made of bottom electrode 357, top electrode 380 ' and capacitance dielectric layer 370, wherein, bottom electrode 357 is positioned at the position that preboarding becomes pixel electrode 392 ', and the side of bottom electrode 357 is to come out, top electrode 380 ' is a bridging line 388, and capacitance dielectric layer 370 is between bottom electrode 357 and bridging line 388, and pixel electrode 392 ' electrically connects at the side and the bottom electrode 357 of bottom electrode 357.
Please continue with reference to Fig. 1 and Fig. 2 F, dot structure 300 can more comprise an ohmic contact material layers 344, and it is disposed between source electrode 352/ drain electrode 354 and the channel layer 340a.Therefore, can reduce channel layer 340a and source electrode 352, the drain electrode 354 and between electrical resistance.
In addition, shown in Fig. 4 F, the width d1 of grid 382 and scan line 384 is less than the width d2 of protective layer 390.That is, utilized the mode of etching (overetching), make grid 382 and scan line 384 compared to the protective layer 390 of its top distance that inwardly contracts.Therefore, formed pixel electrode 392 ' can electrically not contact with grid 382, scan line 384, and can avoid dot structure 300 to lose efficacy, and then promotes the making yield of dot structure 300.
As shown in Figure 3, this dot structure 300 can have one first weld pad 358 and one second weld pad 386, is configured in two edges of substrate 310.Particularly, transparency conducting layer 392 can be positioned at first weld pad 358 and second weld pad, 386 tops, and helps the electric connection of other circuit element.
In addition, light shield layer 320 can comprise a black matrix 322 and be disposed at most the color filter patterns 324 of deceiving in the matrix 322.These color filter patterns 324 comprise most red filter pattern, most green filter pattern and most blue filter pattern.By this, can utilize light shield layer 320 to avoid channel layer 340a to be subjected to irradiate light, and can reduce the leakage current that causes because of light.And this array is positioned at structure on the colored optical filtering substrates, and (Array On Color Filter Substrate AOC) can simplify this dot structure 300 effectively.
In sum, dot structure of the present invention and preparation method thereof has the following advantages:
(1) this one pixel structure process method can utilize three road light shields promptly to finish the making of dot structure, so, can reduce the use number of light shield, and reduce cost of manufacture.
(2) when forming dot structure, can form reservior capacitor in the lump, and promote the demonstration usefulness of dot structure.
(3) in the side direction of the bottom electrode of reservior capacitor, pixel electrode and bottom electrode are electrically connected.So, when charging, can charge for reservior capacitor simultaneously for pixel electrode.
(4) make grid and scan line the protective layer distance that inwardly contracts compared to its top.Therefore, formed pixel electrode can electrically not contact with grid, scan line, and can avoid dot structure to lose efficacy.Therefore, can promote the yield of dot structure.
(5) this dot structure is that array is positioned at structure on the colored optical filtering substrates (Array On ColorFilter Substrate AOC), therefore can simplify the structure of this dot structure effectively, and can avoid channel layer to produce leakage current because of shining light.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim scope person of defining.
Claims (24)
1. one pixel structure process method comprises:
One substrate is provided, has been formed with a light shield layer on the described substrate, and be coated with a flatness layer on the described light shield layer;
On described flatness layer, form a semi-conductor layer and a first metal layer in regular turn;
Described the first metal layer of patterning and described semiconductor layer, and define one source pole, a drain electrode, a channel layer, a data wire and one first weld pad, wherein said channel layer links described source electrode and described drain electrode, and described data wire links described source electrode and described first weld pad;
On described substrate, form a dielectric layer, one second metal level and a protective layer in regular turn;
The described protective layer of patterning, described second metal level and described door dielectric layer, and define a grid, one scan line and one second weld pad, and expose the described drain electrode of part, wherein said grid and described channel layer are overlapping, and described scan line links described grid and described second weld pad;
On described substrate, form a transparency conducting layer; And
The described transparency conducting layer of patterning, to define a pixel electrode, wherein said pixel electrode electrically connects with the described drain electrode that exposes.
2. one pixel structure process method as claimed in claim 1, wherein:
In described the first metal layer of patterning and the described semiconductor layer step, also comprise defining a bottom electrode, and described bottom electrode is positioned at the predetermined position that forms described scan line;
In the described protective layer of patterning, described second metal level and the described door dielectric layer step, also comprise keeping and be positioned at the described door dielectric layer of described bottom electrode top, described second metal level and described protective layer, wherein, described door dielectric layer is that described second metal level as a capacitance dielectric layer, reservation is described scan line and as a top electrode, and the side of described bottom electrode is to come out; And
The described pixel electrode that is defined in the described transparency conducting layer step of patterning electrically connects at the side and the described bottom electrode of described bottom electrode.
3. one pixel structure process method as claimed in claim 1, wherein:
In described the first metal layer of patterning and the described semiconductor layer step, also comprise defining a bottom electrode, and described bottom electrode is positioned at the predetermined position that forms described pixel electrode;
In the described protective layer of patterning, described second metal level and the described door dielectric layer step, also comprise keeping and be positioned at the described door dielectric layer of described bottom electrode top, described second metal level and described protective layer, wherein, described door dielectric layer is as a capacitance dielectric layer, described second metal level that keeps is a bridging line and as a top electrode, and the side of described bottom electrode is to come out; And
The described pixel electrode that is defined in the described transparency conducting layer step of patterning electrically connects at the side and the described bottom electrode of described bottom electrode.
4. one pixel structure process method as claimed in claim 1, described semiconductor layer comprise a passage material layers and an ohmic contact material layers, and described ohmic contact material layers is between described passage material layers and described the first metal layer.
5. one pixel structure process method as claimed in claim 1, wherein, described the first metal layer of patterning and described semiconductor layer step comprise:
Utilize one the first half mode light shield on described the first metal layer, to form one first patterning photoresist layer; And
With the described first patterning photoresist layer is the cover curtain, when defining described source electrode, described drain electrode, described channel layer, described data wire and described first weld pad, remove the described the first metal layer between described source electrode and described drain electrode.
6. one pixel structure process method as claimed in claim 1, wherein the described protective layer of patterning, described second metal level and described door dielectric layer step comprise:
Utilize one the second half mode light shield on described protective layer, to form one second patterning photoresist layer; And
With the described second patterning photoresist layer is cover curtain, define described grid, described scan line, with described second weld pad in, remove the described protective layer that is positioned at above described first weld pad and described second weld pad.
7. one pixel structure process method as claimed in claim 1, wherein,
In the described protective layer of patterning, described second metal level and the described door dielectric layer step; also comprise described second metal level was carried out etching, so that the width of formed described grid and described scan line is less than the width of the described protective layer of patterning.
8. one pixel structure process method as claimed in claim 1, wherein:
In the described transparency conducting layer step of patterning, also comprise keeping the described transparency conducting layer that is positioned at described first weld pad and described second weld pad top.
9. one pixel structure process method as claimed in claim 1, the method that wherein forms described light shield layer on described substrate comprises:
On described substrate, form a black matrix; And
In described black matrix, form most color filter patterns.
10. one pixel structure process method as claimed in claim 9, more wherein said color filter patterns comprise most red filter pattern, most green filter pattern and most blue filter pattern.
11. a dot structure comprises:
One light shield layer is configured on the substrate;
One flatness layer covers on the described light shield layer;
One thin-film transistor, be configured on the described flatness layer, described thin-film transistor is to be covered in one source pole and a drain electrode on the described channel layer, to be disposed at a dielectric layer in described source electrode and the described drain electrode and the grid that is disposed on described the dielectric layer is constituted by a channel layer, part;
One protective layer covers described thin-film transistor, and described source electrode of part and described drain electrode are come out;
One pixel electrode is disposed on the described flatness layer, and described pixel electrode covers described source electrode and described drain electrode, and electrically connects with the described drain electrode that exposes; And
One reservior capacitor, be disposed on the described flatness layer, and described reservior capacitor is made of a bottom electrode, a top electrode and a capacitance dielectric layer, wherein, described bottom electrode is positioned at the predetermined position that forms the one scan line, and the side of described bottom electrode is to come out, described top electrode is described scan line, described capacitance dielectric layer is between described bottom electrode and described scan line, and described pixel electrode electrically connects at the side and the described bottom electrode of described bottom electrode.
12. dot structure as claimed in claim 11 also comprises an ohmic contact material layers, it is disposed between described source/drain and the described channel layer.
13. dot structure as claimed in claim 11, wherein,
The width of described grid and described scan line is less than the width of described protective layer.
14. dot structure as claimed in claim 11 also comprises one first weld pad and one second weld pad, is configured in two edges of described substrate.
15. dot structure as claimed in claim 14 also comprises a transparency conducting layer, is positioned at described first weld pad and described second weld pad top.
16. dot structure as claimed in claim 11, wherein said light shield layer comprise a black matrix and are disposed at most interior color filter patterns of described black matrix.
17. dot structure as claimed in claim 16, more wherein said color filter patterns comprise most red filter pattern, most green filter pattern and most blue filter pattern.
18. a dot structure comprises:
One light shield layer is configured on the substrate;
One flatness layer covers on the described light shield layer;
One thin-film transistor, be configured on the described flatness layer, described thin-film transistor is to be covered in one source pole and a drain electrode on the described channel layer, to be disposed at a dielectric layer in described source electrode and the described drain electrode and the grid that is disposed on described the dielectric layer is constituted by a channel layer, part;
One protective layer covers described thin-film transistor, and described source electrode of part and described drain electrode are come out;
One pixel electrode is disposed on the described flatness layer, and described pixel electrode covers described source electrode and described drain electrode, and electrically connects with the described drain electrode that exposes; And
One reservior capacitor, be disposed on the described flatness layer, and described reservior capacitor is made of a bottom electrode, a top electrode and a capacitance dielectric layer, wherein, described bottom electrode is positioned at the predetermined position that forms described pixel electrode, and the side of described bottom electrode is to come out, described top electrode is a bridging line, described capacitance dielectric layer is between described bottom electrode and described bridging line, and described pixel electrode electrically connects at the side and the described bottom electrode of described bottom electrode.
19. dot structure as claimed in claim 18 also comprises an ohmic contact material layers, it is disposed between described source/drain and the described channel layer.
20. dot structure as claimed in claim 18, wherein,
The width of described grid and described bridging line is less than the width of described protective layer.
21. dot structure as claimed in claim 18 also comprises one first weld pad and one second weld pad, is configured in two edges of described substrate.
22. dot structure as claimed in claim 21 also comprises a transparency conducting layer, is positioned at described first weld pad and described second weld pad top.
23. dot structure as claimed in claim 18, wherein said light shield layer comprise a black matrix and are disposed at most interior color filter patterns of described black matrix.
24. dot structure as claimed in claim 23, more wherein said color filter patterns comprise most red filter pattern, most green filter pattern and most blue filter pattern.
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| CN101527281B (en) * | 2008-03-07 | 2011-01-19 | 中华映管股份有限公司 | Active element array substrate and method for manufacturing same |
| CN102269900A (en) * | 2010-06-03 | 2011-12-07 | 北京京东方光电科技有限公司 | Thin film transistor (TFT) array substrate and making method thereof |
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| CN102269900A (en) * | 2010-06-03 | 2011-12-07 | 北京京东方光电科技有限公司 | Thin film transistor (TFT) array substrate and making method thereof |
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| WO2020108196A1 (en) * | 2018-11-27 | 2020-06-04 | 京东方科技集团股份有限公司 | Display substrate and method for manufacturing same, and display device |
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