CN101527281B - Active element array substrate and method for manufacturing same - Google Patents
Active element array substrate and method for manufacturing same Download PDFInfo
- Publication number
- CN101527281B CN101527281B CN 200810081743 CN200810081743A CN101527281B CN 101527281 B CN101527281 B CN 101527281B CN 200810081743 CN200810081743 CN 200810081743 CN 200810081743 A CN200810081743 A CN 200810081743A CN 101527281 B CN101527281 B CN 101527281B
- Authority
- CN
- China
- Prior art keywords
- layer
- material layer
- patterning photoresist
- active elements
- array substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The invention discloses a method for manufacturing an active element array substrate. The method comprises the following steps: providing the substrate and a multiple transmission type photomask; forming a first metal material layer, a grid insulating material layer, a channel material layer, a second metal material layer and a first photoresist layer on the substrate in sequence; carrying out patterning to the photoresist layer through the multiple transmission type photomask so as to form first patterning photoresist layers with two different thicknesses; carrying out a first removal manufacture process and a second removal manufacture process in sequence by taking the first patterning photoresist layers as masks so as to form a grid, a grid insulating layer, a channel layer, and a source/drain; removing the first patterning photoresist layers; forming a protective layer and a second patterning photoresist layer on the substrate; carrying out a third removal manufacture process so as to form a plurality of contact window openings; forming a pixel electrode material layer on the substrate; and stripping the second patterning photoresist layer so as to form a pixel electrode.
Description
Technical field
The invention relates to a kind of active elements array substrates and manufacture method thereof, and particularly relevant for a kind of active elements array substrates and manufacture method thereof that reduces required photomask quantity by multiple penetration photomask (multi tone mask).
Background technology
Social now multimedia technology is quite flourishing, is indebted to the progress of semiconductor element or display unit mostly.With regard to display, have that high image quality, space utilization efficient are good, the Thin Film Transistor-LCD of low consumpting power, advantageous characteristic such as radiationless becomes the main flow in market gradually.
Thin Film Transistor-LCD is made of the liquid crystal layer that a thin-film transistor array base-plate, a colored optical filtering substrates and are sandwiched between the two substrates.In general; the manufacture method of conventional thin film transistor array base palte needs just can finish by five road photo-marsk processes; wherein the first road photo-marsk process mainly is that grid and scan line (scan line) definition are come out; the second road photo-marsk process mainly is that channel layer (channel) definition is come out; the 3rd road photo-marsk process mainly is with source electrode (source); drain electrode (drain) is come out with data wire (data line) definition; the 4th road photo-marsk process mainly is that protective layer (passivation) definition is come out, and the 5th road photo-marsk process mainly is that pixel electrode (pixel electrode) definition is come out.
Because the number of times that carries out photo-marsk process can directly have influence on the manufacturing cost and the process time of whole thin-film transistor array base-plate, so each tame manufacturer develops towards the number of times of reduction photo-marsk process invariably.In order to promote production capacity (throughput) and to reduce manufacturing cost, the technology of traditional thin-film transistor array base-plate has improved necessity in fact.
Summary of the invention
The invention provides a kind of active elements array substrates and manufacture method thereof, to solve the problem that existing manufacture method can't effectively reduce manufacturing cost and manufacturing time.
The present invention proposes a kind of manufacture method of active elements array substrates, comprises the following steps: at first, and a substrate and a multiple penetration photomask (multi tone mask) are provided.Then, on substrate, form one first metal material layer.Then, on first metal material layer, form a gate insulation material layer.Afterwards, on the gate insulation material layer, form a channel material layer.Then, on the channel material layer, form one second metal material layer.Then, on second metal material layer, form one first photoresist layer, and first photoresist layer is carried out patterning, to form one first patterning photoresist layer by multiple penetration photomask.Wherein, the first patterning photoresist layer has a recess patterns, and second metal material layer of part is exposed to outside the first patterning photoresist layer.Afterwards, with the first patterning photoresist layer serves as that cover curtain carries out one first and removes technology, removing not second metal material layer, channel material layer, gate insulation material layer and first metal material layer that is covered by the first patterning photoresist layer, and then form a grid, a gate insulation layer and a channel layer.Then, carry out one second and remove technology,, and then form an one source pole and a drain electrode, and expose the channel layer of part with second metal material layer of the recess patterns that removes the first patterning photoresist layer and corresponding recess patterns below.Then, remove the first patterning photoresist layer.Afterwards, on substrate, form a protective layer, with substrate, source electrode and the drain electrode of cover part and the channel layer of part.Then, on protective layer, form one second patterning photoresist layer.Wherein, the protective layer corresponding to source electrode and drain electrode top is exposed to outside the second patterning photoresist layer.Then, serve as that cover curtain carries out one the 3rd and removes technology with the second patterning photoresist layer, removing the protective layer of part, and form a plurality of contact windows, to expose source electrode and drain electrode.Afterwards, on protective layer, form a pixel electrode material layer, to cover the second patterning photoresist layer and the source electrode and the drain electrode that expose.Then, peel off (lift off) second patterning photoresist layer, to remove the pixel electrode material layer that is positioned on the second patterning photoresist layer, to form a pixel electrode.
In one embodiment of this invention, above-mentioned multiple penetration photomask comprises semi-modulation type photomask (half tone mask).
In one embodiment of this invention, above-mentioned first removes technology also comprises the first metal material layer over etching (over-etching), forms lateral erosion depression with the lateral margin in grid.
In one embodiment of this invention, when forming above-mentioned grid, also comprise forming an one scan line (scan line) and a shared distribution (common line) in the lump, and scan line and grid electric connection.
In one embodiment of this invention, when forming above-mentioned source electrode and drain electrode, also be included in shared distribution top and form a storage capacitors electrode in the lump.
In one embodiment of this invention, when forming above-mentioned grid, also comprise forming a plurality of first subdata line segments in the lump.
In one embodiment of this invention, when on protective layer, forming above-mentioned pixel electrode, also comprise along the bearing of trend of these first subdata line segments forming a plurality of second subdata line segments in the lump.One of them is electrically connected to source electrode via the corresponding contact window opening these second subdata line segments, and these second subdata line segments and these first subdata line segments electrically connect to form a data wire.
In one embodiment of this invention, the second above-mentioned subdata line segment is electrically connected between the two first subdata line segments by protective layer these contact windows partly.
In one embodiment of this invention, above-mentioned first remove technology and comprise wet etching process.
In one embodiment of this invention, above-mentioned second remove technology and comprise dry etching process.
In one embodiment of this invention, after forming above-mentioned channel material layer, also be included in and form an ohmic contact material layer on the channel material layer.
In one embodiment of this invention, above-mentioned second removes technology also comprises the ohmic contact material layer that removes part, to form an ohmic contact layer (Ohm contact layer).
The present invention also proposes a kind of manufacture method of active elements array substrates, comprises the following steps: at first, and a substrate and a multiple penetration photomask are provided.Then, on substrate, form one first metal material layer.Then, on first metal material layer, form a gate insulation material layer.Afterwards, on the gate insulation material layer, form a channel material layer.Then, on the channel material layer, form one second metal material layer.Then, on second metal material layer, form one first photoresist layer, and first photoresist layer is carried out patterning, to form one first patterning photoresist layer by multiple penetration photomask.Wherein, the first patterning photoresist layer has a recess patterns, and second metal material layer of part is exposed to outside the first patterning photoresist layer.Afterwards, with the first patterning photoresist layer serves as that cover curtain carries out one first and removes technology, removing not second metal material layer, channel material layer, gate insulation material layer and first metal material layer that is covered by the first patterning photoresist layer, and then form a grid, a gate insulation layer and a channel layer.Then, carry out one second and remove technology, with second metal material layer of the recess patterns that removes the first patterning photoresist layer and corresponding recess patterns below, and then form one source pole and drain electrode, and expose the channel layer of part.Then, remove the first patterning photoresist layer.Afterwards, on substrate, form a protective layer, with substrate, source electrode and the drain electrode of cover part and the channel layer of part.Then, on protective layer, form one second patterning photoresist layer.Wherein, the protective layer corresponding to source electrode and drain electrode top is exposed to outside the second patterning photoresist layer.Then, serve as that cover curtain carries out one the 3rd and removes technology with the second patterning photoresist layer, removing the protective layer of part, and form a plurality of contact windows, to expose source electrode and drain electrode.Afterwards, remove this second patterning photoresist layer.Then, on protective layer, form a pixel electrode, insert these contact openings, and electrically connect with drain electrode.
In one embodiment of this invention, above-mentioned multiple penetration photomask comprises semi-modulation type photomask.
In one embodiment of this invention, when forming above-mentioned grid, also comprise forming an one scan line and a shared distribution in the lump, and scan line and grid electric connection.
In one embodiment of this invention, when forming above-mentioned source electrode and drain electrode, also be included in shared distribution top and form a storage capacitors electrode in the lump.
In one embodiment of this invention, when forming above-mentioned source electrode and drain electrode, also comprise forming a plurality of first subdata line segments in the lump.
In one embodiment of this invention, when on protective layer, forming above-mentioned pixel electrode, also comprise along the bearing of trend of these first subdata line segments forming a plurality of second subdata line segments in the lump.One of them is electrically connected to source electrode via the corresponding contact window opening these second subdata line segments, and these second subdata line segments and these first subdata line segments electrically connect to form a data wire.
In one embodiment of this invention, the second above-mentioned subdata line segment is electrically connected between the two first subdata line segments by protective layer these contact windows partly.
In one embodiment of this invention, above-mentioned first remove technology and comprise wet etching process.
In one embodiment of this invention, above-mentioned second remove technology and comprise dry etching process.
In one embodiment of this invention, after forming above-mentioned channel material layer, also be included in and form an ohmic contact material layer on the channel material layer.
In one embodiment of this invention, above-mentioned second removes technology also comprises the ohmic contact material layer that removes part, to form an ohmic contact layer.
In one embodiment of this invention, the step that forms above-mentioned pixel electrode comprises: at first, form a pixel electrode material layer on protective layer, with protective mulch and the source electrode and the drain electrode that expose.Then, on protective layer, form one the 3rd patterning photoresist layer.Then, serve as that the cover curtain carries out patterning to the pixel electrode material layer with the 3rd patterning photoresist layer, to form pixel electrode.
The present invention also proposes a kind of active elements array substrates, comprises a substrate, one scan line, an active element, a protective layer, a pixel electrode, a plurality of first subdata line segment and a plurality of second subdata line segment.Scan line and active element all are disposed on the substrate, and wherein active element comprises a grid, a gate insulation layer, a channel layer and one source pole and a drain electrode.Gate configuration and electrically connects with scan line on substrate, and the lateral margin of grid has lateral erosion depression.Gate insulation layer is disposed on the grid, and channel layer is disposed on the gate insulation layer, and source electrode and drain electrode are disposed at both sides on the channel layer respectively.Protective layer covers active element and scan line, and has a plurality of contact windows.These contact windows of part expose source electrode and drain electrode.Pixel electrode is disposed on the protective layer, and electrically connects with drain electrode by these contact windows of part.These first subdata line segments and source electrode and drain electrode are positioned at the same film layer, and the second subdata line segment is positioned at identical rete with pixel electrode.These second subdata line segments are electrically connected between the two first subdata line segments by these contact windows of part, forming a data wire, and these second subdata line segments one of them be electrically connected to source electrode via the corresponding contact window opening.
In one embodiment of this invention, above-mentioned active elements array substrates comprises that also one is disposed at the shared distribution on the substrate, and shared distribution is positioned at identical rete with grid.
In one embodiment of this invention, above-mentioned active elements array substrates comprises that also one is disposed at the storage capacitors electrode of shared distribution top, and protective layer is between storage capacitors electrode and pixel electrode.Pixel electrode by these corresponding contact windows one of them and electrically connect with the storage capacitors electrode.
The manufacture method of active elements array substrates of the present invention comes photoresist layer is carried out patterning because of adopting multiple penetration photomask, and this can make the patterning photoresist layer can have two kinds of different thickness.Be used as the cover curtain of each rete of patterning with this patterning photoresist layer, minimum need of manufacture method two road photo-marsk processes of active elements array substrates of the present invention can be finished.Therefore, no matter be can reduce effectively manufacturing cost or process time, and then can significantly promote production capacity.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Figure 1A to Fig. 1 H is the section schematic flow sheet of manufacture method of the active elements array substrates of first embodiment of the invention.
Fig. 2 A to Fig. 2 B is the partial top view of manufacturing process of the active elements array substrates of first embodiment of the invention.
Fig. 3 A to Fig. 3 H is the section schematic flow sheet of manufacture method of the active elements array substrates of second embodiment of the invention.
Fig. 4 A to Fig. 4 C is the partial top view of manufacturing process of the active elements array substrates of second embodiment of the invention.
The main element symbol description:
100a, 100b: active elements array substrates
110: substrate
112: the data wire presumptive area
120: the first metal material layers
122: grid
124: the lateral erosion depression
130: the gate insulation material layer
132: gate insulation layer
140: the channel material layer
142: channel layer
150: the ohmic contact material layer
152: ohmic contact layer
160: the second metal material layers
162: the first subdata line segments
164a: source electrode
164b: drain electrode
166: the storage capacitors electrode
170: protective layer
172: contact window
180: the pixel electrode material layer
182: pixel electrode
184: the second subdata line segments
210: the first photoresist layers
212: the first patterning photoresist layers
214: recess patterns
220a, 220b: the second patterning photoresist layer
222: opening
230: the three patterning photoresist layers
CL: shared distribution
DL: data wire
M1: multiple penetration photomask
SL: scan line
T1, T2, T3: transparent area
Embodiment
First embodiment
Figure 1A to Fig. 1 H is the section schematic flow sheet of manufacture method of the active elements array substrates of first embodiment of the invention, and Fig. 2 A to Fig. 2 B is the partial top view of manufacturing process of the active elements array substrates of first embodiment of the invention.Please refer to Figure 1A, at first, provide a substrate 110.Then, on substrate 110, form one first metal material layer 120, a gate insulation material layer 130, a channel material layer 140, one second metal material layer 160 and one first photoresist layer 210 in regular turn.
Specifically, first metal material layer 120 for example is by physical vaporous deposition (physical vapordeposition, PVD) deposit metallic material is on substrate 210, and its material for example is low resistance material such as aluminium, gold, copper, molybdenum, chromium, titanium, aluminium alloy or molybdenum alloy.Gate insulation material layer 130 for example is by chemical vapour deposition technique (chemical vapor deposition, CVD) be deposited on first metal material layer 120, and its material for example is with silicon nitride (SiN) or with tetraethoxysilane (tetra-ethyl-ortho-silicate, TEOS) silica that forms for reacting gas source (SiO).
In addition, channel material layer 140 for example is by chemical vapour deposition technique deposition of amorphous silicon (amorphoussilicon, a-Si) on gate insulation material layer 130, and second metal material layer 160 for example be by the physical vaporous deposition deposit metallic material on channel material layer 140, and second metal material layer 160 can be the electric conducting material identical or approximate with the material of first metal material layer 120.In addition, first photoresist layer 210 in the present embodiment for example is to adopt the eurymeric photoresistance.
It should be noted that, for the contact impedance between the channel material layer 140 and second metal material layer 160 is descended, can also select to form an ohmic contact material layer 150 on the practice between the channel material layer 140 and second metal material layer 160, its material for example is a N type doped amorphous silicon.Ohmic contact material layer 150 for example is after forming channel material layer 140, carries out an ion doping step.Wherein, the material of ohmic contact material layer 150 for example is a N type doped amorphous silicon.
Then, provide a multiple penetration photomask (multi tone mask) M1, it for example is semi-modulation type photomask (halftone mask).Wherein, multiple penetration photomask M1 has one first transparent area T1, one second transparent area T2 and one the 3rd transparent area T3.In detail, the light transmittance of the first transparent area T1 (transmittance) is greater than the light transmittance of the second transparent area T2, and the light transmittance of the second transparent area T2 is greater than the light transmittance of the 3rd transparent area T3.In the present embodiment, the 3rd transparent area T3 can be light tight district.
Please refer to Figure 1B afterwards, first photoresist layer 210 is carried out patterning, to form one first patterning photoresist layer 212 by multiple penetration photomask M1.It should be noted that therefore, first photoresist layer 210 formed first patterning photoresist layer 212 behind patterning also can have two kinds of different residual thickness because multiple penetration photomask M1 has three kinds of different light transmittances.Because the light transmittance of the first transparent area T1 is the strongest.Therefore, first photoresist layer 210 of the corresponding first transparent area T1 can be removed through behind the patterning, and second metal material layer 160 of the corresponding first transparent area T1 can be exposed to outside the first patterning photoresist layer 212.
In addition, since in the present embodiment the 3rd transparent area T3 be light tight district.Therefore, first photoresist layer 210 of corresponding the 3rd transparent area T3 can not be removed.In addition, since the light transmittance of the second transparent area T2 between the light transmittance of the light transmittance of the first transparent area T1 and the 3rd transparent area T3.Therefore, the thickness of first photoresist layer 210 of the corresponding second transparent area T2 can be less than the thickness of first photoresist layer 210 of corresponding the 3rd transparent area T3, to form a recess patterns 214.
Then please refer to Fig. 1 C, with the first patterning photoresist layer 212 serves as that cover curtain carries out one first and removes technology, removing not second metal material layer 160, ohmic contact material layer 150, channel material layer 140, gate insulation material layer 130 and first metal material layer 120 that is covered by the first patterning photoresist layer 212, and then form a grid 122, a gate insulation layer 132 and a channel layer 142.Generally speaking, first remove for example iso wet etching process of right and wrong of technology.
In the present embodiment, first removes technology can also comprise first metal material layer, 120 over etchings (over-etching), caves in 124 with the lateral erosion that the lateral margin in grid 122 forms shown in Fig. 1 C.Identical, the lateral margin that is positioned at first metal material layer 120 of the first subdata line segment, 162 belows also can form the lateral erosion depression 124 shown in Fig. 1 C.Wherein, the function of lateral erosion depression 124 will elaborate after a while.
Please refer to Fig. 1 D then, carry out one second and remove technology, with the recess patterns 214 that removes the first patterning photoresist layer 212 shown in Fig. 1 C and the ohmic contact material layer 150 and second metal material layer 160 of recess patterns 214 belows shown in the corresponding diagram 1C, and then form an one source pole 164a and a drain electrode 164b, and expose the channel layer 142 of part.Wherein, second to remove technology for example be to adopt iso dry etching process.Then, remove the first patterning photoresist layer 212 again.
In addition, please refer to Fig. 2 A, remove first and can also form an one scan line SL and a shared distribution CL (both are all first metal material layer 120 and form) in the technology in the lump, and form a plurality of first subdata line segments 162 (being formed) in the data wire presumptive area 112 on substrate 110 by second metal material layer 160.Wherein, scan line SL and grid 122 electrically connect, and shared distribution CL is parallel to scan line SL.In addition, the bearing of trend of these first subdata line segments 162 for example is crossing with the bearing of trend of scan line SL and shared distribution CL.It should be noted that first metal material layer 120 that is positioned at these first subdata line segment, 162 belows does not electrically connect with scan line SL and shared distribution CL.
In addition, remove in the technology first and can also above shared distribution CL, form a storage capacitors electrode 166 in the lump.Wherein, grid 122, scan line SL and shared distribution CL are formed by first metal material layer 120, and the first subdata line segment 162, source electrode 164a, drain electrode 164b and storage capacitors electrode 166 are formed by second metal material layer 160.
Please refer to Fig. 1 E then, on substrate 110, form a protective layer 170 and one second patterning photoresist layer 220a in regular turn.Protective layer 132 for example is to be formed on the substrate 110 by chemical vapour deposition technique, and its material for example is silica, silicon nitride or silicon oxynitride.In addition, the second patterning photoresist layer 220a forms by one optical mask patternization.In detail, the channel layer 142 of the substrate 110 of protective layer 170 cover parts, part, the first subdata line segment 162, source electrode 164a, drain electrode 164b and storage capacitors electrode 166, and the second patterning photoresist layer 220a has a plurality of openings 222.Wherein, these openings 222 expose the protective layer 170 of part corresponding to these first subdata line segments 162, source electrode 164a, drain electrode 164b and storage capacitors electrode 166 tops.
Then please refer to Fig. 1 F; with the second patterning photoresist layer 220a serves as that cover curtain carries out one the 3rd and removes technology; to remove protective layer 170 partly and to form a plurality of contact windows 172, to expose these first subdata line segments 162, source electrode 164a, drain electrode 164b and storage capacitors electrode 166.
Please refer to Fig. 1 G then; go up formation one pixel electrode material layer 180 in the protective layer 170 and the second patterning photoresist layer 220a, to cover the second patterning photoresist layer 180 and the first subdata line segment 162 that exposes, source electrode 164a, drain electrode 164b and storage capacitors electrode 166.Wherein, pixel electrode material layer 180 for example is to be formed on the substrate 110 by chemical vapour deposition technique, and its material for example is indium tin oxide (indium tin oxide, ITO), indium-zinc oxide (indium zinc oxide, IZO) or the aluminium zinc oxide (aluminum zinc oxide, AZO).
It should be noted that because the second patterning photoresist layer 220a has suitable thickness, and the sidewall of its opening 222 levels off to vertically.Therefore, pixel electrode material layer 180 is difficult for being formed on the sidewall in the opening 222.Specifically, because the lateral margin of grid 122 has lateral erosion depression 124 with the lateral margin that is positioned at first metal material layer 120 of the first subdata line segment, 162 belows.Therefore, the pixel electrode material layer 180 that is formed on the substrate 110 can not be electrically connected at grid 122 and first metal material layer 120 that is positioned at the first subdata line segment, 162 belows.
Then please refer to Fig. 1 H, carry out peeling off (lift off) technology, peeling off the second patterning photoresist layer 220a, and remove the pixel electrode material layer 180 that is positioned on the second patterning photoresist layer 220a, to form a pixel electrode 182.In addition, pixel electrode 182 can electrically connect with storage capacitors electrode 166 by contact window 172, and the shared distribution CL and the storage capacitors electrode 166 of part can constitute a reservior capacitor (storage capacitor).
Please refer to Fig. 2 B afterwards, when forming pixel electrode 182, can also form a plurality of second subdata line segments 184 in the lump along the bearing of trend (in the data wire presumptive area 112) of the first subdata line segment 162.Wherein, the pixel electrode 182 and the second subdata line segment 184 are formed by pixel electrode material layer 180.Particularly, the second subdata line segment 184 is electrically connected between the two first subdata line segments 162, to form a data wire DL.
So far above-mentioned, the manufacture method of active elements array substrates of the present invention can complete active elements array substrates 100a of the present invention only by two road photo-marsk processes and cooperate the suitable technology that removes.Therefore, the manufacture method of active elements array substrates of the present invention can have significantly low manufacturing cost.
Second embodiment
Fig. 3 A to Fig. 3 H is the section schematic flow sheet of manufacture method of the active elements array substrates of second embodiment of the invention, and Fig. 4 A to Fig. 4 C is the partial top view of manufacturing process of the active elements array substrates of second embodiment of the invention.Second embodiment and first embodiment are roughly the same, and the two main difference part is: second embodiment utilizes the cover curtain of one the 3rd patterning photoresist layer 230 as patterning, to form a pixel electrode 182 and a plurality of second subdata line segments 184.
Please refer to Fig. 3 A to Fig. 3 D and Fig. 4 A, at first, on substrate 110, form one first metal material layer 120, a gate insulation material layer 130, a channel material layer 140, one second metal material layer 160 and one first photoresist layer 210 in regular turn.Then, by a multiple penetration photomask M1 first photoresist layer 210 is carried out patterning, to form one first patterning photoresist layer 212.Then, with the first patterning photoresist layer 212 serves as that cover curtain carries out one first in regular turn and removes technology and one second and remove technology, to form a grid 122, a gate insulation layer 132, a channel layer 142, one scan line SL, a shared distribution CL, a plurality of first subdata line segment 162, one source pole 164a, drain 164b, a storage capacitors electrode 166 and an ohmic contact layer 152 on substrate 110.Wherein, the step that forms above-mentioned each rete and material all with first embodiment in the step shown in Figure 1A to 1D and Fig. 2 A similar, do not add to give unnecessary details in this.
Please refer to Fig. 3 E then, on substrate 110, form a protective layer 170 and one second patterning photoresist layer 220b in regular turn.Wherein, the step of formation protective layer 170 and material and first embodiment are similar, do not add to give unnecessary details in this.Then, serve as that cover curtain carries out one the 3rd and removes technology with the second patterning photoresist layer 220b, to remove the protective layer 170 of part.Then, please refer to Fig. 3 F and Fig. 4 B, protective layer 170 meetings form a plurality of contact windows 172, with the first subdata line segment 162, the source electrode 164a of part, the drain electrode 164b of part and the storage capacitors electrode 166 of part that exposes part.Then, remove the second patterning photoresist layer 220b.
It should be noted that compared to first embodiment, because the opening 222 of the second patterning photoresist layer 220b among second embodiment only exposes the protective layer 170 than small part.Therefore, carry out the 3rd remove technology after, the contact window 172 of protective layer 170 only exposes second metal material layer 160 than small part.And, because protective layer 170 can cover first fully and remove the substrate 110 that is exposed after the technology.Therefore, first removes and can not need in the technology first metal material layer, 120 over etchings, to form lateral erosion depression 124.
Then please refer to Fig. 3 G, on substrate 110, form a pixel electrode material layer 180 and the 3rd patterning photoresist layer 230 in regular turn.Wherein, the step of formation pixel electrode material layer 180 and material and first embodiment are similar, do not add to give unnecessary details in this.Then, please refer to Fig. 3 H, serves as that the cover curtain carries out patterning to pixel electrode material layer 180 with the 3rd patterning photoresist layer 230, to form a pixel electrode 182.At this moment, can form a storage capacitors between shared distribution CL and the pixel electrode 182.Then, remove the 3rd patterning photoresist layer 230.
In addition, please refer to Fig. 4 C, when pixel electrode material layer 180 is carried out patterning, can also in the data wire presumptive area 112 on the substrate 110, form a plurality of second subdata line segments 184 in the lump by the bearing of trend along these first subdata line segments 162.Wherein, pixel electrode 182 is formed by pixel electrode material layer 180 with these second subdata line segments 184, and pixel electrode 182 is electrically connected to the 164b that drains, and the second subdata line segment 184 one of them be electrically connected to source electrode 164a.Moreover these second subdata line segments 184 are electrically connected between the two first subdata line segments 162, to form a data wire DL.So far above-mentioned, the manufacture method of active elements array substrates of the present invention is only passed through three road photo-marsk processes, and cooperates the suitable technology that removes, and active elements array substrates 100b of the present invention can be completed.Therefore, the manufacture method of active elements array substrates of the present invention can effectively reduce manufacturing cost.
In sum, because the manufacture method of active elements array substrates of the present invention adopts multiple penetration photomask to come first photoresist layer is carried out patterning, this can make the first patterning photoresist layer can have two kinds of different thickness.Therefore, remove technology and just can produce grid, gate insulation layer, channel layer and source electrode and drain electrode as long as collocation is suitable by one photo-marsk process.Also therefore, the manufacture method of active elements array substrates of the present invention only needs two roads or three road photo-marsk processes to finish.This not only can effectively reduce the process time, also can effectively reduce manufacturing cost, and then reaches the purpose that promotes production capacity.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (27)
1. the manufacture method of an active elements array substrates comprises:
One substrate and a multiple penetration photomask are provided;
On this substrate, form one first metal material layer;
On this first metal material layer, form a gate insulation material layer;
On this gate insulation material layer, form a channel material layer;
On this channel material layer, form one second metal material layer;
On this second metal material layer, form one first photoresist layer, and this first photoresist layer is carried out patterning by this multiple penetration photomask, to form one first patterning photoresist layer, wherein this first patterning photoresist layer has a recess patterns, and this second metal material layer of part is exposed to outside this first patterning photoresist layer;
With this first patterning photoresist layer serves as that cover curtain carries out one first and removes technology, removing not this second metal material layer, this channel material layer, this gate insulation material layer and this first metal material layer that is covered by this first patterning photoresist layer, and then form a grid, a gate insulation layer and a channel layer;
Carry out one second and remove technology, with the recess patterns that removes this first patterning photoresist layer and to this second metal material layer that should the recess patterns below, and then form an one source pole and a drain electrode, and expose this channel layer of part;
Remove this first patterning photoresist layer;
On this substrate, form a protective layer, with this substrate of cover part, this source electrode and should drain electrode and this channel layer of part;
Form one second patterning photoresist layer on this protective layer, wherein this protective layer corresponding to this source electrode and this drain electrode top is exposed to outside this second patterning photoresist layer;
With this second patterning photoresist layer serves as that cover curtain carries out one the 3rd and removes technology, removing this protective layer of part, and forms a plurality of contact windows, to expose this source electrode and this drain electrode;
On this protective layer, form a pixel electrode material layer, to cover this second patterning photoresist layer and this source electrode and this drain electrode that expose; And
Peel off this second patterning photoresist layer, to remove this pixel electrode material layer that is positioned on this second patterning photoresist layer, to form a pixel electrode.
2. the manufacture method of active elements array substrates as claimed in claim 1 is characterized in that, this multiple penetration photomask comprises semi-modulation type photomask.
3. the manufacture method of active elements array substrates as claimed in claim 1 is characterized in that, this first removes technology and also comprise this first metal material layer over etching, forms lateral erosion depression with the lateral margin in this grid.
4. the manufacture method of active elements array substrates as claimed in claim 1 is characterized in that, when forming this grid, also comprise forming a shared distribution and one scan line in the lump, and this scan line and the electric connection of this grid.
5. the manufacture method of active elements array substrates as claimed in claim 4 is characterized in that, when forming this source electrode and should drain, also is included in this shared distribution top and forms a storage capacitors electrode in the lump.
6. the manufacture method of active elements array substrates as claimed in claim 1 is characterized in that, when forming this grid, also comprises forming a plurality of first subdata line segments in the lump.
7. the manufacture method of active elements array substrates as claimed in claim 6; it is characterized in that; when on this protective layer, forming this pixel electrode; also comprise along the bearing of trend of those first subdata line segments and form a plurality of second subdata line segments in the lump; one of them this contact window via correspondence of those second subdata line segments is electrically connected to this source electrode, and those second subdata line segments and those first subdata line segments electrically connect to form a data wire.
8. the manufacture method of active elements array substrates as claimed in claim 7 is characterized in that, those second subdata line segments are electrically connected between the two first subdata line segments by those contact windows of this protective layer part.
9. the manufacture method of active elements array substrates as claimed in claim 1 is characterized in that, this first removes technology and comprise wet etching process.
10. the manufacture method of active elements array substrates as claimed in claim 1 is characterized in that, this second removes technology and comprise dry etching process.
11. the manufacture method of active elements array substrates as claimed in claim 1 is characterized in that, after forming this channel material layer, also is included in and forms an ohmic contact material layer on this channel material layer.
12. the manufacture method of active elements array substrates as claimed in claim 11 is characterized in that, this second remove technology also comprise remove the part this ohmic contact material layer, to form an ohmic contact layer.
13. the manufacture method of an active elements array substrates comprises:
One substrate and a multiple penetration photomask are provided;
On this substrate, form one first metal material layer;
On this first metal material layer, form a gate insulation material layer;
On this gate insulation material layer, form a channel material layer;
On this channel material layer, form one second metal material layer;
On this second metal material layer, form one first photoresist layer, and this first photoresist layer is carried out patterning by this multiple penetration photomask, to form one first patterning photoresist layer, wherein this first patterning photoresist layer has a recess patterns, and this second metal material layer of part is exposed to outside this first patterning photoresist layer;
With this first patterning photoresist layer serves as that cover curtain carries out one first and removes technology, removing not this second metal material layer, this channel material layer, this gate insulation material layer and this first metal material layer that is covered by this first patterning photoresist layer, and then form a grid, a gate insulation layer and a channel layer;
Carry out one second and remove technology, with the recess patterns that removes this first patterning photoresist layer and to this second metal material layer that should the recess patterns below, and then form an one source pole and a drain electrode, and expose this channel layer of part;
Remove this first patterning photoresist layer;
On this substrate, form a protective layer, with this substrate of cover part, this source electrode and should drain electrode and this channel layer of part;
Form one second patterning photoresist layer on this protective layer, wherein this protective layer corresponding to this source electrode and this drain electrode top is exposed to outside this second patterning photoresist layer;
With this second patterning photoresist layer serves as that cover curtain carries out one the 3rd and removes technology, removing this protective layer of part, and forms a plurality of contact windows, to expose this source electrode and this drain electrode;
Remove this second patterning photoresist layer; And
On this protective layer, form a pixel electrode, insert those contact openings, and electrically connect with this drain electrode.
14. the manufacture method of active elements array substrates as claimed in claim 13 is characterized in that, this multiple penetration photomask comprises semi-modulation type photomask.
15. the manufacture method of active elements array substrates as claimed in claim 13 is characterized in that, when forming this grid, also comprises forming an one scan line and a shared distribution in the lump, and this scan line and the electric connection of this grid.
16. the manufacture method of active elements array substrates as claimed in claim 15 is characterized in that, when forming this source electrode and should drain, also is included in this shared distribution top and forms a storage capacitors electrode in the lump.
17. the manufacture method of active elements array substrates as claimed in claim 13 is characterized in that, when forming this grid, also comprises forming a plurality of first subdata line segments in the lump.
18. the manufacture method of active elements array substrates as claimed in claim 17; it is characterized in that; when on this protective layer, forming this pixel electrode; also comprise along the bearing of trend of those first subdata line segments and form a plurality of second subdata line segments in the lump; one of them this contact window via correspondence of those second subdata line segments is electrically connected at this source electrode, and those second subdata line segments and those first subdata line segments electrically connect to form a data wire.
19. the manufacture method of active elements array substrates as claimed in claim 18 is characterized in that, those second subdata line segments are electrically connected between the two first subdata line segments by those contact windows of this protective layer part.
20. the manufacture method of active elements array substrates as claimed in claim 13 is characterized in that, this first removes technology and comprises wet etching process.
21. the manufacture method of active elements array substrates as claimed in claim 13 is characterized in that, this second removes technology and comprises dry etching process.
22. the manufacture method of active elements array substrates as claimed in claim 13 is characterized in that, after forming this channel material layer, also is included in and forms an ohmic contact material layer on this channel material layer.
23. the manufacture method of active elements array substrates as claimed in claim 22 is characterized in that, this second remove technology also comprise remove the part this ohmic contact material layer, to form an ohmic contact layer.
24. the manufacture method of active elements array substrates as claimed in claim 13 is characterized in that, the step that forms this pixel electrode comprises:
On this protective layer, form a pixel electrode material layer, to cover this protective layer and this source electrode and this drain electrode that expose;
On this protective layer, form one the 3rd patterning photoresist layer; And
With the 3rd patterning photoresist layer serves as that the cover curtain carries out patterning to this pixel electrode material layer, to form this pixel electrode.
25. an active elements array substrates comprises:
One substrate;
The one scan line is disposed on this substrate;
One active element is disposed on this substrate, and this active element comprises:
One grid is disposed on this substrate, and electrically connects with this scan line, and the lateral margin of this grid
Has lateral erosion depression;
One gate insulation layer is disposed on this grid;
One channel layer is disposed on this gate insulation layer;
An one source pole and a drain electrode are disposed at the both sides on this channel layer respectively;
One protective layer covers this active element and this scan line, and this protective layer has a plurality of contact windows, and those contact windows of part expose this source electrode and this drain electrode;
One pixel electrode is disposed on this protective layer, and electrically connects with this drain electrode by those contact windows of part;
A plurality of first subdata line segments; And
A plurality of second subdata line segments, those first subdata line segments and this source electrode and this drain electrode are positioned at the same film layer, this second subdata line segment is positioned at identical rete with this pixel electrode, wherein those second subdata line segments are electrically connected between the two first subdata line segments by those contact windows of part, forming a data wire, and one of them this contact window via correspondence of those second subdata line segments is electrically connected to this source electrode.
26. active elements array substrates as claimed in claim 25 is characterized in that, also comprises a shared distribution, be disposed on this substrate, and this shared distribution is positioned at identical rete with this grid.
27. active elements array substrates as claimed in claim 25; it is characterized in that; also comprise a storage capacitors electrode; be disposed at this shared distribution top; and this protective layer is between this storage capacitors electrode and this pixel electrode, this pixel electrode by those corresponding contact windows one of them and electrically connect with this storage capacitors electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810081743 CN101527281B (en) | 2008-03-07 | 2008-03-07 | Active element array substrate and method for manufacturing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810081743 CN101527281B (en) | 2008-03-07 | 2008-03-07 | Active element array substrate and method for manufacturing same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101527281A CN101527281A (en) | 2009-09-09 |
| CN101527281B true CN101527281B (en) | 2011-01-19 |
Family
ID=41095070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810081743 Active CN101527281B (en) | 2008-03-07 | 2008-03-07 | Active element array substrate and method for manufacturing same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101527281B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104122723B (en) * | 2014-07-01 | 2016-08-17 | 深圳市华星光电技术有限公司 | Array base palte and preparation method thereof |
| CN111725135B (en) * | 2020-06-30 | 2023-08-29 | 昆山龙腾光电股份有限公司 | Manufacturing method of array substrate and array substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127322A (en) * | 2006-08-15 | 2008-02-20 | 中华映管股份有限公司 | Pixel structure and its making method |
| CN101136376A (en) * | 2007-09-26 | 2008-03-05 | 友达光电股份有限公司 | Pixel structure and manufacturing method therefor |
-
2008
- 2008-03-07 CN CN 200810081743 patent/CN101527281B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127322A (en) * | 2006-08-15 | 2008-02-20 | 中华映管股份有限公司 | Pixel structure and its making method |
| CN101136376A (en) * | 2007-09-26 | 2008-03-05 | 友达光电股份有限公司 | Pixel structure and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101527281A (en) | 2009-09-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5564464B2 (en) | TFT-LCD array substrate and manufacturing method thereof | |
| CN102034750B (en) | Array substrate and manufacturing method thereof | |
| CN100576550C (en) | Thin-film transistor array base-plate and manufacture method thereof | |
| CN100580937C (en) | Thin film transistor array substrate and method of manufacturing the same | |
| CN102856389B (en) | Thin film transistor and method of manufacturing the same | |
| JP4691681B2 (en) | Thin film transistor array substrate and manufacturing method thereof | |
| US20130140574A1 (en) | Thin film transistor array substrate and method for manufacturing the same and electronic device | |
| US10663820B2 (en) | Display substrate, its manufacturing method, and display device | |
| WO2021077673A1 (en) | Array substrate manufacturing method, and array substrate | |
| CN102683341B (en) | TFT (Thin Film Transistor) array substrate and manufacturing method thereof as well as liquid crystal display | |
| WO2021077674A1 (en) | Method for manufacturing array substrate, and array substrate | |
| CN210272363U (en) | Array substrate and display panel | |
| CN101236932A (en) | Thin film transistor array base plate making method | |
| CN102456620B (en) | Array substrate and manufacturing method thereof | |
| CN102956550A (en) | Method for manufacturing active array substrate and active array substrate | |
| US11114476B2 (en) | Manufacturing method of TFT array substrate, TFT array substrate and display panel | |
| CN110620080A (en) | Manufacturing method of array substrate, array substrate and display panel | |
| CN101527281B (en) | Active element array substrate and method for manufacturing same | |
| US7763416B2 (en) | Fabrication method of active device array substrate | |
| CN101425481B (en) | Pixel construction and manufacturing method thereof | |
| CN104637872A (en) | Method for manufacturing oxide semiconductor thin film transistor array substrate | |
| CN101976650A (en) | Thin film transistor and manufacture method thereof | |
| CN102637631B (en) | Manufacturing method of TFT (thin film transistor)-LCD (liquid crystal display) array substrate | |
| CN104733384B (en) | Display base plate and its manufacture method, display device | |
| CN101409262B (en) | Pixel structure manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20160812 Address after: The Marshall Islands Majuro Adger Island Road trust company Tektronix Tektronix Adger areas MH96960 Patentee after: Hao Chi intangible asset management Investment Limited Address before: Taiwan, Taipei, China Zhongshan North Road three paragraph twenty-two Patentee before: Chunghwa Picture Tubes Ltd. |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20161205 Address after: 430070 Hubei City, Wuhan Province, East Lake Development Zone, high tech Avenue, No. 666 biological city C5 building, Patentee after: Wuhan Hua Xing photoelectricity technology corporation, Ltd. Address before: The Marshall Islands Majuro Adger Island Road trust company Tektronix Tektronix Adger areas MH96960 Patentee before: Hao Chi intangible asset management Investment Limited |