CN210272363U - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
- Publication number
- CN210272363U CN210272363U CN201921788756.1U CN201921788756U CN210272363U CN 210272363 U CN210272363 U CN 210272363U CN 201921788756 U CN201921788756 U CN 201921788756U CN 210272363 U CN210272363 U CN 210272363U
- Authority
- CN
- China
- Prior art keywords
- electrode
- drain
- source
- array substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 156
- 238000000034 method Methods 0.000 claims abstract description 115
- 230000008569 process Effects 0.000 claims abstract description 96
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 76
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 238000001259 photo etching Methods 0.000 claims abstract description 28
- 238000000206 photolithography Methods 0.000 claims description 44
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 14
- 239000004973 liquid crystal related substance Substances 0.000 claims description 12
- 239000011787 zinc oxide Substances 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 35
- 238000009413 insulation Methods 0.000 abstract 3
- 230000005611 electricity Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 190
- 229910052751 metal Inorganic materials 0.000 description 50
- 239000002184 metal Substances 0.000 description 50
- 229920002120 photoresistant polymer Polymers 0.000 description 28
- 238000000151 deposition Methods 0.000 description 23
- 238000010586 diagram Methods 0.000 description 19
- 239000010408 film Substances 0.000 description 17
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 13
- 238000005530 etching Methods 0.000 description 9
- 229910004205 SiNX Inorganic materials 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 239000011241 protective layer Substances 0.000 description 8
- 239000011521 glass Substances 0.000 description 7
- 150000002739 metals Chemical class 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 5
- 239000012495 reaction gas Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000002207 thermal evaporation Methods 0.000 description 5
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 229910020923 Sn-O Inorganic materials 0.000 description 2
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000005300 metallic glass Substances 0.000 description 1
- 239000002052 molecular layer Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The utility model provides an array substrate and display panel, array substrate includes the substrate base plate, the metal oxide semiconductor figure, the pixel electrode, the source electrode, the drain electrode, grid insulation layer and grid, the metal oxide semiconductor figure, pixel electrode and source electrode and drain electrode all set up on the substrate base plate, the at least partial structure of source electrode and drain electrode sets up on the metal oxide semiconductor, the drain electrode is connected with the pixel electrode electricity, and pixel electrode and source electrode, the drain electrode forms in same photoetching process, the grid insulation layer covers on the substrate base plate that is equipped with the metal oxide semiconductor figure, the pixel electrode, the source electrode, the drain electrode, the grid sets up on grid insulation layer. The utility model discloses can reduce the number of times of photoetching process, simple process, the cost of manufacture is low.
Description
Technical Field
The utility model relates to a liquid crystal display field especially relates to an array substrate and display panel.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Displays (LCDs) have the advantages of high image quality, power saving, thin body, and no radiation, and are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, and notebook computers, and become the mainstream of Display devices. The liquid crystal display panel generally comprises an array substrate, a color filter substrate and a liquid crystal molecular layer sandwiched between the array substrate and the color filter substrate, which are oppositely arranged. The liquid crystal molecules can be controlled to rotate by applying a driving voltage between the array substrate and the color film substrate, so that light rays of the backlight module are refracted out to generate a picture.
The manufacturing method of the array substrate provided in the prior art includes five photolithography processes, which is described by taking an array substrate with a thin film transistor as a top gate structure as an example, and includes: the first step is as follows: depositing a metal oxide semiconductor layer on a substrate, and carrying out first photoetching to form a metal oxide semiconductor pattern; depositing a source metal layer and a drain metal layer in sequence, and carrying out second photoetching to form a source, a drain and a channel between the source and the drain; depositing a grid electrode insulating layer and a grid electrode metal layer in sequence, and carrying out third photoetching to form a grid electrode; depositing a passivation layer and a planarization layer, and carrying out fourth photoetching to form a conductive through hole; and fifthly, depositing a transparent conductive film, and carrying out fifth photoetching to form a pixel electrode and a communication pattern of the conductive via hole and the pixel electrode.
The five times of photoetching process procedures provided by the prior art have complex process and high manufacturing cost.
SUMMERY OF THE UTILITY MODEL
The utility model provides an array substrate and display panel can reduce the number of times of photoetching process, simple process, and the cost of manufacture is low.
In a first aspect, the present invention provides an array substrate, including a substrate, a metal oxide semiconductor pattern, a pixel electrode, a source electrode, a drain electrode, a gate insulating layer and a gate, the metal oxide semiconductor pattern, the pixel electrode and the source electrode and the drain electrode are all disposed on the substrate, at least a part of the structure of the source electrode and the drain electrode is disposed on the metal oxide semiconductor, the drain electrode is electrically connected to the pixel electrode, and the pixel electrode and the source electrode, the drain electrode are formed in the same photolithography process, the gate insulating layer covers on the substrate that is provided with the metal oxide semiconductor pattern, the pixel electrode, the source electrode, the drain electrode, and the gate is disposed on the gate insulating layer.
Optionally, at least a part of the drain electrode covers the pixel electrode, so that the drain electrode is electrically connected with the pixel electrode.
Optionally, the semiconductor device further comprises a source buffer layer and a drain buffer layer insulated from each other, the source buffer layer and the drain buffer layer cover a portion of the substrate and cover a portion of the metal oxide semiconductor pattern, and the source buffer layer and the drain buffer layer are spaced between portions above the metal oxide semiconductor pattern to form a channel region, the source and the drain being disposed on the source buffer layer and the drain buffer layer, respectively.
Optionally, the source buffer layer, the drain buffer layer and the pixel electrode are formed in the same photolithography process.
Optionally, the source buffer layer and the drain buffer layer are formed by depositing the same material as the pixel electrode.
Optionally, the source buffer layer and the drain buffer layer are made of the same material as the pixel electrode, and the source buffer layer and the drain buffer layer are formed after the material is made into a conductor.
Optionally, first via holes respectively extending to the source and the drain are further formed on the gate insulating layer.
Optionally, the metal oxide semiconductor is indium gallium zinc oxide IGZO.
Optionally, the pixel electrode is an indium tin oxide ITO film.
In a second aspect, the present invention provides a display panel, including various membrane base plate, liquid crystal layer and foretell array substrate, the liquid crystal layer clamp is established between various membrane base plate and array substrate.
The embodiment of the utility model provides an array substrate and display panel, through forming transparent conducting layer in source drain metal level below, consequently can form pixel electrode simultaneously in same photoetching technology, source electrode and drain electrode, this and among the prior art pixel electrode form in planarization layer top, source electrode and drain electrode form in planarization layer below, need form pixel electrode in twice photoetching technology, the condition of source electrode and drain electrode is compared, the number of times of photoetching technology has been reduced, therefore simple process, the cost of manufacture is low.
Drawings
In order to illustrate the technical solutions of the present invention or the prior art more clearly, the drawings needed for the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic flow chart illustrating a manufacturing method of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an array substrate in a first state in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an array substrate in a second state in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 4a is a schematic structural diagram of the array substrate after exposure and development in the second photolithography process in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 4b is a schematic structural diagram of the array substrate after the first etching in the second photolithography process in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 4c is a schematic structural diagram of the array substrate after the second etching in the second photolithography process in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 4d is a schematic structural diagram of the array substrate in a third state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 5 is a schematic structural diagram of an array substrate in a fourth state in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 6 is a schematic top view illustrating a fourth state of an array substrate in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an array substrate in a fifth state in a manufacturing method of the array substrate according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention.
Reference numerals:
1-a substrate base plate; 2-metal oxide semiconductor pattern; 3-a pixel electrode; 3' -a transparent conductive layer; 4-protecting the pattern; 5-a source electrode; 5' -source drain metal layer; 51-source buffer layer; 6-a drain electrode; 61-a drain buffer layer; 7-a gate insulating layer; 8-a grid; 9-a first via; 10-a channel; 11-a glass substrate; 12-a modification layer; 13-a metal oxide protective layer; 14-a second via; 80-a first photoresist pattern; 81-complete photoresist retention area; 82-photoresist portion retention area; 83-area of complete removal of photoresist; 84-first photoresist pattern after ashing.
Detailed Description
To make the objects, technical solutions and advantages of the present invention clearer, the drawings of the present invention are combined to clearly and completely describe the technical solutions of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Example one
Fig. 1 is a schematic flow chart of a manufacturing method of an array substrate according to an embodiment of the present invention, as shown in fig. 1, the manufacturing method of an array substrate of this embodiment includes:
and S10, depositing a metal oxide semiconductor layer on the substrate, and carrying out a first photoetching process to form a metal oxide semiconductor pattern on the substrate.
The substrate 1 may comprise a glass substrate 11 and a modification layer 12, and the substrate 1 may be formed by, for example, first depositing the substrate on a transparent glass substrate 11 or quartz by a plasma-enhanced chemical vapor deposition method to a thickness of
The modification layer 12 may be an oxide, a nitride or an oxynitride, and when a nitride is used, SiNxThe gas corresponding to the film is SiH4，NH3，N2Or SiH2Cl2，NH3，N2，SiNxOYThe gases of the film are: SiH4、NH3、N2O、N2；SiOxThe corresponding reaction gas is SiH4、N2O、N2。
The modified layer 12 may be a single layer or a multilayer, and preferably a double layer of SiN is usedxAnd SiOxThin film, in contact with the glass substrate 11, is SiNxOn which is SiOx. Wherein, in order to improve the performance of the TFT device, SiOxHas a thickness of
After the base substrate 1 is formed, a metal oxide semiconductor layer is deposited on the base substrate 1, and a first photolithography process is performed to form a metal oxide semiconductor pattern 2 on the base substrate 1. In particular, a layer having a thickness of
The metal oxide semiconductor layer (2) may be Indium Gallium Zinc Oxide (IGZO), or Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4ZnO: al, TiO 2: nb, Cd-Sn-O or other metal oxides; the above-mentioned oxide may be an amorphous metal oxide and may be a polycrystalline metal oxide. The first photolithography process may be a general photolithography process, or may be a halftone mask process or a gray tone mask process.
And S20, sequentially depositing a transparent conducting layer and a source and drain electrode metal layer on the substrate with the metal oxide semiconductor pattern, and carrying out a second photoetching process to form a pixel electrode, a source electrode and a drain electrode.
Specifically, the thickness of the film is about the same by adopting a sputtering or thermal evaporation method to sequentially deposit
And a transparent conductive layer 3' having a thickness of about
The source-drain metal layer 5 'and the transparent conductive layer 3' are generally ITO or IZO, and may be other metals and metal oxides; the source and drain metal layer 5' may be Cr, W, Ti, Ta, Mo, Al, Cu or other metal or alloy, and the metal layer comprising several layers of metal may also meet the requirement.
Specifically, optionally, the second photolithography process is performed by a halftone mask process or a gray tone mask process, and the performing of the second photolithography process to form the pixel electrode 3, the source electrode 5, and the drain electrode 6 specifically includes:
the transparent conductive layer 3 'and the source-drain metal layer 5' are etched to form a channel 10 between the source 5 and the drain 6 and a first layer structure, wherein the first layer structure corresponds to the source, the drain, and the pixel electrode, that is, the first layer structure is a portion of the transparent conductive layer 3 'and the source-drain metal layer 5' corresponding to a region where the source 5, the drain 6, and the pixel electrode 3 are to be formed. And the first layer structure is etched to form the source electrode 5, the drain electrode 6, and the pixel electrode 3.
By forming the transparent conductive layer 3 'under the source-drain metal layer 5', the pixel electrode 3, the source electrode 5, and the drain electrode 6 can be formed in the same photolithography process, i.e., in the second photolithography process.
And S30, sequentially depositing a gate insulating layer and a gate metal layer on the substrate with the pixel electrode, the source electrode and the drain electrode, and performing a third photolithography process to form a first via hole and a gate electrode, wherein the first via hole penetrates through the gate insulating layer and extends to the source electrode and the drain electrode.
Specifically, the plasma enhanced chemical vapor deposition method is used for continuously depositing the film with the thickness of
The gate insulating layer 7 may be an oxide, a nitride, or an oxynitride, wherein SiN is used as the gate insulating layer 7xThe film gas is SiH4，NH3，N2Or SiH2Cl2，NH3，N2，SiNxOYThe gases of the film are: SiH4、NH3、N2O、N2；SiOxThe corresponding reaction gas is SiH4、N2O、N2. In addition, the thickness of the film is about the same by sputtering or thermal evaporation
The gate metal layer of (1) can be Cr, W, Ti, Ta, Mo, Al, Cu and other metals or alloys, and the gate metal layer consisting of multiple layers of metals can also meet the requirement. In addition, the third photolithography process can be performed by a halftone mask process or a gray tone mask process in the same photolithography processWhile simultaneously forming the first via 9 and the gate 8.
Specifically, optionally, performing a third photolithography process to form the first via hole 9 and the gate 8 specifically includes:
etching the gate insulating layer 7 and the gate metal layer to form a first via hole 9; and the gate metal layer is etched to form the gate 8. The first via hole 9 penetrates through the gate insulating layer 7 and extends to the source electrode 5 and the drain electrode 6, so that the source electrode 5 and the drain electrode 6 can be electrically connected with a circuit around the thin film transistor.
In the above method, the transparent conductive layer 3 'is formed below the source-drain metal layer 5', so that the pixel electrode 3, the source electrode 5, and the drain electrode 6 can be simultaneously formed in the same photolithography process, which reduces the number of photolithography processes for one time compared with the case in the prior art in which the pixel electrode 3 is formed above the planarization layer, and the source electrode 5 and the drain electrode 6 are formed below the planarization layer, and the pixel electrode 3, the source electrode 5, and the drain electrode 6 need to be formed in two photolithography processes, so that the process is simple and the manufacturing cost is low.
Further, after depositing the metal oxide semiconductor layer on the substrate base plate 1, the method further comprises: depositing a protective layer on the metal oxide semiconductor layer, and forming a metal oxide semiconductor pattern 2 and a protective pattern 4 on the substrate base plate 1 in a first photoetching process, wherein the protective pattern 4 is used for protecting the metal oxide semiconductor layer; after that, a transparent conductive layer 3 'and a source-drain metal layer 5' are sequentially deposited on the substrate base plate 1 on which the metal oxide semiconductor pattern 2 and the protective pattern 4 are formed. Specifically, the plasma enhanced chemical vapor deposition method is used for continuously depositing the film with the thickness of
The reaction gas corresponding to the protective layer can be SiH4，N2O，N2The protective layer is also called an etching barrier layer to prevent the metal oxide semiconductor layer from being damaged when the source electrode 5, the drain electrode 6 and the pixel electrode 3 are formed by etching after the metal oxide semiconductor pattern 2 is formed. In addition, the first photoetching process can be carried out through a half-tone maskA process or a gray-tone mask process is performed to form the metal oxide semiconductor pattern 2 and the protective pattern 4 in the same photolithography process.
The following describes a manufacturing process of the array substrate according to the present invention by taking a specific example.
The method comprises the following steps: and depositing a modification layer on the glass substrate. Fig. 2 is a schematic structural diagram of the array substrate in the first state in the manufacturing method of the array substrate according to the embodiment of the present invention, as shown in fig. 2, a modification layer 12 is continuously deposited on a glass substrate 11 by a plasma enhanced chemical vapor deposition method, so as to form a substrate 1 as shown in fig. 2.
Step two: and sequentially depositing a metal oxide semiconductor layer and a protective layer on the substrate, and carrying out a first photoetching process to form a metal oxide semiconductor pattern and a protective pattern on the substrate. Fig. 3 is a schematic structural diagram of the array substrate in the second state in the manufacturing method of the array substrate according to the first embodiment of the present invention, as shown in fig. 3, a metal oxide semiconductor layer is deposited by sputtering or thermal evaporation method on the basis of the array substrate in the first state, and then a protective layer is continuously deposited by a vapor deposition method of plasma enhanced chemistry. Then, a metal oxide semiconductor pattern 2 and a protection pattern 4 are formed on the substrate base plate 1 through a first photolithography process, wherein the first photolithography process is performed through a halftone mask process or a gray tone mask process.
Step three: and sequentially depositing a transparent conducting layer and a source and drain electrode metal layer on the substrate with the metal oxide semiconductor pattern and the protection pattern, and carrying out a second photoetching process to form a pixel electrode, a source electrode and a drain electrode. Fig. 4a is the array substrate's structure schematic diagram after exposure and development in the array substrate's manufacturing method, the lithography process of the second time that embodiment a provides, fig. 4b is the utility model provides an in the array substrate's manufacturing method, the array substrate's structure schematic diagram after the first time sculpture in the lithography process of the second time, fig. 4c is the utility model provides an in the array substrate's manufacturing method, the array substrate's structure schematic diagram after the second time sculpture in the lithography process of the second time that embodiment a provides, fig. 4d is the utility model provides a structure schematic diagram when array substrate is in the third state in the array substrate's manufacturing method that embodiment a provides.
As shown in fig. 4a, firstly, on the basis of the array substrate in the second state, a transparent conductive layer 3 'and a source/drain metal layer 5' are sequentially deposited by a sputtering or thermal evaporation method, then a photoresist is coated, and a first photoresist pattern 80 is formed by a patterning process, for example, exposure and development, wherein the first photoresist pattern 80 includes a photoresist complete-retention region 81, a photoresist partial-retention region 82, and a photoresist complete-removal region 83, the photoresist complete-retention region 81 corresponds to a region where the source electrode 5 and the drain electrode 6 are to be formed, and the photoresist partial-retention region 82 corresponds to a region where the pixel electrode 3 is to be formed.
As shown in fig. 4b, the transparent conductive layer 3 'and the source/drain metal layer 5' are etched using the first photoresist pattern 80 as a mask to form a channel 10 between the source 5 and the drain 6 and a first layer structure, where the first layer structure is a portion of the transparent conductive layer 3 'and the source/drain metal layer 5' corresponding to a region where the source 5, the drain 6 and the pixel electrode 3 are to be formed.
As shown in fig. 4c, the first photoresist pattern 80 is ashed to remove the photoresist in the photoresist partial-remaining region 82 and to reduce the photoresist in the photoresist full-remaining region 81, and the first layer structure is etched using the ashed first photoresist pattern 84 as a mask to form the source electrode 5, the drain electrode 6, and the pixel electrode 3. The first layer structure is a transparent conductive layer 3 'and a portion of the source/drain metal layer 5' corresponding to a region where the source electrode 5, the drain electrode 6, and the pixel electrode 3 are to be formed.
The photoresist is then stripped to form the array substrate in the third state as shown in fig. 4 d.
In the third step, when the corresponding source/drain metal layer 5 ' above the pixel electrode 3 is etched away in the process of etching the first layer structure, the transparent conductive layer 3 ' is partially formed 'Under the region where the source electrode 5 and the drain electrode 6 are to be formed, so that the portion of the transparent conductive layer 3' is not etched after the final etching is completed, thereby forming a source buffer layer 51 between the source electrode 5 and the base substrate 1, and a drain buffer layer 61 between the drain electrode 6 and the base substrate 1, it is noted that the source buffer layer 51 and the drain buffer layer 61 are electrically insulated from each other, and further, the drain buffer layer 61 and the pixel electrode 3 are integrally formed. Since the metal constituting the source electrode 5 and the drain electrode 6 is, for example, Al, Cu or the like, which has a strong activity, when the source electrode 5 and the drain electrode 6 are directly in contact with the metal oxide semiconductor pattern 2, the metal is easily bonded to oxygen in the metal oxide semiconductor to form a corresponding oxide, for example, Al2O3And CuO, etc., to damage the metal oxide semiconductor, in the above method, the source buffer layer 51 is formed between the source 5 and the base substrate 1 to perform an isolation function, and the drain buffer layer 61 is formed between the drain 6 and the base substrate 1 to perform an isolation function, thereby effectively preventing the above-mentioned occurrence. Meanwhile, the source buffer layer 51, the drain buffer layer 61 and the pixel electrode 3 may be made of the same material and formed in the same photolithography process, so that the number of photolithography processes may be reduced, and the cost may be reduced.
Of course, the source buffer layer 51 and the drain buffer layer 61 may also be formed by using different materials, for example, a transparent conductive layer 3 'is deposited on the array substrate in the second state shown in fig. 3, then the regions of the transparent conductive layer 3' corresponding to the source electrode 5 and the drain electrode 6 are conducted to be conductive, and then the source buffer layer 51 and the drain buffer layer 61 are finally formed through the same process as described above, so that the source buffer layer 51 and the drain buffer layer 61 with different materials and different pixel electrodes can be formed. The conductor formation method may use a conventional method, for example, a method of forming a conductor by introducing hydrogen gas after depositing the transparent conductive layer 3'. After the formation of the source buffer layer 51 and the drain buffer layer 61, which are made of conductive materials, a source/drain metal layer 5' is deposited, and the formation processes of the remaining source and drain electrodes are similar to those described above, and thus, the description thereof is omitted.
In addition, in the third step, since the photoresist completely removed region corresponds to the region where the channel 10 is to be formed, the region of the channel 10 can be directly formed in the first etching of the transparent conductive layer 3 'and the source/drain metal layer 5', thereby avoiding the occurrence of over-etching of the channel region in the conventional photolithography process and improving the yield of the product.
In addition, in practice, the array substrate may include a plurality of sub-pixel regions defined by scan lines and data lines, each of the sub-pixel regions is provided with a thin film transistor device, for convenience of description, in the drawings of the present application, a schematic diagram of manufacturing only one of the sub-pixel regions is drawn, it can be understood that the array substrate in the present application includes a plurality of sub-pixel regions, and therefore, in the manufacturing process of the array substrate in the present application, the reference to forming the source electrode 5 and the drain electrode 6 on the substrate 1 specifically means forming the source electrode 5 and the drain electrode 6 in the regions of the array substrate corresponding to each of the sub-pixel regions. The pixel electrode 3, the gate 8 and the metal oxide pattern are similar to those described above, and are not described herein again. In addition, in the third step of the present application, for convenience of description, a process of forming a thin film transistor in an array substrate is described, and a forming step of a data line is not included, and actually, the data line and the source electrode 5 are simultaneously formed in the same photolithography process, for example, the photoresist completely-remaining region 81 corresponds to a region where the source electrode 5, the drain electrode 6, and the data line are to be formed, the photoresist partially-remaining region 82 corresponds to a region where the pixel electrode 3 is to be formed, and the photoresist completely-removed region 83 corresponds to a region on the entire surface of the photoresist except for the photoresist completely-remaining region 81 and the photoresist partially-remaining region 82. At this time, the first layer structure includes portions of the transparent conductive layer 3 'and the source-drain metal layer 5' corresponding to regions where the source electrode 5, the drain electrode 6, the data line, and the pixel electrode 3 are to be formed.
Step four: and sequentially depositing a gate insulating layer and a gate metal layer on the substrate with the pixel electrode, the source electrode and the drain electrode, and carrying out a third photoetching process to form a first through hole and a gate. Fig. 5 is a schematic structural diagram of the array substrate in the fourth state in the manufacturing method of the array substrate provided by the first embodiment of the present invention, and fig. 6 is a schematic plan view of the array substrate in the fourth state in the manufacturing method of the array substrate provided by the first embodiment of the present invention, referring to fig. 5 and fig. 6, on the basis of the array substrate in the third state shown in fig. 4d, a gate insulating layer 7 is continuously deposited by a vapor deposition method of plasma enhanced chemistry, then a gate metal layer is sequentially deposited by a sputtering or thermal evaporation method, and a third photolithography process is performed to form a first via hole 9 and a gate electrode 8. Wherein, the third photoetching process is carried out by a half-tone mask process or a gray-tone mask process. In addition, in the fourth step, for convenience of description, the step of forming the scan lines is not included in the array substrate, and actually, the scan lines and the gate electrodes 8 are formed simultaneously in the same photolithography process.
Step five: fig. 7 is a schematic structural diagram of the array substrate in the fifth state in the manufacturing method of the array substrate according to the first embodiment of the present invention, as shown in fig. 7, after the gate 8 is formed, a metal oxide protection layer 13 composed of a passivation layer and a planarization layer may be deposited on the array substrate in the fourth state shown in fig. 5 as needed, and a second via 14 is formed on the metal oxide protection layer 13 through a common photolithography process, where the second via 14 corresponds to the first via 9 in position, and the second via 14 and the first via 9 are matched to connect the source 5 and the drain 6 with the surrounding circuit, and finally, as shown in fig. 7 after the array substrate is formed.
In addition, the second photolithography process is performed by using a halftone mask process or a gray tone mask process, and the specific implementation process of the second photolithography process is described in detail in the third step.
In this embodiment, the method for manufacturing an array substrate includes: depositing a metal oxide semiconductor layer on a substrate, and carrying out a first photoetching process to form a metal oxide semiconductor pattern on the substrate; sequentially depositing a transparent conducting layer and a source drain electrode metal layer on the substrate base plate with the metal oxide semiconductor pattern, and carrying out a second photoetching process to form a pixel electrode, a source electrode and a drain electrode; and sequentially depositing a gate insulating layer and a gate metal layer on the substrate with the pixel electrode, the source electrode and the drain electrode, and carrying out a third photoetching process to form a first through hole and a gate, wherein the first through hole penetrates through the gate insulating layer and extends to the source electrode and the drain electrode. By forming the transparent conductive layer below the source-drain metal layer, a pixel electrode, a source electrode and a drain electrode can be formed simultaneously in the same photoetching process, and compared with the situation that in the prior art, the pixel electrode is formed above the planarization layer, the source electrode and the drain electrode are formed below the planarization layer, and the pixel electrode, the source electrode and the drain electrode need to be formed in two photoetching processes, the number of times of one photoetching process is reduced, so that the process is simple and the manufacturing cost is low.
Example two
The present embodiment provides an array substrate manufactured by the manufacturing method of the first embodiment, fig. 8 is a schematic structural diagram of an array substrate according to the second embodiment of the present invention, as shown in fig. 8, the array substrate of the present embodiment includes a substrate 1, a metal oxide semiconductor pattern 2, a pixel electrode 3, a source electrode 5, a drain electrode 6, a gate insulating layer 7 and a gate electrode 8, the metal oxide semiconductor pattern 2, the pixel electrode 3, the source electrode 5 and the drain electrode 6 are all disposed on the substrate 1, at least a portion of the structures of the source electrode 5 and the drain electrode 6 are disposed on the metal oxide semiconductor, the drain electrode 6 is electrically connected to the pixel electrode 3, the source electrode 5 and the drain electrode 6 are formed in the same photolithography process, the gate insulating layer 7 covers the array substrate having the metal oxide semiconductor pattern, the pixel electrode 3, the source electrode 5, the gate electrode, The drain electrode 6 is provided on the base substrate 1, and the gate electrode 8 is provided on the gate insulating layer 7.
Specifically, the substrate base plate 1 may include a glass base plate 11 and a modification layer 12 covering the release base plate. Optionally, the thickness of finish layer 12 is
Decorative layer12 may be selected from oxides, nitrides or oxynitrides, and in the case of nitrides, SiNxThe gas corresponding to the film is SiH4，NH3，N2Or SiH2Cl2，NH3，N2，SiNxOYThe gases of the film are: SiH4、NH3、N2O、N2；SiOxThe corresponding reaction gas is SiH4、N2O、N2。
Optionally, the thickness of the metal oxide semiconductor pattern 2 is
The metal oxide semiconductor layer may be Indium Gallium Zinc Oxide (IGZO), or Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4ZnO: al, TiO 2: nb, Cd-Sn-O or other metal oxides.
Optionally, the thickness of the pixel electrode 3 is
The material is typically ITO or IZO, and other metals and metal oxides may be used. The thickness of the source electrode 5 and the drain electrode 6 is about
Metals or alloys of Cr, W, Ti, Ta, Mo, Al, Cu, etc. can be selected, and a structure consisting of multiple layers of metals can also meet the requirement.
Optionally, the thickness of the gate insulating layer 7 is
The gate insulating layer 7 may be made of an oxide, nitride, or oxynitride, wherein SiNxThe film gas is SiH4，NH3，N2Or SiH2Cl2，NH3，N2，SiNxOYThe gases of the film are: SiH4、NH3、N2O、N2；SiOxThe corresponding reaction gas is SiH4、N2O、N2. In addition, the thickness of the gate metal layer is about
The grid metal layer can be made of Cr, W, Ti, Ta, Mo, Al, Cu and other metals or alloys, and the grid metal layer consisting of multiple layers of metals can also meet the requirement.
In the above solution, since the metal oxide semiconductor pattern 2, the pixel electrode 3, and the source and drain electrodes 5 and 6 are all disposed on the substrate 1, and the pixel electrode 3, the source and drain electrodes 5 and 6 are formed in the same photolithography process, compared with the prior art in which the pixel electrode 3 is formed above the planarization layer and the source and drain electrodes 5 and 6 are formed below the planarization layer, and the number of photolithography processes is reduced in two photolithography processes, the process is simple and the manufacturing cost is low.
Further, at least a part of the drain electrode 6 is covered on the pixel electrode 3, so that the drain electrode 6 is electrically connected with the pixel electrode 3. Thus, the source electrode 5, the drain electrode 6 and the pixel electrode 3 can be formed in the same photolithography process using a halftone mask process or a gray tone mask process, so as to reduce the number of total photolithography processes. Of course, it is also possible to electrically connect between the pixel electrode 3 and the drain electrode 6 using a conductive via or a conductive metal line.
Further, the array substrate further includes a source buffer layer 51 and a drain buffer layer 61 insulated from each other, the source buffer layer 51 and the drain buffer layer 61 cover a portion of the substrate 1 and cover a portion of the metal oxide semiconductor pattern 2, and the source buffer layer 51 and the drain buffer layer 61 are spaced between portions above the metal oxide semiconductor pattern 2 to form a portion of the region of the channel 10, and the source 5 and the drain 6 are disposed on the source buffer layer 51 and the drain buffer layer 61, respectively.
Since the metal constituting the source electrode 5 and the drain electrode 6 is, for example, Al, Cu or the like, which has a strong activity, the source electrode 5 and the drain electrode 6 are easily brought into direct contact with the metal oxide semiconductor pattern 2Oxygen in the bulk combines to form the corresponding oxide, e.g. Al2O3And CuO, etc., to damage the metal oxide semiconductor, in the above method, the source buffer layer 51 is formed between the source 5 and the base substrate 1 to perform an isolation function, and the drain buffer layer 61 is formed between the drain 6 and the base substrate 1 to perform an isolation function, thereby effectively preventing the above-mentioned occurrence. Meanwhile, the source buffer layer 51, the drain buffer layer 61 and the pixel electrode 3 may be made of the same material and formed in the same photolithography process, so that the number of photolithography processes may be reduced, and the cost may be reduced. This content has already been described in detail in the first embodiment, and is not described herein again.
In addition, the source buffer layer 51 and the drain buffer layer 61 may be formed using different materials from the pixel electrode 3, for example, alternatively, the source buffer layer 51 and the drain buffer layer 61 may be formed by depositing the same material as the pixel electrode 3 and by conducting the material. This part of the content is described in detail in the first embodiment, and is not described herein again.
Optionally, two first vias 9 extending to the source and drain electrodes 5 and 6, respectively, are further formed on the gate insulating layer 7. The first via hole 9 penetrates through the gate insulating layer 7 and extends to the source electrode 5 and the drain electrode 6, so that the source electrode 5 and the drain electrode 6 can be electrically connected with a circuit around the thin film transistor.
Further, a metal oxide protective layer 13 is further included above the gate 8, and a second via 14 is further disposed on the metal oxide protective layer 13, where the second via 14 corresponds to the first via 9, and the second via 14 and the first via 9 cooperate to connect the source 5 and the drain 6 with a surrounding circuit.
Further, as shown in fig. 8, a protection pattern 4 is also formed over the metal oxide semiconductor pattern to protect the metal oxide semiconductor pattern 2.
The array substrate of the embodiment comprises a substrate, a metal oxide semiconductor pattern, a pixel electrode, a source electrode, a drain electrode, a grid insulating layer and a grid, wherein the metal oxide semiconductor pattern pixel electrode, the source electrode and the drain electrode are arranged on the substrate, at least part of the source electrode and the drain electrode are arranged on the metal oxide semiconductor, the drain electrode is electrically connected with the pixel electrode, the source electrode and the drain electrode are formed in the same photoetching process, the grid insulating layer covers the substrate provided with the metal oxide semiconductor pattern, the pixel electrode, the source electrode and the drain electrode, and the grid is arranged on the grid insulating layer. In the above scheme, since the metal oxide semiconductor pattern, the pixel electrode, and the source and drain are all disposed on the substrate, and the pixel electrode, the source and drain are formed in the same photolithography process, compared with the prior art in which the pixel electrode is formed above the planarization layer, and the source and drain are formed below the planarization layer, and the number of photolithography processes is reduced in the case where the pixel electrode, the source and drain need to be formed in two photolithography processes, the process is simple and the manufacturing cost is low.
EXAMPLE III
The present embodiment provides a display panel, which includes a color film substrate, a liquid crystal layer and the array substrate of the second embodiment, where the liquid crystal layer is sandwiched between the color film substrate and the array substrate. The specific structure and function of the array substrate have been described in detail in the second embodiment, and thus are not described herein again.
Another aspect of this embodiment further provides a display device, including the display panel, where the display device may be a flexible display device, and in this embodiment, the display device may be an electronic paper, a tablet computer, or a liquid crystal display.
In the description of the present invention, it is to be understood that the terms "center", "length", "width", "thickness", "top", "bottom", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "inner", "outer", "axial", "circumferential", and the like, which are used to indicate the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplification of the description, and do not indicate or imply that the position or element referred to must have a particular orientation, be of particular construction and operation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; may be mechanically coupled, may be electrically coupled or may be in communication with each other; either directly or indirectly through intervening media, such as through internal communication or through an interaction between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.
Claims (10)
1. An array substrate is characterized by comprising a substrate, a metal oxide semiconductor pattern, a pixel electrode, a source electrode, a drain electrode, a grid insulating layer and a grid electrode, wherein the metal oxide semiconductor pattern, the pixel electrode and the source electrode and the drain electrode are all arranged on the substrate, at least part of structures of the source electrode and the drain electrode are arranged on the metal oxide semiconductor, the drain electrode is electrically connected with the pixel electrode, the source electrode and the drain electrode are formed in the same photoetching process, the grid insulating layer covers the substrate provided with the metal oxide semiconductor pattern, the pixel electrode, the source electrode and the drain electrode, and the grid electrode is arranged on the grid insulating layer.
2. The array substrate of claim 1, wherein at least a portion of the drain electrode covers the pixel electrode such that the drain electrode is electrically connected to the pixel electrode.
3. The array substrate of claim 1, further comprising a source buffer layer and a drain buffer layer insulated from each other, the source buffer layer and the drain buffer layer covering a portion of the substrate and covering a portion of the metal oxide semiconductor pattern, and the source buffer layer and the drain buffer layer being spaced between portions above the metal oxide semiconductor pattern to form a channel region, the source and drain being disposed over the source buffer layer and the drain buffer layer, respectively.
4. The array substrate of claim 3, wherein the source buffer layer, the drain buffer layer and the pixel electrode are formed in a same photolithography process.
5. The array substrate of claim 4, wherein the source buffer layer and the drain buffer layer are deposited with the same material as the pixel electrode.
6. The array substrate of claim 4, wherein the source buffer layer and the drain buffer layer are made of the same material as the pixel electrode and are formed after the material is made conductive.
7. The array substrate of any one of claims 1-6, wherein first vias extending to the source and drain electrodes, respectively, are further formed on the gate insulating layer.
8. The array substrate of any one of claims 1-6, wherein the metal oxide semiconductor is Indium Gallium Zinc Oxide (IGZO).
9. The array substrate of any of claims 1-6, wherein the pixel electrode is an Indium Tin Oxide (ITO) film.
10. A display panel, comprising a color filter substrate, a liquid crystal layer and the array substrate of any one of claims 1 to 9, wherein the liquid crystal layer is sandwiched between the color filter substrate and the array substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921788756.1U CN210272363U (en) | 2019-10-23 | 2019-10-23 | Array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921788756.1U CN210272363U (en) | 2019-10-23 | 2019-10-23 | Array substrate and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210272363U true CN210272363U (en) | 2020-04-07 |
Family
ID=70020627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921788756.1U Active CN210272363U (en) | 2019-10-23 | 2019-10-23 | Array substrate and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210272363U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620080A (en) * | 2019-10-23 | 2019-12-27 | 成都中电熊猫显示科技有限公司 | Manufacturing method of array substrate, array substrate and display panel |
| CN111584520A (en) * | 2020-05-25 | 2020-08-25 | 成都中电熊猫显示科技有限公司 | Array substrate, display panel and manufacturing method of array substrate |
| CN113889576A (en) * | 2021-01-25 | 2022-01-04 | 友达光电股份有限公司 | Organic semiconductor substrate |
-
2019
- 2019-10-23 CN CN201921788756.1U patent/CN210272363U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620080A (en) * | 2019-10-23 | 2019-12-27 | 成都中电熊猫显示科技有限公司 | Manufacturing method of array substrate, array substrate and display panel |
| CN111584520A (en) * | 2020-05-25 | 2020-08-25 | 成都中电熊猫显示科技有限公司 | Array substrate, display panel and manufacturing method of array substrate |
| CN111584520B (en) * | 2020-05-25 | 2023-09-12 | 成都京东方显示科技有限公司 | Array substrate, display panel and manufacturing method of array substrate |
| CN113889576A (en) * | 2021-01-25 | 2022-01-04 | 友达光电股份有限公司 | Organic semiconductor substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9236405B2 (en) | Array substrate, manufacturing method and the display device thereof | |
| US7636135B2 (en) | TFT-LCD array substrate and method for manufacturing the same | |
| CN102034750B (en) | Array substrate and manufacturing method thereof | |
| KR101447843B1 (en) | Thin film transistor array substrate, method for manufacturing the same, display panel and display device | |
| US20120043544A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN210272363U (en) | Array substrate and display panel | |
| CN102654698B (en) | Liquid crystal display array substrate and manufacturing method thereof as well as liquid crystal display | |
| US7799619B2 (en) | Thin film transistor array substrate and fabricating method thereof | |
| US8895334B2 (en) | Thin film transistor array substrate and method for manufacturing the same and electronic device | |
| CN107968097B (en) | Display device, display substrate and manufacturing method thereof | |
| WO2021077673A1 (en) | Array substrate manufacturing method, and array substrate | |
| US20090227054A1 (en) | Pixel structure for flat panel display | |
| CN104779302A (en) | Thin film transistor and manufacturing method, array substrate and display device thereof | |
| WO2015192595A1 (en) | Array substrate and manufacturing method thereof, and display device | |
| CN110620080A (en) | Manufacturing method of array substrate, array substrate and display panel | |
| US20120100652A1 (en) | Fabrication method of active device array substrate | |
| WO2021077674A1 (en) | Method for manufacturing array substrate, and array substrate | |
| CN108305879A (en) | Thin-film transistor array base-plate and production method and display device | |
| WO2014046068A1 (en) | Active matrix substrate, display device, and production method therefor | |
| WO2019196191A1 (en) | Method for preparing tft array substrate, tft array substrate, and display panel | |
| WO2011161875A1 (en) | Substrate for display device and process for production thereof, and display device | |
| CN210837710U (en) | Array substrate and display panel | |
| CN110729250A (en) | Array substrate manufacturing method and array substrate | |
| CN110707105A (en) | Manufacturing method of array substrate and array substrate | |
| CN110707104B (en) | Manufacturing method of array substrate, array substrate and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: No. 1778, Qinglan Road, Huangjia Street, Shuangliu District, Chengdu, Sichuan 610200 Patentee after: Chengdu BOE Display Technology Co.,Ltd. Country or region after: China Address before: No. 1778, Qinglan Road, Gongxing street, Shuangliu District, Chengdu, Sichuan 610200 Patentee before: CHENGDU ZHONGDIAN PANDA DISPLAY TECHNOLOGY Co.,Ltd. Country or region before: China |
|
| CP03 | Change of name, title or address |