CN110707104B - Manufacturing method of array substrate, array substrate and display panel - Google Patents
Manufacturing method of array substrate, array substrate and display panel Download PDFInfo
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- CN110707104B CN110707104B CN201911013116.8A CN201911013116A CN110707104B CN 110707104 B CN110707104 B CN 110707104B CN 201911013116 A CN201911013116 A CN 201911013116A CN 110707104 B CN110707104 B CN 110707104B
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- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 65
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- General Physics & Mathematics (AREA)
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Abstract
The invention provides a manufacturing method of an array substrate, the array substrate and a display panel. The manufacturing method of the array substrate comprises the following steps: depositing a grid metal layer on the substrate base plate, and carrying out a first photoetching process to form a grid on the substrate base plate; sequentially depositing a grid electrode insulating layer, a metal oxide semiconductor layer and a protective layer on the substrate base plate with the grid electrode, and carrying out a second photoetching process to form a metal oxide semiconductor pattern and a protective pattern; and depositing a source and drain metal layer, and carrying out a third photoetching process to form a source electrode and a drain electrode. The invention can reduce the times of photoetching process, and has simple process and low manufacturing cost.
Description
Technical Field
The invention relates to the field of liquid crystal display, in particular to a manufacturing method of an array substrate, the array substrate and a display panel.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Displays (LCDs) have the advantages of high image quality, power saving, thin body, and no radiation, and are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, and notebook computers, and become the mainstream of Display devices. The liquid crystal display panel generally comprises an array substrate, a color filter substrate and a liquid crystal molecular layer sandwiched between the array substrate and the color filter substrate, which are oppositely arranged. The liquid crystal molecules can be controlled to rotate by applying a driving voltage between the array substrate and the color film substrate, so that light rays of the backlight module are refracted out to generate a picture.
The manufacturing method of the array substrate provided by the prior art includes six photolithography processes, including: the first step is as follows: depositing a metal layer on a glass substrate, and carrying out first photoetching to form a grid; depositing a grid insulating layer and an Indium Gallium Zinc Oxide (IGZO) semiconductor layer in sequence, and carrying out second photoetching to form an active island pattern; thirdly, depositing a protective layer and carrying out third photoetching to form a protective pattern; fourthly, depositing a source drain metal layer, and carrying out fourth photoetching to form a source electrode and a drain electrode; depositing a passivation layer and a planarization layer, and performing a fifth photolithography process to form a conductive via hole; and sixthly, depositing a transparent conductive film, and carrying out sixth photoetching to form a pixel electrode and a communication pattern of the conductive through hole and the pixel electrode.
The six-time photoetching process provided by the prior art is complex in process and high in manufacturing cost.
Disclosure of Invention
The invention provides a manufacturing method of an array substrate, the array substrate and a display panel, which can reduce the times of photoetching processes, and have the advantages of simple process and low manufacturing cost.
In a first aspect, the present invention provides a method for manufacturing an array substrate, including: depositing a grid metal layer on the substrate base plate, and carrying out a first photoetching process to form a grid on the substrate base plate; sequentially depositing a grid electrode insulating layer, a metal oxide semiconductor layer and a protective layer on the substrate base plate with the grid electrode, and carrying out a second photoetching process to form a metal oxide semiconductor pattern and a protective pattern; and depositing a source and drain metal layer, and carrying out a third photoetching process to form a source electrode and a drain electrode.
In a second aspect, the present invention provides an array substrate manufactured by the method for manufacturing an array substrate.
In a third aspect, the present invention provides a display panel, which includes a color film substrate, a liquid crystal layer and the array substrate, wherein the liquid crystal layer is sandwiched between the color film substrate and the array substrate.
The embodiment of the invention provides a manufacturing method of an array substrate, the array substrate and a display panel, wherein the manufacturing method of the array substrate comprises the following steps: depositing a grid metal layer on the substrate base plate, and carrying out a first photoetching process to form a grid on the substrate base plate; sequentially depositing a grid electrode insulating layer, a metal oxide semiconductor layer and a protective layer on the substrate base plate with the grid electrode, and carrying out a second photoetching process to form a metal oxide semiconductor pattern and a protective pattern; and depositing a source and drain metal layer on the grid insulating layer with the metal oxide semiconductor pattern and the protection pattern, and carrying out a third photoetching process to form a source electrode and a drain electrode. The metal oxide semiconductor layer and the protective layer are sequentially deposited on the gate insulating layer, and the metal oxide semiconductor pattern and the protective pattern are formed in the same photoetching process, so that the times of photoetching processes can be reduced, the process is simple, and the manufacturing cost is low.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.
Fig. 1 is a schematic flow chart illustrating a manufacturing method of an array substrate according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of an array substrate in a first state in a manufacturing method of the array substrate according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of the array substrate after exposure and development in the second photolithography process in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 4 is a schematic structural diagram of the array substrate after the first etching in the second photolithography process in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 4a is a schematic structural diagram illustrating a first photoresist pattern after ashing in a manufacturing method of an array substrate according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of the array substrate after the second etching in the second photolithography process in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 6 is a schematic structural diagram of the array substrate in a second state in the manufacturing method of the array substrate according to the first embodiment of the invention;
FIG. 7 is a top view of FIG. 6;
fig. 8 is a schematic structural diagram of the array substrate in a third state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
FIG. 9 is a top view of FIG. 8;
fig. 10 is a schematic structural diagram of the array substrate in a fourth state in the manufacturing method of the array substrate according to the first embodiment of the invention;
FIG. 11 is a top view of FIG. 10;
fig. 12 is a schematic structural diagram of the array substrate in a fifth state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
FIG. 13 is a top view of FIG. 12;
fig. 14 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention.
Reference numerals:
1-a substrate base plate; 2-a grid; 3-a gate insulating layer; a 4-metal oxide semiconductor pattern; a 4' -metal oxide semiconductor layer; 5-protecting the graph; 5' -a protective layer; 6-source electrode; 7-a drain electrode; 8-a passivation layer; 9-a conductive via; 10-a first layer structure; 11-scan line; 12-a data line; 13-pixel electrode; 80-a first photoresist pattern; 81-complete photoresist retention area; 82-photoresist portion retention area; 83-area of complete removal of photoresist; 84-first photoresist pattern after ashing.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Fig. 1 is a schematic flow chart of a manufacturing method of an array substrate according to an embodiment of the present invention, as shown in fig. 1, the manufacturing method of an array substrate according to the embodiment includes:
and S10, depositing a gate metal layer on the substrate base plate, and carrying out a first photoetching process to form a gate on the substrate base plate.
Fig. 2 is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the inventionReferring to FIG. 2, the structure of the column substrate in the first state is shown, and it is first necessary to deposit a layer of about thickness on the substrate 1
The gate metal layer is deposited by sputtering or thermal evaporation, and the gate metal layer may be made of Cr, W, Cu, Ti, Ta, Mo, or other metals or alloys. And secondly, carrying out a first photoetching process on the grid metal layer to form a grid 2 in the switch area of the array substrate. The exposure of the first photolithography process may be a general photolithography process, or may be performed by a halftone mask process or a gray tone mask process. In addition, in practice, the array substrate includes a plurality of sub-pixel regions defined by the scan lines 11 and the data lines 12, and each of the sub-pixel regions is provided with one thin film transistor device, for convenience of description, in the drawings of the present application, only a schematic diagram of manufacturing one of the sub-pixel regions is drawn, it can be understood that the array substrate includes a plurality of sub-pixel regions, and therefore, in the manufacturing process of the array substrate of the present application, the reference to forming the gate 2 on the substrate 1 specifically means forming the gate 2 in a region of the array substrate corresponding to each of the sub-pixel regions. Similar to the source electrode 6, the drain electrode 7, and the metal oxide semiconductor pattern 4, the description thereof is omitted.
And S20, sequentially depositing a gate insulating layer, a metal oxide semiconductor layer and a protective layer on the substrate with the gate, and performing a second photoetching process to form a metal oxide semiconductor pattern and a protective pattern.
Fig. 3 is a schematic structural diagram of the array substrate after exposure and development in the second photolithography process in the manufacturing method of the array substrate according to the first embodiment of the present invention, fig. 4 is a schematic structural diagram of the array substrate after the first etching in the second photolithography process in the manufacturing method of the array substrate according to the first embodiment of the present invention, FIG. 4a is a schematic structural diagram illustrating a first photoresist pattern after ashing in a method for manufacturing an array substrate according to an embodiment of the invention, fig. 5 is a schematic structural diagram of the array substrate after the second etching in the second photolithography process in the manufacturing method of the array substrate according to the first embodiment of the present invention, fig. 6 is a schematic structural diagram of the array substrate in the second state in the manufacturing method of the array substrate according to the first embodiment of the invention, fig. 7 is a plan view of fig. 6, and fig. 6 is a sectional view of fig. 7 taken along a direction a-a.
Specifically, as shown in fig. 3, the array substrate in the first state shown in fig. 2 is first deposited continuously by a plasma enhanced chemical vapor deposition method to a thickness of
The gate insulating layer 3 may be an oxide, a nitride, or an oxynitride, and SiH is used as a reaction gas4，N2O; the reaction gas corresponding to the formation of nitride or oxynitride in the plasma enhanced chemical vapor deposition method is SiH4、NH3、N2Or SiH2Cl2、NH3、N2(ii) a Then deposited thereon by sputtering or thermal evaporation to a thickness of about
The metal oxide semiconductor layer 4' of (4) may be formed using amorphous IGZO, HIZO, IZO, a-InZnO, ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metal oxides, and then deposited by a plasma-enhanced chemical vapor deposition method to a thickness of
The protective layer 5' of (2) may be an oxide, nitride or oxynitride, or an oxide of siliconThe corresponding reaction gas may be SiH4，N2O; nitride or oxynitride corresponding to SiH as the gas4，NH3，N2Or SiH2Cl2，NH3，N2(ii) a Al may also be used for the protective layer 52O3Or a double layer barrier structure.
Optionally, the second photolithography process is implemented by a light transmittance modulation mask process, and the partial ultraviolet transmittance is reduced by using the diffraction principle of the semi-permeable membrane or the pattern slit on the mask to ultraviolet rays, so that the patterns on different layers are formed by one photolithography process. The exposure of the second photolithography process may be performed by a halftone mask process or a gray-tone mask process, for example.
Optionally, performing a second photolithography process to form the metal oxide semiconductor pattern 4 and the protection pattern 5 includes:
etching the metal oxide semiconductor layer 4 'and the protective layer 5' to form a first layer structure 10, wherein the first layer structure 10 is a metal oxide semiconductor pattern 4, and a part of the protective layer, which corresponds to and coincides with the metal oxide semiconductor pattern 4; the protective layer of the first layer structure 10 is etched to form the metal oxide semiconductor pattern 4 and the protective pattern 5. By forming the protective layer 5 'under the metal oxide semiconductor layer 4', the metal oxide semiconductor pattern 4 and the protective pattern 5 can be formed in the same photolithography process, i.e., in the second photolithography process. The protective pattern 5 is used to protect the metal oxide semiconductor pattern 4, and prevent the metal oxide semiconductor pattern 4 from being damaged by the etching solution in the etching process of the source electrode 6 and the drain electrode 7, where the protective layer 5' may be an etching barrier layer, and the protective pattern 5 may be an etching barrier pattern.
The detailed process of the second photolithography process is described in detail below with reference to fig. 3 to 7.
As shown in fig. 3, a photoresist is first coated on the protection layer 5', and a first photoresist pattern 80 is formed after exposure and development, wherein the first photoresist pattern 80 includes a photoresist complete remaining region 81, a photoresist partial remaining region 82 and a photoresist complete removing region 83, the photoresist complete remaining region 81 corresponds to a region of the protection pattern 5, the photoresist partial remaining region 82 corresponds to a region of the metal oxide semiconductor pattern 4 directly contacting with the source electrode 6 and the drain electrode 7, i.e., a region of the metal oxide semiconductor pattern 4 not covered by the protection pattern 5, and the photoresist complete removing region 83 corresponds to a region of the photoresist except the photoresist complete remaining region 81 and the photoresist partial remaining region 82.
As shown in fig. 4, the metal oxide semiconductor layer 4 'and the protection layer 5' are etched by using the first photoresist pattern 80 as a mask to form a first layer structure 10, wherein the first layer structure 10 is the metal oxide semiconductor pattern 4, and a portion of the protection layer corresponding to and overlapping with the metal oxide semiconductor pattern 4.
As shown in fig. 4a and 5, the first photoresist pattern 80 is ashed to remove the photoresist in the photoresist partial region 82 and reduce the photoresist in the photoresist complete region 81, and the protective layer of the first layer structure 10 is etched using the ashed first photoresist pattern 84 as a mask, i.e., the protective layer 5' at the corresponding position (the contact portion between the source and the drain of the metal oxide semiconductor pattern) of the photoresist partial region 82 is etched away to form the metal oxide semiconductor pattern 4 and the protective pattern 5. The protective pattern 5 is formed in an island-like pattern.
The photoresist is then stripped to form the array substrate in the second state as shown in fig. 6.
In the above solution, the metal oxide semiconductor layer 4 'and the protective layer 5' are sequentially deposited on the gate insulating layer 3, and the metal oxide semiconductor pattern 4 and the protective pattern 5 are formed in the same photolithography process, which can reduce the number of photolithography processes by one compared with the case of forming in two photolithography processes in the prior art, so the process is simple and the manufacturing cost is low.
And S30, depositing a source and drain metal layer on the gate insulating layer formed with the metal oxide semiconductor pattern and the protection pattern, and carrying out a third photoetching process to form a source electrode and a drain electrode.
Fig. 8 is a schematic structural diagram of the array substrate in a third state in the manufacturing method of the array substrate according to the first embodiment of the present invention; FIG. 9 is a top view of FIG. 8, and further, FIG. 8 is a cross-sectional view taken along A-A of FIG. 9; as shown in fig. 8 and 9, the array substrate in the second state shown in fig. 6 is sequentially deposited by sputtering or thermal evaporation to a thickness of
The source drain metal layer. The source and drain metal layer can be made of Cr, W, Cu, Ti, Ta, Mo and other metals or alloys, and the source and drain metal layer consisting of multiple layers of metals can also meet the requirement. The source electrode 6 and the drain electrode 7 are formed by a common photolithography process, thereby forming the array substrate in the third state. In addition, in the above steps, for convenience of description, a process of forming the thin film transistor in the array substrate is described, and a step of forming the data line 12 is not included, and actually, the data line 12, the source electrode 6, and the drain electrode 7 are simultaneously formed in the same photolithography process. The formation process of the gate electrode 2 and the gate scan line 11 is similar, and the formation step of the gate scan line 11 and the storage capacitor electrode is not included in step S10, and the gate scan line 11 and the storage capacitor electrode may be formed simultaneously with the gate electrode 2 in the same photolithography process.
Optionally, after the third photolithography process, the method further includes:
and S40, depositing a passivation layer on the gate insulating layer on which the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protection pattern are formed, and performing a fourth photolithography process to form a conductive via hole in a region of the passivation layer above the drain electrode.
Fig. 10 is a schematic structural view illustrating a fourth state of the array substrate in the method for manufacturing the array substrate according to the first embodiment of the present invention, fig. 11 is a top view of fig. 10, and fig. 10 is a cross-sectional view of fig. 11 along a direction a-a. As shown in fig. 10 and 11, the array substrate in the third state shown in fig. 8 is deposited by a plasma enhanced chemical vapor deposition method to a thickness of
The passivation layer 8, the passivation layer 8 may be an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be SiH4，NH3，N2Or SiH2Cl2，NH3，N2The conductive via 9 is formed by a common photolithography process, and the array substrate in the fourth state is formed.
And S50, depositing a transparent conductive film on the passivation layer with the conductive via hole, and performing a fifth photolithography process to form a pixel electrode, wherein the pixel electrode is electrically connected with the drain electrode through the conductive via hole.
Fig. 12 is a schematic structural view illustrating a fifth state of the array substrate in the method for manufacturing the array substrate according to the first embodiment of the present invention, fig. 13 is a top view of fig. 12, and fig. 12 is a cross-sectional view of fig. 13 along a direction a-a. As shown in fig. 12 and 13, on the basis of the array substrate in the fourth state shown in fig. 10, the upper layer is continuously deposited to a thickness of about a thickness by sputtering or thermal evaporation
The transparent conductive film of (2) may be ITO or IZO, and then a transparent pixel electrode 13 is formed through a common photolithography process, thereby forming a fifth state of the array substrate.
In this embodiment, the method for manufacturing an array substrate includes: depositing a grid metal layer on the substrate base plate, and carrying out a first photoetching process to form a grid on the substrate base plate; sequentially depositing a grid electrode insulating layer, a metal oxide semiconductor layer and a protective layer on the substrate base plate with the grid electrode, and carrying out a second photoetching process to form a metal oxide semiconductor pattern and a protective pattern; and depositing a source and drain metal layer on the grid insulating layer with the metal oxide semiconductor pattern and the protection pattern, and carrying out a third photoetching process to form a source electrode and a drain electrode. The metal oxide semiconductor layer and the protective layer are sequentially deposited on the gate insulating layer, and the metal oxide semiconductor pattern and the protective pattern are formed in the same photoetching process, so that the times of photoetching processes can be reduced, the process is simple, and the manufacturing cost is low.
Example two
The present embodiment provides an array substrate manufactured by the manufacturing method of the first embodiment, and fig. 14 is a schematic structural diagram of an array substrate according to the second embodiment of the present invention, as shown in fig. 14, the array substrate of the present embodiment includes: the pixel structure comprises a substrate base plate 1, a grid electrode 2, a grid electrode insulating layer 3, a metal oxide semiconductor pattern 4, a protection pattern 5, a source electrode 6, a drain electrode 7, a passivation layer 8, a pixel electrode 13 and a conductive via 9, wherein the grid electrode 2 is arranged on the substrate base plate 1, the grid electrode insulating layer 3 covers the grid electrode 2 and the substrate base plate 1, the metal oxide semiconductor pattern 4 covers part of the grid electrode insulating layer 3 and is positioned above the grid electrode 2, the protection pattern 5 covers the metal oxide semiconductor pattern 4, the source electrode 6 and the drain electrode 7 are arranged above the metal oxide semiconductor pattern 4 and the protection pattern 5, at least part of the source electrode 6 and the drain electrode 7 covers the metal oxide semiconductor pattern 4, and a channel is arranged between the source electrode 6 and the drain.
Specifically, the metal of the gate 2 may be Cr, W, Cu, Ti, Ta, Mo, or other metal or alloy, and the gate 2 formed by multiple layers of metal may also meet the requirement. The gate insulating layer 3 may be made of an oxide, nitride or oxynitride, and SiH is used as a corresponding reaction gas4，N2And O. The metal oxide semiconductor pattern 4 may be formed using amorphous IGZO, HIZO, IZO, a-InZnO, ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metal oxides.
The protective layer 5' may be made of oxide, nitride or oxynitride, and the reaction gas corresponding to the oxide of silicon may be SiH4，N2O; nitride or oxynitride corresponding to SiH as the gas4，NH3，N2Or SiH2Cl2，NH3，N2(ii) a Al may also be used for the protective layer 52O3Or is orA double-layer barrier structure.
The metal of the source electrode 6 and the drain electrode 7 can be Cr, W, Cu, Ti, Ta, Mo, and the like or alloy, and the source electrode 6 and the drain electrode 7 which are composed of multiple layers of metal can also meet the requirement. The passivation layer 8 may be an oxide, nitride or oxynitride, and the corresponding reaction gas may be SiH4，NH3，N2Or SiH2Cl2，NH3，N2。
In the above solution, since the metal oxide semiconductor pattern 4 and the protection pattern 5 are formed in one photolithography process, the number of photolithography processes in the manufacturing process of the array substrate can be reduced to five times, and thus the process is simple and the manufacturing cost is low.
In the present application, the thickness, the material, the process, and the like of each metal layer or film layer are examples, and the present invention is not limited thereto, and other thicknesses and materials may be selected.
Optionally, the dimension of the protection pattern 5 along the arrangement direction of the source electrode 6 and the drain electrode 7 is 1 to 1000 μm or 1 to 200 μm, and the dimension of the protection pattern 5 along the direction perpendicular to the arrangement direction is 1.5 to 90 μm.
Specifically, the arrangement direction of the source electrode 6 and the drain electrode 7 may be a lateral direction in fig. 14, and a direction perpendicular to the arrangement direction may be a longitudinal direction in fig. 14.
When the thin film transistor in the array substrate is a GOA device, the size of the protective pattern 5 along the arrangement direction of the source electrode 6 and the drain electrode 7 is 1-1000 μm. Among them, the GOA (Gate Driver on Array) technology is one of the Gate driving technologies of the liquid crystal panel, and the basic concept is to integrate the Gate driving circuit of the liquid crystal panel on the Array substrate to form the line scanning driving for the liquid crystal panel.
When the thin film transistor in the array substrate is a pixel driving device, the size of the protection pattern 5 along the arrangement direction of the source electrode 6 and the drain electrode 7 is 1 to 200 μm.
The array substrate of the embodiment is manufactured by the manufacturing method of the array substrate described in the first embodiment, and the metal oxide semiconductor pattern and the protection pattern are formed in one photoetching process, so that the number of times of photoetching processes in the manufacturing process of the array substrate can be reduced, and the array substrate is simple in process and low in manufacturing cost.
EXAMPLE III
The present embodiment provides a display panel, which includes a color film substrate, a liquid crystal layer and the array substrate of the second embodiment, where the liquid crystal layer is sandwiched between the color film substrate and the array substrate. The specific structure and function of the array substrate have been described in detail in the second embodiment, and thus are not described herein again.
Another aspect of this embodiment further provides a display device, including the display panel, where the display device may be a flexible display device, and in this embodiment, the display device may be an electronic paper, a tablet computer, or a liquid crystal display.
In the description of the present invention, it is to be understood that the terms "center", "length", "width", "thickness", "top", "bottom", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "inner", "outer", "axial", "circumferential", and the like, are used to indicate an orientation or positional relationship based on that shown in the drawings, merely to facilitate the description of the invention and to simplify the description, and do not indicate or imply that the position or element referred to must have a particular orientation, be of particular construction and operation, and thus, are not to be construed as limiting the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; may be mechanically coupled, may be electrically coupled or may be in communication with each other; either directly or indirectly through intervening media, such as through internal communication or through an interaction between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, and that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is at a lesser elevation than the second feature.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (7)
1. A method for manufacturing an array substrate includes:
depositing a grid metal layer on a substrate, and carrying out a first photoetching process to form a grid on the substrate;
sequentially depositing a grid electrode insulating layer, a metal oxide semiconductor layer and a protective layer on the substrate with the grid electrode formed, and carrying out a second photoetching process to form a metal oxide semiconductor pattern and a protective pattern;
depositing a source drain metal layer on the grid electrode insulating layer formed with the metal oxide semiconductor pattern and the protection pattern, and carrying out a third photoetching process to form a source electrode and a drain electrode;
the performing of the second photolithography process to form the metal oxide semiconductor pattern and the protection pattern includes:
coating photoresist on the protective layer, and forming a first photoresist pattern after exposure and development, wherein the first photoresist pattern comprises a photoresist complete retention region, a photoresist partial retention region and a photoresist complete removal region, and the only photoresist complete retention region is included in the projection range of the grid;
etching the metal oxide semiconductor layer and the protective layer to form a first layer structure, wherein the first layer structure is the metal oxide semiconductor pattern and a part of the protective layer, which is correspondingly overlapped with the metal oxide semiconductor pattern;
etching the protective layer of the first layer structure,
forming the metal oxide semiconductor pattern and a protection pattern, wherein the protection pattern is formed into an island-shaped pattern; the size of the protection pattern along the arrangement direction of the source electrode and the drain electrode is 1-1000 mu m or 1-200 mu m, and the size of the protection pattern along the direction vertical to the arrangement direction is 1.5-90 mu m;
further comprising, after the third photolithography process:
depositing a passivation layer on the gate insulating layer on which the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protection pattern are formed, and performing a fourth photolithography process to form a conductive via hole in a region of the passivation layer above the drain electrode;
and depositing a transparent conductive film on the passivation layer with the conductive through hole, and performing a fifth photoetching process to form a pixel electrode, wherein the pixel electrode is electrically connected with the drain electrode through the conductive through hole.
2. The method for manufacturing the array substrate according to claim 1, wherein the exposure of the second photolithography process is performed by a halftone mask process or a gray-tone mask process.
3. The method of manufacturing an array substrate of claim 1,
the etching the metal oxide semiconductor layer and the protective layer to form a first layer structure comprises:
arranging photoresist on the protective layer, and forming a first photoresist pattern through exposure and development, wherein the first photoresist pattern comprises a photoresist complete retention region, a photoresist partial retention region and a photoresist complete removal region, the photoresist complete retention region corresponds to a region of the protective pattern, the photoresist partial retention region corresponds to a region on the metal oxide semiconductor pattern and is directly contacted with the source electrode and the drain electrode, and the photoresist complete removal region corresponds to a region on the photoresist except the photoresist complete retention region and the photoresist partial retention region;
and etching the metal oxide semiconductor layer and the protective layer by taking the first photoresist pattern as a mask to form the first layer structure.
4. The method for manufacturing the array substrate according to claim 3, wherein the etching the first layer structure to form the metal oxide semiconductor pattern and the protection pattern comprises:
ashing the first photoresist pattern to remove the photoresist in the photoresist partial retention region and to thin the photoresist in the photoresist full retention region;
and etching the first layer structure by taking the first photoresist pattern after ashing as a mask to form the metal oxide semiconductor pattern and a protective pattern.
5. The manufacturing method of the array substrate according to claim 1, wherein the metal oxide semiconductor layer, the transparent conductive layer, the source/drain metal layer and the gate metal layer are deposited by a sputtering or thermal evaporation process, and/or the gate insulating layer, the protective layer and the passivation layer are deposited by a plasma enhanced chemical vapor deposition process.
6. An array substrate manufactured by the manufacturing method according to any one of claims 1 to 5.
7. A display panel, comprising a color film substrate, a liquid crystal layer and the array substrate of claim 6, wherein the liquid crystal layer is sandwiched between the color film substrate and the array substrate.
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