KR100719265B1 - Array plate for liquid crystal display device and fabricating method thereof - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate, and more particularly, in a structure in which a color filter is formed on a lower substrate rather than an upper substrate, the black matrix of the color filter, the gate wiring and the data wiring of the array substrate. By introducing a structure that reduces the overlapping area, by reducing the parasitic capacitance formed between the respective wirings and the black matrix, it is possible to significantly reduce the image distortion caused by the parasitic capacitance, thereby producing a reliable liquid crystal display device.

Description

Array plate for liquid crystal display device and fabrication method thereof

1 is an exploded perspective view showing a conventional color liquid crystal display device;

FIG. 2 is a plan view showing some pixels of an array substrate for a color liquid crystal display device having a TOC structure according to a first embodiment of the present invention;

3 is a cross-sectional view taken along line III-III ′ of FIG. 2;

4 is a plan view showing some pixels of an array substrate for a color liquid crystal display device having a TOC structure according to a second embodiment of the present invention;

5A through 5D are cross-sectional views taken along the line VV ′ of FIG. 4 and shown in a process sequence.

 <Brief description of symbols for the main parts of the drawings>

100: substrate 113: gate wiring

115: data wiring 117: pixel electrode

119 semiconductor layer 121 source electrode

123: drain electrode 124: sub color filter                 

125: gate electrode 126: black matrix

127: drain contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device including an array substrate employing a color filter. .

1 is a view schematically showing a general liquid crystal panel.

As shown, the liquid crystal display includes a color filter 7 including a black matrix 6 and a sub-color filter (red, green, blue) 8 and an upper substrate on which a transparent common electrode 18 is formed on the color filter. And a lower substrate 22 having an array wiring including a pixel region P and a pixel electrode 17 formed on the pixel region, and a switching element T. The upper substrate 5 and the lower substrate are formed of the lower substrate 22. The liquid crystal 14 is filled between the substrates 22.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 and the data wiring 15 passing through the plurality of thin film transistors cross each other. Is formed.

The pixel area P is an area defined by the gate line 13 and the data line 15 intersecting each other. The pixel electrode 17 formed on the pixel region P uses a transparent conductive metal having relatively high light transmittance, such as indium-tin-oxide (ITO).

In the above-described configuration, the color filter may be formed by a printing method, a dyeing method, a polymer electrodeposition method, or a pigment dispersion method.

For example, the pigment dispersion method is described by applying a resist prepared by using a pigment prepared in advance to the substrate, and repeating the process of patterning and developing by exposure, red, green and blue. It is a method of forming a color filter of (BLUE).

At this time, an acrylic resin or the like may be used as a material of the color filter. In order to pattern the resin, pre-bake, exposure, development, post-bake Can be patterned through the process.

As described above, the upper substrate and the lower substrate, which have undergone respective processes, are bonded to each other in the assembling process to form a liquid crystal display device.

In this manner, a color liquid crystal display device can be manufactured.

However, an important point in the process of bonding the upper substrate and the lower substrate is that the arrangement of the upper substrate and the lower substrate must match exactly. However, in the process of forming the color filter, the upper substrate may be deformed by high heat during the pre-baking and the post-baking process, which makes it difficult to accurately adhere to the lower substrate. Therefore, it becomes a cause of the defect of the liquid crystal display device.                         

The present invention for solving the above problems is to form the color filter on the lower array substrate, to prevent defects due to the bonding error of the upper substrate and the lower substrate.

An array substrate for a color liquid crystal display according to the present invention for achieving the above object is a substrate; A plurality of pixel regions defined on the substrate; A black matrix surrounding the circumference of each pixel region defined on the substrate in a band shape; A color filter positioned in the pixel area and partially overlapping the black matrix; A planarization film formed on the color filter and the black matrix; A gate wiring and a data wiring formed on the planarizing film so as to cross each other with an insulating film interposed therebetween and partially overlapping with the adjacent black matrix bands; A thin film transistor comprising a gate electrode connected to the gate wiring, a source electrode and a drain electrode connected to the data wiring, and an active layer; And a pixel electrode connected to the drain electrode and positioned above the subcolor filter.

The black matrix is disposed on both sides of each of the wirings, and is configured to shield light between the wirings and the pixel electrode.

A buffer layer is further formed on the planarization film, thereby improving the adhesion property of the metal wiring formed thereafter. In this case, the buffer layer is formed of one selected from the group consisting of silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ).

An array substrate manufacturing method for a liquid crystal display device according to an aspect of the present invention includes the steps of preparing a substrate; Defining a plurality of pixel regions on the substrate; Forming a black matrix around each of the pixel areas defined on the substrate in a band shape; Forming a color filter positioned in the pixel area and partially overlapping the black matrix; Forming a planarization layer on the color filter and the black matrix; Forming a gate line and a data line formed on the planarization film so as to cross each other with an insulating film interposed therebetween and partially overlapping the black matrix bands adjacent to each other; Forming a thin film transistor comprising a gate electrode connected to the gate wiring, a source electrode and a drain electrode connected to the data wiring, and an active layer; And forming a pixel electrode connected to the drain electrode and positioned above the sub-color filter.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example 1

2 and 3 are plan views showing some pixels of an array substrate for a liquid crystal display according to a first embodiment of the present invention, and sectional views taken along the line III-III ′.

As shown in the drawing, the gate wiring 113 and the data wiring 115 are formed to cross each other in a matrix form on the substrate 100, and at the intersection of the gate wiring 113 and the data wiring 115. The thin film transistor T is formed. The thin film transistor T includes a gate electrode 125, an active layer 119, a source electrode 121, and a drain electrode 123.

The pixel electrode 117 is formed on the entire surface of the area defined by the gate wiring 113 and the data wiring 115 intersecting, and the pixel electrode 117 is connected to the drain electrode 123 through the contact hole 127. Make contact.

In such a configuration, the color filter 129 is formed under the thin film transistor T and the pixel electrode 117, and the color filter 129 is formed with red (RED) formed under the pixel electrode 117. Each of the sub-color filters 124 of green and blue, the gate wiring 113, the data wiring 115, and the thin film transistor (120) which are planarly positioned between the sub-color filters 124. It is composed of a black matrix 126 located under the T).

The black matrix 126 is mainly formed by depositing and patterning chromium (Cr) having low reflectance.

A buffer layer on the planarization layer 128 for deposition characteristics of the planarization layer 128 to planarize the surface of the color filter 129, and the constituent layers for patterning the thin film transistor T and each wiring. (buffer layer) 130 is formed.

In this case, the planarization layer 128 is formed by thickly applying a transparent organic insulating film, such as benzocyclobutene and acryl-based resin.                     

A silicon nitride film (SiN _X ) or a silicon oxide film (SiO ₂ ) is formed as the buffer layer 130.

With the above configuration, an array substrate having a structure of a thin film transistor on color filter (hereinafter referred to as "TOC") according to the present invention can be manufactured.

As described above, the liquid crystal display device of the TOC structure according to the present invention does not need to configure the color filter on the upper substrate, and thus it is possible to reduce the defects generated during the bonding process, thereby improving the yield of the liquid crystal panel. have.

Hereinafter, the second embodiment is a structure further improved than the first embodiment of the present invention, and is a structure that reduces parasitic capacitance that may occur between the black matrix formed on the lower substrate and the respective metal wires.

Example 2

A feature of the TOC structure array substrate according to the second embodiment of the present invention is to place a black matrix between the metal wirings and the pixel electrodes, and propose a structure that reduces the area where the metal wirings and the black matrix overlap.

4 is an enlarged plan view schematically showing a part of a TOC structure array substrate according to a second embodiment of the present invention.

As illustrated, the array substrate 100 includes a pixel P and a thin film transistor T, which is a switching element that applies a signal voltage to the pixel, and a data line 113 and a gate intersecting while being connected to the thin film transistor. The wiring 115 is formed.

The pixel electrode 117 of the pixel P is formed in a region defined by the orthogonality of the gate wiring 115 and the data wiring 113, wherein one side of the pixel electrode 117 is a drain of the thin film transistor. The electrode 123 and the drain contact hole 127 are connected to each other.

In addition, the sub color filter 124 is formed by overlapping the remaining pixel region except for the portion where the thin film transistor T is formed and the data line 113 and the gate line 115 defining the pixel P. .

In a plan view, a black matrix 126 is formed between the sub color filters.

The black matrix 126 according to the present invention is divided into two sides with respect to the gate wiring 113 and the data wiring 115 in a plan view, so that each of the wirings 113 and 115 and the pixel electrode 117 is separated. Configure to exist in between.

That is, since the black matrix 126 is not formed in the center portion of each wiring that does not require light shielding, the single sub color filter 125 is surrounded by the black matrix 126, and the black matrix surrounding each pixel is formed. Are shapes configured to be spaced apart from each other by a predetermined interval.

In this configuration, since the overlapping area of each of the metal wires 113.115 and the black matrix 126 is reduced, the size of the parasitic capacitances C _GB and C _SB is also reduced.

Hereinafter, a method of manufacturing a TOC structure array substrate according to the present invention will be described with reference to FIGS. 5A to 5D.

5A through 5D are cross-sectional views taken along the line VV ′ of FIG. 4 and shown in a process sequence.

First, FIG. 5A is a cross-sectional view illustrating a process of forming the color filter 129.

As illustrated, an opaque metal having a low light reflectance such as chromium (Cr) is deposited and patterned on the substrate 100 to form a black matrix 126 that is a light shielding film.

The black matrix 126 is positioned below the gate wiring (113 in FIG. 4), the data wiring (115 in FIG. 4) and the thin film transistor (T in FIG. 4) which are later formed to cross vertically. It is comprised so that it may not exist in the position corresponding to the center area | region k of wiring.

Next, the red (R), green (G), and blue (B) subcolor filters 124 are formed on the substrate 100 on which the black matrix 126 is formed using a predetermined method.

The pixel electrode 117 of FIG. 2, which is formed in a subsequent process, is positioned on the sub-color filter 124.

Next, an organic insulating material group including benzocyclobutene and acryl-based resin on the substrate 100 on which the sub-color filters 124 and the black matrix 126 are formed. The planarization layer 128 is formed to planarize the surface of the substrate 100 on which the color filter 129 is formed by applying one of the selected ones.                     

Next, silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ) is deposited on the planarization layer 128 to form a buffer layer 130.

Next, as shown in FIG. 5B, aluminum (Al), aluminum alloy (AlNd), chromium (Cr), tungsten (W), molybdenum (Mo), copper (Cu), and the like are formed on the buffer layer 130. A selected one of the included conductive metal groups is deposited and patterned to form a plurality of gate lines (113 in FIG. 2) configured in one direction and a plurality of gate electrodes 125 protruding from the gate lines.

Next, an inorganic insulating material group in which a silicon oxide film (SiO ₂ ) and a silicon nitride film (SiN _x ) are formed on the entire surface of the substrate 100 including the gate wiring (113 in FIG. 4), and in some cases, benzocyclobutene One selected from an organic insulating material group consisting of (Benzocyclobutene) and an acrylic resin (resin) is deposited or coated to form a gate insulating film 141 which is a first insulating film.

Next, as shown in FIG. 5C, amorphous silicon (a-Si: H) and impurity amorphous silicon (n + a-Si: H) are formed on the gate insulating film 141 on the gate wiring 113 (in FIG. 4). ) Are stacked to form a semiconductor layer 119.

In the laminated structure, the lower pure amorphous silicon layer is later an active layer (119a), and the impurity amorphous silicon layer is an ohmic contact layer (ohmic) for reducing the resistance between the active layer and the subsequent metal wiring. contact layer) 119b.

Next, a selected one of the conductive metals is deposited and patterned on the entire surface of the substrate 100 on which the semiconductor layer 119 is formed, and vertically intersects the gate wiring (113 in FIG. 4) to form a pixel region. A data line 115 defining (P), a source electrode 121 protruding from one side of the gate electrode 125 on the data line 115, and a predetermined distance from the source electrode 121. The drain electrode 123 is formed.

Next, as shown in FIG. 5D, one of the above-described organic insulating material group and optionally an inorganic insulating material group is selected on the entire surface of the substrate 100 on which the data wiring 115 and the like are formed. This is applied or deposited to form a protective layer 142, which is a second insulating film.

Next, the passivation layer 142 is patterned to form a drain contact hole 127 disposed on the drain electrode 123 and exposing a part of the drain electrode 123.

Next, a selected one of a transparent conductive metal group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the entire surface of the substrate 100 on which the patterned protective layer 142 is formed, and the pattern is formed. The pixel electrode 117 is formed in contact with the exposed drain electrode 123.

In this case, as illustrated, the black matrix 125 is present only between the data line 115 and the gate line (113 of FIG. 2) and the pixel electrode 117.

In such a configuration, since the area where the respective wirings and the black matrix 126 overlap each other is reduced, the parasitic capacitance can be considerably reduced.

6 is a plan view showing another example of the black matrix structure according to the second embodiment of the present invention.

As shown in the drawing, the black matrix 126 is connected at the intersections of the gate wiring 113 and the data wiring 115, and may be configured not to exist only in the lower center portion of each wiring.

Therefore, the array substrate of each TOC structure as described above has the following effects.

First, since the color filter is not formed on the upper substrate, there is no defect due to the bonding error, thereby improving the yield of the liquid crystal display.

Second, the black matrix is present only between each of the wirings and the pixel electrode, so that the parasitic capacitance that exists between the black matrix and each of the wirings can act as a resistance component to each wiring, thereby reducing the signal distortion. There is.

Therefore, there is an effect that can provide a reliable product.

Claims (13)

A substrate; A data line and a gate line formed on the substrate so as to cross each other to define a pixel area; A thin film transistor formed in the pixel area and connected to the data line and the gate line; A pixel electrode formed in the pixel region and connected to the thin film transistor; A planarization layer formed over the substrate, the data line, the gate line, and the thin film transistor; A color filter formed between the planarization layer and the substrate and formed in an area overlapping the pixel area; A black matrix formed between the color filter and the substrate and formed to enclose the circumference of the pixel area in a band shape, and to expose the data and gate wirings; Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the black matrix is connected to the black matrix of an adjacent pixel area at a portion where the gate line and the data line cross each other. The method of claim 1, And a buffer layer formed on the planarization layer. The method of claim 3, wherein And the buffer layer is selected from the group consisting of silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). Defining a pixel area on the substrate, the pixel area being formed by crossing the data line and the gate line; Forming a black matrix on the substrate to surround the pixel area in a band shape so that the data line and the gate line are exposed; Forming a color filter on the substrate and the black matrix in the pixel region; Forming a planarization layer on the color filter and the black matrix; Forming a data line and a gate line intersecting each other with an insulating layer therebetween on the planarization layer; Forming a thin film transistor connected to the data line and the gate line; Forming a pixel electrode connected to the thin film transistor in the pixel region Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 5, And the black matrix is formed to be connected to the black matrix of an adjacent pixel area at a portion where the data line and the gate line cross each other. The method of claim 5, And forming a buffer layer on the planarization layer. The method of claim 7, wherein And the buffer layer is formed by selecting one of a group consisting of silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). The method of claim 5, And the planarization layer is formed by applying one selected from the group of organic insulating materials including benzocyclobutene (BCB) and acrylic resin. The method of claim 5, The gate wiring and the data wiring are formed of one selected from the group consisting of aluminum (Al), aluminum alloy, copper (Cu), tungsten, (W) chromium (Cr), and molybdenum (Mo). . The method of claim 5, And the black matrix is formed of an opaque metal. The method of claim 5, And the pixel electrode is formed of one selected from the group consisting of ITO and IZO. The method of claim 11, The opaque metal is a method of manufacturing an array substrate for a liquid crystal display device, characterized in that the chromium (Cr).

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