KR20090073772A - Array substrate of liquid crystal display device and method for fabricating the same - Google Patents

Abstract

An array substrate of a liquid crystal display device and a method for manufacturing the same are provided to apply a reverse TFT structure in which locations of an array substrate and a color filter substrate are reverse, thereby removing a process of forming a black matrix through a blocking design of a gate line and a data line by using a barrier pattern. A TFT(Thin Film Transistor) is made on an intersection point of a gate line(120) and a data line(130). A pixel electrode(170) is contacted with the thin film transistor. The first barrier pattern(151) has wider width than width of the gate line correspondingly to a lower part of the gate line. The second barrier pattern(152) has wider width than width of the data line in a lower part overlapped with the data line.

Description

Array Substrate of Liquid Crystal Display Device and Manufacturing Method Thereof {Array Substrate of Liquid Crystal Display Device and Method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a method for manufacturing the same, and more particularly, to improving production yield through shortening of a process step of a liquid crystal display.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, active matrix LCDs (AM-LCDs) in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix manner have attracted the most attention due to their excellent resolution and ability to implement video.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is a plan view illustrating a unit pixel of a conventional array substrate for a liquid crystal display device, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

1 and 2, the gate wiring 20 and the gate electrode 25 extending from the gate wiring 20 are formed in one direction on the substrate 10. The barrier pattern 52 is formed to correspond to the data region D perpendicular to the gate wiring 20, and the barrier pattern 52 is designed to have an electrically insulated island shape.

In this case, the gate wiring 20, the gate electrode 25, and the barrier pattern 52 may be formed of a conductive metal group such as copper (Cu), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) in the same layer. It is formed into one selected.

On the gate line 20, the gate electrode 25, and the barrier pattern 52, a gate insulating layer 45 is formed of one selected from the group of inorganic insulating materials including silicon oxide (SiO ₂ ) and silicon nitride (SiNx).

The active layer 40 and the ohmic contact layer 41 are sequentially stacked on the gate insulating layer 45 overlapping the gate electrode 25. The active layer 40 and the ohmic contact layer 41 form a semiconductor layer 42. In this case, the active layer 40 is formed of pure amorphous silicon (a-Si: H), and the ohmic contact layer 41 is formed of amorphous silicon (n + a-Si: H) containing impurities.

On the semiconductor layer 42, a data line 30 perpendicularly intersecting with the gate line 20 to define a pixel region P, a source electrode 32 extending from the data line 30, and the source electrode A drain electrode 34 spaced apart from the 32 is formed. The gate electrode 25, the semiconductor layer 42, and the source and drain electrodes 32 and 34 are referred to as a thin film transistor T.

A passivation layer 55 including a drain contact hole CH1 exposing a part of the drain electrode 34 is formed on the data line 30 and the source and drain electrodes 32 and 34. The passivation layer 55 is generally made of the same material as the gate insulating layer 45.

On the passivation layer 55 including the drain contact hole CH1, the pixel electrode 70 in contact with the drain electrode 34 is configured to correspond to the pixel region P.

3 is a cross-sectional view taken along line III-III ′ of FIG. 2 and illustrates a state in which an array substrate and a color filter substrate are opposed to each other, and will be described in detail with reference to this.

As illustrated, the color filter substrate 5 and the array substrate 10 respectively divided into the display area AA and the non-display area NAA are opposed to each other, and the color filter substrate 5 and the array substrate ( The liquid crystal layer 15 is interposed in the spaced apart space of 10). The color filters, the array substrates 5 and 10, and the liquid crystal layer 15 form a liquid crystal panel 90. The backlight unit 95 serving as a light source is positioned on the rear surface of the array substrate 10.

On the lower surface of the transparent substrate 1 of the color filter substrate 5, a black matrix 12 corresponding to the non-display area NAA and a red sub R sequentially patterned around the black matrix 12 are provided. A color filter layer 16 including a color filter (not shown), a green (G) sub color filter 16b, and a blue (B) sub color filter 16c, and a common color corresponding to the entire lower surface of the color filter layer 16. A patterned column spacer (not shown) to secure a uniform cell gap between the color filter substrate 5 and the array substrate 10 under the electrode 85, the common electrode 85, and an upper portion covering the column spacer. The alignment film 18 is located in order.

In general, the column spacer is selected from the group of organic insulating materials, and is formed at a position corresponding to the gate line 20 of FIG. 1.

On the other hand, an upper surface of the transparent substrate 2 of the array substrate 10 has an electrically insulated barrier pattern 52, a gate insulating film 45 covering the barrier pattern 52, and a gate insulating film 45. A plurality of pixel electrodes 70 respectively corresponding to the data line 30 corresponding to the data area D, the passivation layer 55 on the data line 30, and both pixel regions P on the passivation layer 55. ) And lower alignment layers 19 on the plurality of pixel electrodes 70 are sequentially disposed.

In this case, the color filter substrate 5 may include a first mask process step of forming a black matrix 12, a second mask process step of forming a red (R) sub color filter on the black matrix 12, A third mask process step of forming the green (G) sub color filter 16b, a fourth mask process step of forming the blue (B) sub color filter 16c, and a column spacer on the common electrode 85. And a fifth mask process step. Since the common electrode 85 is designed in a plate shape corresponding to the entire surface of the color filter substrate 5, the common electrode 85 does not require a mask pattern process.

In the above-described configuration, the barrier pattern 52 formed on the array substrate 10 serves to shield the data line 30. In this barrier pattern 52, the front light incident from the backlight unit 95 is completely prevented. Although there is an advantage to shield, there is a limit to completely shield the light incident from the side by the cell gap designed to the thickness and constant height of the array substrate 10 and the color filter substrate 5 itself.

For this reason, the black matrix 12 is designed in the color filter substrate 5 corresponding to the non-display area NAA.

In addition, the gate wiring and the gate electrode formed in the array substrate according to the prior art are mainly made of a conductive metal material of copper or copper alloy series, but the copper or copper alloy series materials have poor contact characteristics between interfaces with the substrate, resulting in poor deposition. As a result, the reliability of the display element is deteriorated.

The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to improve the production yield by shortening the number of mask processes in the manufacturing process of the liquid crystal display.

According to an aspect of the present invention, a liquid crystal display device includes: a substrate; A gate wiring formed in one direction on the substrate; A data line configured to vertically cross the gate line; A thin film transistor configured at an intersection point of the gate line and the data line; A pixel electrode in contact with the thin film transistor; A first barrier pattern configured to have a width wider than a width of the gate wiring corresponding to a lower portion of the gate wiring; And a second barrier pattern configured to have a width wider than the width of the data line below the data wire.

In this case, the gate wiring, the electrode, and the first and second barrier patterns are formed on the same layer, and the first and second barrier patterns are selected from a group of conductive materials including molybdenum and molybdenum alloys. The first and second barrier patterns function to shield light.

In addition, the first and second barrier patterns may function to improve contact characteristics between interfaces between the substrate, the gate wiring, and the electrode.

The gate wiring and the electrode are composed of one selected from the group of conductive metals such as copper, molybdenum, aluminum, aluminum alloy and chromium.

The pixel electrode extends with the gate wiring at the front end, the gate wiring at the front end as the first electrode, the pixel electrode overlapped with the first electrode as the second electrode, and the first and second electrodes. A storage capacitor is constituted by using an insulating film interposed in the overlapped interspace as a dielectric layer.

The array substrate; A color filter substrate opposed to the array substrate and defined as a display area and a non-display area; A liquid crystal layer interposed in spaced spaces between the array and the color filter substrate; A backlight unit positioned on a rear surface of the color filter substrate spaced apart from the back surface; Red, green, and blue sub color filters sequentially patterned on the non-display area on the color filter substrate; A liquid crystal display device including a common electrode on the red, green, and blue sub color filters is configured.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: forming a gate wiring formed in one direction on the substrate and a gate electrode extending from the gate wiring; Forming a first barrier pattern having a width wider than that of the gate wiring and the electrode corresponding to a lower portion of the gate wiring and the electrode, and a second barrier pattern patterned in an island shape corresponding to the data area; Forming a gate insulating film on the substrate on which the gate wiring and the electrode and the first and second barrier patterns are formed; Forming a data line perpendicular to the gate line, a source electrode extending from the data line, a drain electrode spaced apart from the source electrode, and a semiconductor layer under the source and drain electrodes on the gate insulating layer; ; Forming a protective film exposing a portion of the drain electrode on a substrate on which the semiconductor layer, the source and drain electrodes, and the data wiring are formed; Forming a pixel electrode in contact with the drain electrode on the passivation layer.

In this case, the first and second barrier patterns are formed of one selected from the group of conductive materials including molybdenum and molybdenum alloy, and the gate wire and the electrode are selected from conductive metal groups such as copper, molybdenum, aluminum, aluminum alloy and chromium. It is formed as one.

The pixel electrode extends with the gate wiring at the front end, the gate wiring at the front end as the first electrode, the pixel electrode overlapped with the first electrode as the second electrode, and the first and second electrodes. A storage capacitor is formed which uses an insulating film interposed in the overlapped interspace as a dielectric layer.

In the present invention, first, by applying an inverted TFT structure in which the positions of the array substrate and the color filter substrate are opposite, the black matrix formation process can be omitted by shielding the gate wiring and the data wiring with a barrier pattern.

Second, the failure of lifting of the gate wiring and the electrode can be improved by forming a barrier pattern having good contact characteristics between interfaces with the substrate under the gate wiring and the electrode.

--- Example ---

The present invention is characterized in that the black matrix forming process can be eliminated by fabricating the liquid crystal display device with an inverted TFT structure in which the positions of the array substrate and the color filter substrate are opposite.

Hereinafter, a liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

4 is a plan view illustrating unit pixels of an array substrate for a liquid crystal display according to the present invention.

As shown, the gate wiring 120 and the gate electrode 125 extending from the gate wiring 120 are formed in one direction on the substrate 110. The data line 130 is formed to vertically cross the gate line 120 to define the pixel area P. Referring to FIG.

The first barrier pattern 151 is formed to have a width wider than that of the gate wiring 120 at a lower portion overlapping the gate wiring 120. In addition, a second barrier pattern 152 is formed at a lower portion overlapping with the data line 130 to have a width wider than that of the data line 130, and the second barrier pattern 152 is a gate line 120. And spaced apart design.

That is, the first and second barrier patterns 151 and 152 may protrude to the outside of each of the data line 130 and the gate line 120. In particular, the first barrier pattern 151 functions to improve contact characteristics between the substrate 110, the gate wirings, and the electrodes 120 and 125.

A thin film transistor T is formed at an intersection point of the gate line 120 and the data line 130. The thin film transistor T may include a gate electrode 125, a semiconductor layer (not shown) formed on an upper portion of the gate electrode 125, and a source electrode contacting the semiconductor layer and extending from the data line 130. 132 and a drain electrode 134 spaced apart from the source electrode 132.

The semiconductor layer includes an active layer 140 made of pure amorphous silicon (a-Si: H), and an ohmic contact layer (not shown) made of amorphous silicon (n + a-Si: H) containing impurities. The first amorphous pattern 171 and the second amorphous pattern (not shown) extending from the active layer 140 and the ohmic contact layer, respectively, extend below the data line 130. In particular, the first amorphous pattern 171 protrudes out of the data line 130.

The pixel electrode 170 in contact with the drain electrode 134 through the drain contact hole CH2 exposing a part of the drain electrode 134 is configured to correspond to the pixel region P. Referring to FIG.

The pixel electrode 170 extends to the gate wiring 120 at the front end, the gate wiring 120 at the front end is the first electrode, and the pixel electrode 170 overlapping the first electrode is the second electrode. A storage capacitor Cst having an insulating layer interposed between the first and second electrodes overlapped with each other is formed as a dielectric layer.

The characteristic feature of the above-described configuration is that by forming the first and second barrier patterns corresponding to the overlapped lower portions of the data lines and the gate lines, the process of forming the black matrix corresponding to the color filter substrate can be omitted. This will be described later.

The array substrate for a liquid crystal display device according to the present invention is manufactured in a four mask process.

5A through 5H are cross-sectional views illustrating a process sequence by cutting along the line VV ′ of FIG. 4, which will be described in detail with reference to the drawings.

5A through 5E are cross-sectional views illustrating a first mask process step.

As shown in FIG. 5A, a step of defining a switching region S, a pixel region P, a gate region G, and a data region D is performed on the substrate 110.

The first metal layer is selected from the group of conductive metal materials including molybdenum and molybdenum alloy on the substrate 110 in which the switching region S, the pixel region P, the gate region G, and the data region D are defined. Form 120a. Subsequently, the second metal layer 121a is selected from the group of conductive metals such as copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) on the first metal layer 120a. ).

In this case, the first metal layer 120a is formed for the purpose of improving contact characteristics between the interface between the second metal layer 121a and the substrate 110. In particular, when the second metal layer 121a is formed of copper and a copper alloy, the first metal layer 120a prevents the occurrence of lifting due to poor contact with the substrate 110.

As shown in FIG. 5B, a photoresist is formed on the substrate 110 on which the first metal layer 120a and the second metal layer 121a are formed to form a photosensitive layer 180. Next, a step of aligning the halftone mask HTM including the transmissive part T1, the transflective part T2, and the blocking part T3 is spaced apart from the substrate 110 on which the photosensitive layer 180 is formed. do.

The halftone mask HTM forms a semi-transparent film on the transflective portion T2 to lower the intensity of light or to reduce the amount of light transmitted so that the photosensitive layer 180 may be incompletely exposed. In this case, in addition to the halftone mask HTM, a slit mask may be used to control the amount of light transmitted by placing a slit shape on the transflective portion T2.

In addition, the blocking unit T3 functions to completely block light, and the transmitting unit T1 transmits light and completely exposes the light by chemical change of the photosensitive layer 180 exposed to the light.

In this case, the blocking portion T1 is disposed between the semi-transparent portions T2 on both sides of the switching region S, and the blocking portion T3 is disposed between the semi-transparent portions T2 on both sides of the gate region G. ), The transflective portion T2 is disposed in the transflective portion T2 and all regions except for the transmissive portion T1 corresponding to the data region D. FIG.

Next, as shown in FIG. 5C, an exposure and development process is performed on the mask (HTM of FIG. 5B), and the thickness is reduced by about half on both sides corresponding to the switching region S and the thickness is changed on the center. The first photosensitive pattern 182 having no gap, the second photosensitive pattern 184 having a thickness lowered by about half on both sides, and having no change in thickness at the center corresponding to the gate region G, and the data region D The third photosensitive pattern 186 having a thickness lowered by about half is formed, respectively, and all the photosensitive layers (180 of FIG. 5B) corresponding to the entire region except for this are removed to remove the second metal layer (121a of FIG. 5B). ) Is exposed.

Next, using the first to third photosensitive patterns 182, 184, and 186 as masks, the exposed second metal layer and the first metal layer (120a of FIG. 5B) under the second metal layer are sequentially patterned. Barrier metal patterns 150a patterned in an island shape are formed to correspond to the gate line 120, the gate electrode 125 extending from the gate line 120, and the data area D in one direction.

In this case, a first barrier pattern 151 patterned with the same width as the gate lines and the electrodes 120 and 125 is formed under the gate lines and the electrodes 120 and 125. In the barrier metal pattern 152a, the first metal pattern 120b and the second metal pattern 121b are sequentially stacked.

Next, as illustrated in FIG. 5D, ashing of the first to third photosensitive patterns (FIGS. 5C 182, 184, and 186) may be performed to determine the first and second photosensitive patterns 182 and 184. The thickness is reduced to about half, and the third photosensitive pattern is removed to expose the lower second metal pattern 121b. In this case, a portion of the gate line and the electrodes 120 and 125 are exposed to both sides of each of the first and second photosensitive patterns 282 and 284.

As shown in FIG. 5E, the first and second photosensitive patterns (182 and 184 of FIG. 5D) are used as masks, and the exposed second metal patterns (121b of FIG. 5D), the gate wirings, and the electrodes 120, 125 is patterned to form a second barrier pattern 152 corresponding to the data area D. FIG. In this case, a portion of the gate line and the electrodes 120 and 125 are removed to expose the first barrier pattern 151 to the outside.

The first and second barrier patterns 151 and 152 may function to shield light incident from a backlight unit (not shown) at an overlapping lower portion of the gate line 120 and the data line 130.

Next, the first and second photosensitive patterns (182 and 184 of FIG. 5D) are removed by a strip process. In this way, the first mask process step is finally completed.

5F is a process cross sectional view showing a second mask process step;

As shown in FIG. 5F, silicon oxide (SiO ₂ ) and silicon nitride (I) are formed on the substrate 110 on which the gate wiring 120, the gate electrode 125, and the first and second barrier patterns 151 and 152 are formed. The gate insulating layer 145 is formed of one selected from the group of inorganic insulating materials including SiNx.

Next, a data line 130 on the gate insulating layer 145 perpendicular to the gate line 120 to define the pixel region P, a source electrode 132 extending from the data line 130, and A drain electrode 134 spaced apart from the source electrode 132 is formed. In this case, an active layer 140 made of pure amorphous silicon (a-Si: H) and an amorphous silicon layer (n + a-Si: H) containing impurities are formed below the source and drain electrodes 132 and 134. The ohmic contact layer 141 is sequentially stacked. The active layer 140 and the ohmic contact layer 141 are referred to as a semiconductor layer 142.

In addition, the first amorphous pattern 171 and the second amorphous pattern 172 that extend from the active layer 140 and the ohmic contact layer 141, respectively, extend below the data line 130. In particular, the first amorphous pattern 171 protrudes to the outside of the data line 130. The gate electrode 125, the semiconductor layer 142, and the source and drain electrodes 132 and 134 are referred to as a thin film transistor T.

5G is a process cross sectional view showing a third mask process step;

As shown in FIG. 5G, an inorganic insulating material group including silicon nitride (SiNx) and silicon oxide (SiO ₂ ) on an entire upper surface of the substrate 110 on which the data line 130 and the thin film transistor T are formed. The passivation layer 155 is formed of one selected from the group consisting of one or a group of organic insulating materials including acrylic resin and benzocyclobutene (BCB).

Next, the passivation layer 155 corresponding to the drain electrode 134 is patterned to form a drain contact hole CH2 exposing a part of the drain electrode 134.

5H is a process sectional view showing a fourth mask process step;

As shown in FIG. 5H, one selected from a group of transparent conductive metals such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the passivation layer 155 including the drain contact hole CH2. A transparent metal layer (not shown) is formed and patterned to form the pixel electrode 170 in contact with the drain electrode 134 corresponding to the pixel region P. Referring to FIG.

The pixel electrode 170 extends to overlap the gate wiring 120 of the front end, and the pixel wiring 170 of the front end is the first electrode, and the pixel electrode 170 overlapping the first electrode is removed. A storage capacitor Cst is formed as a second electrode, and the gate insulating layer 145 and the passivation layer 155 interposed between the overlapping spaces of the first and second electrodes are formed as dielectric layers.

As described above, the array substrate for a liquid crystal display device according to the present invention can be produced by a four mask process.

The array substrate manufactured by the aforementioned four mask process is completed as a liquid crystal panel through a cell process step of opposing the color filter substrate. Hereinafter, the liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings. do.

FIG. 6 is a cross-sectional view taken along the line VI-VI 'of FIG. 4, and shows the color filter substrate bonded together with the array substrate.

As illustrated, the array substrate 110 and the color filter substrate 105 each divided into the display area AA and the non-display area NAA are opposed to each other, and the array substrate 110 and the color filter substrate ( The liquid crystal layer 115 is interposed in the space between the gaps 105. The array substrate 110, the color filter substrate 105, and the liquid crystal layer 115 form a liquid crystal panel 190. The backlight unit 195 serving as a light source is positioned on the rear surface of the color filter 105.

A barrier pattern 152 that shields the data region D of the lower surface of the transparent substrate 102 of the array substrate 110, a gate insulating layer 145 that covers the second barrier pattern 152, and the gate insulating layer The semiconductor pattern 173 including the data line 130 corresponding to the data region D under the data region and the first and second amorphous patterns 171 and 172, and a protective layer covering the data line 130. 155, the plurality of pixel electrodes 170 respectively disposed in both pixel areas P under the passivation layer 155, and the lower alignment layer 119 under the plurality of pixel electrodes 170 are sequentially disposed.

On the other hand, the red (R) sub color filter (not shown) and the green (G) sub color filter sequentially patterned on the upper surface of the transparent substrate 101 of the color filter substrate 105 at the boundary of the non-display area (NAA). A color filter layer 116 including a 116b and a blue (B) sub color filter 116c, a common electrode 185 corresponding to the entire upper surface of the color filter layer 116, and an upper portion of the common electrode 185. In order to secure a uniform cell gap between the array substrate 110 and the color filter substrate 105, a patterned column spacer (not shown) and an upper alignment layer 118 covering the column spacer are sequentially disposed.

In general, the column spacer is selected from the group of organic insulating materials and is formed at a position corresponding to the gate wiring 120 (see FIG. 4).

In the above-described configuration, since the positions of the array substrate 110 and the color filter substrate 105 are inverted up and down, light incident from the backlight unit 195 passes through the color filter substrate 105 first.

In detail, the reverse TFT structure in which the positions of the array substrate 110 and the color filter substrate 105 are inverted up and down as in the present invention may include a sub-color filter having little light (not shown) incident from the backlight unit 195. The green (G) sub color filter, the blue (B) sub color filter, and the array element are sequentially penetrated to implement an image.

In this case, the second barrier pattern 152 that shields the data area D may be positioned at the top to completely shield light incident from the front and left and right sides incident from the backlight unit 95.

That is, in the present invention, a process of designing the black matrix (12 of FIG. 3) by designing the first barrier pattern 151 of FIG. 4 and the second barrier pattern 152 corresponding to the non-display area NAA will be omitted. Has the advantage.

Therefore, in the present invention, the step of forming a black matrix can be omitted by applying an inverted TFT structure in which the positions of the array substrate and the color filter substrate are opposite to each other, thereby improving production yield.

However, the present invention is not limited to the above embodiments, and it will be apparent that various changes and modifications can be made without departing from the spirit and the spirit of the present invention.

1 is a plan view showing a unit pixel of a conventional array substrate for a liquid crystal display device.

FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

3 is a cross-sectional view taken along the line III-III ′ of FIG. 2.

4 is a plan view showing unit pixels of an array substrate for a liquid crystal display according to the present invention;

5A to 5H are cross-sectional views taken along the line VV ′ of FIG. 4 and shown in a process sequence.

6 is a cross-sectional view taken along the line VI-VI 'of FIG. 4.

* Explanation of symbols for the main parts of the drawings *

110: substrate 120: gate wiring

125 gate electrode 130 data wiring

132: source electrode 134: drain electrode

140: active layer 151, 152: first and second barrier patterns

170: pixel electrode 171: first amorphous pattern

CH2: Drain contact hole Cst: Storage capacitor

Claims (12)

A substrate; A gate wiring formed in one direction on the substrate; A data line configured to vertically cross the gate line; A thin film transistor configured at an intersection point of the gate line and the data line; A pixel electrode in contact with the thin film transistor; A first barrier pattern configured to have a width wider than a width of the gate wiring corresponding to a lower portion of the gate wiring; A second barrier pattern configured to have a width wider than a width of the data line under the overlapping data line; Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the gate wirings and the electrodes and the first and second barrier patterns are formed on the same layer. The method of claim 1, And the first and second barrier patterns are selected from a group of conductive materials including molybdenum and molybdenum alloys. The method of claim 1, And the first and second barrier patterns function to shield light. The method of claim 1, And the first and second barrier patterns have a function of improving contact characteristics between interfaces between the substrate, the gate lines, and electrodes. The method of claim 1, And the gate wiring and the electrode are selected from a group of conductive metals such as copper, molybdenum, aluminum, aluminum alloy, and chromium. The method of claim 1, The pixel electrode extends with the gate wiring at the front end, the gate wiring at the front end as the first electrode, the pixel electrode overlapped with the first electrode as the second electrode, and the first and second electrodes. An array substrate for a liquid crystal display device, comprising a storage capacitor having an insulating layer interposed in an overlapping interspace as a dielectric layer. An array substrate according to claim 1; A color filter substrate opposed to the array substrate and defined as a display area and a non-display area; A liquid crystal layer interposed between the array and the space between the color filter substrate; A backlight unit positioned on a rear surface of the color filter substrate spaced apart from the back surface; Red, green, and blue sub color filters sequentially patterned on the non-display area on the color filter substrate; Common electrode on the red, green and blue sub color filters Liquid crystal display comprising a. Forming a gate wiring formed in one direction on the substrate and a gate electrode extending from the gate wiring; Forming a first barrier pattern having a width wider than that of the gate wiring and the electrode corresponding to a lower portion of the gate wiring and the electrode, and a second barrier pattern patterned in an island shape corresponding to the data area; Forming a gate insulating film on the substrate on which the gate wiring and the electrode and the first and second barrier patterns are formed; Forming a data line perpendicular to the gate line, a source electrode extending from the data line, a drain electrode spaced apart from the source electrode, and a semiconductor layer under the source and drain electrodes on the gate insulating layer; ; Forming a protective film exposing a portion of the drain electrode on a substrate on which the semiconductor layer, the source and drain electrodes, and the data wiring are formed; Forming a pixel electrode in contact with the drain electrode on the passivation layer Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 9, And the first and second barrier patterns are selected from a group of conductive materials including molybdenum and molybdenum alloys. The method of claim 9, And the gate wiring and the electrode are formed of one selected from a group of conductive metals such as copper, molybdenum, aluminum, aluminum alloy, and chromium. The method of claim 9, The pixel electrode extends with the gate wiring at the front end, the gate wiring at the front end as the first electrode, the pixel electrode overlapping with the first electrode as the second electrode, and the first and second electrodes. An array substrate for a liquid crystal display device, characterized in that a storage capacitor having an insulating layer interposed in an overlapping interspace is formed as a dielectric layer.

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