KR20040050237A - Array substrate for LCD and Method for fabricating of the same - Google Patents

Abstract

PURPOSE: An array substrate for an LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to improve an aperture ratio by forming a color filter at a lower portion of a top gate type TFT(Thin Film Transistor) array and constructing a black matrix at a lower portion of a gate wire and a data wire of the TFT. CONSTITUTION: A switching region(T), a pixel region(P), a data region(D), and a gate/storage region(G/S) are defined on a substrate(100). A black matrix(102) corresponding to the switching region(T), the data region(D), and the gate region(G) is formed by depositing and then patterning Cr or Cr/CrOx on the substrate(100). Color filters(104a,104b) are formed on the pixel region(P). A buffer layer(106) is formed on the substrate(100) by coating one of organic insulation groups including BCB or acryl resin or polyimide on the entire surface of the substrate(100). A source electrode(112) and a drain electrode(114) corresponding to the switching region(T) are formed separately. A data wire(116) corresponding to the data region(D) is formed on the buffer layer(106). A pixel electrode(138) is formed at the pixel region(P), contacting an exposed drain electrode(114) and an exposed island shape metal layer(118).

Description

Array substrate for LCD and its manufacturing method {Array substrate for LCD and Method for fabricating of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device having a TFT on color filter (TOC) structure that forms a color filter under a thin film transistor array unit, and a manufacturing method thereof.

In general, a liquid crystal display device displays an image by using optical anisotropy and birefringence characteristics of liquid crystal molecules. When an electric field is applied, the alignment of liquid crystals is changed, and the characteristics of light transmission vary according to the arrangement direction of the changed liquid crystals.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by the electric field is a device that represents the image by the transmittance of light that varies accordingly.

1 is a view schematically showing a general liquid crystal display device.

As shown, a general color liquid crystal display 11 includes a color filter 7 and a color filter 7 including a black matrix 6 formed between a sub color filter 8 and each sub color filter 8. The upper substrate 5 having the common electrode 18 deposited thereon, the pixel region P, and the pixel electrode 17 and the switching element T formed in the pixel region, and the pixel region P The liquid crystal 14 is filled between the lower substrate 22 and the upper substrate 5 and the lower substrate 22 on which array wiring is formed.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 crosses the plurality of thin film transistors TFT. ) And data wirings 15 are formed.

In this case, the pixel area P is an area defined by the gate wiring 13 and the data wiring 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area P as described above.

The pixel electrode 17 uses a transparent conductive metal having a relatively high transmittance of light, such as indium-tin-oxide (ITO).

A storage capacitor C connected in parallel with the pixel electrode 17 is formed on the gate wiring 13, and a part of the gate wiring 13 is used as the first electrode of the storage capacitor C, and a second As the electrode, an island-like metal layer 30 formed of the same material as the source and drain electrodes is used.

In this case, the island-shaped metal layer 30 is configured to be in contact with the pixel electrode 17 to receive a signal of the pixel electrode.

As described above, when the upper color filter substrate 5 and the lower array substrate 22 are bonded to each other to produce a liquid crystal panel, light leakage defects due to the bonding error between the color filter substrate 5 and the array substrate 22 may be reduced. It is very likely to occur.

A description with reference to FIG. 2 is as follows.

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1.

As described above, the first substrate 22, which is an array substrate, and the second substrate 5, which is a color filter substrate, are spaced apart from each other, and the liquid crystal layer 14 is disposed between the first and second substrates 22, 5. This is located.

The thin film transistor T including the gate electrode 32, the active layer 34, the source electrode 36, and the drain electrode 38 is disposed on the array substrate 22, and the thin film transistor T is disposed on the thin film transistor T. A protective film 40 is configured to protect it.

In the pixel region P, a transparent pixel electrode 17 is formed in contact with the drain electrode 38 of the thin film transistor T. A storage capacitor C connected in parallel with the pixel electrode 17 includes a gate line 13. It is configured on the top.

The upper substrate 5 includes a black matrix 6 corresponding to the gate wiring 13, the data wiring 15, and the thin film transistor T, and corresponds to the pixel region P of the lower substrate 22. Thus, color filters 7a, 7b, and 7c are formed.

In this case, the general array substrate is configured such that the data line 15 and the pixel electrode 17 are spaced apart by a predetermined distance A to prevent vertical cross talk, and the gate line 13 and the pixel electrode are spaced apart from each other. In addition, a predetermined interval (B) is configured to be spaced apart.

Since the spaces A and B spaced apart between the data line 15 and the gate line 13 and the pixel electrode 17 are regions where light leakage occurs, a black matrix formed on the upper color filter substrate 5 matrix) (6) will cover this part.

In addition, the black matrix 6 formed on the thin film transistor T serves to block the light so that the light radiated from the outside does not affect the active layer 34 through the passivation layer 40. .

However, a misalignment may occur during the process of bonding the upper substrate 5 and the lower substrate 22. In view of this, a margin of a constant value is determined when designing the black matrix 6. Since the design is carried out with reference to), the aperture ratio decreases by that amount.

In addition, in the case where the bonding error beyond the margin occurs, there is often a case of light leakage defects in which the light leakage regions A and B are not covered by the black matrix 6.

In this case, since the light leakage appears to the outside, there is a problem of degrading the image quality.

The present invention has been proposed to solve the above-described problems. To summarize the present invention, a color filter is formed below the top gate thin film transistor array unit, and a black matrix is disposed below the thin film transistor, the gate wiring, and the data wiring. Configure

In this case, the first configuration is to form a protective film on the thin film transistor, and then to form a transparent pixel electrode in contact with the thin film transistor on the protective film, the second structure does not form the protective film, the transparent pixel electrode The third structure is to form the thin film transistor array unit after the transparent pixel electrode is formed.

As described above, the TOC structure directly configures the black matrix under the gate wiring, the data wiring, and the thin film transistor, and thus, unlike the related art, it is not necessary to consider the bonding margin when designing the black matrix. There is an advantage that the display device can be manufactured.

1 is a diagram schematically illustrating a configuration of a general liquid crystal display device.

FIG. 2 is a cross-sectional view of the liquid crystal display device taken along the line II-II ′ of FIG. 1;

3 is a plan view schematically showing the configuration of an array substrate for a liquid crystal display device according to the present invention;

4A to 4F are cross-sectional views illustrating the process sequence according to the first embodiment of the present invention, taken along the line IV-IV ′ of FIG. 3;

FIG. 5 is a cross-sectional view illustrating a cross-sectional configuration according to a second embodiment of the present invention, cut along line IV-IV ′ of FIG. 3;

6A to 6E are cross-sectional views illustrating the process sequence according to the third embodiment of the present invention, taken along the line IV-IV ′ of FIG. 3.

<Brief description of the main parts of the drawing>

100: substrate 102: black matrix

104a, b, c Color filter 106 Buffer layer

112 source electrode 114 drain electrode

116: data wiring 118: island-shaped metal layer

120: impurity amorphous silicon layer

128 gate insulating film 130 gate electrode

132: gate wiring 138: pixel electrode

According to an aspect of the present invention, an array substrate for a liquid crystal display device includes: a substrate in which a pixel region, a switching region, a gate region, and a data region are defined; A black matrix including an opening corresponding to the pixel area and configured to correspond to the switching area, the gate area, and the data area; A color filter configured to correspond to the pixel region; A buffer layer which is an insulating film formed on the black matrix and the color filter; A data line formed over the buffer layer and extending in one direction corresponding to the data area; A gate wiring vertically intersecting the data wiring and the insulating layer therebetween and extending in one direction corresponding to the gate region; A thin film transistor including a source electrode and a drain electrode, an active layer formed over the source and drain electrodes, and a gate electrode formed over the active layer with an insulating layer interposed therebetween. Wow; And a pixel electrode configured to be in contact with the drain electrode and formed in the pixel region.

A protective film, which is an insulating film, is further formed between the thin film transistor and the pixel electrode.

The protective film is formed of one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ).

The pixel electrode may be in contact with the drain electrode under the drain electrode.

An auxiliary capacitor portion further comprising an island-shaped metal layer with an insulating film interposed therebetween, serving as a first electrode and a gate wiring thereon as a second electrode.

An array substrate for a liquid crystal display device according to an aspect of the present invention includes the steps of defining a pixel region, a switching region, a gate region and a data region on a substrate; Forming a black matrix corresponding to the pixel area, the opening including a corresponding opening, and corresponding to the switching area, the gate area, and the data area; Forming a color filter corresponding to the pixel area; Forming an insulating layer buffer layer on an entire surface of the substrate including the black matrix and the color filter; The first metal layer and the impurity amorphous silicon layer are stacked and patterned on the buffer layer, the data lines extending in one direction corresponding to the data region, the source and drain electrodes spaced at predetermined intervals, and the ohmic on the source and drain electrodes. Forming a contact layer; Forming an island-like active layer over the source and drain electrodes; A gate insulating film and a second metal layer are stacked and patterned on the entire surface of the substrate on which the active layer is formed, and connected to the gate insulating film, the gate electrode and the gate electrode on the ohmic contact layer, and extend in one direction corresponding to the gate area. Forming a data line; Forming a pixel electrode in contact with the drain electrode corresponding to the pixel region.

The black matrix is formed of a double layer of chromium (Cr) or chromium / chromium oxide (Cr / CrO _X ), and the buffer layer is an organic insulating material including benzocyclobutene (BCB) and an acrylic resin (resin). It may be formed by applying or depositing one selected from the group or an organic insulating material group including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ).

The first metal layer and the second metal layer are formed of a conductive metal group including aluminum (Al), aluminum alloy (AlNd), chromium (Cr), tungsten (W), copper (Cu), and titanium (Ti). .

And forming an inorganic insulating layer between the pixel electrode and the thin film transistor, which is silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ).

An auxiliary capacitor portion is further formed to form an island-shaped metal layer under the gate wiring with an insulating film interposed therebetween as a first electrode and a gate wiring thereon as a second electrode.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: defining a pixel region, a switching region, a gate region, and a data region on a substrate; Forming a black matrix corresponding to the pixel area, the opening including a corresponding opening, and corresponding to the switching area, the gate area, and the data area; Forming a color filter corresponding to the pixel area; Forming a buffer layer, which is an insulating film, on the entire surface of the substrate including the black matrix and the color filter; Forming a pixel electrode over a portion of the switching region and a buffer layer corresponding to the pixel region; The first metal layer and the impurity amorphous silicon layer are stacked and patterned on an upper portion of the buffer layer corresponding to the entire surface of the substrate on which the pixel electrode is formed, and data lines extending in one direction corresponding to the data region, and sources and drains spaced at predetermined intervals. Forming an ohmic contact layer over the electrode and the source and drain electrodes; Forming an island-like active layer over the source and drain electrodes; A gate insulating film and a second metal layer are stacked and patterned on the entire surface of the substrate on which the active layer is formed, and connected to the gate insulating film, the gate electrode and the gate electrode on the ohmic contact layer, and extend in one direction corresponding to the gate area. Forming a data line.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First Embodiment

3 is a plan view schematically illustrating a configuration of an array substrate for a liquid crystal display device having a TFT on color filter (TOC) structure according to the present invention.

As shown in the drawing, the data forming the gate lines 102 extending in one direction on the substrate 100 in parallel with each other and crossing the gate lines 102 perpendicularly to define a plurality of pixel regions P. As shown in FIG. The wiring 116 is configured.

The thin film transistor T including the gate electrode 104, the active layer 108, and the source and drain electrodes 112 and 114 is formed at the point where the gate line 102 and the data line 116 intersect.

In this case, the thin film transistor is a top gate type thin film transistor in which a source and a drain electrode, an active layer, and a gate electrode are sequentially formed.

A transparent pixel electrode is formed in the pixel region P defined by the crossing of the two wires 102 and 116.

In the above-described configuration, a black matrix is formed under the thin film transistor, the gate wiring, and the data wiring, and color filters of red, green, and blue are sequentially formed in each pixel region under the pixel electrode.

The pixel electrode is connected in parallel with the storage capacitor C _st configured on the gate wiring 102.

The storage capacitor C _st uses a portion of the gate wiring 102 as a first electrode and an island metal layer below the second electrode.

The island-shaped metal layer is formed on the same layer as the data line and is in contact with the pixel electrode.

As shown in the figure, the TOC structure includes a black matrix 124 and red, green, and blue color filters 130a, 130b, and 130c formed under the thin film transistor T array unit.

The black matrix 124 covers the light leakage region, and as described above, the black matrix 124 is configured to correspond to the gate wiring, the data wiring 116, and the thin film transistor T.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to a first embodiment of the present invention will be described with reference to FIGS. 4A to 4F.

4A to 4F are cross-sectional views illustrating the process sequence according to the first embodiment of the present invention, taken along the line IV-IV ′ of FIG. 3.

(Cutting lines IV-IV` in FIG. 3 are cutting lines between the thin film transistor and the pixel.)

As shown in FIG. 4A, the switching region T, the pixel region P, the data region D, and the gate / storage region G / S are defined on the substrate 100.

Subsequently, by depositing and patterning chromium (Cr) or chromium / chromium oxide (Cr / CrO _X ) on the substrate 100 in which the plurality of regions are defined, the switching region T and the data region D and The black matrix 102 is formed corresponding to the gate region G.

Next, color resins containing pigments representing a specific color (red, green, or blue) are applied to form color filters 104a, 104b and 104c in the pixel region P. FIG.

In this case, the color filters 104a, 104b and 104c of FIG. 3 represent red, green, and blue, and the color filters 104a, 104b, and 104c may be sequentially processed.

Subsequently, benzocyclobutene (BCB) and acrylic resin (resin) or polyimide are formed on the entire surface of the substrate 100 on which the black matrix 102 and the color filters 104a and 104b and 104c of FIG. 3 are formed. The buffer layer 106 is formed by applying one selected from the group of organic insulating materials including poly-imide.

The buffer layer 106 is formed for the purpose of protecting the lower color filter during the process of forming the thin film transistor array unit.

In this case, an inorganic insulating layer formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SIO ₂ ) may be used as the buffer layer. The inorganic insulating layer has an advantage of excellent interface characteristics with metal films directly contacting the buffer layer among the thin film transistor array units formed thereafter.

As shown in FIG. 4B, chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), copper (Cu) and aluminum (Al) are formed on the entire surface of the substrate 100 on which the buffer layer 106 is formed. ) And one selected from the group of conductive metals including aluminum alloy (AlNd) to form a first metal layer 108, and subsequently, an amorphous silicon layer including impurities on the first metal layer 108. 110).

Subsequently, when the first metal layer 108 and the impurity amorphous silicon layer 110 are collectively etched, the source electrode 112 spaced apart from each other in correspondence with the switching region T, as shown in FIG. 4C. The drain electrode 114, the data line 116 extending in one direction with respect to the substrate 100 in a plane from the source electrode 112, and an island shape corresponding to the gate / storage region G / S. The metal layer 118 is formed, and the patterned amorphous silicon layer 120 is positioned on the top of each component.

In this case, the amorphous silicon layer 120 positioned above the source and drain electrodes 112 and 114 is particularly referred to as an ohmic contact layer.

As shown in FIG. 4D, pure amorphous silicon (a-Si: H) is deposited and patterned on the entire surface of the substrate 100 on which the source and drain electrodes 112 and 114 and the ohmic contact layer 120 are formed. And an active layer 122 formed in an island shape over the drain electrodes 112 and 114.

In this case, the active layer 122 may be formed of crystalline silicon to improve operating characteristics of the device.

Next, the gate insulating layer 124 is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 on which the active layer 122 is formed. Form.

Subsequently, the conductive metal as described above is deposited on the gate insulating layer 124 to form the second metal layer 126.

The gate insulating layer 124 and the second metal layer 126 are collectively etched through dry etching, and as shown in FIG. 4E, a gate overlapping a portion corresponding to the spaced apart space of the source and drain electrodes 112 and 114, as shown in FIG. 4E. An insulating film 128 and a gate electrode 130 are formed, and a gate wiring 132 connected to the gate electrode 130 and intersecting with the data wiring 116 to pass through one side of the pixel region P is formed. .

In this case, the gate line 132 passes over the island-shaped metal layer 118.

In this portion, the storage capacitor portion C _st is formed using the metal layer 118 as the first electrode with the gate insulating layer 128 interposed therebetween, and the second gate electrode 132 as the second electrode.

The gate line 132 is generally formed of a double metal layer containing aluminum.

Next, a transparent organic insulating material group including benzocyclobutene (BCB) and an acrylic resin is selected on the entire surface of the substrate 100 on which the gate electrode 130 and the gate insulating layer 128 are formed. Deposition of one to form a protective film 134, the drain electrode 114 and the drain contact to expose a portion of the drain electrode 114 by etching the protective film 134 corresponding to the island-shaped metal layer 118 A storage contact hole 138 exposing the hole 136 and a portion of the island-shaped metal layer 118 is formed.

As shown in FIG. 4F, one selected from a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO) on the entire surface of the substrate 100 on which the passivation layer 134 is formed. By depositing and patterning, the pixel electrode 138 positioned in the pixel region P is formed while contacting the exposed drain electrode 114 and the exposed island metal layer 118.

Through the above process, the top gate type thin film transistor array unit having the TOC structure according to the first embodiment of the present invention can be formed.

The manufacturing process of the first embodiment includes, except for a color filter manufacturing process, a first mask process for forming a black matrix, a second mask process for forming source and drain electrodes, a data line, and an ohmic contact layer, and the active layer. And a third mask process for forming the gate insulating film and a gate electrode, a fifth mask process for patterning the protective film, and a sixth mask process for forming the pixel electrode.

Hereinafter, the second embodiment is a modification of the first embodiment, and can be configured to reduce one mask than the first embodiment.

The second embodiment is

The second embodiment of the present invention is characterized by omitting the process of forming the protective film in the first embodiment.

5 is a cross-sectional view of the configuration according to the second embodiment of the present invention, taken along line IV-IV` of FIG. 3.

As shown, the configuration of the second embodiment is the same as the process of forming the thin film transistor and the data and gate wirings 116 and 132 as compared with the first embodiment described above.

That is, the black matrix 102 is formed by the first mask process, the color filters 104a and 104b are formed by the next process, and the source and drain electrodes 112 and 114 and the ohmic contact layer 120 are formed by the second mask process. Forming the active layer 122 in the third mask process, and forming the gate insulating film 128 and the gate electrode 130 in the fourth mask process.

In the second embodiment, as shown in the drawing, after the process of forming the gate electrode 130 is finished, the pixel region (5) is contacted with the drain electrode 114 and the island-shaped metal layer 118 in a fifth mask process. A pixel electrode 138 positioned at P) is formed.

According to the above process, an array substrate for a liquid crystal display device having a TOC structure according to a second embodiment of the present invention can be manufactured.

Hereinafter, another modification of the first embodiment will be described with reference to the third embodiment.

Third Embodiment

The third embodiment of the present invention is characterized in that the pixel electrode is first formed before forming the top-gate thin film transistor array unit, and this configuration can also reduce one mask as compared with the first embodiment.

6A to 6E, a manufacturing process of an array substrate for a liquid crystal display device having a TOC structure according to a third embodiment of the present invention will be described.

6A through 6E are cross-sectional views taken along the line IV-IV ′ of FIG. 3 and illustrating the present invention according to the process sequence according to the third embodiment.

First, as illustrated in FIG. 6A, the switching region T, the pixel region P, the data region D, the gate region G, and the storage region S are defined on the substrate 200.

In succession, the switching is performed by depositing and patterning chromium (Cr) or chromium / chromium oxide (Cr / CrO _X ) on the substrate 200 in which the plurality of regions T, P, D, and G / S are defined. The black matrix 202 is formed corresponding to the region T, the data region G, and the gate region G.

Next, color resins containing pigments representing a specific color (red, green, or blue) are applied to form color filters 204a, 204b, and 204c in the pixel region.

In this case, the color filters 204a, 204b, and 204c represent red, green, and blue, and the color filters 204a, 204b, and 204c may be sequentially processed.

Subsequently, benzocyclobutene (BCB) and acrylic resin (resin) or polyimide (poly-) are formed on the entire surface of the substrate 200 on which the black matrix 202 and the color filters 204a, 204b, and 204c are formed. A buffer layer 206 is formed by applying one selected from a group of organic insulating materials including an imide).

The buffer layer 206 is then formed for the purpose of protecting the lower color filter during the process of forming the thin film transistor array unit.

In this case, an inorganic insulating layer formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SIO ₂ ) may be used as the buffer layer. The inorganic insulating layer has an excellent interface property with metal layers directly contacting the buffer layer 206 among the thin film transistor array units formed thereafter.

As shown in FIG. 6B, one selected from a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO) on the front surface of the substrate 200 on which the buffer layer 206 is formed. By depositing and patterning, the pixel electrode 208 positioned in the pixel region is formed while extending to a portion of the switch region T and a portion of the gate / storage region G / S.

Next, chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), and an aluminum alloy are formed on the entire surface of the substrate 200 on which the pixel electrode 208 is formed. One selected from the group of conductive metals including (AlNd) is deposited to form a first metal layer 210, and subsequently, an amorphous silicon layer 212 including impurities is formed on the first metal layer 210. .

Subsequently, when the first metal layer 210 and the impurity amorphous silicon layer 212 are collectively etched, the source electrode 212 spaced apart from each other in correspondence with the switching region T, as shown in FIG. 6C. The drain electrode 214, the data line 216 extending in one direction with respect to the substrate 200 in a plane from the source electrode 212, and an island shape corresponding to the gate / storage region G / S. A metal layer 218 is formed, and a patterned amorphous silicon layer 218 is positioned on top of each component.

In this case, the amorphous silicon layer 218 located above the source and drain electrodes 212 and 214 is particularly referred to as an ohmic contact layer.

As shown in FIG. 6D, pure amorphous silicon (a-Si: H) is deposited and patterned on the entire surface of the substrate 200 on which the source and drain electrodes 212 and 214 and the ohmic contact layer 220 are formed. And an active layer 224 having an island shape over the drain electrodes 212 and 214.

In this case, the active layer 224 may be formed of crystalline silicon to improve the operation characteristics of the device.

Next, the gate insulating layer 226 is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 200 on which the active layer 224 is formed. Form.

Subsequently, a conductive metal as described above is deposited on the gate insulating film 226 to form a second metal layer 228.

The gate insulating layer 226 and the second metal layer 228 are collectively etched through dry etching, and as shown in FIG. 6E, a gate overlapping a portion corresponding to the spaced apart spaces of the source and drain electrodes 212 and 214, as shown in FIG. 6E. An insulating layer 230 and a gate electrode 232 are formed, and a gate line 234 connected to the gate electrode 232 and intersecting with the data line 230 to define a pixel region P is formed.

In this case, the gate line 234 passes over the island-shaped metal layer 218.

In this portion, the storage capacitor C _st is formed using the metal layer 218 as the first electrode with the gate insulating layer 230 interposed therebetween, and the gate wiring 234 thereon as the second electrode.

The gate line 234 is generally formed of a double metal layer including aluminum (Al).

Through the above-described process, an array substrate for a liquid crystal display device having a TOC structure according to a third embodiment of the present invention can be manufactured.

In the above-described process, except for forming the color filter, a black matrix is formed by the first mask process, a color filter is formed by the next process, and a pixel electrode is formed by the second mask process. The source and drain electrodes and the ohmic contact layer are formed by the third mask process, the active layer is formed by the fourth mask process, and the gate insulating film and the gate electrode are formed by the fifth mask process.

Thus, the third embodiment of the present invention also has the advantage of reducing one mask process compared to the first embodiment.

According to the present invention according to the first and third embodiments described above. In the liquid crystal display of the structure, the array substrate has a color filter and a black matrix formed under the thin film transistor array, and thus, when designing the black matrix, the bonding margin does not have to be taken into consideration. have.

In addition, since the mask process can be reduced through the processes of the second and third embodiments, the process time can be reduced and the cost can be reduced, thereby improving the competitiveness of the product.

Claims (13)

A substrate in which a pixel region, a switching region, a gate region and a data region are defined; A black matrix including an opening corresponding to the pixel area and configured to correspond to the switching area, the gate area, and the data area; A color filter configured to correspond to the pixel region; A buffer layer which is an insulating film formed on the black matrix and the color filter; A data line formed over the buffer layer and extending in one direction corresponding to the data area; A gate wiring vertically intersecting the data wiring and the insulating layer therebetween and extending in one direction corresponding to the gate region; A thin film transistor including a source electrode and a drain electrode, an active layer formed over the source and drain electrodes, and a gate electrode formed over the active layer with an insulating layer interposed therebetween. Wow; A pixel electrode formed in the pixel region in contact with the drain electrode Array substrate for a liquid crystal display device comprising a. The method of claim 1, And a protective film as an insulating film between the thin film transistor and the pixel electrode. The method of claim 1, And the pixel electrode is in contact with the drain electrode under the drain electrode. The method of claim 1, And a storage capacitor portion further comprising an island-shaped metal layer having an insulating film interposed therebetween, serving as a first electrode, and having a second wiring formed thereon as a second electrode. Defining a pixel region, a switching region, a gate region and a data region on the substrate; Forming a black matrix corresponding to the pixel area, the opening including a corresponding opening, and corresponding to the switching area, the gate area, and the data area; Forming a color filter corresponding to the pixel area; Forming a buffer layer, which is an insulating film, on the entire surface of the substrate including the black matrix and the color filter; The first metal layer and the impurity amorphous silicon layer are stacked and patterned on the buffer layer, the data lines extending in one direction corresponding to the data region, the source and drain electrodes spaced at predetermined intervals, and the ohmic on the source and drain electrodes. Forming a contact layer; Forming an island-like active layer over the source and drain electrodes; A gate insulating film and a second metal layer are stacked and patterned on the entire surface of the substrate on which the active layer is formed, and connected to the gate insulating film, the gate electrode and the gate electrode on the ohmic contact layer, and extend in one direction corresponding to the gate area. Forming a data line; Forming a pixel electrode in contact with the drain electrode corresponding to the pixel area; Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 5, wherein The black matrix is a method of manufacturing an array substrate for a liquid crystal display device formed of a double layer of chromium or chromium (Cr) / chromium oxide (CrO _X ). The method of claim 5, wherein The buffer layer is selected from an organic insulating material group including benzocyclobutene (BCB) and an acrylic resin (resin) or an organic insulating material group including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). Method of manufacturing an array substrate for a liquid crystal display device formed by coating or depositing. The method of claim 5, wherein And the active layer is formed of pure amorphous silicon (a-Si: H). The method of claim 5, wherein The first metal layer and the second metal layer are liquid crystals formed of a selected one of conductive metal groups including aluminum (Al), aluminum alloy (AlNd), chromium (Cr), tungsten (W), copper (Cu), and titanium (Ti). Method of manufacturing array substrate for display device. The method of claim 5, wherein And the pixel electrode is formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO). The method of claim 5, wherein And forming an inorganic insulating layer between the pixel electrode and the thin film transistor. The method of claim 5, wherein A method of manufacturing an array substrate for a liquid crystal display device, in which an island-shaped metal layer is further formed with an insulating film interposed therebetween to serve as a first electrode, and an auxiliary capacitor portion further including an upper gate wiring as a second electrode. . Defining a pixel region, a switching region, a gate region and a data region on the substrate; Forming a black matrix corresponding to the pixel region, the opening including a corresponding opening; Forming a color filter corresponding to the pixel area; Forming a buffer layer, which is an insulating film, on the entire surface of the substrate including the black matrix and the color filter; Forming a pixel electrode over a portion of the switching region and a buffer layer corresponding to the pixel region; The first metal layer and the impurity amorphous silicon layer are stacked and patterned on an upper portion of the buffer layer corresponding to the entire surface of the substrate on which the pixel electrode is formed, and data lines extending in one direction corresponding to the data region, and sources and drains spaced at predetermined intervals. Forming an ohmic contact layer over the electrode and the source and drain electrodes; Forming an island-like active layer over the source and drain electrodes; A gate insulating film and a second metal layer are stacked and patterned on the entire surface of the substrate on which the active layer is formed, and connected to the gate insulating film, the gate electrode and the gate electrode on the ohmic contact layer, and extend in one direction corresponding to the gate area. Forming a data line Array substrate manufacturing method for a liquid crystal display device comprising a.