WO2014015617A1 - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
- Publication number
- WO2014015617A1 WO2014015617A1 PCT/CN2012/086228 CN2012086228W WO2014015617A1 WO 2014015617 A1 WO2014015617 A1 WO 2014015617A1 CN 2012086228 W CN2012086228 W CN 2012086228W WO 2014015617 A1 WO2014015617 A1 WO 2014015617A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- array
- array substrate
- electrode
- gate
- groove
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 86
- 239000011347 resin Substances 0.000 claims description 46
- 229920005989 resin Polymers 0.000 claims description 46
- 239000011159 matrix material Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 7
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 32
- 239000010408 film Substances 0.000 description 20
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 238000000034 method Methods 0.000 description 17
- 239000004065 semiconductor Substances 0.000 description 10
- 238000002161 passivation Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- NPXOKRUENSOPAO-UHFFFAOYSA-N Raney nickel Chemical class [Al].[Ni] NPXOKRUENSOPAO-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- RSWGJHLUYNHPMX-ONCXSQPRSA-N abietic acid Chemical compound C([C@@H]12)CC(C(C)C)=CC1=CC[C@@H]1[C@]2(C)CCC[C@@]1(C)C(O)=O RSWGJHLUYNHPMX-ONCXSQPRSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- -1 copper Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
Definitions
- Embodiments of the present invention relate to an array substrate and a display device. Background technique
- TFT-LCDs Thin film transistor liquid crystal displays
- a liquid crystal display device of the prior art generally includes an array substrate, a color filter substrate, and a liquid crystal filled between the two substrates.
- the array substrate may include gate lines, data lines, thin film transistors, and pixel electrodes.
- the color filter substrate may include a black matrix, a colored resin layer, and a transparent conductive layer. The electric field is applied to the liquid crystal molecules through the pixel electrode and the transparent conductive layer, thereby achieving deflection of the liquid crystal molecules.
- the prior art prepares a liquid crystal display device by forming an array substrate on one sheet of glass and forming a color film substrate on another sheet of glass, and finally placing the two substrates on the cassette and injecting a liquid crystal therebetween.
- the array substrate and the color film substrate are not flat, and there are step regions, so that there are many bad phenomena after the box is on the other hand; on the other hand, the process is improved to reduce the step region, to a certain extent.
- the thickness of the substrate is increased, which hinders the development of the liquid crystal display in the direction of thinning. Summary of the invention
- the display device can eliminate the step region caused by the surface unevenness of the array substrate and the color filter substrate and does not increase the thickness of the liquid crystal display device.
- Embodiments of the present invention provide an array substrate including a color film and an array formed on a substrate, the array being located above the color film.
- the color film may include a color resin layer formed on the base substrate, and a transparent layer formed over the color resin layer, the array may include a gate line, a thin film transistor, and a pixel electrode, and the groove may be disposed in the transparent layer At the surface, the gate of the thin film transistor can be located in the recess.
- the color film may further include a black matrix between the colored resin layers, and the grooves may be located above and opposite to the black matrix.
- the depth, width and length of the groove can be respectively related to the thickness, width and width of the gate The lengths are equal.
- the shape of the groove may be the same as the overall shape of the gate line and the gate, and the depth of the groove may be equal to the thickness of the gate line and the gate.
- the array may further comprise a common electrode, and the common electrode may be located below the pixel electrode.
- the common electrode may be located in another recess formed in the transparent layer and in the same horizontal plane as the gate.
- the array may further comprise a common electrode, and the common electrode may be located above the pixel electrode.
- the electrode located above the common electrode and the pixel electrode is a slit electrode.
- the colored resin layer may include a red resin, a green resin, and a blue resin.
- the transparent layer may utilize an acrylic material.
- the present invention also provides a display device comprising the array substrate as described above.
- the array substrate provided by the above technical solution, by arranging the array on the color film and forming a groove in the transparent layer of the color film to set the gate and/or the gate line of the array in the groove, not only the array substrate but also the gate line can be disposed in the groove.
- the overall thickness of the liquid crystal display device is reduced to make it thinner and lighter; the flatness of the liquid crystal display device can also be increased, so that some display defects of the liquid crystal display device can be reduced.
- FIG. 1 is a schematic structural view of a liquid crystal display device according to a first embodiment of the present invention
- FIG. 2 is a schematic structural view of a lower substrate according to a first embodiment of the present invention.
- FIG. 3 is a schematic view of a lower substrate after forming a black matrix pattern according to a first embodiment of the present invention
- FIG. 4 is a schematic view of the lower substrate after forming a colored resin pattern according to the first embodiment of the present invention
- FIG. 5 is a schematic view of a lower substrate after forming a transparent layer according to a first embodiment of the present invention
- FIG. 6 is a schematic view of a lower substrate after forming a gate pattern according to a first embodiment of the present invention
- the lower substrate of an embodiment is formed with an active layer, a source, a drain, and a TFT. a schematic view of a channel region;
- FIG. 8 is a schematic view of a lower substrate after forming a passivation layer pattern according to a first embodiment of the present invention
- FIG. 9 is a schematic view of a lower substrate after forming a pixel electrode pattern according to a first embodiment of the present invention
- Fig. 10 is a view showing the configuration of a liquid crystal display device according to a second embodiment of the present invention. detailed description
- FIG. 1 is a schematic structural view of a liquid crystal display device according to a first embodiment
- FIG. 2 is a schematic structural view of a lower substrate of FIG. 1.
- the liquid crystal display device of this embodiment may include an upper substrate 16, a lower substrate 1, and a liquid crystal 18 filled between the two substrates.
- the lower substrate 1 may include a lower substrate (not shown), a color film formed on the lower substrate, and an array above the color film.
- the upper substrate 16 may include an upper substrate (not shown) and a common electrode 17 formed on the lower surface of the upper substrate.
- the color film may include a black matrix 2 and a color resin layer formed on the upper surface of the lower substrate, and a transparent layer 6 formed on the black matrix 2 and the color resin layer, and the transparent layer 6 may be Made of acrylic material.
- the array may include a gate line (not shown) formed over the transparent layer 6, a data line (not shown), a thin film transistor (TFT) 7 and a pixel electrode 15.
- TFT 7 may include a gate 8, a gate insulating layer 9, a semiconductor layer 10, a doped semiconductor layer 11, a source 12, a drain 13, and a passivation layer 14. .
- a groove is provided at the surface of the transparent layer 6, so that the gate 8 is located in the groove. And the depth and width of the groove may correspond to the thickness and width of the gate 8, respectively Equal, making the surface of the lower substrate flat.
- the transparent layer 6 described in this embodiment may not be provided with a groove, and the gate electrode 8 is directly formed on the transparent layer 6.
- the person skilled in the art can freely select and set according to actual needs.
- the color resin layer may include a red resin 3, a green resin 4, and a blue resin 5, and the black matrix 2 is located between two adjacent resins of the red resin 3, the green resin 4, and the blue resin 5.
- the groove may be disposed above and opposite the black matrix 2.
- the color resin layer may further include other color resins depending on design requirements, and embodiments of the present invention are not limited to the above colors.
- the gate line may also be located in the recess, the shape of the recess may be the same as the overall shape of the gate line and the gate, and the depth of the recess may be equal to the thickness of the gate line and/or the gate.
- the embodiment further provides a method for manufacturing the array substrate of the above liquid crystal display device, which specifically includes the following steps:
- a lower substrate is provided, and a patterned black matrix 2 is formed on the lower substrate.
- a black matrix material is deposited on the lower substrate, and the black matrix material may be made of a metal material or a resin material having better light shielding properties or other materials having better light shielding properties; and then arranged in an array by patterning the black matrix material.
- Black matrix 2 If the black matrix material is made of a metal material, the black matrix pattern can be formed by a glue coating, exposure, development, etching, and lift-off process; if the black matrix material is made of a resin material, black is formed by exposure, development, and baking treatment. Matrix graphics.
- a color resin pattern is deposited on the substrate shown in Fig. 3, and a color resin is distributed between the black matrixes 2.
- a color resin material is deposited on the base substrate after forming the black matrix pattern, a color resin pattern is formed by exposure, development, and baking treatment, and a color resin pattern is distributed between the black matrixes 2.
- the color resin may include a red resin 3, a green resin 4, and a blue tree, or may further include a resin of another color such as a white resin or a yellow resin.
- resin patterns of various colors can be arranged in any order.
- the color resin including the red resin 3, the green resin 4, and the blue resin 5 will be described as an example.
- a transparent layer 6 is deposited on the substrate shown in Figure 4. Specifically, a transparent layer 6 is deposited on a base substrate on which a colored resin pattern is formed to form a flat surface, and grooves are formed in the transparent layer 6 by exposure, development, and baking treatment. The depth and width of the grooves can be equal to the thickness and width of the gate, respectively. The depth and width of the formed groove can be controlled by adjusting the exposure amount. Transparent layer Then, an array was prepared on a color film.
- a gate metal layer is deposited on the substrate of the transparent layer pattern by magnetron sputtering, and the gate metal layer may be made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or For metals such as copper, a combination of films of the above materials may also be used.
- a pattern including a gate electrode 8 and a gate line (not shown) is formed by a normal mask process in which the gate electrode 8 is located in the recess of the transparent layer 6, and forms a planarized surface together with the transparent layer 6.
- a gate insulating layer 9, a semiconductor layer 10, a doped semiconductor layer 11, and a source/drain electrode layer are sequentially deposited on a substrate on which a gate pattern is completed.
- the material of the gate insulating layer 9 may be silicon nitride, silicon oxide or silicon oxynitride.
- the source and drain electrode layers may be made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper. A combination of the above several materials is used.
- a pattern including an active layer, a source 12, a drain 13, a data line (not shown), and a TFT channel (not shown) may be formed by a gray scale mask process.
- the steps of forming the active layer, the source 12, the drain 13 and the TFT channel region by the gray scale mask process may be specifically as follows:
- the source/drain metal layer is deposited by magnetron sputtering, and after the photoresist is applied, the photoresist is exposed by a gray scale mask.
- the photoresist is formed into a completely removed region, a partially removed region, and a completely reserved region, wherein the photoresist completely reserved region corresponds to a region where the data line, the source 12 and the drain 13 are located, and the photoresist portion reserved region corresponds to the TFT
- the region where the channel region is located, the photoresist completely removed region corresponds to the region other than the above-mentioned pattern;
- the thickness of the photoresist in the completely remaining area of the photoresist is not changed, the photoresist in the remaining portion of the photoresist is thinned, and the photoresist in the completely removed region of the photoresist is completely removed;
- etching away the source/drain metal layer in the completely removed region of the photoresist by a wet etching process and etching the doped semiconductor layer 11 and the semiconductor layer 10 in the completely removed region of the photoresist by a dry etching process to perform the photoresist
- the ashing process completely removes the photoresist in the remaining portion of the photoresist, exposes the source and drain metal layers, and performs a second etching by an etching process to completely etch away the source and drain metal layers of the remaining portion of the photoresist.
- a substrate base in which an active layer, a source 12, a drain 13 and a TFT channel region are formed The passivation layer 14 is deposited on the upper surface by a plasma enhanced chemical vapor deposition method, and via holes are formed in the passivation layer by a common mask process, wherein the material of the passivation layer 14 can be oxidized by silicon nitride, silicon oxide or nitrogen. silicon.
- a transparent conductive layer is deposited on the base substrate on which the passivation layer 14 is formed.
- the transparent conductive layer may be made of indium tin oxide (ITO), indium oxide (IZO) or aluminum oxide (AZO). And other materials; the transparent conductive layer is patterned by a common mask process to form the pixel electrode 15, and the pixel electrode 15 may be directly connected to the drain 13 through a via hole in the passivation layer.
- the specific preparation process of the upper substrate may include providing an upper substrate, depositing a transparent conductive layer on the upper substrate, and patterning the transparent conductive layer to form the common electrode 17.
- the liquid crystal display device can be formed by relatively arranging the upper substrate and the lower substrate fabricated as described above, and injecting liquid crystal between the upper substrate and the lower substrate.
- Fig. 10 is a view showing the configuration of a liquid crystal display device according to a second embodiment, in which a partial enlarged view of the TFT 7 can be referred to Fig. 9.
- the structure of the liquid crystal display device according to the present embodiment is similar to that of the liquid crystal display device of the first embodiment, and the difference is that the array substrate in the first embodiment is set to the TN mode, and the array substrate in this embodiment. Set to ADS mode.
- the common electrode 17 and the pixel electrode 15 may be disposed on the lower substrate 1, the pixel electrode 15 may be located above the common electrode 17, the pixel electrode 15 may be in the shape of a slit, and the common electrode 17 may be connected to the gate.
- the common electrode 17 is located in another recess formed in the transparent layer 6 and at the same level as the gate 8, in which case the common electrode 17 may be slit-like or planar.
- the common electrode 17 and the pixel electrode 15 may still be disposed on the lower substrate 1, but the common electrode 17 is disposed above the pixel electrode 15, at which time the common electrode 17 is disposed in a slit shape, and the common electrode 17 and the pixel electrode 15 are respectively Located above and below the passivation layer 14, the pixel electrode 15 may be slit or planar.
- the structure and formation method of the color film and other components of the array on the lower substrate 1 in this embodiment are the same as those of the first embodiment, and are not described herein again.
- the embodiment of the present invention can reduce the liquid crystal display device by disposing the array on the color film and forming a groove in the transparent layer of the color film to set the gate in the groove.
- the overall thickness is made thinner and lighter; on the other hand, the flatness of the liquid crystal display device can be increased, so that some display defects of the liquid crystal display can be reduced.
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
Abstract
An array substrate and a display device. The array substrate (1) comprises a colour film and an array which are formed on an underlay substrate, and the array is located on the colour film. By arranging the array on the colour film, forming a groove on the surface of a transparent layer (6) of the colour film, and arranging a gate electrode (8) and/or a gate line of the array in the groove, on the one hand, the overall thickness of a liquid crystal display device can be reduced to enable the liquid crystal display device to be thinner and lighter; and on the other hand, the flatness of the liquid crystal display device can be increased, thereby being able to reduce the poor display phenomena of the liquid crystal display device.
Description
阵列基板及显示装置 技术领域 Array substrate and display device
本发明实施例涉及一种阵列基板及显示装置。 背景技术 Embodiments of the present invention relate to an array substrate and a display device. Background technique
薄膜晶体管液晶显示器(TFT-LCD ) 由于具有体积小、 功耗低、 无辐射 等特点, 在平板显示领域占据了主导地位, 被广泛地应用到各个领域中。 Thin film transistor liquid crystal displays (TFT-LCDs) are dominant in flat panel display due to their small size, low power consumption, and no radiation. They are widely used in various fields.
现有技术中的液晶显示装置通常包括阵列基板、 彩膜基板以及填充在这 两个基板之间的液晶。 阵列基板可以包括栅线、 数据线、 薄膜晶体管以及像 素电极。 彩膜基板可以包括黑矩阵、 彩色树脂层以及透明导电层。 通过像素 电极和透明导电层向液晶分子施加电场, 从而实现液晶分子的偏转。 A liquid crystal display device of the prior art generally includes an array substrate, a color filter substrate, and a liquid crystal filled between the two substrates. The array substrate may include gate lines, data lines, thin film transistors, and pixel electrodes. The color filter substrate may include a black matrix, a colored resin layer, and a transparent conductive layer. The electric field is applied to the liquid crystal molecules through the pixel electrode and the transparent conductive layer, thereby achieving deflection of the liquid crystal molecules.
现有技术通过在一张玻璃上形成阵列基板并在另一张玻璃上形成彩膜基 板, 最后将这两个基板对盒并将液晶注入在其间来制备液晶显示装置。 一方 面, 阵列基板和彩膜基板在制造过程中, 表面均不平整, 均存在段差区域, 使得在对盒后出现不良现象较多; 另一方面,通过工艺改进来减少段差区域, 在一定程度上会增加基板的厚度, 阻碍了液晶显示器向薄型化方向的发展。 发明内容 The prior art prepares a liquid crystal display device by forming an array substrate on one sheet of glass and forming a color film substrate on another sheet of glass, and finally placing the two substrates on the cassette and injecting a liquid crystal therebetween. On the one hand, in the manufacturing process, the array substrate and the color film substrate are not flat, and there are step regions, so that there are many bad phenomena after the box is on the other hand; on the other hand, the process is improved to reduce the step region, to a certain extent. The thickness of the substrate is increased, which hinders the development of the liquid crystal display in the direction of thinning. Summary of the invention
根据本发明实施例的显示装置可以消除由阵列基板和彩膜基板的表面不 平整所带来的段差区域并且不增加液晶显示装置的厚度。 The display device according to the embodiment of the present invention can eliminate the step region caused by the surface unevenness of the array substrate and the color filter substrate and does not increase the thickness of the liquid crystal display device.
本发明实施例提供一种阵列基板, 该阵列基板包括形成在衬底基板上的 彩膜和阵列, 阵列位于彩膜的上方。 Embodiments of the present invention provide an array substrate including a color film and an array formed on a substrate, the array being located above the color film.
在实施例中, 彩膜可以包括形成在衬底基板上的彩色树脂层、 以及形成 在彩色树脂层上方的透明层, 阵列可以包括栅线、 薄膜晶体管和像素电极, 凹槽可以设置在透明层的表面处, 薄膜晶体管的栅极可以位于凹槽内。 In an embodiment, the color film may include a color resin layer formed on the base substrate, and a transparent layer formed over the color resin layer, the array may include a gate line, a thin film transistor, and a pixel electrode, and the groove may be disposed in the transparent layer At the surface, the gate of the thin film transistor can be located in the recess.
在实施例中, 彩膜还可以包括位于彩色树脂层之间的黑矩阵, 凹槽可以 位于黑矩阵的上方且与其相对设置。 In an embodiment, the color film may further include a black matrix between the colored resin layers, and the grooves may be located above and opposite to the black matrix.
在实施例中, 凹槽的深度、 宽度和长度可以分别与栅极的厚度、 宽度和
长度对应相等。 In an embodiment, the depth, width and length of the groove can be respectively related to the thickness, width and width of the gate The lengths are equal.
在实施例中, 凹槽的形状可以与栅线和栅极的整体形状相同, 凹槽的深 度可以与栅线和栅极的厚度相等。 In an embodiment, the shape of the groove may be the same as the overall shape of the gate line and the gate, and the depth of the groove may be equal to the thickness of the gate line and the gate.
在实施例中, 阵列还可以包括公共电极, 公共电极可以位于像素电极的 下方。 In an embodiment, the array may further comprise a common electrode, and the common electrode may be located below the pixel electrode.
在实施例中, 公共电极可以位于透明层中形成的另一凹槽内且处于与栅 极相同的水平面。 In an embodiment, the common electrode may be located in another recess formed in the transparent layer and in the same horizontal plane as the gate.
在实施例中, 阵列还可以包括公共电极, 公共电极可以位于像素电极的 上方。 In an embodiment, the array may further comprise a common electrode, and the common electrode may be located above the pixel electrode.
在实施例中, 至少公共电极和像素电极中位于上方的电极为狭缝电极。 在实施例中, 彩色树脂层可以包括红色树脂、 绿色树脂和蓝色树脂。 在实施例中, 透明层可以釆用亚克力材料。 In an embodiment, at least the electrode located above the common electrode and the pixel electrode is a slit electrode. In an embodiment, the colored resin layer may include a red resin, a green resin, and a blue resin. In an embodiment, the transparent layer may utilize an acrylic material.
本发明还提供了一种显示装置, 包括如上所述的阵列基板。 The present invention also provides a display device comprising the array substrate as described above.
在上述技术方案所提供的阵列基板中, 通过将阵列设置在彩膜上、 并在 彩膜的透明层中开设凹槽以将阵列的栅极和 /或栅线设置在凹槽内,不仅可以 减小液晶显示装置的总体厚度, 使其更薄、 更轻; 还可以增加液晶显示装置 的平坦性, 从而能够减小液晶显示装置的一些显示不良现象。 附图说明 In the array substrate provided by the above technical solution, by arranging the array on the color film and forming a groove in the transparent layer of the color film to set the gate and/or the gate line of the array in the groove, not only the array substrate but also the gate line can be disposed in the groove. The overall thickness of the liquid crystal display device is reduced to make it thinner and lighter; the flatness of the liquid crystal display device can also be increased, so that some display defects of the liquid crystal display device can be reduced. DRAWINGS
为了更清楚地说明本发明实施例的技术方案, 下面将对实施例的附图作 简单地介绍,显而易见地,下面描述中的附图仅仅涉及本发明的一些实施例, 而非对本发明的限制。 In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .
图 1是根据本发明第一实施例的液晶显示装置的结构示意图; 1 is a schematic structural view of a liquid crystal display device according to a first embodiment of the present invention;
图 2是根据本发明第一实施例的下基板的结构示意图; 2 is a schematic structural view of a lower substrate according to a first embodiment of the present invention;
图 3是根据本发明第一实施例的下基板在形成黑矩阵图形后的示意图; 图 4 是根据本发明第一实施例的下基板在形成彩色树脂图形后的示意 图; 3 is a schematic view of a lower substrate after forming a black matrix pattern according to a first embodiment of the present invention; FIG. 4 is a schematic view of the lower substrate after forming a colored resin pattern according to the first embodiment of the present invention;
图 5是根据本发明第一实施例的下基板在形成透明层后的示意图; 图 6是根据本发明第一实施例的下基板在形成栅极图形后的示意图; 图 7是根据本发明第一实施例的下基板在形成有源层、源极、漏极和 TFT
沟道区域的示意图; 5 is a schematic view of a lower substrate after forming a transparent layer according to a first embodiment of the present invention; FIG. 6 is a schematic view of a lower substrate after forming a gate pattern according to a first embodiment of the present invention; The lower substrate of an embodiment is formed with an active layer, a source, a drain, and a TFT. a schematic view of a channel region;
图 8是根据本发明第一实施例的下基板在形成钝化层图形后的示意图; 图 9 是根据本发明第一实施例的下基板在形成像素电极图形后的示意 图; 以及 8 is a schematic view of a lower substrate after forming a passivation layer pattern according to a first embodiment of the present invention; FIG. 9 is a schematic view of a lower substrate after forming a pixel electrode pattern according to a first embodiment of the present invention;
图 10是才艮据本发明第二实施例的液晶显示装置的结构示意图。 具体实施方式 Fig. 10 is a view showing the configuration of a liquid crystal display device according to a second embodiment of the present invention. detailed description
为使本发明实施例的目的、 技术方案和优点更加清楚, 下面将结合本发 明实施例的附图,对本发明实施例的技术方案进行清楚、 完整地描述。显然, 所描述的实施例是本发明的一部分实施例, 而不是全部的实施例。 基于所描 述的本发明的实施例, 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例, 都属于本发明保护的范围。 The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.
第一实施例 First embodiment
图 1示出才艮据第一实施例的液晶显示装置的结构示意图, 图 2为图 1中 的下基板的结构示意图。 本实施例的液晶显示装置可以包括上基板 16、 下基 板 1和填充在这两个基板之间的液晶 18。 下基板 1可以包括下衬底基板 (图 中未示出)、 形成在下衬底基板上的彩膜和位于彩膜上方的阵列。 上基板 16 可以包括上衬底基板(图中未示出)和形成在上衬底基板的下表面上的公共 电极 17。 1 is a schematic structural view of a liquid crystal display device according to a first embodiment, and FIG. 2 is a schematic structural view of a lower substrate of FIG. 1. The liquid crystal display device of this embodiment may include an upper substrate 16, a lower substrate 1, and a liquid crystal 18 filled between the two substrates. The lower substrate 1 may include a lower substrate (not shown), a color film formed on the lower substrate, and an array above the color film. The upper substrate 16 may include an upper substrate (not shown) and a common electrode 17 formed on the lower surface of the upper substrate.
参照图 1和图 2,彩膜可以包括形成在下衬底基板的上表面上的黑矩阵 2 和彩色树脂层、 以及形成在黑矩阵 2和彩色树脂层上的透明层 6, 透明层 6 可以釆用亚克力材料制作。 如图 2所示, 阵列可以包括形成在透明层 6之上 的栅线(图中未示出)、 数据线(图中未示出)、 薄膜晶体管 ( TFT ) 7和像 素电极 15。阵列的 TFT 7的放大图如图 9所示,其中 TFT 7可以包括栅极 8、 栅极绝缘层 9、 半导体层 10、 掺杂半导体层 11、 源极 12、 漏极 13和钝化层 14。将彩膜和阵列一体设置(即彩膜和阵列设置在同一个衬底基板上), 能够 减小液晶显示装置的整体厚度, 使液晶显示器朝着更薄更轻化发展。 Referring to FIGS. 1 and 2, the color film may include a black matrix 2 and a color resin layer formed on the upper surface of the lower substrate, and a transparent layer 6 formed on the black matrix 2 and the color resin layer, and the transparent layer 6 may be Made of acrylic material. As shown in FIG. 2, the array may include a gate line (not shown) formed over the transparent layer 6, a data line (not shown), a thin film transistor (TFT) 7 and a pixel electrode 15. An enlarged view of the TFT 7 of the array is shown in FIG. 9, wherein the TFT 7 may include a gate 8, a gate insulating layer 9, a semiconductor layer 10, a doped semiconductor layer 11, a source 12, a drain 13, and a passivation layer 14. . By integrally arranging the color film and the array (i.e., the color film and the array are disposed on the same substrate), the overall thickness of the liquid crystal display device can be reduced, and the liquid crystal display can be made thinner and lighter.
为了避免阵列和彩膜在制造过程中因表面不平整存在段差区域从而引起 不良现象较多的问题, 本实施例中, 在透明层 6的表面处设置凹槽, 使栅极 8位于凹槽内, 并且凹槽的深度和宽度可以分别与栅极 8的厚度和宽度对应
相等, 使得下基板的表面平坦。 需要说明的是, 本实施例所述的透明层 6上 也可以不设置凹槽, 栅极 8直接形成于透明层 6上方, 本领域技术人员可以 根据实际需要自由选择设置。 彩色树脂层可以包括红色树脂 3、 绿色树脂 4 和蓝色树脂 5 ,黑矩阵 2位于红色树脂 3、绿色树脂 4和蓝色树脂 5中相邻的 两个树脂之间。 凹槽可以设置在黑矩阵 2上方且与其相对设置。 当然, 根据 设计需要, 彩色树脂层还可以包括其它颜色的树脂, 本发明实施例不限于上 述颜色。 In order to avoid the problem that the array and the color film have a stepped area due to unevenness of the surface during the manufacturing process, in the embodiment, a groove is provided at the surface of the transparent layer 6, so that the gate 8 is located in the groove. And the depth and width of the groove may correspond to the thickness and width of the gate 8, respectively Equal, making the surface of the lower substrate flat. It should be noted that the transparent layer 6 described in this embodiment may not be provided with a groove, and the gate electrode 8 is directly formed on the transparent layer 6. The person skilled in the art can freely select and set according to actual needs. The color resin layer may include a red resin 3, a green resin 4, and a blue resin 5, and the black matrix 2 is located between two adjacent resins of the red resin 3, the green resin 4, and the blue resin 5. The groove may be disposed above and opposite the black matrix 2. Of course, the color resin layer may further include other color resins depending on design requirements, and embodiments of the present invention are not limited to the above colors.
此外, 栅线也可以位于凹槽内, 凹槽的形状可以与栅线和栅极的整体形 状相同, 并且凹槽的深度可以与栅线和 /或栅极的厚度相等。 In addition, the gate line may also be located in the recess, the shape of the recess may be the same as the overall shape of the gate line and the gate, and the depth of the recess may be equal to the thickness of the gate line and/or the gate.
本实施例还提供了制造上述液晶显示装置的阵列基板的方法, 具体包括 以下步骤: The embodiment further provides a method for manufacturing the array substrate of the above liquid crystal display device, which specifically includes the following steps:
首先, 制备彩膜。 First, a color film is prepared.
参照图 3 , 提供下衬底基板, 并在下衬底基板上形成图案化的黑矩阵 2。 具体地, 在下衬底基板上沉积黑矩阵材料, 黑矩阵材料可以釆用遮光性较好 的金属材料或树脂材料或者其它遮光性较好的材料; 然后通过图案化黑矩阵 材料形成以阵列方式布置的黑矩阵 2。 如果黑矩阵材料釆用金属材料, 则可 以通过涂胶、 曝光、 显影、 刻蚀和剥离工艺形成黑矩阵图形; 如果黑矩阵材 料釆用树脂材料, 则通过曝光、 显影和烘烤处理来形成黑矩阵图形。 Referring to Fig. 3, a lower substrate is provided, and a patterned black matrix 2 is formed on the lower substrate. Specifically, a black matrix material is deposited on the lower substrate, and the black matrix material may be made of a metal material or a resin material having better light shielding properties or other materials having better light shielding properties; and then arranged in an array by patterning the black matrix material. Black matrix 2. If the black matrix material is made of a metal material, the black matrix pattern can be formed by a glue coating, exposure, development, etching, and lift-off process; if the black matrix material is made of a resin material, black is formed by exposure, development, and baking treatment. Matrix graphics.
参照图 4 , 在图 3所示的基板上沉积彩色树脂图形, 并且彩色树脂分布 于黑矩阵 2之间。 具体地, 在形成黑矩阵图形之后的衬底基板上沉积彩色树 脂材料, 通过曝光、 显影、 烘烤处理形成彩色树脂图形, 并且彩色树脂图形 分布于黑矩阵 2之间。 彩色树脂可以包括红色树脂 3、 绿色树脂 4和蓝色树 月旨 5 , 或者还可以包括白色树脂、 黄色树脂等其它颜色的树脂。 在实际应用 中, 各种颜色的树脂图形可以釆用任意顺序排列。 在本实施例中以彩色树脂 包括红色树脂 3、 绿色树脂 4和蓝色树脂 5为例进行说明。 Referring to Fig. 4, a color resin pattern is deposited on the substrate shown in Fig. 3, and a color resin is distributed between the black matrixes 2. Specifically, a color resin material is deposited on the base substrate after forming the black matrix pattern, a color resin pattern is formed by exposure, development, and baking treatment, and a color resin pattern is distributed between the black matrixes 2. The color resin may include a red resin 3, a green resin 4, and a blue tree, or may further include a resin of another color such as a white resin or a yellow resin. In practical applications, resin patterns of various colors can be arranged in any order. In the present embodiment, the color resin including the red resin 3, the green resin 4, and the blue resin 5 will be described as an example.
参照图 5 , 在图 4所示的基板上沉积透明层 6。 具体地, 在形成彩色树脂 图形的衬底基板上沉积透明层 6以形成平整表面, 并通过曝光、 显影、 烘烤 处理在透明层 6中形成凹槽。 凹槽的深度和宽度可以分别与栅极的厚度和宽 度相等。 可以通过调节曝光量来控制所形成的凹槽的深度和宽度。 透明层的
然后, 在彩膜上制备阵列。 Referring to Figure 5, a transparent layer 6 is deposited on the substrate shown in Figure 4. Specifically, a transparent layer 6 is deposited on a base substrate on which a colored resin pattern is formed to form a flat surface, and grooves are formed in the transparent layer 6 by exposure, development, and baking treatment. The depth and width of the grooves can be equal to the thickness and width of the gate, respectively. The depth and width of the formed groove can be controlled by adjusting the exposure amount. Transparent layer Then, an array was prepared on a color film.
参照图 6, 在完成透明层图形的衬底基板上釆用磁控溅射的方法沉积栅 极金属层, 栅极金属层可以釆用钼、 铝、 铝镍合金、 钼钨合金、 铬、 或铜等 金属, 也可以使用上述几种材料薄膜的组合结构。 通过普通掩模工艺形成包 括栅极 8和栅线(图中未示出)的图形, 其中栅极 8位于透明层 6的凹槽内, 并与透明层 6—起形成平坦化表面。 Referring to FIG. 6, a gate metal layer is deposited on the substrate of the transparent layer pattern by magnetron sputtering, and the gate metal layer may be made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or For metals such as copper, a combination of films of the above materials may also be used. A pattern including a gate electrode 8 and a gate line (not shown) is formed by a normal mask process in which the gate electrode 8 is located in the recess of the transparent layer 6, and forms a planarized surface together with the transparent layer 6.
参照图 7 ,在完成栅极图形的衬底基板上依次沉积栅极绝缘层 9、半导体 层 10、 掺杂半导体层 11和源漏电极层。 栅极绝缘层 9的材料可以釆用氮化 硅、 氧化硅或氮氧化硅等, 源漏电极层可以釆用钼、 铝、 铝镍合金、 钼钨合 金、 铬、 或铜等金属, 也可以使用上述几种材料薄膜的组合结构。 可以通过 灰度掩模工艺形成包括有源层、 源极 12、 漏极 13、 数据线(图中未示出)和 TFT沟道(图中未示出 ) 的图形。 Referring to Fig. 7, a gate insulating layer 9, a semiconductor layer 10, a doped semiconductor layer 11, and a source/drain electrode layer are sequentially deposited on a substrate on which a gate pattern is completed. The material of the gate insulating layer 9 may be silicon nitride, silicon oxide or silicon oxynitride. The source and drain electrode layers may be made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper. A combination of the above several materials is used. A pattern including an active layer, a source 12, a drain 13, a data line (not shown), and a TFT channel (not shown) may be formed by a gray scale mask process.
釆用灰度掩模工艺形成有源层、 源极 12、 漏极 13和 TFT沟道区域的步 骤可以具体为: The steps of forming the active layer, the source 12, the drain 13 and the TFT channel region by the gray scale mask process may be specifically as follows:
在完成栅极图形的衬底基板上, 釆用等离子体增强化学气相沉积 Plasma enhanced chemical vapor deposition on a substrate that completes the gate pattern
( PECVD )方法依次沉积栅极绝缘层 9、 半导体层 10和掺杂半导体层 11之 后, 再釆用磁控溅射方法沉积源漏金属层, 涂光刻胶后, 釆用灰度掩模版曝 光, 使光刻胶形成完全去除区域、 部分去除区域和完全保留区域, 其中光刻 胶完全保留区域对应于数据线、 源极 12和漏极 13所在的区域, 光刻胶部分 保留区域对应于 TFT的沟道区域所在的区域,光刻胶完全去除区域对应于上 述图形以外的区域; After the gate insulating layer 9, the semiconductor layer 10, and the doped semiconductor layer 11 are sequentially deposited by a (PECVD) method, the source/drain metal layer is deposited by magnetron sputtering, and after the photoresist is applied, the photoresist is exposed by a gray scale mask. The photoresist is formed into a completely removed region, a partially removed region, and a completely reserved region, wherein the photoresist completely reserved region corresponds to a region where the data line, the source 12 and the drain 13 are located, and the photoresist portion reserved region corresponds to the TFT The region where the channel region is located, the photoresist completely removed region corresponds to the region other than the above-mentioned pattern;
经过显影处理, 光刻胶完全保留区域的光刻胶厚度没有变化, 光刻胶部 分保留区域的光刻胶变薄, 光刻胶完全去除区域的光刻胶被完全去除; After the development process, the thickness of the photoresist in the completely remaining area of the photoresist is not changed, the photoresist in the remaining portion of the photoresist is thinned, and the photoresist in the completely removed region of the photoresist is completely removed;
釆用湿刻工艺刻蚀掉光刻胶完全去除区域的源漏金属层, 釆用干刻工艺 刻蚀掉光刻胶完全去除区域的掺杂半导体层 11和半导体层 10, 对光刻胶进 行灰化处理, 完全去除光刻胶部分保留区域的光刻胶, 露出源漏金属层, 釆 用刻蚀工艺进行第二次刻蚀, 完全刻蚀掉光刻胶部分保留区域的源漏金属层 和掺杂半导体层, 并刻蚀掉部分半导体层 10, 形成 TFT的沟道区域; 刻蚀 etching away the source/drain metal layer in the completely removed region of the photoresist by a wet etching process, and etching the doped semiconductor layer 11 and the semiconductor layer 10 in the completely removed region of the photoresist by a dry etching process to perform the photoresist The ashing process completely removes the photoresist in the remaining portion of the photoresist, exposes the source and drain metal layers, and performs a second etching by an etching process to completely etch away the source and drain metal layers of the remaining portion of the photoresist. And doping the semiconductor layer, and etching away part of the semiconductor layer 10 to form a channel region of the TFT;
最后, 剥离剩余光刻胶, 完成 TFT的制作。 Finally, the remaining photoresist is stripped to complete the fabrication of the TFT.
参照图 8, 在形成有源层、 源极 12、 漏极 13和 TFT沟道区域的衬底基
板上釆用等离子体增强化学气相沉积方法沉积钝化层 14,通过普通掩模工艺 在钝化层中形成过孔,其中钝化层 14的材料可以釆用氮化硅、氧化硅或氮氧 化硅。 Referring to FIG. 8, a substrate base in which an active layer, a source 12, a drain 13 and a TFT channel region are formed The passivation layer 14 is deposited on the upper surface by a plasma enhanced chemical vapor deposition method, and via holes are formed in the passivation layer by a common mask process, wherein the material of the passivation layer 14 can be oxidized by silicon nitride, silicon oxide or nitrogen. silicon.
参照图 9, 在形成钝化层 14的衬底基板上沉积透明导电层, 透明导电层 的材料可以釆用铟锡氧化物( ITO )、铟辞氧化物( IZO )或铝辞氧化物( AZO ) 等材料; 通过普通掩模工艺图案化透明导电层以形成像素电极 15, 像素电极 15可以通过钝化层中的过孔与漏极 13直接相连。 Referring to FIG. 9, a transparent conductive layer is deposited on the base substrate on which the passivation layer 14 is formed. The transparent conductive layer may be made of indium tin oxide (ITO), indium oxide (IZO) or aluminum oxide (AZO). And other materials; the transparent conductive layer is patterned by a common mask process to form the pixel electrode 15, and the pixel electrode 15 may be directly connected to the drain 13 through a via hole in the passivation layer.
上基板的具体制备过程可以包括提供上衬底基板、 在上衬底基板上沉积 透明导电层、 以及图案化该透明导电层以形成公共电极 17。 The specific preparation process of the upper substrate may include providing an upper substrate, depositing a transparent conductive layer on the upper substrate, and patterning the transparent conductive layer to form the common electrode 17.
最后,液晶显示装置可以通过相对设置如上所述制造的上基板和下基板、 以及在上基板和下基板之间注入液晶而形成。 Finally, the liquid crystal display device can be formed by relatively arranging the upper substrate and the lower substrate fabricated as described above, and injecting liquid crystal between the upper substrate and the lower substrate.
第二实施例 Second embodiment
图 10是才艮据第二实施例的液晶显示装置的结构示意图,其中 TFT 7的局 部放大图可以参见图 9。 根据本实施例的液晶显示装置的结构与第一实施例 的液晶显示装置的结构相似, 其区别之处在于: 第一实施例中的阵列基板设 置为 TN模式, 而本实施例中的阵列基板设置为 ADS模式。 具体地, 在本实 施例中, 公共电极 17和像素电极 15可以均设置在下基板 1上, 像素电极 15 可以位于公共电极 17上方,像素电极 15可以为狭缝状,公共电极 17可以与 栅极 8在同一层形成,也就是说,公共电极 17位于透明层 6中形成的另一凹 槽内且处于与栅极 8相同的水平面,此时公共电极 17可以为狭缝状或平面状。 替代地, 公共电极 17和像素电极 15可以仍然都设置在下基板 1上, 但是将 公共电极 17设置在像素电极 15上方,此时公共电极 17设置为狭缝状,公共 电极 17和像素电极 15分别位于钝化层 14的上方和下方, 此时像素电极 15 可以为狭缝状或平面状。 本实施例中下基板 1上的彩膜和阵列的其它部件的 结构和形成方法与第一实施例的相同, 这里不再赘述。 Fig. 10 is a view showing the configuration of a liquid crystal display device according to a second embodiment, in which a partial enlarged view of the TFT 7 can be referred to Fig. 9. The structure of the liquid crystal display device according to the present embodiment is similar to that of the liquid crystal display device of the first embodiment, and the difference is that the array substrate in the first embodiment is set to the TN mode, and the array substrate in this embodiment. Set to ADS mode. Specifically, in this embodiment, the common electrode 17 and the pixel electrode 15 may be disposed on the lower substrate 1, the pixel electrode 15 may be located above the common electrode 17, the pixel electrode 15 may be in the shape of a slit, and the common electrode 17 may be connected to the gate. 8 is formed in the same layer, that is, the common electrode 17 is located in another recess formed in the transparent layer 6 and at the same level as the gate 8, in which case the common electrode 17 may be slit-like or planar. Alternatively, the common electrode 17 and the pixel electrode 15 may still be disposed on the lower substrate 1, but the common electrode 17 is disposed above the pixel electrode 15, at which time the common electrode 17 is disposed in a slit shape, and the common electrode 17 and the pixel electrode 15 are respectively Located above and below the passivation layer 14, the pixel electrode 15 may be slit or planar. The structure and formation method of the color film and other components of the array on the lower substrate 1 in this embodiment are the same as those of the first embodiment, and are not described herein again.
由以上实施例可以看出, 本发明实施例通过将阵列设置在彩膜上, 并在 彩膜的透明层中形成凹槽, 将栅极设置在凹槽内, 一方面可以减小液晶显示 装置的总体厚度, 使其更薄、 更轻; 另一方面可以增加液晶显示装置的平坦 性, 从而能够减小液晶显示的一些显示不良现象。 It can be seen from the above embodiment that the embodiment of the present invention can reduce the liquid crystal display device by disposing the array on the color film and forming a groove in the transparent layer of the color film to set the gate in the groove. The overall thickness is made thinner and lighter; on the other hand, the flatness of the liquid crystal display device can be increased, so that some display defects of the liquid crystal display can be reduced.
以上所述仅是本发明的示范性实施方式, 而非用于限制本发明的保护范 围, 本发明的保护范围由所附的权利要求确定。
The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.
Claims
权利要求书 claims
I、 一种阵列基板, 所述阵列基板包括形成在衬底基板上的彩膜和阵列, 所述阵列位于所述彩膜的上方。 I. An array substrate, the array substrate includes a color filter and an array formed on the base substrate, the array is located above the color filter.
2、如权利要求 1所述的阵列基板,其中所述彩膜包括形成在所述衬底基 板上的彩色树脂层以及形成在所述彩色树脂层上的透明层; 所述阵列包括栅 线、 薄膜晶体管和像素电极; 凹槽设置在所述透明层的表面处, 所述薄膜晶 体管的栅极位于所述凹槽内。 2. The array substrate of claim 1, wherein the color filter includes a color resin layer formed on the base substrate and a transparent layer formed on the color resin layer; the array includes gate lines, Thin film transistor and pixel electrode; a groove is provided on the surface of the transparent layer, and the gate electrode of the thin film transistor is located in the groove.
3、如权利要求 2所述的阵列基板,其中所述彩膜还包括位于所述彩色树 脂层之间的黑矩阵, 所述凹槽位于所述黑矩阵的上方且与其相对设置。 3. The array substrate of claim 2, wherein the color filter further includes a black matrix located between the color resin layers, and the groove is located above and opposite to the black matrix.
4、 如权利要求 2-3中任一项所述的阵列基板, 其中所述凹槽的深度、 宽 度和长度分别与所述栅极的厚度、 宽度和长度对应相等。 4. The array substrate according to any one of claims 2-3, wherein the depth, width and length of the groove are respectively equal to the thickness, width and length of the gate electrode.
5、如权利要求 2-4中任一项所述的阵列基板, 其中所述 IHJ槽的形状与所 述栅线和所述栅极的整体形状相同, 并且所述凹槽的深度与所述栅线和所述 栅极的厚度相等。 5. The array substrate according to any one of claims 2 to 4, wherein the shape of the IHJ groove is the same as the overall shape of the gate line and the gate electrode, and the depth of the groove is the same as the overall shape of the gate line and the gate electrode. The thickness of the gate line and the gate electrode are equal.
6、如权利要求 2-5中任一项所述的阵列基板, 其中所述阵列还包括公共 电极, 所述公共电极位于所述像素电极的下方。 6. The array substrate according to any one of claims 2 to 5, wherein the array further includes a common electrode, and the common electrode is located below the pixel electrode.
7、如权利要求 6所述的阵列基板,其中所述公共电极位于所述透明层中 形成的另一凹槽内且处于与所述栅极相同的水平面。 7. The array substrate of claim 6, wherein the common electrode is located in another groove formed in the transparent layer and at the same level as the gate electrode.
8、如权利要求 2-5中任一项所述的阵列基板, 其中所述阵列还包括公共 电极, 所述公共电极位于所述像素电极的上方。 8. The array substrate according to any one of claims 2 to 5, wherein the array further includes a common electrode, the common electrode is located above the pixel electrode.
9、如权利要求 6-8中任一项所述的阵列基板, 其中至少所述公共电极和 所述像素电极中位于上方的电极为狭缝电极。 9. The array substrate according to any one of claims 6 to 8, wherein at least the upper electrode among the common electrode and the pixel electrode is a slit electrode.
10、 如权利要求 2-9中任一项所述的阵列基板, 其中所述彩色树脂层包 括红色树脂、 绿色树脂和蓝色树脂。 10. The array substrate according to any one of claims 2 to 9, wherein the colored resin layer includes red resin, green resin and blue resin.
II、 如权利要求 2-10中任一项所述的阵列基板, 其中所述透明层釆用亚 克力材料。 II. The array substrate according to any one of claims 2-10, wherein the transparent layer is made of acrylic material.
12、 一种显示装置, 包括如权利要求 1-11中任一项所述的阵列基板。
12. A display device, comprising the array substrate according to any one of claims 1-11.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210260959.X | 2012-07-25 | ||
CN201210260959XA CN102819138A (en) | 2012-07-25 | 2012-07-25 | Array base plate and display device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014015617A1 true WO2014015617A1 (en) | 2014-01-30 |
Family
ID=47303330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2012/086228 WO2014015617A1 (en) | 2012-07-25 | 2012-12-07 | Array substrate and display device |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN102819138A (en) |
WO (1) | WO2014015617A1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103489922B (en) * | 2013-09-30 | 2017-01-18 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, array substrate and preparation method thereof and display device |
CN104393002A (en) * | 2014-10-29 | 2015-03-04 | 合肥京东方光电科技有限公司 | Display substrate and manufacturing method thereof and display device |
US10175515B2 (en) * | 2016-03-17 | 2019-01-08 | Japan Display Inc. | Image display device |
CN107515488B (en) * | 2017-08-01 | 2020-06-23 | 惠科股份有限公司 | Display panel |
CN108388041B (en) * | 2018-02-08 | 2021-06-01 | Tcl华星光电技术有限公司 | Color film substrate and manufacturing method thereof, shading material and manufacturing method of shading layer |
CN108333830B (en) * | 2018-02-08 | 2021-03-26 | Tcl华星光电技术有限公司 | Color film substrate and manufacturing method thereof, and light shielding layer and manufacturing method thereof |
CN118259510B (en) * | 2024-05-30 | 2024-08-23 | Tcl华星光电技术有限公司 | Display panel and display terminal |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030020851A1 (en) * | 2001-07-30 | 2003-01-30 | Woong-Kwon Kim | Liquid crystal display panel and manufacturing method thereof |
KR20040050237A (en) * | 2002-12-09 | 2004-06-16 | 엘지.필립스 엘시디 주식회사 | Array substrate for LCD and Method for fabricating of the same |
CN101149546A (en) * | 2006-09-22 | 2008-03-26 | 北京京东方光电科技有限公司 | Liquid crystal display device with thin-film transistor on color film and its manufacture method |
CN101436601A (en) * | 2008-12-18 | 2009-05-20 | 上海广电光电子有限公司 | Array substrate of thin-film transistor |
CN202025170U (en) * | 2011-04-22 | 2011-11-02 | 京东方科技集团股份有限公司 | Display screen and display device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100325072B1 (en) * | 1998-10-28 | 2002-08-24 | 주식회사 현대 디스플레이 테크놀로지 | Manufacturing method of high opening rate and high transmittance liquid crystal display device |
KR100629174B1 (en) * | 1999-12-31 | 2006-09-28 | 엘지.필립스 엘시디 주식회사 | Thin Film Transistor Substrate And Method for Fabricating the Same |
KR20080003078A (en) * | 2006-06-30 | 2008-01-07 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display device and and method for fabricating the same |
CN102033370B (en) * | 2009-09-25 | 2014-05-28 | 北京京东方光电科技有限公司 | Liquid crystal display substrate and manufacturing method thereof |
-
2012
- 2012-07-25 CN CN201210260959XA patent/CN102819138A/en active Pending
- 2012-12-07 WO PCT/CN2012/086228 patent/WO2014015617A1/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030020851A1 (en) * | 2001-07-30 | 2003-01-30 | Woong-Kwon Kim | Liquid crystal display panel and manufacturing method thereof |
KR20040050237A (en) * | 2002-12-09 | 2004-06-16 | 엘지.필립스 엘시디 주식회사 | Array substrate for LCD and Method for fabricating of the same |
CN101149546A (en) * | 2006-09-22 | 2008-03-26 | 北京京东方光电科技有限公司 | Liquid crystal display device with thin-film transistor on color film and its manufacture method |
CN101436601A (en) * | 2008-12-18 | 2009-05-20 | 上海广电光电子有限公司 | Array substrate of thin-film transistor |
CN202025170U (en) * | 2011-04-22 | 2011-11-02 | 京东方科技集团股份有限公司 | Display screen and display device |
Also Published As
Publication number | Publication date |
---|---|
CN102819138A (en) | 2012-12-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8692258B2 (en) | Array substrate of TFT-LCD including a black matrix and method for manufacturing the same | |
US9716110B2 (en) | Array substrate, method for manufacturing the same, and display device | |
US9274368B2 (en) | COA substrate, method for fabricating the same and display device | |
KR101322885B1 (en) | Array substrate and liquid crystal display | |
WO2014015617A1 (en) | Array substrate and display device | |
WO2016123931A1 (en) | Thin film transistor and manufacturing method thereof, display substrate and display device | |
JP4594292B2 (en) | Photomask and method for manufacturing array substrate for liquid crystal display device using the same | |
WO2018120691A1 (en) | Array substrate and method for manufacturing same, and display device | |
JP2012150435A (en) | Array substrate for thin film transistor liquid crystal display and method for manufacturing the same | |
US8441592B2 (en) | TFT-LCD array substrate and manufacturing method thereof | |
US20140273362A1 (en) | Method for manufacturing thin film transistor and array substrate | |
WO2016029601A1 (en) | Array substrate and manufacturing method therefor, and display apparatus | |
JP2010114459A (en) | Liquid crystal display device using small molecule organic semiconductor material, and method of manufacturing the same | |
WO2017012306A1 (en) | Method for manufacturing array substrate, array substrate, and display device | |
CN102779783B (en) | Pixel structure, as well as manufacturing method and display device thereof | |
KR20190077570A (en) | Array substrate, method of manufacturing the same, and display device | |
US20180059456A1 (en) | Pixel structure and manufacturing method thereof, array substrate and display apparatus | |
WO2016150286A1 (en) | Array substrate and preparation method therefor, and display device | |
WO2013135073A1 (en) | Transflective liquid crystal display array substrate, manufacturing method therefor, and display device | |
WO2014131238A1 (en) | Array substrate and manufacturing method therefor, display panel and manufacturing method therefor | |
TW200905262A (en) | Color filter substrate and manufacturing thereof and liquid crystal display panel | |
JP2016533530A (en) | TFT-LCD array substrate manufacturing method, liquid crystal panel, and liquid crystal display device. | |
CN102931138B (en) | Array substrate and manufacturing method thereof and display device | |
WO2018214740A1 (en) | Display substrate, method for manufacturing same, and display device | |
US9057923B2 (en) | Wire, method of manufacture, and related apparatus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12881558 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 11.06.2015) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 12881558 Country of ref document: EP Kind code of ref document: A1 |