CN102033370B - Liquid crystal display substrate and manufacturing method thereof - Google Patents
Liquid crystal display substrate and manufacturing method thereof Download PDFInfo
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- CN102033370B CN102033370B CN200910093195.8A CN200910093195A CN102033370B CN 102033370 B CN102033370 B CN 102033370B CN 200910093195 A CN200910093195 A CN 200910093195A CN 102033370 B CN102033370 B CN 102033370B
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Abstract
The invention relates to a liquid crystal display substrate and a manufacturing method thereof. The liquid crystal display substrate comprises a substrate; patterns of various conductive structures are formed on the substrate; and the conductive structures are mutually spaced or insulated through an insulating layer, wherein trenches are formed on the insulating layer with the conductive structures, and the patterns of the conductive structures are at least partially formed in the trenches. By adopting a technical means of forming the conductive structures in the trenches of the insulating layer, the height difference of the conductive structures on the surface of the insulating layer below the conductive structures is reduced, so that the limitation for the thickness of the conductive structures is reduced.
Description
Technical field
The embodiment of the present invention relates to lcd technology, relates in particular to a kind of liquid crystal display substrate and manufacture method thereof.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor-Liquid CrystalDisplay; Hereinafter to be referred as: TFT-LCD) there is the features such as volume is little, low in energy consumption, radiationless, in current flat panel display market, occupied leading position.
TFT-LCD generally include to box arrange two liquid crystal display substrates, be generally array base palte and color membrane substrates to box, filling liquid crystal therebetween.Array base palte generally comprises a underlay substrate, is formed with data line and controlling grid scan line that transverse and longitudinal is intersected on underlay substrate, encloses the multiple pixel cells that form matrix form.In each pixel cell, be provided with a TFT switch, TFT switch comprises gate electrode, active layer, source electrode and drain electrode.Gate electrode is connected with controlling grid scan line, generally adopts identical material to form with controlling grid scan line simultaneously; Source electrode connection data line, drain electrode connects pixel electrode, and source electrode and drain electrode adopt identical material to form with data line simultaneously conventionally.Active layer is between gate electrode and source electrode and drain electrode.In the time that gate electrode passes into high level, source electrode and drain electrode, by active layer conducting, pass into pixel electrode by the voltage of data line.
In the structure of existing array base palte, between the pattern of the conductive structures such as controlling grid scan line, gate electrode, data line, source electrode and drain electrode, there is overlapping region mutually, between these overlapping regions, easily form overlap capacitance C, make to form actuation time of TFT switch certain delay.Time delay is also relevant with the resistance R of each conductive structure.Product between resistance R and capacitor C more postpones more obvious.
The cross-sectional area that increases conductive structure is to fall low-resistance a kind of approach.But the width that increases the patterns such as data line, controlling grid scan line can reduce the area that pixel cell can transmission region, has reduced aperture opening ratio.If increase the thickness of the patterns such as data line, controlling grid scan line, make on array base palte conductive structure pattern excessive in the difference in height of the insulation course plane of its lower floor, when forming subsequently another layer of conductive structure pattern, just easily there is the phenomenon of broken string and cause bad, or in the time carrying out friction orientation (Rubbing), easily there is fracture, problem of non-uniform, so prior art has larger restriction to the thickness of conductive structure pattern conventionally.
Summary of the invention
The object of this invention is to provide a kind of liquid crystal display substrate and manufacture method thereof, to reduce the restriction to conductive structure pattern thickness.
For achieving the above object, the invention provides a kind of liquid crystal display substrate, comprise underlay substrate, on described underlay substrate, form the pattern of multiple conductive structure, each described conductive structure space or by insulation course keep insulation, wherein:
Be formed with on the insulation course of conductive structure and be formed with groove, the pattern of described conductive structure is formed in described groove at least partly.
For achieving the above object, the invention provides a kind of manufacture method of liquid crystal display substrate, be included in the step that forms space on underlay substrate or keep the pattern of the conductive structure of insulation by insulation course, wherein, form conductive structure on insulation course before, also comprise:
On described insulation course, form groove, the pattern of described conductive structure is formed in described groove at least partly.
From above technical scheme, the present invention adopts conductive structure is formed on to the technological means in the groove of insulation course, has reduced the difference in height of conductive structure at its lower surface of insulating layer, thereby has reduced the restriction to conductive structure thickness.The thickness that suitably increases different conductive structures can bring many-sided beneficial effect.
Accompanying drawing explanation
The fragmentary top TV structure schematic diagram of the liquid crystal display substrate that Fig. 1 provides for the embodiment of the present invention one;
Fig. 2 is that A-A in Fig. 1 is to cross-sectional view;
Fig. 3 is that B-B in Fig. 1 is to cross-sectional view;
The part section structural representation of the liquid crystal display substrate that Fig. 4 provides for the embodiment of the present invention two;
The fragmentary top TV structure schematic diagram of insulated substrate layer in the liquid crystal display substrate that Fig. 5 provides for the embodiment of the present invention two;
The part section structural representation of the liquid crystal display substrate that Fig. 6 provides for the embodiment of the present invention three;
The fragmentary top TV structure schematic diagram of gate insulation layer in the liquid crystal display substrate that Fig. 7 provides for the embodiment of the present invention three;
The process flow diagram of the manufacture method of the liquid crystal display substrate that Fig. 8 provides for the embodiment of the present invention four;
In the manufacture method of the liquid crystal display substrate that Fig. 9 provides for the embodiment of the present invention five, prepare the process flow diagram of insulated substrate layer;
The process flow diagram of the manufacture method of the liquid crystal display substrate that Figure 10 provides for the embodiment of the present invention six.
Embodiment
Also by reference to the accompanying drawings the present invention is described in further detail below by specific embodiment.
The embodiment of the present invention provides a kind of liquid crystal display substrate, and this liquid crystal display substrate comprises underlay substrate, forms the pattern of multiple conductive structure on underlay substrate.Concrete, conductive structure can comprise the structures such as controlling grid scan line, gate electrode, public electrode wire, data line, source electrode, drain electrode and pixel electrode.Each conductive structure space or by insulation course keep insulation, for example, controlling grid scan line, gate electrode and public electrode wire are formed on underlay substrate, and data line, source electrode and drain electrode are formed on gate insulation layer, pixel electrode is formed on passivation layer, between each layer, keeps mutually insulated.Wherein, be formed with on the insulation course of conductive structure and be formed with groove, the pattern of conductive structure is formed in groove at least partly.
Adopt conductive structure is formed on to the technical scheme in groove, can reduce the height that conductive structure exposes with respect to groove place surface of insulating layer, even make conductive structure concordant with insulation course.In the time further forming other layer and when applying photoresist and carrying out composition technique, can not make because the height of lower floor's conductive structure projection is excessive photoresist apply uneven, disconnection in the side of conductive structure, the photoresist evenly applying can keep the accurate of composition pattern that technique forms, and is not prone to the phenomenon of broken string.Reducing of conductive structure difference in height, (PI rubbing) is bad in the orientation friction forming can also avoid applying alignment films time.
Concrete, for the array base palte in TFT-LCD, the conductive structure being formed in groove can comprise at least one in controlling grid scan line, gate electrode, public electrode wire, data line, source electrode and drain electrode.Underlay substrate is also for insulating material is made, be equivalent to insulation course, for controlling grid scan line, gate electrode and public electrode wire be can be formed in the groove of insulation course, can adopt the material that is easy to etching as underlay substrate, or on underlay substrate, form again one deck and be easy to the insulation course of etching.
Above-mentioned conductive structure is formed in groove, not only can avoids the defects such as composition is inaccurate, can also reduce the restriction to conductive structure pattern thickness, the thickness of increase conductive structure pattern that can be suitable.The advantage that thickness increases is to reduce the resistance of conductive structure, the resistance value of controlling grid scan line, gate electrode, public electrode wire, data line, source electrode and/or drain electrode reduces, can reduce formed RC value, and then can reduce the delayed impact to TFT switch motion, optimize the lag characteristic of TFT switch motion.Or, reduce the width of conductive structure pattern constant in the situation that maintaining resistance, and then increase the area in light-permeable region.
Introduce several preferred embodiment of the present invention below.
Embodiment mono-
The fragmentary top TV structure schematic diagram of the liquid crystal display substrate that Fig. 1 provides for the embodiment of the present invention one, Fig. 2 be A-A in Fig. 1 to cross-sectional view, Fig. 3 is that B-B in Fig. 1 is to cross-sectional view.The liquid crystal display substrate of the present embodiment is specifically as follows array base palte, comprises a underlay substrate 1, is formed with data line 2 and controlling grid scan line 3 that transverse and longitudinal is intersected on underlay substrate 1, encloses the multiple pixel cells that form matrix form.In each pixel cell, be provided with a TFT switch, TFT switch comprises gate electrode 4, active layer 5, source electrode 6 and drain electrode 7.Gate electrode 4 is connected with controlling grid scan line 3, generally adopts identical material to form with controlling grid scan line 3 simultaneously; Source electrode 6 connection data lines 2, drain electrode 7 connects pixel electrode 16, and source electrode 6 and drain electrode 7 adopt identical material to form with data line 2 simultaneously conventionally.Active layer 5 is between gate electrode 4 and source electrode 6 and drain electrode 7.In the time that gate electrode 4 passes into high level, source electrode 6 and drain electrode 7, by active layer 5 conductings, pass into pixel electrode 16 by the voltage of data line 2.For the public electrode wire 8 of public electrode transmission common electric voltage adopts identical material to form with controlling grid scan line 3 conventionally simultaneously.For keeping the insulation between above-mentioned conductive structure, on controlling grid scan line 3, gate electrode 4 and public electrode wire 8, be coated with gate insulation layer 10, on data line 2, source electrode 6 and drain electrode 7, be coated with passivation layer 11, pixel electrode 16 is connected with drain electrode 7 by the via hole 12 on passivation layer 11.
In the present embodiment, also set up a layer insulating, i.e. insulated substrate layer 9, is formed directly on underlay substrate 1, and controlling grid scan line 3, gate electrode 4 and public electrode wire 8 are formed on this insulated substrate layer 9.The groove forming on insulated substrate layer 9 comprises the first groove 13, and controlling grid scan line 3, gate electrode 4 and public electrode wire 8 are formed in the first groove 13.In the present embodiment, the thickness of controlling grid scan line 3, gate electrode 4 and public electrode wire 8 and the deep equality of the first groove 13, in concrete application, the thickness of controlling grid scan line 3, gate electrode 4 and public electrode wire 8 also can be greater than or less than the degree of depth of the first groove 13.
Adopt the technical scheme of the present embodiment, because controlling grid scan line 3, gate electrode 4 and public electrode wire 8 embed among the first groove 13, so there is no the controlling grid scan line 3, gate electrode 4 and the public electrode wire 8 that protrude on the surface of insulated substrate layer 9, or the thickness of projection is less than the thickness of controlling grid scan line 3, gate electrode 4 and public electrode wire 8 while being formed directly on underlay substrate 1, on the surface of insulated substrate layer 9, do not form or stair step patterns that height of formation is less.
Under normal process conditions, be generally 200～500 nanometers (nm) by the thickness of the film formed controlling grid scan line of grid metal foil, gate electrode and public electrode wire.In the follow-up composition technique of preparing the patterns such as data line, the side of stair step patterns is weak position, if the height of stair step patterns is larger, can cause apply photoresist inhomogeneous or disconnect, make follow-up etching pattern inaccurate.The technical scheme of the present embodiment has reduced the height of stair step patterns, can address the above problem, and makes the pattern of subsequent etching more accurate, can avoid the problem of the broken data wire that occurs etching.
In addition, because the side of stair step patterns is weak location, so prior art often needs to increase the thickness of stair step patterns, also increased the thickness of gate insulation layer, the defect causing is like this that the vertical range between gate electrode and active layer, source electrode and drain electrode increases, and in gate electrode, needs to pass into higher voltage and just can make active layer conducting source electrode and drain electrode.So the technical scheme of the present embodiment also provides the possibility that reduces gate insulation layer thickness, can effectively reduce the turn-on threshold voltage of TFT switch, reduce driving power consumption.
Have, the technical scheme of the present embodiment has reduced the restriction to controlling grid scan line, gate electrode and public electrode wire thickness again, therefore can increase thickness, and the resistance of conductive structure is reduced, thereby optimizes the lag characteristic of TFT switch, improves the display quality of LCD.
Or, due to the reducing of thickness limits, can in increasing thickness, the width of controlling grid scan line, gate electrode and public electrode line pattern be reduced.Due to the increase of thickness, so reduce the remarkable increase that pattern width can not cause resistance.Width reduces to increase the region area of printing opacity in pixel cell, has increased the aperture opening ratio of pixel cell.
The pattern of the first groove is the position of corresponding controlling grid scan line, gate electrode and public electrode wire preferably, and controlling grid scan line, gate electrode and public electrode wire are all formed in the first groove.The also position of at least one or more pattern in corresponding controlling grid scan line, gate electrode and public electrode wire according to specific needs of the pattern of the first groove, is formed on the partial pattern in controlling grid scan line, gate electrode and public electrode wire in the first groove.For example, only data line and the overlapping place of controlling grid scan line are formed to the first groove, can reach the problem breaking while avoiding follow-up data line etching.
Embodiment bis-
The part section structural representation of the liquid crystal display substrate that Fig. 4 provides for the embodiment of the present invention two, be that with the difference of embodiment mono-groove forming on insulated substrate layer 9 also comprises the second groove 14, the data line 2, source electrode 6 and the drain electrode 7 that are formed on gate insulation layer 10 are formed in the second groove 14.The plan structure of the present embodiment liquid crystal display substrate can be shown in Figure 1, Fig. 4 can be the schematic diagram liquid crystal display substrate of the present embodiment being dissectd along the B-B line in Fig. 1, the fragmentary top TV structure schematic diagram of insulated substrate layer 9 in the liquid crystal display substrate that Fig. 5 provides for the embodiment of the present invention two.The first groove 13 and the second groove 14 can be grooves that connect, deep equality.
Adopt the technical scheme of the present embodiment can reduce similarly the thickness limits to data line, source electrode and drain electrode, and then can reduce its resistance or reduce its width, can optimize the lag characteristic of TFT switch or the aperture opening ratio of pixel cell is provided.
In concrete application, the degree of depth of the first groove 13 and the second groove 14 can equate, preferably the degree of depth of the first groove 13 is greater than the degree of depth of the second groove 14, the second groove 14 that holds data line 2 is slightly shallower than the first groove 13, at the crossover location of data line 2 and controlling grid scan line 3, the height that makes data line 2 need to cross controlling grid scan line 3 reduces, and can further reduce the possibility that data line 2 broken strings occur.
The pattern of the second groove is the position of respective data lines, source electrode and drain electrode preferably, and data line, source electrode and drain electrode are all formed in the second groove.The also position of at least one or more pattern in respective data lines, source electrode and drain electrode according to specific needs of the pattern of the second groove.
Embodiment tri-
The part section structural representation of the liquid crystal display substrate that Fig. 6 provides for the embodiment of the present invention three, the fragmentary top TV structure schematic diagram of gate insulation layer 10 in the liquid crystal display substrate that Fig. 7 provides for the embodiment of the present invention three.In the present embodiment, insulation course between data line 2, source electrode 6 and drain electrode 7 and controlling grid scan line 3, gate electrode 4 and public electrode wire 8 is gate insulation layer 10, the groove forming on gate insulation layer 10 comprises the 3rd groove 15, and at least one or more in data line 2, source electrode 6 and drain electrode 7 is formed in the 3rd groove 15.The degree of depth of the 3rd groove 15 is less than the thickness of gate insulation layer 10, avoids contacting conducting with the controlling grid scan line 3 under gate insulation layer 10.
In the present embodiment, can comprise as shown in Figure 6 insulated substrate layer 9 and on the first groove 13, or insulated substrate layer 9 also can be set.
Adopt the technical scheme of the present embodiment can reduce similarly the thickness limits to data line, source electrode and drain electrode, and then can reduce its resistance or reduce its width, can optimize the lag characteristic of TFT switch or the aperture opening ratio of raising pixel cell.
The liquid crystal display substrate that the embodiment of the present invention provides is not limited to (the Twisted Nematic of the twisted nematic shown in figure; Hereinafter to be referred as: TN) type array base palte, can also be for forming the array base palte of horizontal component of electric field, for example fringing field switches (Fringe Field Switching; Hereinafter to be referred as: FFS) type array base palte.Both can under insulated substrate layer, form the public electrode of monoblock pattern, can also on insulated substrate layer, form the public electrode of the blocky at interval, the pattern of public electrode is also formed in the first groove, and with gate electrode and controlling grid scan line space.
The present invention also provides a kind of manufacture method of liquid crystal display substrate, be included in the step that forms space on underlay substrate or keep the pattern of the conductive structure of insulation by insulation course, form conductive structure on insulation course before, also on insulation course, form groove, the pattern of conductive structure is formed in groove at least partly.Manufacture method of the present invention can be used for preparing liquid crystal display substrate of the present invention, according to the difference of concrete technology flow scheme design, can have different manufacture methods, below describes by preferred embodiment.
Embodiment tetra-
The process flow diagram of the manufacture method of the liquid crystal display substrate that Fig. 8 provides for the embodiment of the present invention four, comprises the steps:
Step 801, on underlay substrate, form insulated substrate film, underlay substrate can be transparency glass plate or quartz plate, can be about 5000～20000 (Ethylmercurichlorendimides) by chemical vapor deposition method (PECVD) deposit thickness
insulated substrate film, the material of insulated substrate film can be selected oxide, nitride or oxynitrides, and corresponding chemical reaction gas is silane (SiH4), ammonia (NH3), nitrogen (N2) or dichloro-dihydro silicon (SiH2Cl2), ammonia (NH3), nitrogen (N2);
Step 802, insulated substrate film is carried out to composition technique, form the pattern of the insulated substrate layer that comprises the first groove, so-called composition technique, the operation such as comprise exposure imaging, etching and peel off;
Step 803, on insulated substrate layer, deposit grid metallic film, can carry out deposit thickness by sputter or thermal evaporation method and be 5000～
grid metallic film, grid metallic film can be selected the metal or alloy such as Cr, W, Ti, Ta, Mo, Al or Cu, the grid metal level being made up of multiple layer metal also can be satisfied the demand;
Step 804, grid metallic film is carried out to composition technique, form the pattern that comprises gate electrode, controlling grid scan line and public electrode wire, and at least one in gate electrode, controlling grid scan line and public electrode wire is formed in the first groove;
Step 805, form gate insulation layer, active layer film and data wire metal film forming on the underlay substrate of gate electrode, controlling grid scan line and public electrode wire, can be about 3000 by PECVD successively deposit thickness～
gate insulation layer, thickness be 1000～
semiconductor layer, thickness be 500～
ohmic contact layer, semiconductor layer and ohmic contact layer form active layer jointly, gate insulation layer can be selected oxide, nitride or oxynitrides, corresponding reacting gas can be SiH4, NH3, N2 or SiH2Cl2, NH3, N2, the reacting gas that semiconductor layer is corresponding can be SiH4, H2 or SiH2Cl2, hydrogen (H2), the reacting gas of ohmic contact layer can be SiH4, hydrogen phosphide (PH3), H2 or SiH2Cl2, PH3, H2, can carry out deposit thickness by sputter or thermal evaporation method and be 2000～
data wire metal film, data wire metal film can be selected metal and the alloys such as (chromium) Cr, (tungsten) W, (titanium) Ti, (tantalum) Ta, (molybdenum) Mo, (aluminium) Al or (copper) Cu, can be that individual layer can be also multilayer;
Step 806, data line metallic film and active layer film are carried out to composition technique, formation comprises the pattern of data line, source electrode, drain electrode and active layer, can adopt duotone mask plate to etch at twice the pattern of data line, source electrode and drain electrode, and the pattern of TFT raceway groove on active layer;
Step 807, on the underlay substrate that forms data line, source electrode, drain electrode and active layer, form passivation layer film, can be about 1500 by PECVD deposit thickness～
passivation layer film, passivation layer film can be selected oxide, nitride or oxynitrides, corresponding reacting gas can be SiH4, NH3, N2 or SiH2Cl2, NH3, N2;
Step 808, passivation layer film is carried out to composition technique, form the pattern of the passivation layer of via hole, the position of the corresponding drain electrode of via hole;
Step 809, on passivation layer pixel deposition electrode film, can be 300 by sputter or thermal evaporation method deposition a layer thickness～
pixel electrode film, its material can be indium tin oxide (Indium Tin Oxides; Hereinafter to be referred as: ITO) or indium-zinc oxide (Indium Zinc Oxides; Hereinafter to be referred as: IZO), can be also other transparent metal and metal oxide;
Step 810, pixel electrode film is carried out to composition technique, form the pattern that comprises pixel electrode.
The liquid crystal display substrate structure that above-mentioned steps forms can be referring to shown in Fig. 1～3.Reduce the thickness limits to controlling grid scan line, gate electrode and public electrode wire, can increase its thickness and reduce resistance, optimized TFT lag characteristic, also can reduce its width and improve aperture opening ratio.
On the basis of the present embodiment, be not limited to prepare the TN type array base palte shown in Fig. 1～3 with technique scheme, can also prepare based on such scheme the array base palte of the horizontal component of electric fields such as FFS type, for example, before can forming insulated substrate film on underlay substrate, also comprise: on underlay substrate, deposit the public electrode of monoblock, then form again insulated substrate film.
Or, before can also depositing grid metallic film on insulated substrate layer, also comprise: on insulated substrate layer, deposit public electrode film, adopt composition technique to form the pattern of the block public electrode at interval, the pattern of this public electrode is formed in part the first groove, is formed on controlling grid scan line and gate electrode space in the first groove so that follow-up.The pattern of the first groove can carry out composition according to the requirement of space.
On underlay substrate, form space or keep the pattern of conductive structure of insulation by insulation course, and the step that forms groove on insulation course can also be specially:
The gate insulation layer covering on gate electrode and controlling grid scan line is carried out to composition technique, form the pattern of the gate insulation layer that comprises the 3rd groove, and the degree of depth of the 3rd groove is less than the thickness of gate insulation layer;
On gate insulation layer, deposit active layer film and data wire metal film;
Described data wire metal film and active layer film are carried out to composition technique, form the pattern that comprises data line, source electrode, drain electrode and active layer, at least one in described data line, source electrode and drain electrode is formed in the 3rd groove.
The technology that forms the 3rd groove can independently be implemented, and also four scheme is implemented in the lump in conjunction with the embodiments.
Embodiment five
The manufacture method of the liquid crystal display substrate that the embodiment of the present invention five provides, can be take embodiment tetra-as basis, and step 802 can be specially: insulated substrate film is carried out to composition technique, form the pattern of the insulated substrate layer that comprises the first groove and the second groove, the position of at least one in position respective data lines, source electrode and the drain electrode of the second groove simultaneously.
The liquid crystal display substrate structure that adopts this scheme to form can be referring to shown in Figure 4 and 5.Can further reduce the thickness limits to data line, source electrode and drain electrode, can increase its thickness and reduce resistance, optimize TFT lag characteristic, also can reduce its width and improve aperture opening ratio.
Insulated substrate film is carried out to composition technique, form the pattern of insulated substrate layer that comprises the first groove and the second groove, can be specifically to form the first groove that the degree of depth is identical and the pattern of the second groove by composition technique simultaneously.
Or, insulated substrate film is carried out to composition technique, the pattern that forms the insulated substrate layer that comprises the first groove and the second groove can also be to form different the first groove and the second grooves of the degree of depth, and the degree of depth of the first groove is greater than the degree of depth of the second groove.Can form respectively the first groove and the second groove by twice composition technique, also can adopt following step to realize, as shown in Figure 9:
Such scheme can form the first groove and the second groove by mask exposure, a twice etching, and operation is simple, can enhance productivity.
Embodiment six
The process flow diagram of the manufacture method of the liquid crystal display substrate that Figure 10 provides for the embodiment of the present invention six, comprises the steps:
On the basis of technique scheme, can also further form gate electrode, after controlling grid scan line and public electrode wire, to forming gate electrode, on the insulated substrate layer of controlling grid scan line and public electrode wire, carry out composition technique, on insulated substrate layer, form the pattern of the second groove, so that the gate insulation layer forming subsequently, active layer, data line, source electrode and drain electrode are formed on the insulated substrate layer with the second groove, the second groove respective data lines, the position of at least one in source electrode and drain electrode, thereby reduce data line, the thickness limits of source electrode and/or drain electrode.
The manufacture method of liquid crystal display substrate provided by the present invention can be used for preparing liquid crystal display substrate of the present invention, but liquid crystal display substrate of the present invention is not limited to be prepared by above-mentioned manufacture method, can also adopt additive method to prepare.Technical scheme of the present invention provides a kind of technical scheme that can reduce conductive structure thickness limits.Each conductive structure thickness can suitably increase, this can bring many-sided advantage: the resistance that can reduce by thickness increase conductive structure, for example the resistance of controlling grid scan line, gate electrode, data line, source electrode and drain electrode reduces, can reduce RC value, thereby optimize the lag characteristic of TFT switch, improve display quality; Can increase under the prerequisite of thickness, just can suitably reduce the width of conductive structure pattern, can improve the area of transmission region, improve aperture opening ratio; Lower floor's conductive structure embeds in groove, makes in the time of the pattern of etching upper strata conductive structure, and photoresist can apply more evenly, and pattern etch is more accurate, is not prone to broken string; Controlling grid scan line and gate electrode embed in groove, the thickness of gate insulation layer can suitably be reduced, can shorten the distance between gate electrode and source electrode and drain electrode, and then can reduce the magnitude of voltage of gate electrode drive TFT switch open, can reduce driving power consumption.
Technical scheme of the present invention is not only applicable to liquid crystal display substrate, is also applicable to various semiconductor integrated devices.
Finally it should be noted that: above embodiment only, in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (6)
1. a liquid crystal display substrate, comprise underlay substrate, on described underlay substrate, form the pattern of multiple conductive structure, each described conductive structure space or by insulation course keep insulation, be formed with on the insulation course of conductive structure and be formed with groove, the pattern of described conductive structure is formed in described groove at least partly;
The conductive structure being formed in described groove comprises at least one in controlling grid scan line, gate electrode, public electrode wire, data line, source electrode and drain electrode;
Insulation course between described controlling grid scan line, gate electrode or public electrode wire and described underlay substrate is insulated substrate layer, the groove forming on described insulated substrate layer comprises the first groove, and at least one in described controlling grid scan line, gate electrode and public electrode wire is formed in described the first groove;
It is characterized in that, the insulation course covering on described controlling grid scan line, gate electrode or public electrode wire is gate insulation layer, and described data line, source electrode and drain electrode are formed on described gate insulation layer;
The groove forming on described insulated substrate layer also comprises the second groove, and at least one being formed in described data line, source electrode and the drain electrode on described gate insulation layer is formed in described the second groove.
2. liquid crystal display substrate according to claim 1, is characterized in that: the degree of depth of described the first groove is more than or equal to the degree of depth of described the second groove.
3. a manufacture method for liquid crystal display substrate, is included in the step that forms space on underlay substrate or keep the pattern of the conductive structure of insulation by insulation course, before forming conductive structure, also comprises on insulation course:
On described insulation course, form groove, the pattern of described conductive structure is formed in described groove at least partly;
On underlay substrate, form space or keep the pattern of conductive structure of insulation by insulation course, and on insulation course, forming groove and comprise:
On underlay substrate, form insulated substrate film;
Described insulated substrate film is carried out to composition technique, form the pattern of the insulated substrate layer that comprises the first groove;
On described insulated substrate layer, deposit grid metallic film;
Described grid metallic film is carried out to composition technique, form and comprise the pattern of gate electrode, controlling grid scan line and public electrode wire, and at least one in described gate electrode, controlling grid scan line and public electrode wire is formed in described the first groove;
It is characterized in that, described insulated substrate film is carried out to composition technique, form when comprising the pattern of insulated substrate layer of the first groove, also comprise:
On insulated substrate layer, form the pattern of the second groove, the position of at least one in position respective data lines, source electrode and the drain electrode of described the second groove.
4. the manufacture method of liquid crystal display substrate according to claim 3, is characterized in that, described insulated substrate film is carried out to composition technique, and the pattern that forms the insulated substrate layer that comprises the first groove and the second groove comprises:
On described insulated substrate film, apply photoresist;
Adopt duotone mask plate to carry out exposure imaging processing to described photoresist, form complete reserve area, part reserve area and remove region completely;
Carry out etching for the first time, remove insulated substrate film corresponding to region completely described in etching, form the pattern of the insulated substrate layer of the first groove that comprises partial depth;
Remove photoresist according to the thickness ashing of part reserve area photoresist;
Carry out etching for the second time, part reserve area and remove insulated substrate film corresponding to region completely described in etching, form the pattern of the insulated substrate layer that comprises the first groove and the second groove, and the degree of depth of described the first groove is greater than the degree of depth of described the second groove.
5. the manufacture method of liquid crystal display substrate according to claim 3, is characterized in that, forms space or keeps the pattern of conductive structure of insulation by insulation course, and on insulation course, form groove and comprise on underlay substrate:
On underlay substrate, form insulated substrate film;
On described insulated substrate film, apply photoresist;
Adopt monotone mask plate to carry out exposure imaging processing to described photoresist, form and remove region and complete reserve area completely;
Described insulated substrate film is carried out to etching, form the pattern of the insulated substrate layer that comprises the first groove;
On the described insulated substrate layer that is coated with photoresist, deposit grid metallic film;
Peel off described photoresist and on grid metallic film, form and comprise the pattern of gate electrode, controlling grid scan line and public electrode wire, and described gate electrode, controlling grid scan line and public electrode wire are retained in described the first groove.
6. the manufacture method of liquid crystal display substrate according to claim 5, is characterized in that, after forming gate electrode, controlling grid scan line and public electrode wire, also comprises:
Carry out composition technique to forming on the insulated substrate layer of described gate electrode, controlling grid scan line and public electrode wire, on described insulated substrate layer, form the pattern of the second groove.
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| CN102819138A (en) * | 2012-07-25 | 2012-12-12 | 京东方科技集团股份有限公司 | Array base plate and display device |
| KR102081599B1 (en) * | 2013-06-28 | 2020-02-26 | 엘지디스플레이 주식회사 | Array substrate for Liquid Crystall Display Device and methode for fabricating the same |
| CN103713437B (en) * | 2013-12-16 | 2016-03-09 | 合肥京东方光电科技有限公司 | A kind of array base palte, its method for making, LCDs and display device |
| CN104103645B (en) * | 2014-06-16 | 2017-03-29 | 京东方科技集团股份有限公司 | A kind of substrate and preparation method thereof, display device |
| CN106932942B (en) * | 2017-03-24 | 2020-07-28 | 厦门天马微电子有限公司 | Touch control display device |
| WO2020191661A1 (en) * | 2019-03-27 | 2020-10-01 | 京东方科技集团股份有限公司 | Display substrate, display device, mask plate, and manufacturing method |
| CN111697008B (en) * | 2020-06-22 | 2023-07-14 | 成都京东方显示科技有限公司 | Array substrate and manufacturing method thereof |
| CN112631003B (en) * | 2020-12-30 | 2022-11-29 | 成都中电熊猫显示科技有限公司 | Array substrate and broken line repairing method of array substrate |
| US20240188349A1 (en) * | 2021-08-25 | 2024-06-06 | Hefei Boe Joint Technology Co., Ltd. | Display substrate and display device |
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