CN101436601A

CN101436601A - Array substrate of thin-film transistor

Info

Publication number: CN101436601A
Application number: CNA2008102072704A
Authority: CN
Inventors: 高孝裕
Original assignee: SVA Group Co Ltd
Current assignee: SVA Group Co Ltd
Priority date: 2008-12-18
Filing date: 2008-12-18
Publication date: 2009-05-20

Abstract

The invention relates to an array substrate of a film transistor. The array substrate comprises an insulating substrate; a grid electrode conducting layer is formed on the insulating substrate; a grid electrode line and a capacitance storage electrode are formed on the grid electrode conducting layer, wherein a ditch is formed on the insulating substrate; the thickness of the grid electrode conducting layer is equal to the depth of the ditch on the whole; and the grid electrode line and the capacitance storage electrode are positioned inside the ditch. The array substrate of the film transistor solves the problems of line disconnection caused by section difference of a data line and improves the qualified rate of a product.

Description

Thin-film transistor array base-plate

Technical field

The present invention relates to a kind of array base palte, particularly relate to a kind of thin-film transistor array base-plate of avoiding broken data wire.

Background technology

(thin film transistor liquid crystal display is a kind of flat-panel screens that is widely used most at present TFT-LCD) to Thin Film Transistor-LCD, and it has advantages such as low-power, thin type light weight and low voltage drive.Yet along with the continuous increase of panel designs size, the distance of signal conveys is also more and more longer, brings holding wire broken string problem thereupon.

Fig. 1 is the structural representation of the array base palte of prior art, see also Fig. 1, thin-film transistor is arranged on the insulated substrate 100, and it comprises that one is positioned at grid 110, storage capacitors electrode 112, on this insulated substrate 100 and is positioned at gate insulator 120, on this grid 110 and this insulated substrate 100 and is positioned at semiconductor layer 130, on this gate insulator 120 and is positioned at ohmic contact layer 132 and on this semiconductor layer 130 and is positioned at source electrode 140 and drain electrode 142 on the ohmic contact layer 132.The manufacturing process of the array base palte of prior art is as follows: at first on insulated substrate 100 surface sputterings of cleaning the ground floor metal film as grid material, at coating photoresist on this metal film and graphically, form grid 110 and storage capacitor electrode 112 then by etching.On first metal film, deposit thin film layer 120, for example SiNx or SiO subsequently by pecvd process ₂Gate insulating film.Then at SiNx or SiO ₂By CVD technology, continue deposited semiconductor material a-Si 130 and N+Si 132 thin layers on the dielectric film, adopt sputter sputter second layer metal film at last, as the data wire material.After adopting exposure and etching, define source 142, drain electrode 144 and semiconductor figure 130 respectively, make the TFT switch element, 132 ohmic contact as source electrode and TFT.In this technical process, after grid is finished, adopt the method for deposit to continue other material of deposition, so the pattern of gate patterns remains inevitably, the material of other on gate patterns is will the section of generation poor like this.Along with the area increase of LCD panel, the raising of resolution needs more gate line of production quantity and data wire, makes live width become narrower, causes the raising of difficulty in process degree, and is therefore easier of gate line and data wire overlapping place generation broken string phenomenon.When there is the disconnection portion timesharing in data wire, the pixel with latter half circuit control of broken string just can not be normally luminous, makes LCD become bad product, reduces the product yield.Therefore being necessary to take measures, it is poor to reduce section, improves the product yield.

Summary of the invention

Technical problem to be solved by this invention provides a kind of thin-film transistor array base-plate, solves the problem of the broken string that data wire causes because of the section difference, improves the product yield.

The present invention solves the problems of the technologies described above the technical scheme that adopts to provide a kind of thin-film transistor array base-plate, comprise an insulated substrate, be formed with grid conducting layer on the described insulated substrate, be formed with gate line and storage capacitors electrode on the described grid conducting layer, wherein, be formed with irrigation canals and ditches on the described insulated substrate, the thickness of described grid conducting layer and the degree of depth of described irrigation canals and ditches are about the same, and described gate line and storage capacitors electrode are positioned at described irrigation canals and ditches.

Above-mentioned thin-film transistor array base-plate wherein, also is formed with gate line and/or storage capacitors electrode terminal in the described irrigation canals and ditches.

The present invention contrasts prior art following beneficial effect: thin-film transistor array base-plate provided by the invention, by on insulated substrate, etching the irrigation canals and ditches of gate line and capacitor storage beam, on described irrigation canals and ditches, deposit grid conducting layer then, the degree of depth of this grid conducting layer thickness and irrigation canals and ditches is roughly suitable, after finishing first procedure, whole base plate is in the same plane like this.In follow-up manufacture process, poor in the place section of appearance of gate line and data wire overlapping during deposition data wire metal because substrate is in the same plane, so the broken string problem that can avoid data wire to cause because of the section difference effectively.

Description of drawings

Fig. 1 is the structural representation of the array base palte of prior art.

Fig. 2 a～2i is the schematic diagram of array base palte manufacturing process section of the present invention.

Fig. 3 a～3d is the vertical view of array base palte manufacturing process of the present invention.

Among the figure:

100 insulated substrates, 110 grids, 112 storage capacitors electrodes

120 gate insulators, 130 semiconductor layers, 132 ohmic contact layers

140 source electrodes, 142 drain electrodes, 200 insulated substrates

204 gate line irrigation canals and ditches 204a area of grid 204b gate line zones

204c terminal area 206 electric capacity duct canal 206b electric capacity line zones

206c terminal area 210 grid conducting layers 220 gate insulators

230 semiconductor amorphous silicon layers, 232 doped amorphous silicon layers, 234 semiconductor amorphous silicon figures

236 doped amorphous silicon figures, 240 data wire 240c data wire terminal area

242 source electrodes, 244 drain electrodes, 250 passivation layers

252 contact holes, 260 pixel electrodes

Embodiment

The invention will be further described below in conjunction with accompanying drawing and exemplary embodiments.

Fig. 2 a～2i is the schematic diagram of array base palte manufacturing process section of the present invention, and Fig. 3 a～3d is the vertical view of array base palte manufacturing process of the present invention.

Please be simultaneously referring to Fig. 2 b, 2d and 3a, wherein, Fig. 2 d is the profile along A-A ' line among Fig. 3 a, the invention provides a kind of thin-film transistor array base-plate, comprise an insulated substrate 200, be formed with grid conducting layer 210 on the insulated substrate 200, be formed with grid 110 on the grid conducting layer 210, gate line and storage capacitors electrode 112, wherein, be formed with irrigation canals and ditches on the described insulated substrate, comprise gate line irrigation canals and ditches 204 and capacitor storage beam irrigation canals and ditches 206, the thickness of grid conducting layer 210 and the degree of depth of described irrigation canals and ditches are about the same, and described gate line and storage capacitors electrode are positioned at described irrigation canals and ditches.

Specify array base palte manufacturing process of the present invention below.See also Fig. 2 a, at first on insulated substrate 200, apply one deck photoresist 202, utilize one light shield (figure does not show) to expose, develop then, define gate line and storage capacitance line figures.Use acid as etching agent then, on insulated substrate, form gate line irrigation canals and ditches 204 and capacitor storage beam irrigation canals and ditches 206 simultaneously, shown in Fig. 2 b.Please refer to shown in Fig. 3 a, the gate line irrigation canals and ditches can be divided into three zones, and it is respectively area of grid 204a, gate line zone 204b and terminal area 204c.Electric capacity duct canal then only is divided into two zones, and it is respectively electric capacity line zone 206b and terminal area 206c.

Please be simultaneously referring to Fig. 2 c and Fig. 3 a, deposit grid conducting layer 210 in gate line irrigation canals and ditches 204 on insulated substrate 200 and the electric capacity duct canal 206 and on first photoresist layer 202, its material is aluminium (Al) or aluminium alloy (AlNd), or metal multilayer film (AlNd/MoNb) is as grid material, and wherein Chen Ji metal thickness is roughly identical with the irrigation canals and ditches degree of depth on the insulated substrate.

Please continue d referring to Fig. 2, utilize the appropriate solvent of prior art (Liftoff technology) that first photoresist layer 202 is peeled off then, the grid conducting layer 210 that will be positioned at jointly on first photoresist layer is peeled off together, grid conducting layer in only remaining gate line irrigation canals and ditches 204 and the electric capacity duct canal 206 is shown in Fig. 3 b.Grid conducting layer 210 in the area of grid 204a of gate line irrigation canals and ditches 204 is as the grid of TFT.Grid conducting layer in the 206b of the reservior capacitor zone of electric capacity duct canal 206 is as the electric capacity line of reservior capacitor, the double usefulness of doing the bottom electrode of reservior capacitor.After finishing first procedure, whole base plate is in the same plane like this, for follow-up manufacturing process provides a smooth platform.

Then referring to Fig. 2 e, on this insulated substrate 200, adopt the method for chemical vapour deposition (CVD), continue the gate insulator 220 that deposition one covers this gate line and electric capacity line, at the surface deposition semiconductor amorphous silicon layer 230 and the doped amorphous silicon layer 232 of this gate insulator.

Please continue f referring to Fig. 2, after applying one deck photoresist (figure does not show) on the semiconductor layer, adopt one light shield (figure does not show) to semi-conducting material expose, development and etching, on area of grid 204a, form semiconductor amorphous silicon figure 234 and doped amorphous silicon figure 236.

Then referring to Fig. 2 g and Fig. 3 c, physical deposition metal level (figure does not show) on semiconductor layer thereafter, material can be aluminium, chromium etc. and alloy material thereof.Then after applying one deck photoresist (figure does not show) on the metal level, adopt one light shield to its expose, development and etching, form data wire 240, data wire terminal area 240c, the source electrode 242 of TFT and drain electrode 244.As can be seen from the figure, in grid and source, the place section of appearance that overlaps of drain electrode is poor.Similarly, it is poor section also to occur in the place of gate line and data wire overlapping.So just can effectively avoid the problem of the broken data wire that causes because of the section difference.

Please continue h referring to Fig. 2, by chemical vapour deposition (CVD) deposition one passivation layer 250 in insulating barrier 220 and source electrode 242, drain electrode 244, then after applying one deck photoresist (figure does not show) on the passivation layer, adopt one light shield to its expose, development and etching, form contact hole 252.

Shown in Fig. 2 i and Fig. 3 d, continue deposition one transparency electrode (figure does not show) on passivation layer 250 at last, material is ITO (tin indium oxide) or IZO (indium zinc oxide) etc.Then after applying one deck photoresist (figure does not show) on the ITO, adopt one light shield to its expose, development and etching, form pixel electrode 260.So just can finish the manufacture process of whole array base palte.

Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.

Claims

1, a kind of thin-film transistor array base-plate, comprise an insulated substrate, be formed with grid conducting layer on the described insulated substrate, be formed with gate line and storage capacitors electrode on the described grid conducting layer, it is characterized in that, be formed with irrigation canals and ditches on the described insulated substrate, the thickness of described grid conducting layer and the degree of depth of described irrigation canals and ditches are about the same, and described gate line and storage capacitors electrode are positioned at described irrigation canals and ditches.

2, thin-film transistor array base-plate according to claim 1 is characterized in that, also is formed with gate line and/or storage capacitors electrode terminal in the described irrigation canals and ditches.