KR100930918B1 - Array substrate for liquid crystal display device and manufacturing method - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and a liquid crystal display device having a COT structure in which a color filter is formed on an array substrate.

In the liquid crystal display according to the present invention, in the structure of forming the color filter on the thin film transistor array, instead of forming an overcoat layer on the color filter to prevent the color filter from directly contacting the liquid crystal, the color filter is encapsulated. As a means of doing this, a black matrix and a transparent pixel electrode are used.

In this way, there is no need to form the overcoat layer separately, thereby reducing the process cost and the process time.

Description

Array substrate for LCD and manufacturing method thereof {Array substrate for LCD and method for fabricating of the same}             

1 is a diagram schematically illustrating a configuration of a general liquid crystal display device.

FIG. 2 is a cross-sectional view of the liquid crystal display device according to the first example, taken along line II-II ′ of FIG. 1;

3 is a plan view schematically showing the configuration of a liquid crystal display array substrate having a COT structure according to the prior art;

4 and 5 are cross-sectional views taken along the lines IV-IV and V-V of FIG. 3, respectively.

6 is a plan view schematically showing the configuration of an array substrate for a liquid crystal display device having a COT structure according to the present invention;

7A to 7D and FIGS. 8A to 8D are cross-sectional views illustrating a cutting process taken along the line VI-VI, VIII-V of FIG. 6 according to the process sequence of the present invention.

<Brief description of the main parts of the drawing>

100 substrate 102 gate electrode

104: gate wiring 106: gate insulating film                 

108: ohmic contact layer 110: active layer

112 source electrode 114 drain electrode

120: gate insulating film 122: black matrix

124a: color filter 126: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display (COT) structure for forming a color filter on the thin film transistor array unit and a manufacturing method thereof.

In general, a liquid crystal display device displays an image by using optical anisotropy and birefringence characteristics of liquid crystal molecules. When an electric field is applied, the alignment of liquid crystals is changed, and the characteristics of light transmission vary according to the arrangement direction of the changed liquid crystals.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by the electric field is a device that represents the image by the transmittance of light that varies accordingly.

1 is a view schematically showing a general liquid crystal display device.                         

As shown, a general color liquid crystal display 11 includes a color filter 7 and a color filter 7 including a black matrix 6 formed between a sub color filter 8 and each sub color filter 8. The upper substrate 5 having the common electrode 18 deposited thereon, the pixel region P, and the pixel electrode 17 and the switching element T formed in the pixel region, and the pixel region P The liquid crystal 14 is filled between the lower substrate 22 and the upper substrate 5 and the lower substrate 22 on which array wiring is formed.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 crosses the plurality of thin film transistors TFT. ) And data wirings 15 are formed.

In this case, the pixel area P is an area defined by the gate wiring 13 and the data wiring 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area P as described above.

The pixel electrode 17 uses a transparent conductive metal having a relatively high transmittance of light, such as indium-tin-oxide (ITO).

A storage capacitor C connected in parallel with the pixel electrode 17 is formed on the gate wiring 13, and a part of the gate wiring 13 is used as the first electrode of the storage capacitor C, and a second As an electrode, an island-shaped source / drain metal layer 30 formed of the same material as the source and drain electrodes is used.

In this case, the source / drain metal layer 30 is configured to be in contact with the pixel electrode 17 to receive a signal of the pixel electrode.

As described above, when the upper color filter substrate 5 and the lower array substrate 22 are bonded to each other to produce a liquid crystal panel, light leakage defects due to the bonding error between the color filter substrate 5 and the array substrate 22 may be reduced. It is very likely to occur.

A description with reference to FIG. 2 is as follows.

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1.

As described above, the first substrate 22, which is an array substrate, and the second substrate 5, which is a color filter substrate, are spaced apart from each other, and the liquid crystal layer 14 is disposed between the first and second substrates 22, 5. This is located.

The thin film transistor T including the gate electrode 32, the active layer 34, the source electrode 36, and the drain electrode 38 is disposed on the array substrate 22, and the thin film transistor T is disposed on the thin film transistor T. A protective film 40 is configured to protect it.

In the pixel region P, a transparent pixel electrode 17 is formed in contact with the drain electrode 38 of the thin film transistor T. A storage capacitor C connected in parallel with the pixel electrode 17 includes a gate line 13. It is configured on the top.

The upper substrate 5 includes a black matrix 6 corresponding to the gate wiring 13, the data wiring 15, and the thin film transistor T, and corresponds to the pixel region P of the lower substrate 22. The sub color filters 7a, 7b, and 7c are formed.

In this case, the general array substrate is configured such that the data line 15 and the pixel electrode 17 are spaced apart by a predetermined distance A to prevent vertical cross talk, and the gate line 13 and the pixel are spaced apart from each other. The electrodes are also configured to be spaced apart by a predetermined interval (B).

Since the spaces A and B spaced apart between the data line 15 and the gate line 13 and the pixel electrode 17 are regions where light leakage occurs, a black matrix formed on the upper color filter substrate 5 matrix) (6) will cover this part.

In addition, the black matrix 6 formed on the thin film transistor T serves to block the light so that the light radiated from the outside does not affect the active layer 34 through the passivation layer 40. .

However, a misalignment may occur during the process of bonding the upper substrate 5 and the lower substrate 22. In view of this, a margin of a constant value is determined when designing the black matrix 6. Since the design is carried out with reference to), the aperture ratio decreases by that amount.

In addition, in the case where the bonding error beyond the margin occurs, there is often a case of light leakage defects in which the light leakage regions A and B are not covered by the black matrix 6.

In this case, since the light leakage appears to the outside, there is a problem of degrading the image quality.

In order to solve this problem, a COT (color filter on TFT) structure for constructing a color filter on an array substrate has recently been proposed.

3 is a plan view schematically illustrating a part of a configuration of a liquid crystal display array substrate having a COT structure according to the related art.

As shown in the drawing, the gate wiring 54 extending in one direction on the substrate 50 and the data wiring 66 defining the pixel region P by perpendicularly crossing the gate wiring 54 are formed.

The thin film transistor T composed of the gate electrode 52, the active layer 58, and the source and drain electrodes 62 and 64 is formed at the intersection of the gate line 54 and the data line 66.

At this time, the source electrode 62 is formed in a "U" shape, the drain electrode 64 is configured while maintaining a distance parallel to the inside of the source electrode.

In this configuration, since the channel length between the source and drain electrodes 62 and 64 can be shortened and the channel width can be wide, the advantage of improving the operation of the thin film transistor can be obtained by inducing a rapid flow of carriers. have.

A storage capacitor C _ST is formed on the gate wiring 54. The storage capacitor C _ST uses a portion of the gate wiring 54 as a first electrode, and is formed on the gate wiring 54. The metal pattern 68 positioned in the shape and in contact with the pixel electrode 90 is used as the second electrode.

The black matrix 72 having a larger area is formed on the thin film transistor T, the gate lines, and the data lines 54 and 66.

Color filters 74a and 74b are formed on the substrate 50 including the black matrix 72 and extend in one direction to correspond to the pixels P adjacent to each other above and below.

The pixel electrode 80 is formed in the pixel region P while contacting the drain electrode 64 with an overcoat layer (not shown) interposed with the color filter.                         

The reason why the overcoat is further formed under the pixel electrode 80 is to shield the color filters 74a and 74b from the upper alignment layer or the liquid crystal (not shown).

Normally, the color filters 74a and 74b are sequentially formed with red, green, and blue color filters 74a (not shown).

The cross-sectional structure of a conventional liquid crystal display array substrate having a COT structure configured as described above will be described below with reference to FIGS. 4 and 5.

4 and 5 are cross-sectional views illustrating a cross section taken along lines IV-IV and V-V of FIG. 3 (IV-IV is a cross-sectional view of a thin film transistor, a capacitor, and a pixel unit, and FIGS. The cross section which cuts around wiring is shown.)

4 and 5, the gate electrode 52 and the gate wiring 54 are formed on the substrate. The gate insulating layer 56 is formed on the entire surface of the substrate 50 including the gate electrode and the gate lines 53 and 54. An active layer 58 and an ohmic contact layer 60 stacked on a portion of the gate insulating layer 56 corresponding to the gate electrode 52 are formed.

On the ohmic contact layer 60, source and drain electrodes 62 and 64 spaced apart from each other, and a data line 66 connected to the source electrode 62 and extending perpendicular to the gate line 54. ) Is configured. In addition, an island-shaped metal pattern 68 is further formed on a portion of the gate wiring 54 while forming the source and drain electrodes 62 and 64.                         

A thin film transistor T including the gate electrode 52, the active and ohmic contact layers 58 and 60, and the source and drain electrodes 62 and 64, and the gate and data lines 54 and 55. The protective layer 70 is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ) on the entire surface of the substrate 50.

After applying or coating black resin (photosensitive organic material) (black resin) on the protective film 70 corresponding to the thin film transistor (T), the gate wiring and the data wiring (54, 66), the black matrix ( 72).

In this case, the black matrix 72 does not exist in a portion corresponding to a part of the gate wiring 54 in which the metal pattern 68 is located.

Among the substrates 50 on which the black matrix 72 is formed, the color filter 74a is formed in one direction corresponding to the pixels P adjacent to each other up and down.

The color filter has a shape in which red, green, and blue color filters are sequentially formed in left and right directions.

An overcoat layer 76 is formed by coating or coating an organic insulating film on the entire surface of the substrate 50 including the color filter.

A transparent pixel electrode 80 is formed on the overcoat layer 76 corresponding to the pixel region at the same time as the drain electrode 64 and the metal pattern 68.

The metal pattern 68 in contact with the pixel electrode 80 and the gate line 54 below the pixel electrode 80 form a storage capacitor C _ST .

As described above, the array substrate for a liquid crystal display device having a COT structure according to the related art can be manufactured.

However, in the above-described configuration, the overcoating layer 76 is configured to prevent the color filter 74a from contaminating adjacent to the alignment film and the liquid crystal (not shown) positioned on the pixel electrode 80.

However, as the overcoating layer 76 is used, the cost increases, which acts as a burden for manufacturing the liquid crystal panel, which lowers the price competition order.

The present invention has been proposed to solve the above problems, in the COT-shaped array substrate structure, instead of forming an overcoating layer on top of the color filter, a transparent pixel electrode is formed directly on the color filter layer. The transparent pixel electrode is configured in a shape surrounding the color filter.

In addition, for this shape, the color filter is formed by patterning each pixel.

The configuration as described above is such that the black matrix 72 and the pixel electrode 80 present in portions corresponding to the gate wiring 54 and the data wiring 66 completely surround the color filter up and down. Therefore, the color filter is not exposed to the outside.                         

Therefore, since the structure does not use the overcoat layer as compared with the prior art, it is possible to save the cost and simplify the process, which has the advantage of improving the price competitiveness and process yield.

According to an aspect of the present invention, an array substrate for a liquid crystal display device includes: gate wiring extending in one direction on a substrate; A data line crossing the gate line perpendicularly to form a pixel area; A thin film transistor positioned at an intersection point of the gate line and the data line; A black matrix covering the thin film transistor, the gate wiring, and the data wiring; A color filter configured in the pixel region; The present invention provides an array substrate for a liquid crystal display device including a transparent pixel electrode covering the color filter while being in contact with the thin film transistor and being in contact with the lower black matrix around the pixel area.
An inorganic insulating layer is formed between the thin film transistor and the black matrix, and the black matrix is formed of black resin (photosensitive organic material).
In addition, the pixel electrode extends above the gate line and the data line to contact the lower black matrix to shield the color filter from the outside, and a metal pattern contacting the pixel electrode on the gate line. This is made up.
Here, a storage capacitor having the metal pattern as the first electrode and the gate wiring under the metal pattern as the second electrode is configured, and the thin film transistor includes a gate electrode, an active layer, a source electrode, and a drain electrode.
In addition, a method of manufacturing an array substrate for a liquid crystal display device according to an aspect of the present invention includes the steps of forming a gate wiring extending in one direction on the substrate; Forming a data line crossing the gate line perpendicularly to form a pixel region; Forming a thin film transistor at an intersection point of the gate line and the data line; Forming a black matrix covering the thin film transistor, the gate wiring, and the data wiring; Forming a color filter in the pixel region; And forming a transparent pixel electrode surrounding the color filter while being in contact with the thin film transistor and in contact with the lower black matrix in the periphery of the pixel region.
Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

delete

delete

delete

delete

delete

delete

Example

6 is a view schematically showing the configuration of an array substrate for a liquid crystal display device according to the present invention.

As shown in the drawing, the gate wiring 102 extending in one direction on the substrate 100 and the data wiring 116 defining the pixel region P are perpendicularly intersected with each other.

The thin film transistor T including the gate electrode 102, the active layer 108, and the source and drain electrodes 112 and 114 is formed at the intersection of the gate line 104 and the data line 116.                     

At this time, the source electrode 112 is configured in a "U" shape, the drain electrode 114 is configured while maintaining a distance parallel to the inside of the source electrode 112.

In this configuration, since the channel length between the source and drain electrodes 112 and 114 can be shortened and the channel width can be wide, the operation of the thin film transistor can be improved by inducing fast flow of the carrier.

A storage capacitor C is formed on the gate wiring 104. The storage capacitor C has a portion of the gate wiring 104 as a first electrode, and is formed in an island shape on the gate wiring 104. The metal pattern 118 is positioned as a second electrode.

The black matrix 122 having a larger area is formed on the thin film transistor T, the gate lines, and the data lines 104 and 116.

Color filters 124a and 124b are formed on the substrate 100 including the black matrix 1222 by independently patterning the pixels.

In this case, the color filters configured in the up and down neighboring pixels may be the same color or different colors.

In general, the color filters include red, green, and blue color filters 124a (not shown) 124b.

The pixel region P includes the drain electrode 114, the metal pattern 118, and the transparent pixel electrode 126 positioned above the color filter.

In the above-described configuration, the pixel electrode 126 is configured to surround the color filters 124a and 124b.                     

That is, the pixel electrode 126 is configured to be in contact with the black matrix 122 in the vicinity of the edge of the pixel region P. In this case, the pixel electrode and the black matrix 122 are arranged in the pixel region. An encapsulation is performed so as not to expose the color filters 124a and 124b at the edge portion of (P).

Accordingly, although not illustrated, the alignment layer, the liquid crystal, and the color filter may not be in contact with the pixel electrode 126, thereby preventing display defects.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device having a COT structure according to the present invention will be described with reference to 7A to 7D and 8A to 8D.

7A to 7D and 8A to 8D are cross-sectional views taken along the line VI-VI, VIII-VIII of FIG. 6 and according to the process sequence of the present invention.

As shown in FIGS. 7A and 8A, a pixel region P, a thin film transistor region T, and a storage region C are defined on one side of the pixel region P on the substrate 100.

Corresponding to the thin film transistor region T of the substrate 100, a gate electrode 102 and a gate wiring 104 extending in one direction while being connected to the gate electrode 102 are formed. The gate insulating layer 106 is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 on which the gate electrode and the gate wirings 102 and 104 are formed. Form.

Next, pure amorphous silicon (a-Si: H) and impurities are deposited and patterned on top of the gate insulating layer 106 to form an island-like active layer ( 108 and an ohmic contact layer 110 are formed.

As shown in FIGS. 7B and 8B, chromium (Cr), molybdenum (Mo), tungsten (W), and copper (Cr) are formed on the entire surface of the substrate 100 on which the active layer 108 and the ohmic contact layer 110 are formed. And depositing and patterning one selected from a group of conductive metals including Cu, tantalum (Ta), titanium (Ti), and the like, and contacting the ohmic contact layer 108 with the source electrode 112 and the drain electrode 114. The data line 116 is formed to be connected to the source electrode 112 and extend in a direction perpendicular to the gate line 104.

At the same time, an island-shaped metal pattern 118 is formed on a portion of the gate wiring 104.

Subsequently, the ohmic contact layer 110 exposed between the spaced source and drain electrodes 112 and 114 is etched to expose the lower active layer 108.

Next, the protective film 120 is deposited by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 on which the source and drain electrodes 112 and 114 are formed. To form.

As shown in FIGS. 7C and 8C, a black resin (photosensitive organic material) is deposited and patterned on the entire surface of the substrate 100 on which the passivation layer 120 is formed, and the thin film transistor T and the gate are patterned. The black matrix 122 is formed on the wiring 102 and the data wiring 116.

In this case, the black matrix 122 does not exist on a part of the metal pattern 118. This part is the part where a contact hole is formed in a later process.

As shown in FIGS. 7D and 8D, a color filter is formed on the substrate 100 on which the black matrix 122 is formed.

The color filters 124a and 124b are formed to be independently patterned for each pixel P, and color filters of the same color may be formed in pixels adjacent to each other up and down, or color filters of different colors may be formed. In this case, the color filter may form a first open hole H1 and a second open hole H2 in a portion corresponding to the drain electrode of the thin film transistor corresponding to one side of the pixel and in a portion in which the metal pattern is located. do.

Accordingly, the lower passivation layer 120 is exposed by the first open hole H1 and the second open hole H2.

Subsequently, the passivation layer 120 inside the first and second open holes H1 and H2 is etched to expose a portion of the lower drain electrode 114 and a portion of the metal pattern 118. do.

Next, the exposed drain electrode 114 and the metal pattern 118 are in contact with each other to form a pixel electrode 126 positioned above the color filter of the pixel region P.

The pixel electrode is formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO).

In this case, the pixel electrode 126 partially extends above the gate line 102 and the data line 116 so as to completely surround the color filters 124a and 124b positioned in the pixel area P. The extended portion is configured to contact the lower black matrix 122.

In the above-described configuration, since the pixel electrode and the lower black matrix 122 completely block the color filters 124a and 124b from the outside in the peripheral portion of the pixel region P, the color filters 124a and 124b. There is an advantage that a defect caused by the effect of) does not occur.

As described above, in the COT structure, the color filter is independently patterned for each pixel, and the pixel electrode disposed above the color filter is configured to completely surround the color filter, so that the color filter is disposed around the pixel area. The pixel electrode and the lower black matrix are completely shielded from the outside.

Therefore, since the process of forming the overcoating layer, which has been conventionally performed for the color filter shielding as described above, can be omitted, cost and processing time can be reduced, thereby improving price competitiveness and process yield.

Claims (18)

A gate wiring extending in one direction on the substrate; A data line crossing the gate line perpendicularly to form a pixel area; A thin film transistor positioned at an intersection point of the gate line and the data line; A black matrix covering the thin film transistor, the gate wiring, and the data wiring; A color filter configured in the pixel region; And a transparent pixel electrode formed around the color filter while being in contact with the thin film transistor, the transparent pixel electrode being formed in contact with the lower black matrix in the periphery of the pixel area. The method of claim 1, And an inorganic insulating film formed between the thin film transistor and the black matrix. The method of claim 1, And the black matrix is formed of black resin (photosensitive organic material). The method of claim 1, And the pixel electrode extends above the gate line and the data line to contact a black matrix at the bottom thereof to shield the color filter from the outside. The method of claim 1, And a metal pattern in contact with the pixel electrode on the gate wiring. The method of claim 5, wherein And a storage capacitor having the metal pattern as the first electrode and the gate wiring under the metal pattern as the second electrode. The method of claim 1, The thin film transistor includes a gate electrode, an active layer, a source electrode and a drain electrode. Forming a gate wiring extending in one direction on the substrate; Forming a data line crossing the gate line perpendicularly to form a pixel region; Forming a thin film transistor at an intersection point of the gate line and the data line; Forming a black matrix covering the thin film transistor, the gate wiring, and the data wiring; Forming a color filter in the pixel region; Forming a transparent pixel electrode surrounding the color filter while being in contact with the thin film transistor and in contact with the lower black matrix around the pixel area. Array substrate manufacturing method for a liquid crystal display comprising a. The method of claim 8, A method of manufacturing an array substrate for a liquid crystal display device, wherein an inorganic insulating film is formed between the thin film transistor and the black matrix. The method of claim 9, And the inorganic insulating layer is silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ). The method of claim 8, And the black matrix is made of black resin (photosensitive organic material). The method of claim 8, And the pixel electrode extends above the gate line and the data line to contact a lower black matrix to shield the color filter from the outside. The method of claim 8, And a metal pattern in contact with the pixel electrode is formed on the gate wiring. The method of claim 13, And a storage capacitor having the metal pattern as the first electrode and the gate wiring formed under the metal pattern as the second electrode. The method of claim 8, The thin film transistor includes a gate electrode, an active layer, a source and a drain electrode. Forming a gate wiring extending in one direction and a gate electrode in contact with the substrate; Forming an inorganic barrier film on the gate wiring and the gate electrode; Depositing amorphous silicon and impurity amorphous silicon sequentially on the inorganic insulating film corresponding to the gate electrode, and then patterning them to form a stacked active layer and an ohmic contact layer; Forming a source electrode and a drain electrode spaced apart from each other on the ohmic contact layer, and a data line connected to the source electrode and vertically intersecting with the gate line to form a pixel region; Forming a black matrix corresponding to the source and drain electrodes, the gate wiring, and the data wiring; Forming a color filter in the pixel region; Forming a pixel electrode which extends over the color filter to contact the drain electrode and surrounds the color filter and contacts the black matrix on the gate wiring and the data wiring; Array substrate manufacturing method for a liquid crystal display comprising a. The method of claim 16, And the pixel electrode extends above the gate line and the data line to contact a lower black matrix to shield the color filter from the outside. The method of claim 16, And an inorganic insulating film is formed between the source and drain electrodes and the black matrix.

Images