KR20080073573A - Liquid crystal panel and manufacturing method thereof - Google Patents

Abstract

An LCD(Liquid Crystal Display) panel and a method for manufacturing the same are provided to remove a space between a data line and a common voltage line, thereby improving an aperture ratio and preventing leakage of light. A plurality of gate lines(120) and a plurality of data lines(160) are formed in a matrix type on a first insulating substrate. A plurality of common voltage lines(130) are disposed adjacent to the gate lines along the extending direction of the gate lines. Thin film transistors are formed at crossing portions of the gate lines and the data lines. Pixel electrodes are electrically connected to the thin film transistors respectively. Each of the data lines is composed of a first region(b) and a second region(a), where a first width(d5) of the first region is smaller than a second width(d3) of the second region. The second region of the data line is disposed in an area where the thin film transistor, the gate line, and the common voltage line are not formed. The second region of the data line overlaps with a pixel electrode(180) to form a storage capacitance together with the pixel electrode.

Description

Liquid crystal panel and its manufacturing method {LIQUID CRYSTAL PANEL AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a conventional thin film transistor substrate,

2 is a plan view showing a black matrix formed on a conventional color filter substrate;

3 is a schematic cross-sectional view taken along line III-III of FIGS. 1 and 2;

4 is a layout view of a thin film transistor substrate according to the first embodiment of the present invention;

5 is a plan view showing a black matrix formed on a color filter substrate according to a first embodiment of the present invention;

6 is a cross-sectional view taken along VI-VI of FIGS. 4 and 5;

7 is a layout view of a thin film transistor substrate according to a second embodiment of the present invention;

8A to 8C are diagrams for sequentially explaining a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

Explanation of Signs of Major Parts of Drawings

10: liquid crystal panel 100: thin film transistor substrate

110: first insulating substrate 120: gate wiring

130: common voltage line 140: gate insulating film

150: semiconductor layer 155: ohmic contact layer

160: data wiring 170: protective film

180: pixel electrode 200: color filter substrate

210: second insulating substrate 220: black matrix

230: color filter layer 240: overcoat film

250: common electrode

The present invention relates to a liquid crystal panel and a method for manufacturing the same, and more particularly, to a liquid crystal panel and a method for manufacturing the same has improved aperture ratio and reduced light leakage.

The liquid crystal display (LIQUID CRYSTAL DISPLAY), which is widely used as a flat panel display, has a thin, light, and low power consumption compared to a CRT.

A liquid crystal display device is an apparatus for controlling an arrangement state of liquid crystals by changing an electric field generated by a potential difference between electrodes facing each other, and forming an image by adjusting light transmittance according to the arrangement state of liquid crystals.

Such a liquid crystal display device includes a liquid crystal panel. The liquid crystal panel includes a thin film transistor substrate 1 on which a thin film transistor is formed, a color filter substrate (not shown) and a thin film transistor substrate 1 and a color filter substrate (not shown) attached to the thin film transistor substrate 1. It includes a liquid crystal layer (not shown) positioned between.

The thin film transistor substrate 1 includes a plurality of gate lines 2 arranged in parallel with each other, a common voltage line 3 formed at the same time as the gate lines 2, and a pixel area crossing the gate lines 2. A data line 4 and a pixel electrode 5 formed in the pixel region. The gate line 2 includes a gate line 2a extending in one direction and a gate electrode 2b branched from the gate line 2a, and the data line 4 crosses the gate line 2a. A source electrode 4b and a drain electrode 4c, which are branched from the line 4a and the data line 4a, are separated on both sides of the gate electrode 2b.

Among them, the common voltage line 3 is formed in each pixel region along the edge of the pixel region, and is substantially formed in a shape like 'U'. Each common voltage line 3 is interconnected in the extending direction of the gate line 2. That is, as shown in FIG. 1, the common voltage line 3 is provided on both sides of the data line 4a centering on the data line 4a, and is mutually connected. The common voltage line 3 overlaps the pixel electrode 5 to form a storage capacitance.

Meanwhile, a black matrix 8 having a shape as shown in FIG. 2 is formed on a color filter substrate (not shown) facing the thin film transistor substrate 1 provided as described above. The black matrix 8 has a matrix shape that may cover all of the gate wiring 2, the common voltage line 3, and the data wiring 4 of the thin film transistor substrate 1 to prevent light leakage between adjacent pixels. Is formed.

Here, the black matrix 8 formed in the region corresponding to the data line 4a has a thick width d2 so as to cover both the data line 4a and the common voltage line 3 formed on both sides of the data line 4a. It is prepared to have. In particular, the thin film transistor substrate 1 having the above-described structure is formed so that the overlap region of the common voltage line 3 and the data line 4a is minimized in order to minimize the interference between the common voltage line 3 and the data line 4a. do.

Accordingly, the common voltage line 3 is formed to be spaced apart from the data line 4a by a predetermined interval, which leads to an increase in the distance d1 from the common voltage line 3 on one side to the common voltage line 3 on the other side. . This leads to an increase in the width d2 of the black matrix 8, resulting in a problem that the aperture ratio is reduced in the pixel. In addition, such a structure may result in an increase in the area blocking light, thereby reducing the overall luminance. In addition, as shown in FIG. 3, light may flow into the space between the common voltage line 3 and the data line 4a, which passes through the uncontrolled liquid crystal layer 7. Accordingly, there is a problem that light leakage occurs.

It is an object of the present invention to provide a liquid crystal panel in which the aperture ratio is improved and the light leakage is reduced according to the present invention.

In addition, another object of the present invention is to provide a method of manufacturing a liquid crystal panel with improved aperture ratio and reduced light leakage.

The above object is, according to the present invention, a liquid crystal panel comprising a first substrate and a second substrate bonded to each other, and a liquid crystal layer positioned between the first substrate and the second substrate, wherein the first substrate comprises: A plurality of gate wirings arranged side by side on one insulating substrate; A plurality of common voltage lines arranged adjacent to the gate wiring along the extending direction of the gate wiring; A plurality of data lines defining a plurality of pixel regions crossing the gate lines; And a plurality of pixel electrodes respectively formed in the pixel region and partially overlapping the common voltage line, wherein one region of the data line is widened and overlaps the pixel electrode. .

Here, the gate wiring includes a gate line and a gate electrode constituting the thin film transistor as part of the gate line, and the data wiring includes a data line crossing the gate line, a source electrode and a gate electrode branched from the data line and extending onto the gate electrode. And a drain electrode separated from the source electrode, wherein the data line has a first region in which the source electrode is branched, and a width thereof is extended compared to the first region to overlap the pixel electrode to form storage capacitance. It may include a second area that is present.

The second region of the data line may be formed in a region other than the thin film transistor, the gate wiring, and the common voltage line.

In addition, the second substrate includes a black matrix formed in a matrix shape on the second insulating substrate in correspondence with the gate wiring, the data wiring and the thin film transistor, and the width of the black matrix corresponding to the data wiring is equal to the width of the data line. It may be substantially equal to the width of the two areas.

Here, the common voltage line may extend along one side of the data line along the data line, and the second region of the data line may extend in the other direction compared to the first region.

The gate wiring and the common voltage line may be formed of the same material at the same time.

Another object of the present invention is to form a plurality of gate wirings, which are arranged in parallel with each other on a first insulating substrate according to the present invention; Forming a plurality of common voltage lines along the extending direction of the gate wiring so as to be adjacent to the gate wiring; Defining a plurality of pixel regions crossing the gate wirings, and forming a plurality of data wirings so that the width of one region is expanded; And forming a plurality of pixel electrodes in the pixel region such that a part of the common voltage line and a width of the common voltage line overlap one region of the extended data line.

The method may further include forming a thin film transistor at an intersection point of the gate line and the data line, wherein the data line includes a data line extending in one direction, a source electrode and a drain electrode branched from the data line to form the thin film transistor. The data line may include a first region in which the source electrode is branched, and a second region in which a width thereof is extended compared to the first region and overlaps the pixel electrode to form storage capacitance.

The data line may be formed so that the second region is formed in a region other than the thin film transistor, the gate wiring, and the common voltage line.

In addition, the common voltage line may be branched to extend along the data line on one side of the data line, and the second region of the data line may be formed to extend in the other direction compared to the first region.

The gate wiring and the common voltage line may be formed of the same material at the same time.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail. In the following, a film is formed (located) on another layer, not only when two films are in contact with each other but also when another film is between two layers. It also includes the case where it exists.

4 is a layout view of a thin film transistor substrate according to a first embodiment of the present invention, FIG. 5 is a plan view illustrating a black matrix formed on a color filter substrate according to the first embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along VI-VI.

In general, as shown in FIG. 6, the liquid crystal display device includes a thin film transistor substrate 100 having a thin film transistor T as a switching and driving element for controlling and driving the operation of each pixel. The liquid crystal panel 10 includes a color filter substrate 200 that is opposite to the thin film transistor substrate 100 and a liquid crystal layer 300 between the substrates 100 and 200.

First, as illustrated in FIGS. 4 and 6, the thin film transistor substrate 100 includes a first insulating substrate 110 and a plurality of gate wirings 120 formed in a matrix form on the first insulating substrate 110. And the plurality of data lines 160, the plurality of common voltage lines 130 disposed adjacent to the gate line 120 along the extending direction of the gate line 120, the gate line 120 and the data line ( A thin film transistor (TFT) T, which is a switching element formed at an intersection point of 160, and a pixel electrode 180 connected to the thin film transistor T are included.

As the first insulating substrate 110, a substrate made of an insulating material such as glass, quartz, ceramic, or plastic may be used.

The gate wiring 120 is formed on the first insulating substrate 110. The gate line 120 includes a gate line 121 extending in the horizontal direction and a gate electrode 123 constituting the thin film transistor T as part of the gate line 121. As illustrated in FIG. 3, the gate electrode 123 may be branched from the gate line 121, or, unlike the illustrated example, may have a width extending from the gate line 121.

The common voltage line 130 is formed on the same layer as the gate line 120. The common voltage line 130 is disposed adjacent to the gate line 120 in the extending direction of the gate line 120. The common voltage line 130 overlaps the pixel electrode 180 to be described later to form storage capacitance. A constant common voltage Vcom is applied to the common voltage line 130. The common voltage line 130 is simultaneously formed of the same material as the gate line 120, but is physically separated.

The gate wiring 120 and the common voltage line 10 may be a metal single layer or multiple layers, and may include molybdenum, manganese, tungsten, nickel, aluminum, chromium, gold, silver, alloys thereof, and the like. The reason for forming the gate wiring 120 and the common voltage line 130 in multiple layers is to compensate for the disadvantages of each metal or alloy and to obtain desired physical properties.

On the first insulating substrate 110, a gate insulating layer 140 made of silicon nitride (SiNx), silicon oxide (SiO 2), or the like covers the gate wiring 120.

As illustrated in FIG. 6, a semiconductor layer 150 made of a semiconductor such as amorphous silicon or crystalline silicon is formed on the gate insulating layer 140 of the gate electrode 123, and the semiconductor layer 150 is formed on the semiconductor layer 150. An ohmic contact layer 155 made of a material such as n + hydrogenated amorphous silicon in which silicide or n-type impurities are heavily doped is formed. The ohmic contact layer 155 is removed from the channel portion between the source electrode 163 and the drain electrode 165.

The data line 160 is formed on the ohmic contact layer 155 and the gate insulating layer 140. The data line 160 may also be a single layer or multiple layers of a metal layer. The data line 160 is a branch of the data line 161 and the data line 161 which are formed in the vertical direction and cross the gate line 121 to form a pixel, and which extends to the upper portion of the ohmic contact layer 155. The drain electrode 165 is separated from the electrode 163 and the source electrode 163 and is formed on the resistive contact layer 155 opposite to the source electrode 163.

The data lines 160 according to the present invention are formed to have different widths. Specifically, as shown in FIG. 4, the data line 161 according to the present invention includes a first region b and a width d3 larger than the width d5 of the first region b. It consists of two areas (a). In other words, the data line 161 according to the present invention has an extended width in one region (second region). The first region b of the data line 161 is a portion adjacent to the region where the source electrode 163 is branched, and the second region a is a portion other than the first region b. That is, the second region a of the data line 161 is formed in a region other than the thin film transistor T, the gate wiring 120, and the common voltage line 130. In addition, the second region a having a width d3 extended to overlap the pixel electrode 180 to be described later to form storage capacitance together with the pixel electrode 180.

The data line 160 is covered by the passivation layer 170. A drain contact hole 171 exposing the drain electrode 165 is formed in the passivation layer 170. Here, the protective film 151 may be made of an inorganic material such as SiNx, SiO2, or may be made of an organic material such as an acrylic polymer.

The pixel electrode 180 is formed on the passivation layer 170. The pixel electrode 180 is generally made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 180 is electrically connected to the drain electrode 165 through the drain contact hole 171. The pixel electrode 180 according to the present invention is formed to overlap the second region a and the common voltage line 130 of the data line 161 in the pixel region. In addition, as illustrated in FIG. 4, the pixel electrode 180 may be formed to partially overlap the gate line of an adjacent pixel.

Next, the color filter substrate 200 will be described.

As shown in FIGS. 5 and 6, a black matrix 220 is formed on the second insulating substrate 210. As illustrated in FIG. 5, the black matrix 220 may cover the gate wiring 120 (see FIG. 4), the common voltage line 130 (see FIG. 4), and the thin film transistor T formed on the first substrate 100. It is provided in a matrix shape so that it can be. The width d4 of the black matrix 220 corresponding to the data line 161 is substantially the same as the second area a of the data line 161. The black matrix 220 generally distinguishes between red, green, and blue filters, and serves to block direct light irradiation to the thin film transistor T positioned on the first substrate 100. In addition, the black matrix 220 serves to prevent light leakage between adjacent pixels. The black matrix 220 is usually made of a photosensitive organic material to which black pigment is added. As the black pigment, carbon black or titanium oxide is used.

The color filter layer 230 is formed by repeating red, green, and blue filters with the black matrix 220 as a boundary. The color filter layer 230 serves to impart color to light emitted from the backlight unit (not shown) and passed through the liquid crystal layer 300. The color filter layer 230 is usually made of a photosensitive organic material.

An overcoat layer 240 is formed on the black matrix 220 which is not covered by the color filter layer 230 and the color filter layer 230. The overcoat layer 240 serves to protect the color filter layer 230 while planarizing the color filter layer 230, and an acrylic epoxy material is generally used.

The common electrode 250 is formed on the overcoat layer 240. The common electrode 250 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode 250 directly applies a voltage to the liquid crystal layer 300 together with the pixel electrode 180 of the first substrate 100.

The liquid crystal layer 300 is positioned between the first substrate 100 and the second substrate 200. The liquid crystal layer 300 is composed of a plurality of liquid crystal molecules, and may be in a VA (vertically aligned) mode. However, the present invention is not limited thereto, and various types of liquid crystals may be used.

Hereinafter, effects according to the first embodiment of the present invention will be described with reference to the drawings.

In the thin film transistor substrate 100 according to the present invention, as shown in FIG. 4, the common voltage line 130 is not formed on both sides of the data line 161 as compared with the related art. As a result, the overlapping region between the pixel electrode 180 and the common voltage line 130 is reduced, thereby reducing storage capacitance. In order to solve this problem, in the present invention, the width d3 of the second region a of the data line 161 is extended, and the second region a of the data line 161 is connected to the pixel electrode 180. The storage capacitance was formed by overlapping.

Meanwhile, as illustrated in FIGS. 1 and 2, the common voltage line 3 positioned on both sides of the data line 4a is formed to be spaced apart from the data line 4a by a predetermined distance, and thus, the black matrix 8 may be formed. ) Has been increased to reduce the aperture ratio of the pixel.

However, in the present invention, as shown in FIG. 4, the common voltage line 130 located on both sides of the data line 161 and the space between the data line 161 and the common voltage line 130 are removed to remove black. The width d4 of the matrix 220 was reduced compared to the prior art. That is, the width d3 of the second region a of the data line 161 is the distance d1 from one common voltage line 3 (see FIG. 1) to the common voltage line 3 (see FIG. 1) on the other side. 3), the width d4 of the black matrix 220 is also reduced to improve the overall aperture ratio of the pixel. Accordingly, since the area blocking the light incident from the backlight unit (not shown) is reduced, the amount of light passing through the pixel is increased, thereby increasing the luminance.

In addition, as the separation space between the data line 161 and the common voltage line 130 is removed, light leakage generated by the light flowing into the separation space is prevented.

Hereinafter, a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, only characteristic parts distinguished from the first embodiment will be described and described, and descriptions omitted or summarized will follow the first embodiment and known technology. In addition, for the convenience of description, the same reference numerals are assigned to the same components to be described.

The second embodiment is a modified embodiment of the first embodiment. As shown in FIG. 7, the common voltage line 130 according to the second embodiment extends along the data line 161 on one side of the data line 161, and the second region ( a) is wider in the other direction than the first region b.

With this configuration, the second embodiment has removed the space between the common voltage line 130 and the data line 161 and the common voltage line 130, which existed in the other direction as compared with the prior art, as in the first embodiment. As the width of the black matrix is reduced, the aperture ratio is increased. Meanwhile, one side of the common voltage line 130 is maintained to stably form storage capacitance.

Hereinafter, a manufacturing method of the first substrate 100 according to the first embodiment of the present invention will be described with reference to FIGS. 8A to 8C.

First, as illustrated in FIG. 8A, a gate wiring metal material is deposited on the first insulating substrate 110 by sputtering or the like, and then patterned by a photolithography process using a mask. The gate line 120 including the line 121 and the gate electrode 123 and the common voltage line 130 are simultaneously formed.

Next, although not shown as relief, the three-layer film is stacked by sequentially applying a gate insulating material, a semiconductor material, and an ohmic contact material on the gate electrode 123 and the first insulating substrate 110. Then, the layer of the semiconductor material and the layer of the ohmic contact material are simultaneously photo-etched, and as shown in FIG. 6, the semiconductor layer 150 and the ohmic contact layer (not shown) on the gate insulating layer 140 on the gate electrode 123. 155). The stack of the gate insulating layer 140, the semiconductor layer 150, and the ohmic contact layer 155 may be a known method such as plasma enhanced chemical vapor deposition (PECVD).

Thereafter, as shown in FIG. 8B, the metal material for data wiring is deposited by a method such as sputtering, and then patterned by a photolithography process using a mask to intersect the data line 161 with the gate line 121. A data line including a source electrode 163 connected to the data line 161 and extending to an upper portion of the gate electrode 123, and a drain electrode 165 separated from the source electrode 163 on the gate electrode 123. To form 160.

Here, the data lines 161 according to the present invention are formed to have different widths. Specifically, as shown in FIG. 8B, the data line 161 according to the present invention includes a first region b and a width d3 larger than the width d5 of the first region b. It is formed to have two regions (a). The second region a of the data line 161 may be formed in a region other than the thin film transistor T, the gate wiring 120, and the common voltage line 130. The first region b of the data line 161 is formed in a region other than the second region a.

Meanwhile, in the process of forming the data line 160, the ohmic contact layer 155 is etched and separated into both sides, and the semiconductor layer 140 is exposed to the outside. As a result, the thin film transistor T is completed.

Next, the passivation layer 170 (see FIG. 6) is formed to cover the data line 160, and the passivation layer 170 (see FIG. 6) is patterned to form a drain contact hole 171 (see FIG. 6).

Finally, as shown in FIG. 8C, the conductive material is formed on the passivation layer 151 through sputtering, and then the pixel electrode 180 is formed using a photolithography process or an etching process. The pixel electrode 180 is formed to overlap the second region a of the common voltage line 130 and the data line 161. Also, the gate line 121 is formed to overlap the gate line 121 of the adjacent pixel. The conductive material may be a transparent conductive metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Accordingly, as the overlapping area between the pixel electrode 180 and the common voltage line 130 decreases as compared with the related art, the storage capacitance decreases as compared with the second area a of the data line 161. It is possible to compensate with the storage capacitance formed between the pixel electrodes 180.

Since the method of manufacturing the first substrate 100 described above does not form the common voltage line 130 positioned at both sides of the data line 161, unlike the conventional method, the data line 161 has a relatively smaller width d3. ) Can be formed. That is, the width d3 of the second region a of the data line 161 is the distance d1 from one common voltage line 3 (see FIG. 1) to the common voltage line 3 (see FIG. 1) on the other side. (See 3). Accordingly, in manufacturing the second substrate 200, the width d4 of the black matrix 220 (see FIG. 5) can be made smaller than in the related art. Accordingly, the aperture ratio of the pixel is improved, and the area blocking the light incident from the backlight unit (not shown) is reduced, so that the amount of light passing through the pixel is increased, thereby increasing the luminance.

In addition, as the separation space between the data line 161 and the common voltage line 130 is removed, light leakage generated by the light flowing into the separation space is prevented.

As described above, according to the present invention, there is provided a liquid crystal panel in which the aperture ratio is improved and light leakage is prevented.

In addition, a method of manufacturing a liquid crystal panel in which an aperture ratio is improved and light leakage is prevented is provided.

Claims (11)

A liquid crystal panel comprising a first substrate and a second substrate bonded to each other, and a liquid crystal layer positioned between the first substrate and the second substrate. The first substrate, A plurality of gate wirings arranged side by side on the first insulating substrate; A plurality of common voltage lines arranged adjacent to the gate wiring along an extension direction of the gate wiring; A plurality of data lines crossing the gate lines to define a plurality of pixel regions; And A plurality of pixel electrodes respectively formed in the pixel region and partially overlapping the common voltage line; The liquid crystal panel according to claim 1, wherein one region of the data line is extended to overlap the pixel electrode. The method of claim 1, The gate line includes a gate line and a gate electrode constituting a thin film transistor as part of the gate line, The data line includes a data line crossing the gate line, a source electrode branched from the data line and extending onto the gate electrode, and a drain electrode separated from the source electrode on the gate electrode, The data line includes a first region in which the source electrode is branched, and a second region in which a width thereof is extended compared to the first region and overlaps the pixel electrode to form storage capacitance. A liquid crystal panel characterized by the above. The method of claim 2, And the second region of the data line is formed in a region other than the thin film transistor, the gate wiring, and the common voltage line. The method of claim 2, The second substrate includes a black matrix formed on a second insulating substrate in a matrix shape corresponding to the gate wiring, the data wiring, and the thin film transistor. And a width of the black matrix corresponding to the data line is substantially the same as that of the second area of the data line. The method of claim 2, The common voltage line extends along the data line on one side of the data line. And the second area of the data line is wider in the other direction than the first area. The method of claim 2, And the gate wiring and the common voltage line are formed of the same material at the same time. Forming a plurality of gate wires on the first insulating substrate so as to be arranged in parallel with each other; Forming a plurality of common voltage lines along an extension direction of the gate wiring so as to be adjacent to the gate wiring; Defining a plurality of pixel regions to cross the gate lines, and forming a plurality of data lines to extend a width of one region; And forming a plurality of pixel electrodes in the pixel region so as to overlap a part of the common voltage line and one region of the data line, the width of which is extended. The method of claim 7, wherein Forming a thin film transistor at an intersection point of the gate line and the data line, The data line includes a data line extending in one direction, a source electrode and a drain electrode branched from the data line to form the thin film transistor. The data line includes a first region in which the source electrode is branched, and a second region in which a width thereof is extended compared to the first region and overlaps the pixel electrode to form storage capacitance. Method for producing a liquid crystal panel. The method of claim 8, And the data line is formed such that the second region is formed in a region other than the thin film transistor, the gate wiring, and the common voltage line. The method of claim 8, The common voltage line is branched to extend along the data line on one side of the data line. And the second region of the data line is formed to extend in a width direction in the other direction compared with the first region. The method of claim 8, And the gate line and the common voltage line are formed of the same material at the same time.

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