CN104049430B - Array substrate, display device and manufacturing method of array substrate - Google Patents
Array substrate, display device and manufacturing method of array substrate Download PDFInfo
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- CN104049430B CN104049430B CN201410274667.0A CN201410274667A CN104049430B CN 104049430 B CN104049430 B CN 104049430B CN 201410274667 A CN201410274667 A CN 201410274667A CN 104049430 B CN104049430 B CN 104049430B
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Abstract
The invention discloses an array substrate, a display device and a manufacturing method of the array substrate. According to the array substrate, the display device and the manufacturing method of the array substrate, the array substrate is provided with pixel regions defined by first common electrode wires and second common electrode wires; scanning lines and data lines are arranged on central lines of the pixel regions, and active elements are formed in intersection regions of the scanning lines and the data lines; pixel electrodes are connected to storage electrodes and common electrodes of a first metal layer through contact holes to form storage capacitors; after the pixel electrodes are formed, a black organic insulating layer is formed on the array substrate; through the halftone mask plate photoetching process or the gray tone mask plate photoetching process, a first height pattern and a second height pattern are formed, wherein the first height pattern is a supporting post, and the second height pattern is a black matrix. The display device further comprises a color filter substrate and a display medium clamped between the array substrate and the color filter substrate. Through the manufacturing method, one manufacturing process can be omitted, the process cost is lowered, and the percentage of pass of products is increased.
Description
Technical field
The present invention relates to display technology field, more particularly, to a kind of array base palte, display device and its manufacture method.
Background technology
As shown in figure 1, Thin Film Transistor-LCD (TFT-LCD) is by array base palte 11, colored filter substrate
13 and the liquid crystal 13 that riddles between this two pieces of substrates be collectively forming, backlight 14 is incident from the side of array base palte 11, in battle array
Post array side Polarizer 115 and colored filter lateral deviation tabula rasa 124 on row substrate 11 and colored filter substrate respectively.Array
Gate metal layer 111, gate insulator, semiconductor layer 112, the insulation of Source and drain metal level 113, source and drain are generally comprised on substrate 11
The 5-6 film-forming process such as layer, organic insulator, pixel electrode layer 114；Colored filter side includes black-matrix layer 121, color blocking
122 (green color blocking layer, red color resistance layer, blue color blocking layer) of layer, common electrode layer 123, support column layer (hereinafter referred to as PS)
As 6 film-forming process.
Many one-time process engineerings, will increase the probability of the unqualified generation of panel.In addition, after film forming is completed, it is colored
The Anawgy accuracy of filter sheet base plate and array base palte can also affect the qualification rate of product, and laminating is bad to cause product light leak.
The content of the invention
Shared by effectively merging production process and material, it is possible to reduce bad reduces cost.By color membrane substrates and battle array
Part film layer is shared on row substrate, it is possible to reduce membrane formation times, material-saving, reduces cost.
One embodiment of the invention provides a kind of array base palte, and it includes：One substrate, is configured with successively thereon the first metal
Layer, metal dielectric layer, semiconductor layer, second metal layer, protection insulating barrier, transparent organic insulating film, pixel electrode layer, black have
Machine insulating barrier；Wherein, the first metal layer, it includes：Multi-strip scanning line, each scan line is arranged on each pixel region
Horizontal central line on, and with a plurality of data lines setting intersected with each other；Multiple storage electrodes, are configured at the lower section of pixel electrode,
And it is Chong Die with the view field of the second public electrode with the first public electrode, and the storage electrode is by the second contact hole and the picture
Plain electrode is electrically connected with；Second metal layer, it includes：A plurality of first public electrode wire, with being uniformly distributed the discontinuous of gap
Distributing line；A plurality of second public electrode wire, with a plurality of first public electrode wire interconnection pixel region array is surrounded；It is a plurality of
Data wire, each data wire is arranged on the median vertical line of each pixel region, and through to should the first common electrical
The gap of polar curve；Active member, is arranged at each data wire with each scan line intersection region；Multiple pixel electrodes,
Each pixel electrode is electrically connected with by the first contact hole with the active member；Black organic insulator, forms the first height
Pattern and the second elevational pattern, wherein, the first elevational pattern is support column, and the second elevational pattern is black matrix".
Preferably, first elevational pattern and second elevational pattern are by intermediate tone mask version or gray tone mask plate
Exposure is formed.
Preferably, the black matrix" covers the scan line, the storage electrode, the data wire, first and second public electrode
Line, the active member；The support column is evenly arranged in the scan line with data wire intersection region and/or first and second public power
Polar curve intersection region.
Present invention also offers a kind of display device, it includes the array base palte described in above-described embodiment, also including a pair
Substrate is put, the substrate is the glass substrate for being coated with ITO；Display medium is folded between the array base palte and the counter substrate
Layer.
Present invention also offers a kind of manufacture method of array base palte as described in as described in including above-described embodiment, it includes
Following steps：
A. the first metal layer is formed on the substrate, and it includes scan line and pixel storage electrode；
B. semiconductor figure is formed, semi-conducting material is non-crystalline silicon, polysilicon or metal oxide；
C. source, drain electrode, data wire, first and second public electrode wire are formed；
D. protection insulating barrier, transparent organic insulating film are formed；
E. contact hole is formed；
F. pixel electrode is formed；
G. black organic insulator is formed, by intermediate tone mask version or gray tone mask plate, the first height map is formed
Case and the second elevational pattern, wherein, the first elevational pattern is support column, and the second elevational pattern is black matrix".
Preferably, the protection insulating barrier be SiO2, SiNx or Al2O3, and the thickness of the protection insulating barrier be 1000A-
4000A, the thickness of the organic insulator is in 1um-3um.
The present invention compared with prior art, has an advantage in that：By arranging black organic insulation, while forming black
Matrix and support column, can effectively reduce the technological process of liquid crystal panel, the qualification rate of product be improved, additionally, due to black square
Battle array is located on array base palte, and colored filter substrate and array base palte do not have aligning accuracy to require, therefore, the qualification rate of product
Can be further improved.
Description of the drawings
Fig. 1 is the generalized section of display device in prior art
Fig. 2 is the structural representation of display device of the present invention；
Fig. 3 is the dot structure schematic diagram in Fig. 2 of the present invention on array base palte；
Fig. 4 (a) is the plan of the first metal layer pattern of dot structure in Fig. 3 of the present invention；
Fig. 4 (b) is the profile in the first metal layer pattern AA ' directions of dot structure in Fig. 3 of the present invention；
Fig. 5 (a) is the plan of the semiconductor layer pattern of dot structure in Fig. 3 of the present invention；
Fig. 5 (b) is the profile in the semiconductor layer pattern AA ' directions of dot structure in Fig. 3 of the present invention；
Fig. 6 (a) is the plan of the second metal layer pattern of dot structure in Fig. 3 of the present invention；
Fig. 6 (b) is the profile in the second metal layer pattern AA ' directions of dot structure in Fig. 3 of the present invention；
Fig. 7 (a) is the plan of the contact hole pattern of dot structure in Fig. 3 of the present invention；
Fig. 7 (b) is the profile in the contact hole pattern AA ' directions of dot structure in Fig. 3 of the present invention；
Fig. 8 (a) is the plan of the pixel electrode pattern of dot structure in Fig. 3 of the present invention；
Fig. 8 (b) is the profile in the pixel electrode pattern AA ' directions of dot structure in Fig. 3 of the present invention；
Fig. 9 (a) is the plan of the black organic insulation layer pattern of dot structure in Fig. 3 of the present invention；
Fig. 9 (b) is the profile in the black organic insulation layer pattern AA ' directions of dot structure in Fig. 3 of the present invention；
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Fig. 2 is the structural representation of display device of the present invention.As shown in Fig. 2 the present invention provides a kind of display device, its bag
Include：Array basal plate 21, is sequentially distributed the first metal layer, the grid of the formation of scan line 211, storage electrode on the array base palte 21
Pole insulating barrier 212, semiconductor layer 213, the second metal layer formed by first and second public electrode wire, source-drain electrode, data wire 214
Pattern, protection insulating barrier 215, transparent organic insulating film 216, contact hole 217, pixel electrode 218, black organic insulator
219；Also include a counter substrate 22, such as colored filter substrate, thereon distributing transparent ito surface electrode 221.It is organic absolutely in black
In edge layer, the first elevational pattern and the second elevational pattern are formed, wherein, the first elevational pattern is support column, the second elevational pattern
For black matrix".
Fig. 3 is the dot structure schematic diagram in Fig. 2 of the present invention on array base palte.As shown in figure 3, the present invention is also provided for a moment
Row substrate, it includes：One substrate (not shown), be configured with successively thereon the first metal layer, metal dielectric layer, semiconductor layer,
Two metal levels, protection insulating barrier, transparent organic insulating film, pixel electrode layer, black organic insulator；Wherein, the first metal layer,
It includes：Multi-strip scanning line 31, each scan line is arranged on the horizontal central line of each pixel region, and with a plurality of number
According to line setting intersected with each other；Multiple storage electrodes 32, are configured at the lower section of pixel electrode, and with the first public electrode and second
The view field of public electrode overlaps to form storage electrode, and the storage electrode 32 by the second contact hole and the pixel electrode electricity
Property connection；Second metal layer, it includes：A plurality of first public electrode wire 35, with the discontinuous distributing line for being uniformly distributed gap；
A plurality of second public electrode wire 35, with a plurality of first public electrode wire interconnection pixel region array is surrounded；Many datas
Line 34, each data wire is arranged on the median vertical line of each pixel region, and through to should the first public electrode
The gap of line；Active member, it is included comprising semiconductor layer 33, source electrode 34, drain electrode 36, and is arranged at each data wire 34
With each intersection region of scan line 31；Multiple pixel electrodes 38, each pixel electrode 38 is by the first contact hole 37 and is somebody's turn to do
Active member is electrically connected with；Black organic insulator, forms the first elevational pattern and the second elevational pattern, wherein, the first height
Pattern is support column 30, and the second elevational pattern is black matrix" 39.
Dot structure provided as an embodiment, the embodiment and preparation method thereof only exists with the difference of above-described embodiment
In：In the lower section of the pixel electrode, the first area of the storage electrode and first public electrode wire and second common electrical
The view field of polar curve partly overlaps to form storage capacitance.
Difference of the dot structure provided as a preferred embodiment, the embodiment and preparation method thereof with above-described embodiment
It is only that：In the lower section of the pixel electrode, the first area of the storage electrode and first public electrode are second public with this
The completely overlapped formation storage capacitance of view field of electrode.
The present invention surrounds to be formed by the public electrode wire in the configuration shading of four borders of pixel, can greatly improve picture
The aperture opening ratio of element.The storage capacitance that storage electrode is overlapped to form with public electrode wire can be when upper lower metal layer shifts certainly
The size of dynamic compensation storage capacitance.
Wherein, first elevational pattern and second elevational pattern are exposed by intermediate tone mask version or gray tone mask plate
Light is formed.
Wherein, the black matrix" cover the scan line, the storage electrode, the data wire, first and second public electrode wire,
The active member；The support column is evenly arranged in the scan line with data wire intersection region and/or the first and second public power polar curve
Intersection region.
In the prior art, the black-matrix layer on colored filter substrate is needed using two mask plate twice with PS layers
Manufacturing process is formed, and adopts array base palte of the present invention, forms black simultaneously by arranging black organic insulation layer pattern
Color matrix layer and support column layer, therefore, it can reduce by mask plate technique with together with, so as to save process costs.In addition, this
The black organic insulator is invented in addition to the interception for playing black matrix", also as organic insulator, completely cuts off pixel
Electricity interference between electrode and metal wire.
The preparation method that the present invention provides array base palte described in above-described embodiment, it is comprised the following steps that：
Step a, the sputtering on array base palte 40 forms the first metal layer, and the first metal layer can be Ti, Al, Cu, Mo etc.
Metal or alloy, the thickness of the first metal layer isUsing first mask plate, by the coating of photoresist,
The techniques such as exposure, development, etching form the pattern as shown in Fig. 4 (a).In Fig. 4 (a), middle pattern is scan line 41, left
Inferior horn is storage electrode 42 with the pattern in the upper right corner.Shown in cross-section structure such as Fig. 4 (b) of correspondence Fig. 4 (a) dotted line AA '.
Step b, on the pattern of the first metal layer, with chemical vapor deposition method transparent gate insulator 50 is formed.
In the disposed thereon semiconductive thin film of gate insulator 50, semi-conducting material can be non-crystalline silicon, polysilicon or oxide half
Conductor etc., thickness isExtremelyUsing second mask plate, by the coating of photoresist, exposure, development, etching etc.
Technique forms the pattern as shown in Fig. 5 (a).In Fig. 5 (a), the pattern above scan line is semiconductor channel layer 51.Corresponding diagram
Shown in cross-section structure such as Fig. 5 (b) of 5 (a) dotted line AA '.
Step c, on the pattern of semiconductor layer, sputtering forms second layer metal film.Second metal layer can for Ti,
The metals such as Al, Cu, Mo or alloy, the thickness of Source and drain metal level isUsing the 3rd mask plate, by photoetching
The techniques such as coating, exposure, development, the etching of glue form the pattern as shown in Fig. 6 (a).In Fig. 6 (a), what centre was run through up and down
Pattern is data wire 61, and the pattern that left and right is run through up and down is public electrode wire main line 63, and left and right extends on public electrode wire main line
Be public electrode wire subordinate line 64.In data wire 61 and the region of scanning line overlap, form TFT in the top of semiconductor layer and open
Close.The grid of TFT switch is scan line, and the source electrode of TFT switch is data wire 61, and the drain electrode 62 of TFT switch is same with data wire 61
Layer.If metal wire upper strata is Al, need to be designed as on metal at contact hole U-shaped.The cross-section structure of correspondence Fig. 6 (a) dotted line AA '
As shown in Fig. 6 (b).
Step d, on the pattern of second metal layer, with chemical vapor deposition method transparent protection insulating barrier 70 is formed.
Protection insulating barrier can be SiO2, SiNx or Al2O3 etc., and the thickness for protecting insulating barrier isIt is exhausted in protection
The top of edge layer 70 is coated with the organic insulating film 71 of layer of transparent.The thickness of organic insulating film 71 is 2um.Using the 4th mask
Version, by techniques such as the coating of photoresist, exposure, development, etchings the pattern as shown in Fig. 7 (a) is formed.In Fig. 7 (a), TFT
Contact hole 72 above the drain electrode of switch left and right is used to connect pixel electrode；Up and down the contact hole 73 above storage electrode is used to connect
Pixel electrode.It is connected with pixel electrode simultaneously by contact hole 72 and contact hole 73, the drain signal of TFT switch passes to picture simultaneously
Plain electrode and storage electrode.Shown in cross-section structure such as Fig. 7 (b) of correspondence Fig. 7 (a) dotted line AA '.
Step e, in organic film and the top of contact hole, sputtering forms transparent conductive film.The thickness of ito thin film isExtremelyUsing the 5th mask plate, such as Fig. 8 is formed by techniques such as the coating of photoresist, exposure, development, etchings
Pattern shown in (a).In Fig. 8 (a), transparent conductive film is covered in the top in pixel openings area, forms pixel electrode 81
, there is the overlapping region of 2um in surrounding and the public electrode wire of pixel electrode 81 in region.The section of correspondence Fig. 8 (a) dotted line AA '
Shown in structure such as Fig. 8 (b).
Step f, in the top of pixel electrode the organic insulating film of one layer of black is coated with.The thickness of the organic insulating film of black
For 0.5～2um.Using the 6th mask plate, the pattern as shown in Fig. 9 (a) is formed by techniques such as exposure, developments.4th
Mask plate is intermediate tone mask version or gray tone mask plate, and using intermediate tone mask version or gray tone mask plate height is formed
The organic insulating film pattern of different black.In Fig. 9 (a), TFT devices top is the of a relatively high support column 91 of thickness, its
The top of his metal wire is the relatively low black matrix" 92 of thickness.Cross-section structure such as Fig. 9 (b) of correspondence Fig. 9 (a) dotted line AA '
It is shown.Dot structure provided as another embodiment, the embodiment and preparation method thereof only exists with the difference of above-described embodiment
In：The storage electrode is configured at the upper left corner and the lower right corner of first public electrode wire and the second public electrode wire view field
First area, and the storage electrode configures second bump region in the non-projection lap, and second contact is formed thereon
Hole, for the equipotential link between the pixel electrode.
The above, the only specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, all should contain
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be defined by the scope of the claims.
Claims (9)
1. a kind of array base palte, it includes：
One substrate, is configured with successively thereon the first metal layer, metal dielectric layer, semiconductor layer, second metal layer, protection insulation
Layer, transparent organic insulating film, pixel electrode layer, black organic insulator；
Wherein, the first metal layer, it includes：Multi-strip scanning line and multiple storage electrodes；
Multi-strip scanning line, each scan line is arranged on the horizontal central line of each pixel region, and with a plurality of data lines that
This is arranged in a crossed manner；
Multiple storage electrodes, are configured at the lower section of pixel electrode, and with the first public electrode and the second public electrode view field
Overlap, and the storage electrode is electrically connected with by the second contact hole with the pixel electrode；
Second metal layer, it includes：A plurality of first public electrode wire, a plurality of second public electrode wire, a plurality of data lines；
A plurality of first public electrode wire, with the discontinuous distributing line for being uniformly distributed gap；
A plurality of second public electrode wire, with a plurality of first public electrode wire interconnection pixel region array is surrounded；
A plurality of data lines, each data wire is arranged on the median vertical line of each pixel region, and through to should
The gap of one public electrode wire；
Active member, is arranged at each data wire with each scan line intersection region；
Multiple pixel electrodes, each pixel electrode is electrically connected with by the first contact hole with the active member；
The storage electrode is configured at the upper left corner and bottom right of first public electrode wire and the second public electrode wire view field
The first area at angle, and the storage electrode configures second bump region in the non-projection lap, forms thereon this and second connects
Contact hole, for the equipotential link between the pixel electrode；
Black organic insulator, is configured at the pixel electrode top, and forms the first elevational pattern and the second elevational pattern, its
In, the first elevational pattern is support column, and the second elevational pattern is black matrix".
2. a kind of array base palte, it includes：
One substrate, is configured with successively thereon the first metal layer, metal dielectric layer, semiconductor layer, second metal layer, protection insulation
Layer, transparent organic insulating film, pixel electrode layer, black organic insulator；
Wherein, the first metal layer, it includes：Multi-strip scanning line and multiple storage electrodes；
Multi-strip scanning line, each scan line is arranged on the horizontal central line of each pixel region, and with a plurality of data lines that
This is arranged in a crossed manner；
Multiple storage electrodes, are configured at the lower section of pixel electrode, and with the first public electrode and the second public electrode view field
Overlap, and the storage electrode is electrically connected with by the second contact hole with the pixel electrode；
Second metal layer, it includes：A plurality of first public electrode wire, a plurality of second public electrode wire, a plurality of data lines；
A plurality of first public electrode wire, with the discontinuous distributing line for being uniformly distributed gap；
A plurality of second public electrode wire, with a plurality of first public electrode wire interconnection pixel region array is surrounded；
A plurality of data lines, each data wire is arranged on the median vertical line of each pixel region, and through to should
The gap of one public electrode wire；
Active member, is arranged at each data wire with each scan line intersection region；
Multiple pixel electrodes, each pixel electrode is electrically connected with by the first contact hole with the active member；
The storage electrode is configured at the lower left corner of first public electrode wire with the second public electrode wire view field and upper right
Angle first area, and the storage electrode configures the second bump region in the non-projection lap, and second contact is formed thereon
Hole, for the equipotential link between the pixel electrode；
Black organic insulator, is configured at the pixel electrode top, and forms the first elevational pattern and the second elevational pattern, its
In, the first elevational pattern is support column, and the second elevational pattern is black matrix".
3. the array base palte as described in claim 1 or 2, wherein, first elevational pattern and second elevational pattern pass through
Intermediate tone mask version or gray tone mask plate expose to be formed.
4. the array base palte as described in claim 1 or 2, wherein, the black matrix" cover the scan line, the storage electrode,
The data wire, first and second public electrode wire, the active member；The support column is evenly arranged in the scan line and hands over data wire
Fork region and/or the first and second public power polar curve intersection region.
5. array base palte as claimed in claim 1 or 2, it is characterised in that：In the lower section of the pixel electrode, the storage electrode
The first area partly overlaps to form storage capacitance with first public electrode wire with the view field of second public electrode wire.
6. array base palte as claimed in claim 1 or 2, it is characterised in that：In the lower section of the pixel electrode, the storage electrode
The first area and first public electrode and the completely overlapped formation storage capacitance of view field of second public electrode.
7. a kind of display device, it includes the array base palte as described in claim 1 or 2, also including a counter substrate, the base
Plate is the glass substrate for being coated with ITO；Display dielectric layer is folded between the array base palte and the counter substrate.
8. a kind of manufacture method of array base palte as claimed in claim 1 or 2, it is comprised the following steps：
A. the first metal layer is formed on the substrate, and it includes scan line and pixel storage electrode；
B. semiconductor figure is formed, semi-conducting material is non-crystalline silicon, polysilicon or metal oxide；
C. source, drain electrode, data wire, first and second public electrode wire are formed；
D. protection insulating barrier, transparent organic insulating film are formed；
E. contact hole is formed；
F. pixel electrode is formed；
G. form black organic insulator, by intermediate tone mask version or gray tone mask plate, formed the first elevational pattern and
Second elevational pattern, wherein, the first elevational pattern is support column, and the second elevational pattern is black matrix".
9. the manufacture method of the array base palte as described in claim 8, wherein, the protection insulating barrier be SiO2, SiNx or
Al2O3, and the thickness of the protection insulating barrier isThe thickness of the black organic insulator is in 1um-3um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410274667.0A CN104049430B (en) | 2014-06-18 | 2014-06-18 | Array substrate, display device and manufacturing method of array substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410274667.0A CN104049430B (en) | 2014-06-18 | 2014-06-18 | Array substrate, display device and manufacturing method of array substrate |
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| Publication Number | Publication Date |
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| CN104049430A CN104049430A (en) | 2014-09-17 |
| CN104049430B true CN104049430B (en) | 2017-04-19 |
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| CN104280959B (en) * | 2014-09-30 | 2018-07-10 | 南京中电熊猫液晶显示科技有限公司 | Dot structure, display panel and its manufacturing method |
| CN104576655B (en) * | 2014-12-01 | 2017-07-18 | 深圳市华星光电技术有限公司 | A kind of COA substrates and preparation method thereof |
| CN104485349B (en) * | 2014-12-26 | 2017-08-25 | 昆山工研院新型平板显示技术中心有限公司 | Rimless display screen device |
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