CN101350330A - Thin-film transistor array substrate and manufacturing method thereof - Google Patents
Thin-film transistor array substrate and manufacturing method thereof Download PDFInfo
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- CN101350330A CN101350330A CNA200810042574XA CN200810042574A CN101350330A CN 101350330 A CN101350330 A CN 101350330A CN A200810042574X A CNA200810042574X A CN A200810042574XA CN 200810042574 A CN200810042574 A CN 200810042574A CN 101350330 A CN101350330 A CN 101350330A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
Abstract
The invention discloses a thin film transistor array base-plate and a method for the preparation thereof, the method comprises the following steps: orderly forming a first metallic layer, a grid insulation layer, an active layer, an ohmic contact layer, a second metallic layer and a transparent conducting layer on the base-plate, forming a grid electrode and a grid electrode jointing pad on the first metallic layer, forming a source electrode, a drain and a data jointing pad on the second metallic layer, and forming a pixel electrode and a transparent electrode which is electrically connected with the grid electrode jointing pad and the data jointing pad on the transparent conducting layer. The thin film transistor array base-plate and the method for the preparation thereof provided by the invention are characterized in that the number of light shields can be reduced to three and the cost can be reduced through connecting a discontinuous grid electrode wire and a discontinuous data wire by the transparent electrode and the jointing pads, furthermore, since the exposure frequency is reduced, thereby the error between each of exposure is reduced, and the yield and the rate of finished products are improved.
Description
Technical field
The present invention relates to a kind of LCD device array substrates and manufacture method thereof, relate in particular to a kind of thin-film transistor array base-plate and manufacture method thereof.
Background technology
(liquid crystal display is a kind of flat-panel screens that is widely used most at present LCD) to LCD, has low-power consumption, external form is thin, in light weight and feature such as low driving voltage.Generally speaking, the viewing area of LCD comprises a plurality of subpixel area, each subpixel area is generally two gate line (gate line, claim scan line again) intersect defined rectangle or other shape area with two data wires (data line), be provided with thin-film transistor (TFT) and pixel electrode in it, thin-film transistor serves as switch element.
Yet in TFT-LCD, the manufacturing process complexity of thin-film transistor array base-plate, because in manufacture process, relate to the semiconductor technology processing procedure, need a plurality of mask process, therefore when making thin-film transistor, one of most important consideration is exactly to reduce manufacturing technology steps, and then reduces cost of manufacture.Particularly, employed light shield cost is higher in manufacturing process, therefore if can reduce the light shield number, then can effectively reduce manufacturing cost.The manufacturing technology of TFTLCD array base palte has experienced from seven road light shield technical developments, five road light shields up till now, the evolution of four road light shield technology.Yet in order to simplify processing step and to save manufacturing cost, those skilled in the art still expect to reach with number of optical mask still less the same usefulness of thin-film transistor.
Summary of the invention
Technical problem to be solved by this invention provides a kind of thin-film transistor array base-plate and manufacture method thereof, can effectively reduce the light shield number of times, thereby simplified manufacturing technique, reduces manufacturing cost.
The present invention solves the problems of the technologies described above the manufacture method that the technical scheme that adopts provides a kind of thin-film transistor array base-plate, may further comprise the steps: a substrate is provided, and form the first metal layer, gate insulation layer, active layer, ohmic contact layer, second metal level on this substrate, be coated with photoresist then, wherein said the first metal layer has grid connection pad district and storage capacitors district, described active layer has thin-film transistor channel region, and described second metal level has data connection pad district, thin-film transistor source area and drain region;
Utilize first light shield to form one first photoresist pattern, the photoresist layer that wherein covers described data connection pad district, thin-film transistor source area and drain region has first height, the photoresist that covers described thin-film transistor channel region has second height, the photoresist layer that covers described grid connection pad district and storage capacitors district has the 3rd height, and this first height greater than second height greater than the 3rd highly;
With this first photoresist pattern is mask, removes this second metal level, active layer, ohmic contact layer, gate insulation layer and the first metal layer of part;
Remove the segment thickness of this first photoresist pattern,, form grid and storage capacitors through etching to expose by the 3rd height grid connection pad district and storage capacitors district that photoresist layer covered;
Continue to remove the segment thickness of this first photoresist pattern,, remove second metal level of this channel region and ohmic contact layer to form raceway groove to expose by the second height thin-film transistor channel region that photoresist layer covered;
Continue to remove the segment thickness of this first photoresist pattern, to expose by the source electrode of the first height thin-film transistor that photoresist layer covered, drain electrode and data connection pad;
Utilize one second light shield to form passivation layer, after exposure, development, etching, expose grid connection pad and data connection pad;
Utilize one the 3rd light shield to form pixel electrode, and a transparency electrode is on described exposure grid connection pad, a transparency electrode is on described exposure data connection pad
The manufacture method of above-mentioned thin-film transistor array base-plate, described first light shield uses the plate of gray level mask more than, the corresponding described data connection pad of this mask plate district, thin-film transistor source area and drain region have first transparent area, corresponding described thin-film transistor channel region has second transparent area, corresponding described grid connection pad district and storage capacitors district have the 3rd transparent area, other parts have the 4th transparent area, and the penetrating light intensity of first transparent area to the, four transparent areas increases successively.
The manufacture method of above-mentioned thin-film transistor array base-plate, described photoresist layer are the eurymeric photoresist layer.
The present invention also provides a kind of thin-film transistor array base-plate of being made by said method for solving the problems of the technologies described above, comprise an insulated substrate, the gate line of cross arrangement and data wire, be formed at the thin-film transistor of gate line and data wire crossover location, the pixel electrode that limits by gate line and data wire separated region, described gate line is formed at the first metal layer, described data wire is formed at second metal level, described pixel electrode is formed at transparency conducting layer, between the first metal layer and second metal level, deposit a gate insulation layer successively, one active layer and an ohmic contact layer, wherein, described gate line is interrupted shape and is distributed between the described data wire, described the first metal layer also is formed with the grid connection pad, and described transparency conducting layer also is formed with the transparency electrode that electrically contacts with described grid connection pad.
The present invention also provides the another kind of thin-film transistor array base-plate of being made by said method for solving the problems of the technologies described above, comprise an insulated substrate, the gate line of cross arrangement and data wire, be formed at the thin-film transistor of gate line and data wire crossover location, the pixel electrode that limits by gate line and data wire separated region, described pixel electrode is formed at transparency conducting layer, described gate line is formed at the first metal layer, described data wire is formed at second metal level, between the first metal layer and second metal level, deposit a gate insulation layer successively, one active layer and an ohmic contact layer, wherein, described data wire is interrupted shape and is distributed between the described gate line, described second metal level also is formed with the data connection pad, and described transparency conducting layer also is formed with the transparency electrode that electrically contacts with described data connection pad.
The present invention contrasts prior art following beneficial effect: thin-film transistor array base-plate provided by the invention and manufacture method thereof can reduce to three to the light shield number, reduce cost.In addition, because the minimizing of exposure frequency, the error between each exposure has also reduced, and has improved output and rate of finished products.
Description of drawings
Figure 1A has deposited the first metal layer, gate insulation layer, active layer, ohmic contact layer, second metal level for the present invention and has applied the sectional view of photoresist layer metacoxal plate.
Figure 1B carries out the pattern that obtains after mask, exposure and the development for the present invention adopts the first road light shield.
Fig. 1 C carries out the pattern that obtains after the etching for no photoresist overlay area among Figure 1B.
Fig. 1 D is the pattern that obtains behind the photoresist attenuate.
Fig. 1 E is that grid connection pad district and storage capacitors district carry out the pattern that obtains after the etching.
Fig. 1 F is the pattern that photoresist obtains behind the attenuate for the second time.
Fig. 1 G is that thin-film transistor channel region carries out the pattern that obtains after the etching.
The pattern of Fig. 1 H for obtaining after the present invention's first road light shield photoresist lift off.
Fig. 2 is the pattern after the present invention's second road light shield forms passivation layer.
Fig. 3 is the pattern after the present invention's the 3rd road light shield forms pixel electrode.
Fig. 4 is the present invention's one dot structure pattern.
Fig. 5 is another dot structure pattern of the present invention.
Among the figure
1 substrate, 2 mask plates, 3 photoresist layers
12 thin film transistor region 12a pixel bonding pads, 11 grid connection pad districts
13 storage capacitance districts, 14 data connection pad district 21a, first transparent area
The 21b first transparent area 21c first transparent area 22a second transparent area
23a the 3rd transparent area 23b the 3rd transparent area 24a the 4th transparent area
24b the 4th transparent area 24c the 4th transparent area 24d the 4th transparent area
24e the 4th transparent area 31 photoresist figures 32 photoresist figures
33 photoresist figures, 40 grids, 41 data wires
42 source electrodes, 43 drain electrodes, 44 gate lines
45 pixel electrodes, 46 grid connection pads, 47 data connection pads
101 the first metal layers, 102 gate insulation layers, 103 active layers
104 ohmic contact layers, 105 second metal levels, 106 passivation layers
D1 first thickness d 2 second thickness d 3 the 3rd thickness
Embodiment
The invention will be further described below in conjunction with drawings and Examples.
Please refer to Figure 1A to 1H, it is the first road light shield of a preferred embodiment of the present invention.
At first, shown in Figure 1A, on substrate 1, deposit the first metal layer 101, gate insulation layer 102, active layer 103, ohmic contact layer 104, second metal level 105 successively, wherein substrate 1 can be used glass, gate insulation layer 102 can be used silicon nitride (SiNx), active layer 103 uses amorphous silicon (a-Si), and ohmic contact layer 104 is n+a-Si, forms a photoresist layer 3 afterwards on second metal level 105.Each pixel has a grid connection pad district 11, a thin film transistor region 12, a storage capacitors district 13 and a data connection pad district 14.
One mask plate 2 with four kinds of penetrations of not sharing the same light is provided, above-mentioned photoresist layer 3 is carried out exposure imaging.In each pixel, the mask plate 2 in the present embodiment has a plurality of first transparent area 21a, 21b, 21c, the second transparent area 22a, the 3rd transparent area 23a, 23b and the 4th transparent area 24a, 24b, 24c, 24d, 24e.The penetrating light intensity of first transparent area to the, four transparent areas increases successively.Photoresist layer 3 is the eurymeric photoresist layer.
The photoresist figure 31 that is produced after developing has three kinds of different-thickness, please then refer to Figure 1B:
(1) has the 3rd thickness d 3 at photoresist, and remove fully corresponding to the photoresist at grid connection pad district 11 and 13 peripheral places, storage capacitors district corresponding to grid connection pad district 11 and storage capacitors district 13;
(2) have second thickness d 2 at photoresist, have first thickness d 1 corresponding to the photoresist of source electrode and drain region corresponding to the channel region place of thin film transistor region 12;
(3) has first thickness d 1 at photoresist corresponding to data connection pad district 14;
(4) photoresist of its elsewhere is removed fully;
And this first thickness d 1 greater than second thickness d 2 greater than the 3rd thickness d 3.
Afterwards, shown in Fig. 1 C, etch away second metal level 105, ohmic contact layer 104, amorphous silicon layer 103, gate insulator 102 and the first metal layer 101 in no photoresist district successively.
Then, photoresist figure 31 is carried out thinning handle, the photoresist figure 32 after the thinning is as Fig. 1 D.Wherein, removed fully corresponding to the photoresist in grid connection pad district 11 and storage capacitors district 13, the photoresist in thin film transistor region 12 and data connection pad district 14 is thinned.
Then, shown in Fig. 1 E, grid connection pad district 11 and storage capacitors district 13 are carried out etching, expose the first metal layer, form grid connection pad and storage capacitors electrode.
Again photoresist figure 32 is carried out reduction processing, the photoresist figure 33 after the thinning is as Fig. 1 F.Wherein, removed fully corresponding to the photoresist of thin film transistor region 12 channel regions, the photoresist of remainder is thinned.
Then, shown in Fig. 1 G, etch away second metal level 105, the ohmic contact layer 104 of thin-film transistor channel region successively, form raceway groove.
Then, shown in Fig. 1 H, remove the photoresist at thin film transistor region 12 source areas, drain region and 14 places, data connection pad district, to expose the source electrode of the thin-film transistor that is covered by first thickness d, 1 photoresist, drain electrode and data connection pad, at this moment, photoresist Removes All on all figures.
Please refer to Fig. 2, it is the pattern after the present invention's second road light shield forms passivation layer.Continue deposit passivation layer 106 on as the formed pattern of Fig. 1 H, after exposure, development, etching, be removed, expose the first metal layer corresponding to the passivation layer in grid connection pad district 11; Passivation layer corresponding to data connection pad district 14 and transistor pixels bonding pad 12a is removed, and exposes second metal level.
At last, please refer to Fig. 3, form a transparency conducting layer (figure do not show) on passivation silicon layer 106,, form a transparency electrode on the exposed the first metal layer in grid connection pad district 11, promptly form a transparency electrode 1071 on grid connection pad 46 through behind the patterning; Form a transparency electrode on the second exposed metal level of data connection pad district 14 and thin-film transistor pixel bonding pad 12a, promptly form a pixel electrode 45 on the 12a of transistor pixels bonding pad, a transparency electrode 1072 is on data connection pad 47.
Through above-mentioned three road light shields, the dot structure that the invention provides a kind of thin-film transistor LCD device array substrate as shown in Figure 4, please in conjunction with Fig. 3, the dot structure of array base palte provided by the invention comprises substrate 1, gate line 44, grid 40, gate insulation layer 102, active layer 103, ohmic contact layer 104, data wire 41, source electrode 42, drain electrode 43 and pixel electrode 45.Wherein, gate line 44, grid 40 are formed on the first metal layer 101, also are formed with storage capacitors and grid connection pad 46 on the first metal layer 101; Source electrode 42 and drain electrode 43 are formed on second metal level 102; Pixel electrode 45 is formed on the transparency conducting layer, and transparency conducting layer also is formed with transparency electrode 1071.Data wire 41 and source electrode 42, drain electrode remain with the first metal layer 101, gate insulation layer 102, active layer 103 and ohmic contact layer 104 43 times, gate line 44 is interrupted shape and is distributed between the data wire 41, and transparency electrode 1071 connects interrupted gate line 44 by grid connection pad 46.
The dot structure of thin-film transistor LCD device array substrate provided by the invention, also can connect by the data connection pad data wire by transparency electrode, as shown in Figure 5, please in conjunction with Fig. 3, the dot structure of array base palte provided by the invention comprises substrate 1, gate line 44, grid 40, gate insulation layer 102, active layer 103, ohmic contact layer 104, data wire 41, source electrode 42, drain electrode 43 and pixel electrode 45.Wherein, gate line 44, grid 40 are formed on the first metal layer 101; Source electrode 42 and drain electrode 43 are formed on second metal level 102, also are formed with data connection pad 47 on second metal level 102; Pixel electrode 45 is formed on the transparency conducting layer, and transparency conducting layer also is formed with transparency electrode 1072.Data wire 41 and source electrode 42, drain electrode remain with the first metal layer 101, gate insulation layer 102, active layer 103 and ohmic contact layer 104 43 times, data wire 41 is interrupted shape and is distributed between the gate line 44, and transparency electrode 1072 connects interrupted data wire 41 by data connection pad 47.
In sum, thin-film transistor array base-plate provided by the invention and manufacture method thereof are connected interrupted gate line, data wire by transparency electrode with connection pad, can reduce to three to the light shield number, reduce cost.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (5)
1. the manufacture method of a thin-film transistor array base-plate may further comprise the steps:
One substrate is provided, and form the first metal layer, gate insulation layer, active layer, ohmic contact layer, second metal level on this substrate, be coated with photoresist then, wherein said the first metal layer has grid connection pad district and storage capacitors district, described active layer has thin-film transistor channel region, and described second metal level has data connection pad district, thin-film transistor source area and drain region;
Utilize first light shield to form one first photoresist pattern, the photoresist layer that wherein covers described data connection pad district, thin-film transistor source area and drain region has first height, the photoresist that covers described thin-film transistor channel region has second height, the photoresist layer that covers described grid connection pad district and storage capacitors district has the 3rd height, and this first height greater than second height greater than the 3rd highly;
With this first photoresist pattern is mask, removes this second metal level, active layer, ohmic contact layer, gate insulation layer and the first metal layer of part;
Remove the segment thickness of this first photoresist pattern,, form grid and storage capacitors through etching to expose by the 3rd height grid connection pad district and storage capacitors district that photoresist layer covered;
Continue to remove the segment thickness of this first photoresist pattern,, remove second metal level of this channel region and ohmic contact layer to form raceway groove to expose by the second height thin-film transistor channel region that photoresist layer covered;
Continue to remove the segment thickness of this first photoresist pattern, to expose by the source electrode of the first height thin-film transistor that photoresist layer covered, drain electrode and data connection pad;
Utilize one second light shield to form passivation layer, after exposure, development, etching, expose grid connection pad and data connection pad;
Utilize one the 3rd light shield to form pixel electrode, and a transparency electrode is on described exposure grid connection pad, a transparency electrode is on described exposure data connection pad.
2. the manufacture method of thin-film transistor array base-plate according to claim 1, it is characterized in that, described first light shield uses the plate of gray level mask more than, the corresponding described data connection pad of this mask plate district, thin-film transistor source area and drain region have first transparent area, corresponding described thin-film transistor channel region has second transparent area, corresponding described grid connection pad district and storage capacitors district have the 3rd transparent area, other parts have the 4th transparent area, and the penetrating light intensity of first transparent area to the, four transparent areas increases successively.
3. the manufacture method of thin-film transistor array base-plate according to claim 1 is characterized in that, described photoresist layer is the eurymeric photoresist layer.
4. thin-film transistor array base-plate that uses the described method of claim 1 to make, comprise an insulated substrate, the gate line of cross arrangement and data wire, be formed at the thin-film transistor of gate line and data wire crossover location, the pixel electrode that limits by gate line and data wire separated region, described gate line is formed at the first metal layer, described data wire is formed at second metal level, described pixel electrode is formed at transparency conducting layer, between the first metal layer and second metal level, deposit a gate insulation layer successively, one active layer and an ohmic contact layer, it is characterized in that, described gate line is interrupted shape and is distributed between the described data wire, described the first metal layer also is formed with the grid connection pad, and described transparency conducting layer also is formed with the transparency electrode that electrically contacts with described grid connection pad.
5. thin-film transistor array base-plate that uses the described method of claim 1 to make, comprise an insulated substrate, the gate line of cross arrangement and data wire, be formed at the thin-film transistor of gate line and data wire crossover location, the pixel electrode that limits by gate line and data wire separated region, described pixel electrode is formed at transparency conducting layer, described gate line is formed at the first metal layer, described data wire is formed at second metal level, between the first metal layer and second metal level, deposit a gate insulation layer successively, one active layer and an ohmic contact layer, it is characterized in that, described data wire is interrupted shape and is distributed between the described gate line, described second metal level also is formed with the data connection pad, and described transparency conducting layer also is formed with the transparency electrode that electrically contacts with described data connection pad.
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| CN101577254B (en) * | 2009-03-30 | 2011-03-23 | 上海广电光电子有限公司 | Method for manufacturing thin film transistor array substrate |
| CN102931138A (en) * | 2012-11-05 | 2013-02-13 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| CN103123910A (en) * | 2012-10-31 | 2013-05-29 | 京东方科技集团股份有限公司 | Array substrate, manufacture method of array substrate and display device |
| CN103178021A (en) * | 2013-02-28 | 2013-06-26 | 京东方科技集团股份有限公司 | Oxide thin-film transistor array substrate, manufacturing method for same and display panel |
| CN103762199A (en) * | 2013-12-31 | 2014-04-30 | 深圳市华星光电技术有限公司 | Method for manufacturing array base plate of liquid crystal display |
| CN104716091A (en) * | 2013-12-13 | 2015-06-17 | 昆山国显光电有限公司 | Array substrate preparation method, array substrate, and organic light-emitting display device |
| WO2017049824A1 (en) * | 2015-09-21 | 2017-03-30 | 京东方科技集团股份有限公司 | Manufacturing method of tft array substrate, tft array substrate, and display device |
| CN108573928A (en) * | 2018-04-13 | 2018-09-25 | 深圳市华星光电技术有限公司 | A kind of preparation method and tft array substrate, display panel of tft array substrate |
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| CN101577254B (en) * | 2009-03-30 | 2011-03-23 | 上海广电光电子有限公司 | Method for manufacturing thin film transistor array substrate |
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| US9190432B2 (en) | 2013-02-28 | 2015-11-17 | Boe Technology Group Co., Ltd | Oxide thin-film transistor array substrate, manufacturing method thereof and display panel |
| CN104716091A (en) * | 2013-12-13 | 2015-06-17 | 昆山国显光电有限公司 | Array substrate preparation method, array substrate, and organic light-emitting display device |
| CN104716091B (en) * | 2013-12-13 | 2018-07-24 | 昆山国显光电有限公司 | Preparation method, array substrate and the organic light emitting display of array substrate |
| CN103762199A (en) * | 2013-12-31 | 2014-04-30 | 深圳市华星光电技术有限公司 | Method for manufacturing array base plate of liquid crystal display |
| CN103762199B (en) * | 2013-12-31 | 2016-05-18 | 深圳市华星光电技术有限公司 | A kind of manufacture method of array base palte of liquid crystal display |
| WO2017049824A1 (en) * | 2015-09-21 | 2017-03-30 | 京东方科技集团股份有限公司 | Manufacturing method of tft array substrate, tft array substrate, and display device |
| US10020325B2 (en) | 2015-09-21 | 2018-07-10 | Boe Technology Group Co., Ltd. | Method for producing TFT array substrate, TFT array substrate, and display apparatus |
| CN108573928A (en) * | 2018-04-13 | 2018-09-25 | 深圳市华星光电技术有限公司 | A kind of preparation method and tft array substrate, display panel of tft array substrate |
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| CN113206038B (en) * | 2021-04-30 | 2022-04-01 | 北海惠科光电技术有限公司 | Array substrate manufacturing method and display panel manufacturing method |
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| CN100578761C (en) | 2010-01-06 |
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