WO2014190733A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2014190733A1
WO2014190733A1 PCT/CN2013/089596 CN2013089596W WO2014190733A1 WO 2014190733 A1 WO2014190733 A1 WO 2014190733A1 CN 2013089596 W CN2013089596 W CN 2013089596W WO 2014190733 A1 WO2014190733 A1 WO 2014190733A1
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Prior art keywords
electrode
electrode layer
layer
array substrate
protrusions
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PCT/CN2013/089596
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English (en)
French (fr)
Inventor
崔承镇
金熙哲
宋泳锡
刘圣烈
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/345,864 priority Critical patent/US9117707B2/en
Publication of WO2014190733A1 publication Critical patent/WO2014190733A1/zh
Priority to US14/802,241 priority patent/US9419027B2/en

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    • H01L27/1259—
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L27/124—
    • H01L27/1248—
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134381—Hybrid switching mode, i.e. for applying an electric field with components parallel and orthogonal to the substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/124—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode interdigital
    • H01L27/1218—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • Embodiments of the present invention relate to the field of liquid crystal displays, and in particular, to an array substrate, a manufacturing method thereof, and a display device. Background technique
  • the liquid crystal display devices commonly used in the prior art mainly include AD-SDS (Advanced-Super Dimensional Switching), IPS (In Plane Switch) type, and ⁇ (Twist Nematic). , twisted nematic) type.
  • AD-SDS Advanced-Super Dimensional Switching
  • IPS In Plane Switch
  • ⁇ Twiist Nematic
  • the ADS type display device forms a multi-dimensional electric field by a parallel electric field generated by the edge of the pixel electrode in the same plane and a longitudinal electric field generated between the pixel electrode layer and the common electrode layer, so that all the aligned liquid crystal molecules are directly between the pixel electrodes in the liquid crystal cell and above the electrode. Both can produce rotation.
  • the pixel electrode and the common electrode are usually arranged in a staggered manner, but in general, since the pixel electrode and the common electrode are only staggered by the patterning process of the mask, the exposure is very required. The precision of the process will undoubtedly increase the difficulty and cost of equipment and process control. Summary of the invention
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which can reduce the manufacturing cost and the difficulty of the manufacturing process.
  • an array substrate including a plurality of gate lines, a plurality of data lines, and a plurality of pixel regions defined by the plurality of gate lines and the plurality of data lines, each of which is
  • the pixel region includes a thin film transistor, and further includes:
  • a substrate at the bottom of the village a substrate at the bottom of the village; one or more protrusions disposed on the substrate of the village;
  • first electrode layer the first electrode layer includes at least one first electrode strip, and the first electrode strip is disposed in a gap of adjacent protrusions; a second electrode layer, the second electrode layer includes at least one second electrode strip, and the second electrode strip is disposed above the protrusion.
  • the pixel region further includes an insulating layer disposed between the first electrode layer and the second electrode layer.
  • more than one of the protrusions on the substrate substrate are equally spaced.
  • the plurality of protrusions are disposed, and each of the gaps between the plurality of protrusions is disposed with the first electrode strip, and each of the protrusions is disposed above The second electrode strip is described.
  • the thin film transistor includes a gate, a gate insulating layer, an active layer, a source, and a drain.
  • the gate insulating layer is disposed between the first electrode layer and the second electrode layer;
  • the first electrode layer is connected to the drain through a via hole on the gate insulating layer.
  • the array substrate further includes a passivation layer, the gate insulating layer is disposed under the first electrode layer, and the passivation layer is disposed on the first electrode layer and the second electrode Between layers;
  • the first electrode layer is directly connected to the drain.
  • the array substrate further includes a passivation layer disposed between the first electrode layer and the second electrode layer;
  • the second electrode layer is connected to the drain through a via on the passivation layer.
  • the array substrate further includes a passivation layer disposed between the first electrode layer and the second electrode layer, and the passivation layer is disposed on the second electrode Above the layer;
  • the second electrode layer is directly connected to the drain.
  • the material of the protrusion is a transparent resin material, and the protrusion has a thickness greater than a thickness of the first electrode layer.
  • a method for fabricating an array substrate comprising forming a gate line, a data line, and a thin film transistor on a substrate substrate, further includes:
  • Forming a first electrode layer the first electrode layer includes at least one first electrode strip, and the first electrode strip is disposed in a gap of adjacent protrusions; Forming a second electrode layer, the second electrode layer includes at least one second electrode strip, and the second electrode strip is disposed above the protrusion.
  • the fabrication method further includes forming an insulating layer between the first electrode layer and the second electrode layer.
  • the method of making includes:
  • a second transparent conductive film on the glue pattern forms a second electrode layer including at least one second electrode strip.
  • the thin film transistor includes a gate, a gate insulating layer, an active layer, a source, and a drain,
  • the insulating layer includes at least one of a gate insulating layer or a passivation layer;
  • the first electrode layer is connected to the drain, or the second electrode layer is connected to the drain.
  • the protrusions made on the substrate of the village are equally spaced.
  • the material of the protrusion is a transparent resin material, and the protrusion has a thickness greater than a thickness of the first electrode layer.
  • a display device comprising the above array substrate.
  • FIG. 1 is a schematic cross-sectional structural view of an array substrate in the prior art
  • FIG. 2 is a schematic structural view of a cross-sectional substrate of an array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram showing a first cross-sectional structure of an array substrate in an array substrate manufacturing method according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram showing a second cross-sectional structure of an array substrate in an array substrate manufacturing method according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram showing a third cross-sectional structure of an array substrate in a method of fabricating an array substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram showing a fourth cross-sectional structure of an array substrate in a method of fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram showing a fifth cross-sectional structure of an array substrate in a method of fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram showing a sixth cross-sectional structure of an array substrate in a method of fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram showing a seventh cross-sectional structure of an array substrate in a method of fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram showing an eighth cross-sectional structure of an array substrate in an array substrate manufacturing method according to an embodiment of the present invention.
  • Figures 11a-lld illustrate various positional relationships of the first and second electrode layers in the array substrate.
  • An embodiment of the present invention provides an array substrate, the array substrate includes a plurality of gate lines, a plurality of data lines, and a plurality of pixel regions defined by the plurality of gate lines and the plurality of data lines.
  • the pixel region includes a thin film transistor.
  • the pixel area further includes: a substrate substrate 11 on which the substrate substrate 11 is provided with one or more protrusions 110; a first electrode layer 12, and the first electrode layer 12 includes at least one a first electrode strip 120, the first electrode strip 120 is disposed in a gap of an adjacent protrusion 110; a second electrode layer 13, the second electrode layer 13 includes at least one second electrode strip 130, The second electrode strip 130 is disposed above the protrusion 110.
  • the array substrate provided by the embodiment of the present invention is configured by disposing a substrate substrate of the array substrate as a substrate substrate having a groove, and disposing the first electrode layer in the groove, and the second electrode layer is disposed outside the groove.
  • the protrusions 110 disposed on the substrate of the village are equally spaced.
  • the protrusion 110 has a depth greater than a thickness of the first electrode layer.
  • the first electrode strips 120 are disposed in the gaps of the respective protrusions 110, and the second electrode strips 130 are disposed above each of the protrusions.
  • the pixel region further includes an insulating layer disposed between the first electrode layer 12 and the second electrode layer 13.
  • one of the first electrode layer and the second electrode layer is connected as a pixel electrode and a drain.
  • the first electrode layer may be connected to the drain electrode, or the second electrode layer may be connected to the drain electrode.
  • the electrode electrically connected to the common electrode line is a common electrode
  • the electrode electrically connected to the drain of the thin film transistor is a pixel electrode.
  • the thin film transistor includes a gate, a gate insulating layer, an active layer, a source, and a drain.
  • the first electrode layer may be connected to the drain, that is, the first electrode layer is a pixel electrode, and the second electrode layer is a common electrode. In this case, there are two cases:
  • the first electrode layer is directly connected to the drain.
  • a thin film transistor is first formed on the array substrate, and then a first electrode layer, a passivation layer, and a second electrode layer are sequentially formed.
  • a passivation layer is disposed between the first electrode layer and the second electrode layer.
  • the first electrode layer is located above the gate insulating layer, and there is no other hierarchical structure between the first electrode layer and the drain, and the first electrode layer may directly overlap the drain. Extremely (as shown in Figure 11a).
  • the first electrode layer is connected to the drain through a via hole on the gate insulating layer. In this case, a first electrode layer is first formed on the array substrate to form a thin film transistor.
  • a passivation layer and a second electrode layer are then formed.
  • a gate insulating layer is disposed between the first electrode layer and the second electrode layer. At this time, the gate insulating layer is located above the first electrode layer, and a via hole is formed on the gate insulating layer, and a via hole on the gate insulating layer is above the first electrode layer, the drain
  • the electrode layer may be connected to the first electrode layer through a via hole on the gate insulating layer (as shown in FIG.
  • the second electrode layer may also be connected to the drain, that is, the second electrode layer is a pixel electrode, and the first electrode layer is a common electrode.
  • the second electrode layer is a pixel electrode
  • the first electrode layer is a common electrode.
  • the second electrode layer is connected to the drain through a via hole on the passivation layer.
  • a passivation layer is formed on the array substrate to form a second electrode layer.
  • a second electrode layer is located above the passivation layer, a via on the passivation layer is above the drain, and the second electrode layer can pass through a via on the passivation layer
  • the two electrode layers are connected (as shown in Figure 11c).
  • the second electrode layer is directly connected to the drain.
  • the first electrode layer is first formed on the array substrate to form a thin film transistor, and then the second electrode layer and the passivation are sequentially formed.
  • a layer, the second electrode layer is located under the passivation layer, the second electrode layer and the drain There is no other hierarchical structure between the poles, and the second electrode layer can be directly overlapped on the drain (shown as id in FIG. 1).
  • Another embodiment of the present invention further provides a method for fabricating an array substrate, comprising: forming a gate line, a data line, and a thin film transistor on a substrate of the substrate, and further comprising:
  • the first electrode layer includes at least one first electrode strip, and the first electrode strip is disposed in a gap of adjacent protrusions;
  • a second electrode layer is formed, the second electrode layer including at least one second electrode strip, and the second electrode strip is disposed above the bump.
  • a resin layer is formed on the substrate 11 and then more than one protrusion 110 is formed on the substrate 11 by a patterning process.
  • the protrusions 110 on the substrate substrate 11 are equally spaced.
  • a first transparent conductive film 12a is formed on the substrate substrate 11 shown in FIG. 3, and a first photoresist 12b is coated on the substrate on which the first transparent conductive film 12a is formed.
  • the first photoresist 12b is ashed to form a first photoresist pattern 12c, and the first photoresist pattern 12c covers only the gap of the protrusion 110. .
  • a first electrode layer 12 including a plurality of electrically conductive first electrode strips 120 is formed.
  • the thickness of the protrusion 110 is greater than the thickness of the first electrode layer 12.
  • An insulating layer is formed on the substrate substrate on which the first electrode layer 12 is formed, and then a second photoresist 13b is coated on the substrate on which the insulating layer is formed to form a substrate as shown in FIG. It should be noted here that the insulating layer is, for example, a gate insulating layer or a passivation layer.
  • the second photoresist 13b is ashed to form a second photoresist pattern 13c as shown in FIG. 9, and the second photoresist pattern 13c covers only the gap of the protrusion 110. . 58.
  • a second transparent conductive film 13a is formed on the substrate on which the second photoresist pattern 13c is formed.
  • the second photoresist pattern 13c and the second transparent conductive film on the second photoresist pattern are removed by a photoresist stripping process, thereby forming a plurality of conductive layers as shown in FIG.
  • the formed first electrode layer is connected to the drain, or the formed second electrode layer is connected to the drain. It should be noted here that regardless of the first electrode layer or the second electrode layer, the electrode electrically connected to the common electrode line is a common electrode, and the electrode electrically connected to the drain of the thin film transistor is a pixel electrode.
  • the manufacturing method includes: after step S1, referring to the existing manufacturing process A non-display area of the substrate of the substrate is used to fabricate a thin film transistor including a gate, a gate insulating layer, an active layer, a source, and a drain. Then, steps S2-S5 are sequentially performed to form a first electrode layer, and the first electrode layer can be directly formed on the drain. Finally, a passivation layer can be formed first and then steps S6-S10 are performed in sequence to form a second electrode layer. At this time, the insulating layer is a passivation layer.
  • the manufacturing method includes: Steps S1 - S5 are performed to form a first electrode layer. Then, a thin film transistor is fabricated in a non-display area of the substrate of the substrate with reference to an existing fabrication process, the thin film transistor including a gate, a gate insulating layer, an active layer, a source, and a drain.
  • a gate insulating layer including via holes may be formed by a patterning process, and a via hole of the gate insulating layer is formed above the first electrode layer, and the formed drain electrode can be formed The first electrode layer is connected through a via hole on the gate insulating layer.
  • the passivation layer may be first formed and then the steps S6-S10 may be sequentially performed to form the second electrode layer; or the steps S6-S10 may be sequentially performed to form the second electrode layer, and then the passivation layer is formed.
  • the insulating layer is a gate insulating layer, or the insulating layer is a gate insulating layer and a passivation layer.
  • the manufacturing method includes: first sequentially performing steps S1 - S5 to form a first electrode
  • the thin film transistor is fabricated in a non-display area of the substrate of the substrate, and the thin film transistor includes a gate, a gate insulating layer, an active layer, a source, and a drain.
  • steps S6-S10 are sequentially performed to form a second electrode layer, and the second electrode layer can be directly fabricated in the drain Extremely.
  • a passivation layer is formed.
  • the insulating layer is a gate insulating layer.
  • the manufacturing method includes: first at the bottom of the village Forming a first electrode layer and a thin film transistor on the substrate, then forming a passivation layer film on the substrate, and forming a passivation layer including via holes by a patterning process, wherein a via hole of the passivation layer is formed at the drain Above. Finally, steps S6-S10 may be sequentially performed to form a second electrode layer, and the formed second electrode layer may be connected to the drain through a via of the passivation layer.
  • the insulating layer is a passivation layer, or the insulating layer is a gate insulating layer and a passivation layer.
  • the embodiment of the present invention further provides a display device, where the display device includes the array substrate of the above embodiment, and the display device can be any display function such as a liquid crystal display, a liquid crystal television, a digital camera, a mobile phone, a tablet computer, or the like. Product or component.
  • the protrusions and the substrate are independently formed separately, but in other embodiments, the two may be integrally formed, for example, one or more of the flat surfaces of the substrate are dug. Groove.
  • the array substrate provided by the above embodiment of the present invention, the manufacturing method thereof, and the display device are provided with a protrusion on the substrate of the village, and the first electrode layer is disposed in the groove formed by the protrusion, and the second electrode layer is disposed.
  • the protrusions zero overlap between the common electrode and the pixel electrode is realized; whereas in the prior art, the array substrate is mostly as shown in FIG. 1 , and the common electrode 1 and the pixel electrode 2 are alternately arranged due to the pixel electrode.
  • Both the 1 and the common electrode 2 are made of a transparent electrode material, which requires precise overlap between the two electrode layers by a relatively complicated fabrication process and high fabrication cost.
  • the present invention can accurately ensure the zero overlap between the two electrode layers by using the protrusions on the substrate of the substrate, thereby reducing the manufacturing cost and the difficulty of the manufacturing process.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

一种阵列基板，包括多个栅线、多个数据线以及多个栅线和多个数据线交叉限定的多个像素区域，每一个像素区域包括薄膜晶体管，还包括：衬底基板（11）；间隔设置在衬底基板（11）上的一个以上凸起物（110）；第一电极层（12），第一电极层（12）包括至少一个第一电极条（120），第一电极条（120）设置在相邻凸起物（110）的间隙中；第二电极层（13），第二电极层（13）包括至少一个第二电极条（130），第二电极条（130）设置在凸起物（110）上方。还披露了阵列基板的制作方法、显示装置。

Description

阵列基板及其制作方法、 显示装置 技术领域
本发明实施例涉及液晶显示器领域， 尤其涉及一种阵列基板及其制作方 法、 显示装置。 背景技术
现有技术中常见的液晶显示装置主要有 AD-SDS ( Advanced-Super Dimensional Switching, 筒称为 ADS, 高级超维场开关）型、 IPS ( In Plane Switch , 横向电场效应）型以及 ΤΝ ( Twist Nematic , 扭曲向列）型。 其中， ADS 型显示装置通过同一平面内像素电极边缘所产生的平行电场以及像素 电极层与公共电极层间产生的纵向电场形成多维电场， 使液晶盒内像素电极 间、 电极正上方所有取向液晶分子都能够产生旋转。
现有的 ADS 型显示装置中由于像素电极和公共电极的重叠面积大且间 距小， 从而导致存储电容 Cst非常大， 因此在设计时会受到很多限制。 目前 为了解决 Cst过大的问题，通常都采取像素电极和公共电极交错排列的方式， 但一般情况下， 由于像素电极和公共电极仅依靠掩模板的构图工艺制成交错 排列的方式， 非常要求曝光工艺的精确度， 这样无疑会增加设备以及工艺控 制的难度和成本。 发明内容
本发明的实施例提供一种阵列基板及其制作方法、 显示装置， 可以降低 制作成本和制作工艺的难度。
为达到上述目的， 本发明的实施例采用如下技术方案：
根据本发明的第一方面， 提供一种阵列基板， 包括多个栅线、 多个数据 线以及所述多个栅线和所述多个数据线交叉限定的多个像素区域， 每一个所 述像素区域包括薄膜晶体管， 还包括：
村底基板； 间隔设置在村底基板上的一个以上凸起物；
第一电极层， 所述第一电极层包括至少一个第一电极条， 所述第一电极 条设置在相邻凸起物的间隙中； 第二电极层， 所述第二电极层包括至少一个第二电极条， 所述第二电极 条设置在所述凸起物上方。
在一个示例中， 所述像素区域还包括绝缘层， 设置在所述第一电极层和 所述第二电极层之间。
在一个示例中， 所述村底基板上的一个以上凸起物是等间距设置的。 在一个示例中， 所述凸起物为多个， 该多个凸起物之间的每个间隙内都 设置有所述第一电极条， 每个所述凸起物的上方都设置有所述第二电极条。
在一个示例中， 所述薄膜晶体管包括栅极、 栅绝缘层、 有源层、 源极以 及漏极。
在一个示例中， 所述栅绝缘层设置在所述第一电极层和所述第二电极层 之间；
所述第一电极层通过所述栅绝缘层上的过孔与所述漏极连接。
在一个示例中， 所述阵列基板还包括钝化层， 所述栅绝缘层设置在所述 第一电极层的下方， 所述钝化层设置在所述第一电极层和所述第二电极层之 间；
所述第一电极层直接与所述漏极连接。
在一个示例中， 所述阵列基板还包括钝化层， 所述钝化层设置在所述第 一电极层和所述第二电极层之间；
所述第二电极层通过钝化层上的过孔与所述漏极连接。
在一个示例中， 所述阵列基板还包括钝化层， 所述栅绝缘层设置在所述 第一电极层和所述第二电极层之间， 所述钝化层设置在所述第二电极层的上 方；
所述第二电极层直接连接所述漏极。
在一个示例中， 所述凸起物的材料为透明树脂材料， 且所述凸起物的厚 度大于所述第一电极层的厚度。
根据本发明的第二方面， 提供一种阵列基板的制作方法， 包括在村底基 板上制作栅线、 数据线以及薄膜晶体管所述制作方法还包括：
在村底基板上形成间隔设置的一个以上凸起物；
形成第一电极层， 所述第一电极层包括至少一个第一电极条， 所述第一 电极条设置在相邻凸起物的间隙中； 形成第二电极层， 所述第二电极层包括至少一个第二电极条， 所述第二 电极条设置在所述凸起物上方。
在一个示例中， 该制作方法还包括在所述第一电极层和第二电极层之间 制作绝缘层。
在一个示例中， 该制作方法包括：
在村底基板上制作间隔设置的一个以上凸起物；
在形成有所述凸起物的基板上制作第一透明导电薄膜， 并在制作有所述 第一透明导电薄膜的基板上涂敷第一光刻胶；
对所述第一光刻胶进行灰化处理， 形成第一光刻胶图案， 所述第一光刻 胶图案只覆盖所述凸起物的间隙；
进行刻蚀工艺， 除去所述第一光刻胶图案未覆盖的第一透明导电薄膜； 进行光刻胶剥离工艺， 将所述第一光刻胶图案剥离， 从而形成包括至少 一个第一电极条的第一电极层；
在形成有所述第一电极层的村底基板上制作绝缘层；
在制作有所述绝缘层的基板上涂敷第二光刻胶,对所述光刻胶进行灰化 处理，形成第二光刻胶图案，所述第二光刻胶图案只覆盖所述凸起物的间隙； 在所述形成有第二光刻胶图案的基板上制作第二透明导电薄膜， 然后通 过光刻胶剥离工艺， 去除所述第二光刻胶图案以及位于所述第二光刻胶图案 上的第二透明导电薄膜， 从而形成包括至少一个第二电极条的第二电极层。
在一个示例中， 所述薄膜晶体管包括栅极、 栅绝缘层、 有源层、 源极以 及漏极，
所述绝缘层包括栅绝缘层或钝化层中的至少一个；
所述第一电极层与所述漏极连接， 或所述第二电极层与所述漏极连接。 在一个示例中， 制作在村底基板上的凸起物是等间距的。
在一个示例中， 所述凸起物的材料为透明树脂材料， 且所述凸起物的厚 度大于所述第一电极层的厚度。
根据本发明的第三方面， 提供一种显示装置， 包括上述的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中的一种阵列基板的剖面结构示意图；
图 2为本发明实施例提供的一种阵列基板的剖面基板结构示意图； 图 3为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第一 种剖面结构的示意图；
图 4为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第二 种剖面结构的示意图；
图 5为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第三 种剖面结构的示意图；
图 6为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第四 种剖面结构的示意图；
图 7为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第五 种剖面结构的示意图；
图 8为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第六 种剖面结构的示意图；
图 9为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第七 种剖面结构的示意图；
图 10 为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第 八种剖面结构的示意图；
图 lla-lld示出了阵列基板中第一和第二电极层的各种位置关系。
附图标记：
1-公共电极， 2-像素电极， 11-村底基板， 12-第一电极层， 13-第二电极 层， 110-凸起物， 120-第一电极条， 130-第二电极条， 12a-第一透明导电薄膜， 12b-第一光刻胶， 12c-第一光刻胶图案， 13a-第二透明导电薄膜， 13b-第二光 刻胶， 13c-第二光刻胶图案， 14-栅极， 15-栅绝缘层， 16-有源层， 17-源漏电 极， 18-钝化层。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于所描述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前 提下所获得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个" 或者 "一" 等类似词语也不表示数量限制，而是表示存在至少一个。 "包括"或者 "包含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵盖出 现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排除其 他元件或者物件。 "连接"或者 "相连"等类似的词语并非限定于物理的或者 机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上"、 "下"、 "左"、 "右" 等仅用于表示相对位置关系， 当被描述对象的绝对位置 改变后， 则该相对位置关系也可能相应地改变。
本发明实施例提供了一种阵列基板， 所述阵列基板包括多个栅线、 多个 数据线以及所述多个栅线和所述多个数据线交叉限定的多个像素区域， 每个 所述像素区域包括薄膜晶体管。 如图 2所示， 所述像素区域还包括： 村底基 板 11 , 所述村底基板 11上设置有一个以上凸起物 110; 第一电极层 12, 所 述第一电极层 12包括至少一个第一电极条 120,所述第一电极条 120设置在 相邻的凸起物 110的间隙中； 第二电极层 13, 所述第二电极层 13包括至少 一个第二电极条 130, 所述第二电极条 130设置在所述凸起物 110的上方。
本发明实施例提供的阵列基板， 通过将阵列基板的村底基板设置成带有 凹槽的村底基板，并将第一电极层设置在凹槽内，第二电极层设置在凹槽外， 这样利用村底基板上的凸起物， 就可以精确地保证了两个电极层之间的零重 叠， 降低制作成本和制作工艺的难度。
在一个示例中， 所述村底基板上设置的凸起物 110是等间距的。
在一个示例中， 所述凸起物 110的深度大于所述第一电极层的厚度。 在一个示例中， 如图 2所示， 各个凸起物 110的间隙内都设置有所述第 一电极条 120, 每个所述凸起物的上方都设置有所述第二电极条 130。 在一个示例中，像素区域还包括绝缘层，设置在所述第一电极层 12和所 述第二电极层 13之间。
本发明实施例提供的阵列基板中， 所述第一电极层和所述第二电极层中 有一个电极层要作为像素电极与漏极连接。 可以是所述第一电极层与所述漏 极连接， 也可以是所述第二电极层与所述漏极连接。 在这里需要说明的是， 无论第一电极层还是第二电极层， 只要与公共电极线电连接的电极就为公共 电极， 与薄膜晶体管的漏极电连接的电极就为像素电极。
在一个示例中， 所述薄膜晶体管包括栅极、 栅绝缘层、 有源层、 源极以 及漏极。 可选的， 所述第一电极层可以与所述漏极连接， 即第一电极层为像 素电极， 所述第二电极层为公共电极， 此时可以有以下两种情况：
一种情况为： 所述第一电极层直接连接所述漏极， 此种情况下， 所述阵 列基板上先制作有薄膜晶体管， 再依次制作第一电极层、 钝化层和第二电极 层， 所述第一电极层与所述第二电极层之间设置有钝化层。 此时， 所述第一 电极层位于所述栅绝缘层的上方， 所述第一电极层与所述漏极之间没有其他 层级结构， 所述第一电极层可以直接搭接在所述漏极上（如图 11a所示）。 另 一种情况为： 所述第一电极层通过所述栅绝缘层上的过孔与所述漏极连接， 此种情况下， 所述阵列基板上先制作第一电极层再制作薄膜晶体管， 然后制 作钝化层和第二电极层。 所述第一电极层与所述第二电极层之间设置有栅绝 缘层。 此时， 所述栅绝缘层位于所述第一电极层上方， 在所述栅绝缘层上制 作过孔， 所述栅绝缘层上的过孔在所述第一电极层的上方， 所述漏极可以通 过所述栅绝缘层上的过孔与所述第一电极层连接（如图 l ib所示）。
可选的， 所述第二电极层也可以与所述漏极连接， 即第二电极层为像素 电极， 所述第一电极层为公共电极， 此时可以有以下两种情况：
一种情况为： 所述第二电极层通过钝化层上的过孔与所述漏极连接， 此 种情况下， 所述阵列基板上先制作钝化层再制作第二电极层， 所述第二电极 层位于所述钝化层上方， 所述钝化层上的过孔在所述漏极的上方， 所述第二 电极层可以通过所述钝化层上的过孔与所述第二电极层连接（如图 11c所 示）。 另一种情况为： 所述第二电极层直接连接所述漏极， 此种情况下， 所述 阵列基板上先制作第一电极层再制作薄膜晶体管， 然后依次制作第二电极层 和钝化层， 所述第二电极层位于所述钝化层下方， 所述第二电极层与所述漏 极之间没有其他层级结构， 所述第二电极层可以直接搭接在所述漏极上（如 图 l id所示）。
本发明另一实施例还提供了一种阵列基板的制作方法， 包括在村底基板 上制作栅线、 数据线以及薄膜晶体管， 还包括：
在村底基板上形成间隔设置的一个以上凸起物；
形成第一电极层， 所述第一电极层包括至少一个第一电极条， 所述第一 电极条设置在相邻凸起物的间隙中；
形成第二电极层， 所述第二电极层包括至少一个第二电极条， 所述第二 电极条设置在所述凸起物上方。
在一个示例中， 非显示区域处的栅线、 数据线以及薄膜晶体管的制作工 艺可以参考现有的制作工艺； 所述阵列基板的显示区域处的两个电极层的制 作方法包括以下步骤：
51、 如图 3所示， 在村底基板 11上制作树脂层， 然后通过一次构图工 艺在村底基板 11上形成一个以上凸起物 110。 在一个示例中， 所述村底基板 11上的凸起物 110是等间距的。
52、 如图 4所示， 在图 3所示的村底基板 11上制作第一透明导电薄膜 12a, 并在制作有所述第一透明导电薄膜 12a的基板上涂敷第一光刻胶 12b。
53、 如图 5所示， 对所述第一光刻胶 12b进行灰化处理， 形成第一光刻 胶图案 12c, 所述第一光刻胶图案 12c只覆盖所述凸起物 110的间隙。
S4、 进行刻蚀工艺， 除去所述第一光刻胶图案 12c未覆盖的第一透明导 电薄膜， 如图 6所示， 在基板的凹槽（例如由凸起物之间的间隙形成） 内形 成包括多个导电的第一电极条 120的第一电极层 12。 在一个示例中， 所述凸 起物 110的厚度大于所述第一电极层 12的厚度。
55、 进行光刻胶剥离工艺， 将所述第一光刻胶图案剥离， 形成如图 7所 示的基板。
56、 在形成有所述第一电极层 12 的村底基板上制作绝缘层， 然后在制 作有所述绝缘层的基板上涂敷第二光刻胶 13b, 形成如图 8所示的基板。 在 这里需要说明的是， 所述绝缘层例如为栅绝缘层或钝化层。
57、 对所述第二光刻胶 13b进行灰化处理， 形成如图 9所示的第二光刻 胶图案 13c, 所述第二光刻胶图案 13c只覆盖所述凸起物 110的间隙。 58、如图 10所示，在所述形成有第二光刻胶图案 13c的基板上制作第二 透明导电薄膜 13a。
59、 通过光刻胶剥离工艺， 去除所述第二光刻胶图案 13c以及所述第二 光刻胶图案上的第二透明导电薄膜， 从而形成如图 2所示的包括多个导电的 第二电极条 130的第二电极层 13。
其中， 制作成的所述第一电极层与所述漏极连接， 或制作成的所述第二 电极层与所述漏极连接。 在这里需要说明的是， 无论第一电极层还是第二电 极层， 只要与公共电极线电连接的电极就为公共电极， 与薄膜晶体管的漏极 电连接的电极就为像素电极。
若所述制作成的第一电极层与所述漏极连接， 且所述第一电极层直接连 接所述漏极， 则所述制作方法包括： 在步骤 S1 后， 参考现有的制作工艺在 村底基板的非显示区域制作薄膜晶体管， 所述薄膜晶体管包括栅极、 栅绝缘 层、 有源层、 源极以及漏极。 然后依次进行步骤 S2-S5, 制作第一电极层， 所述第一电极层就可以直接制作在所述漏极上。 最后可以先制作钝化层再依 次进行步骤 S6-S10, 制作第二电极层。 此时， 所述绝缘层为钝化层。
若所述制作成的第一电极层与所述漏极连接， 且所述第一电极层通过所 述栅绝缘层上的过孔与所述漏极连接， 则所述制作方法包括： 首先依次进行 步骤 S1-S5 , 制作第一电极层。 然后参考现有的制作工艺在村底基板的非显 示区域制作薄膜晶体管， 所述薄膜晶体管包括栅极、 栅绝缘层、 有源层、 源 极以及漏极。 其中， 在制作栅绝缘层时， 可以通过构图工艺制作成包含有过 孔的栅绝缘层， 所述栅绝缘层的过孔形成在所述第一电极层的上方， 制作成 的漏极就可以通过所述栅绝缘层上的过孔与所述第一电极层连接。 最后可以 先制作钝化层再依次进行步骤 S6-S10, 制作第二电极层； 或者先依次进行步 骤 S6-S10, 制作第二电极层，再制作钝化层。此时， 所述绝缘层为栅绝缘层， 或者， 所述绝缘层为栅绝缘层和钝化层。
若所述制作成的第二电极层与所述漏极连接， 且所述第二电极层直接连 接所述漏极， 则所述制作方法包括： 首先依次进行步骤 S1-S5 , 制作第一电 极层， 再参考现有的制作工艺在村底基板的非显示区域制作薄膜晶体管， 所 述薄膜晶体管包括栅极、 栅绝缘层、 有源层、 源极以及漏极。 然后， 依次进 行步骤 S6-S10, 制作第二电极层， 所述第二电极层就可以直接制作在所述漏 极上。 最后制作钝化层。 此时， 所述绝缘层为栅绝缘层。
若所述制作成的第二电极层与所述漏极连接， 且所述第二电极层通过钝 化层上的过孔与所述漏极连接， 则所述制作方法包括： 先在村底基板上制作 第一电极层和薄膜晶体管， 然后在基板上制作钝化层薄膜， 并通过构图工艺 制作成包含有过孔的钝化层， 所述钝化层的过孔形成在所述漏极的上方。 最 后可以依次进行步骤 S6-S10, 制作第二电极层， 制作成的第二电极层可以通 过所述钝化层的过孔与所述漏极连接。 此时， 所述绝缘层为钝化层， 或者， 所述绝缘层为栅绝缘层和钝化层。
本发明实施例还提供了一种显示装置， 所述显示装置包括上述实施例的 的阵列基板， 所述显示装置可以为液晶显示器、 液晶电视、数码相机、 手机、 平板电脑等具有任何显示功能的产品或者部件。
在本发明上述实施例中， 所述凸起物与村底基板为各自独立地形成， 然 而在其他实施例中， 二者可以一体形成， 例如在村底基板的平坦表面上挖出 一个以上的凹槽。
本发明上述实施例提供的阵列基板及其制作方法、 显示装置， 通过在村 底基板上设置凸起物， 并将第一电极层设置在凸起物形成的凹槽内， 第二电 极层设置在凸起物的上方， 来实现公共电极和像素电极之间的零重叠； 而现 有技术中的阵列基板多如图 1所示，所述公共电极 1与像素电极 2交错设置， 由于像素电极 1和公共电极 2均采用透明电极材料， 这就需要通过较复杂制 作工艺和较高的制作成本来精确地保证了两个电极层之间的零重叠。 与现有 技术相比， 本发明利用村底基板上的凸起物， 就可以精确地保证了两个电极 层之间的零重叠， 降低制作成本和制作工艺的难度。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板， 包括多个栅线、 多个数据线以及所述多个栅线和所述 多个数据线交叉限定的多个像素区域,每一个所述像素区域包括薄膜晶体管， 还包括：
村底基板； 间隔设置在村底基板上的一个以上凸起物；
第一电极层， 所述第一电极层包括至少一个第一电极条， 所述第一电极 条设置在相邻凸起物的间隙中；
第二电极层， 所述第二电极层包括至少一个第二电极条， 所述第二电极 条设置在所述凸起物上方。
2、 根据权利要求 1或 2所述的阵列基板， 所述像素区域还包括绝缘层， 设置在所述第一电极层和所述第二电极层之间。
3、根据权利要求 1或 2所述的阵列基板，其中所述村底基板上的一个以 上凸起物是等间距设置的。
4、 根据权利要求 1-3任意一项所述的阵列基板， 其中， 所述凸起物为多 个， 该多个凸起物之间的每个间隙内都设置有所述第一电极条， 每个所述凸 起物的上方都设置有所述第二电极条。
5、根据权利要求 1-4任意一项所述的阵列基板， 其中所述薄膜晶体管包 括栅极、 栅绝缘层、 有源层、 源极以及漏极。
6、根据权利要求 5所述的阵列基板，其中所述栅绝缘层设置在所述第一 电极层和所述第二电极层之间；
所述第一电极层通过所述栅绝缘层上的过孔与所述漏极连接。
7、 根据权利要求 5所述的阵列基板， 其中所述阵列基板还包括钝化层， 所述栅绝缘层设置在所述第一电极层的下方， 所述钝化层设置在所述第一电 极层和所述第二电极层之间；
所述第一电极层直接与所述漏极连接。
8、 根据权利要求 5所述的阵列基板， 其中所述阵列基板还包括钝化层， 所述钝化层设置在所述第一电极层和所述第二电极层之间；
所述第二电极层通过钝化层上的过孔与所述漏极连接。
9、 根据权利要求 5所述的阵列基板， 其中所述阵列基板还包括钝化层， 所述栅绝缘层设置在所述第一电极层和所述第二电极层之间， 所述钝化层设 置在所述第二电极层的上方；
所述第二电极层直接连接所述漏极。
10、 根据权利要求 1-9任意一项所述的阵列基板， 其中所述凸起物的材 料为透明树脂材料， 且所述凸起物的厚度大于所述第一电极层的厚度。
11、 一种阵列基板的制作方法， 包括在村底基板上制作栅线、 数据线以 及薄膜晶体管所述制作方法还包括：
在村底基板上形成间隔设置的一个以上凸起物；
形成第一电极层， 所述第一电极层包括至少一个第一电极条， 所述第一 电极条设置在相邻凸起物的间隙中；
形成第二电极层， 所述第二电极层包括至少一个第二电极条， 所述第二 电极条设置在所述凸起物上方。
12、根据权利要求 11所述的制作方法，还包括在所述第一电极层和第二 电极层之间制作绝缘层。
13、 根据权利要求 12所述的制作方法， 包括：
在村底基板上制作间隔设置的一个以上凸起物；
在形成有所述凸起物的基板上制作第一透明导电薄膜， 并在制作有所述 第一透明导电薄膜的基板上涂敷第一光刻胶；
对所述第一光刻胶进行灰化处理， 形成第一光刻胶图案， 所述第一光刻 胶图案只覆盖所述凸起物的间隙；
进行刻蚀工艺， 除去所述第一光刻胶图案未覆盖的第一透明导电薄膜； 进行光刻胶剥离工艺， 将所述第一光刻胶图案剥离， 从而形成包括至少 一个第一电极条的第一电极层；
在形成有所述第一电极层的村底基板上制作绝缘层；
在制作有所述绝缘层的基板上涂敷第二光刻胶,对所述光刻胶进行灰化 处理，形成第二光刻胶图案，所述第二光刻胶图案只覆盖所述凸起物的间隙； 在所述形成有第二光刻胶图案的基板上制作第二透明导电薄膜， 然后通 过光刻胶剥离工艺， 去除所述第二光刻胶图案以及位于所述第二光刻胶图案 上的第二透明导电薄膜， 从而形成包括至少一个第二电极条的第二电极层。
14、 根据权利要求 12-13任意一项所述的制作方法， 其中所述薄膜晶体 管包括栅极、 栅绝缘层、 有源层、 源极以及漏极，
所述绝缘层包括栅绝缘层或钝化层中的至少一个；
所述第一电极层与所述漏极连接， 或所述第二电极层与所述漏极连接。
15、 根据权利要求 11-14任意一项所述的制作方法， 其中制作在村底基 板上的凸起物是等间距的。
16、 根据权利要求 11-15任意一项所述的制作方法， 其中所述凸起物的 材料为透明树脂材料， 且所述凸起物的厚度大于所述第一电极层的厚度。
17、 一种显示装置， 包括权利要求 1-10任一项所述的阵列基板。
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