CN102779783B - 一种像素结构及其制造方法、显示装置 - Google Patents

一种像素结构及其制造方法、显示装置 Download PDF

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CN102779783B
CN102779783B CN201210181978.3A CN201210181978A CN102779783B CN 102779783 B CN102779783 B CN 102779783B CN 201210181978 A CN201210181978 A CN 201210181978A CN 102779783 B CN102779783 B CN 102779783B
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photoresist
tft
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CN102779783A (zh
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沈奇雨
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to PCT/CN2012/087157 priority patent/WO2013181915A1/zh
Priority to JP2015514320A priority patent/JP6188793B2/ja
Priority to KR1020137008367A priority patent/KR101467710B1/ko
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Abstract

本发明提供了一种像素结构及其制造方法、显示装置，所述方法包括：通过第一道掩模板工艺形成栅极线后，依次进行栅绝缘(GI)层、钝化(PVX)层的镀膜；通过第二道掩模板工艺，得到TFT漏极、像素电极和位于所述TFT漏极之上的半导体层；通过第三道掩模板工艺，得到TFT源极以及TFT源极和漏极之间的半导体沟道。本发明通过三道掩模板工艺即可制得需要的像素结构，并且在制造过程中未改变TFT的特性，实现工艺过程最简化，节省制造成本，有利于阵列基板的推广应用。

Description

一种像素结构及其制造方法、显示装置
技术领域
本发明涉及阵列基板技术领域，尤其涉及一种像素结构及其制造方法、显示装置。
背景技术
薄膜场效应晶体管液晶显示装置（Thin Film Transis-Liquid Crystal Display，TFT-LCD）具有体积小、功耗低、无辐射等优点，在当前的平板显示器市场占据了主导地位。TFT-LCD器件是由阵列基板和彩膜基板对盒形成。在阵列基板中相互交叉地配置定义像素区域的栅极线和信号线，在各像素区域中配置了像素电极和薄膜晶体管（TFT）。将驱动信号施加到栅极线上，图像数据通过信号线施加到像素电极。在彩膜基板上配置黑底，使光不能透过像素电极之外的区域，在各像素区域配置滤色层，在此基础上配置公共电极；然后在阵列基板和彩膜基板之间充入液晶，通过如上加载驱动信号的像素电极的电压来控制液晶的偏转，进而控制光线的强弱，配合彩膜基板显示所要表达的图像。
然而传统的阵列基板一般采用五道掩模板（5Mask）或四道掩模板（4Mask）工艺制造过程，采用5Mask或4Mask工艺制造出来的阵列基板，由于制造过程中掩模板数量较多，投入的开发费用较大；而且产线由于制造工艺的复杂，需要配套大量的产线进行生产，增加了产线的投入成本。
发明内容
有鉴于此，本发明的主要目的在于提供一种像素结构及其制造方法、显示装置，能够降低像素结构制作的复杂度。
为达到上述目的，本发明的技术方案是这样实现的：
本发明提供了一种像素结构制造方法，所述方法包括：
在玻璃基板上沉积金属膜，通过第一道掩模板工艺形成栅极和栅极线，依次进行栅绝缘GI层、钝化PVX层的镀膜；
依次进行铟锡金属氧化物ITO层、源漏SD金属层、欧姆接触层的沉积，通过第二道掩模板工艺，形成薄膜晶体管TFT漏极、像素电极和位于所述TFT漏极之上的欧姆接触层；
依次进行半导体层、欧姆接触层、SD金属层的沉积，通过第三道掩模板工艺，形成TFT源极以及TFT源极和漏极之间的半导体沟道。
上述方案中，所述通过第二道掩模板工艺，形成TFT漏极、像素电极和位于所述TFT漏极之上的欧姆接触层为：
在沉积的欧姆接触层上涂覆光刻胶，形成无光刻胶区域、第一厚度光刻胶区域、以及第二厚度光刻胶区域；
进行第二道掩模板工艺，形成TFT漏极、像素电极和位于所述TFT漏极之上的欧姆接触层；
其中，所述第一厚度光刻胶区域为所述TFT漏极上方的区域，所述第二厚度光刻胶区域为所述像素电极上方的区域，除去所述第一厚度光刻胶区域和所述第二厚度光刻胶区域的其他区域为无光刻胶区域。
上述方案中，所述光刻胶的第一厚度和第二厚度的关系a/3≤b≤a/2；其中，a为第一厚度，b为第二厚度；
所述进行第二道掩模板工艺，形成TFT漏极、像素电极和位于所述TFT漏极之上的欧姆接触层为：
进行干法刻蚀，将无光刻胶区域的欧姆接触层刻蚀掉；再进行SD金属层的湿法刻蚀，将无光刻胶区域的SD金属层刻蚀掉；最后进行ITO层湿法刻蚀，将像素电极以外的ITO层刻蚀掉；
进行光刻胶的灰化，将第二厚度光刻胶区域的光刻胶灰化掉，露出第二厚度光刻胶覆盖的区域，并依次对所述区域的欧姆接触层进行干法刻蚀掉，对SD金属层进行湿法刻蚀；
将剩余的光刻胶进行剥离，得到TFT漏极、像素电极和位于所述TFT漏极之上的欧姆接触层。
上述方案中，所述通过第三道掩模板工艺，形成TFT源极以及TFT源极和漏极之间的半导体沟道：
在沉积的SD金属层上涂覆光刻胶，形成无光刻胶区域、第三厚度光刻胶区域、以及第四厚度光刻胶区域；
进行第三道掩模板工艺，形成TFT源极、所述TFT源极与漏极之间的半导体沟道；
其中，所述第三厚度光刻胶区域为所述TFT源极上方以及所述TFT源极和漏极之间区域上方的区域；所述第四厚度光刻胶区域为所述TFT漏极上方的区域；除去所述第三厚度光刻胶区域和所述第四厚度光刻胶区域的其他区域为无光刻胶区域。
上述方案中，所述光刻胶的第三厚度和第四厚度的关系为c/3≤d≤c/2；其中，c为第三厚度，d为第四厚度；
所述进行第三道掩模板工艺，形成TFT源极、所述TFT源极与漏极之间的半导体沟道为：
进行SD金属层的湿法刻蚀，将无光刻胶区域的SD金属层刻蚀掉；然后对所述欧姆接触层、半导体层进行干法刻蚀，保留下被光刻胶覆盖的膜层；
进行光刻胶的灰化，将第四厚度光刻胶区域的光刻胶灰化掉，露出第四厚度光刻胶覆盖的区域，并依次对所述区域的SD金属层和欧姆接触层分别进行刻蚀；
将剩余的光刻胶进行剥离，得到TFT源极以及TFT源极和漏极之间的半导体沟道。
上述方案中，所述a或c的取值范围为2.1um～2.7um。
本发明还提供了一种像素结构，包括TFT和像素电极，所述像素结构是利用前面所述方法制作得到的像素结构，其中，
所述TFT的半导体沟道包括位于TFT漏极上方的第一欧姆接触层、位于TFT源极下方的第二欧姆接触层、以及位于所述第一欧姆接触层和所述第二欧姆接触层之间的半导体层。
本发明还提供了一种阵列基板，所述阵列基板包括像素结构，所述像素结构是前面所述的像素结构。
本发明还提供了一种显示装置，所述显示装置包括前面所述的阵列基板。
本发明通过三道掩模板工艺即可制得需要的像素结构，并且在制造过程中未改变TFT的特性，实现工艺过程最简化，节省制造成本，有利于阵列基板的推广应用。
附图说明
图1为本发明像素结构制造方法的实现流程示意图；
图2为本发明像素结构制造方法中第一道掩模板完成后像素结构的剖面将结构示意图；
图3为基于图2所示结构形成GI层和PVX层后像素结构的剖面结构示意图；
图4为本发明像素结构制造方法中进行第二道掩模板工艺时像素结构的剖面结构示意图；
图5为本发明像素结构制造方法中完成第二道掩模板工艺后像素结构的剖面结构示意图；
图6为本发明像素结构制造方法中进行第三道掩模板工艺时像素结构的剖面结构示意图；
图7为本发明像素结构制造方法中完成第三道掩模板工艺后像素结构的剖面结构示意图。
附图标记说明：
1-玻璃基板；2-栅极线；3-GI层；4-PVX层；5-ITO层；6-SD1；7-n+a-Si半导体层；8-a-Si半导体层；9-n+a-Si半导体层；10-SD2；11-公共电极；12-厚度为a的光电胶；13-厚度为b的光电胶；14-厚度为c的光电胶；15-厚度为d的光电胶。
具体实施方式
本发明的基本思想为：在玻璃基板上沉积金属膜，通过第一道掩模板工艺形成栅极和栅极线，进行栅绝缘（GI）层、钝化（PVX）层的镀膜；依次进行铟锡金属氧化物（ITO）层、源漏（SD）金属层、欧姆接触层的沉积，通过第二道掩模板工艺，形成TFT漏极、像素电极和位于所述TFT漏极之上的欧姆接触层；依次进行半导体层、欧姆接触层、SD金属层的镀膜，通过第三道掩模板工艺，形成TFT源极以及TFT源极和漏极之间的半导体沟道。
为使本发明的目的、技术方案和优点更加清楚明白，以下举实施例并参照附图，对本发明进一步详细说明。
图1示出了本发明像素结构制造方法的实现流程，如图1所示，所述方法包括下述步骤：
步骤101，在玻璃基板上沉积金属膜，通过第一道掩模板工艺形成栅极和栅极线，依次进行GI层、PVX层的镀膜；
具体地，参照图2示出的第一道掩模板完成后像素结构的剖面结构，本步骤具体为首先在玻璃基板1上镀一层金属膜，再进行Mask工艺，形成所需的栅极和栅极线2及公共电极线11的图形；再进行湿法刻蚀，完成所需图形的成形，最后进行剥离，形成最终所需要的图形；具体工艺过程同5Mask或4Mask工艺，不再赘述。
在图2所示的阵列基板基础上进行GI层和PVX层的成膜，其工艺过程只需要成膜的工艺，具体与正常的GI层与PVX层的形成一样。首先镀一层GI膜：SiNx介质，如图3中标注3所示；再镀一层PVX膜，介质材料仍为SiNx，如图3中标注4所示。GI层和PVX层的膜镀完成后当前层不再需要Mask工艺。
步骤102，依次进行铟锡金属氧化物（ITO）层、SD金属层、欧姆接触层的沉积，通过第二道掩模板工艺，形成TFT漏极、像素电极和位于所述TFT漏极之上的欧姆接触层；
这里，所述欧姆接触层具体可以为n+a-Si半导体层；具体地，参照图4，依次进行ITO层5、源漏金属层SD16、n+a-Si半导体层7的沉积；在沉积的n+a-Si半导体层7上涂覆光刻胶，形成无光刻胶区域、第一厚度光刻胶区域、以及第二厚度光刻胶区域；进行第二道掩模板工艺，形成TFT漏极、像素电极和位于所述TFT漏极之上的n+a-Si半导体层；
其中，所述第一厚度光刻胶区域为所述TFT漏极上方的区域，所述第二厚度光刻胶区域为所述像素电极上方的区域，除去所述第一厚度光刻胶区域和所述第二厚度光刻胶区域的其他区域为无光刻胶区域；具体如图4所示，在所述TFT漏极上方覆盖厚度为a的光刻胶12，在所述像素电极上方覆盖厚度为b的光刻胶13；其中，所述a/3≤b≤a/2，所述a的取值范围可以为2.1um～2.7um；
所述进行第二道掩模板工艺，形成TFT漏极、像素电极和位于所述TFT漏极之上的n+a-Si半导体层为：
进行干法刻蚀，将无光刻胶区域的n+a-Si半导体层7刻蚀掉；再进行SD16的湿法刻蚀，将无光刻胶区域的SD16刻蚀掉；最后进行ITO层5湿法刻蚀，将像素电极以外的ITO层5刻蚀掉；进行光刻胶的灰化（ashing），将第二厚度光刻胶区域的光刻胶即厚度为b的光刻胶13灰化掉，露出所述厚度为b的光刻胶13覆盖的区域，并依次对所述区域的n+a-Si半导体层7进行干法刻蚀掉，对SD16进行湿法刻蚀;这里，由于a/3≤b≤a/2，因此，厚度为b的光刻胶13灰化掉后，厚度为a的光刻胶12还会有部分剩余，将剩余的光刻胶进行剥离，得到TFT漏极、像素电极和位于所述TFT漏极之上的半导体层，如图5所示。此时，图5中的标注6为TFT漏极，标注5为像素电极，标注7为位于所述TFT漏极6之上的半导体层。
步骤103，依次进行半导体层、欧姆接触层、SD金属层的沉积，通过第三道掩模板工艺，形成TFT源极以及TFT源极和漏极之间的半导体沟道；
这里，所述半导体层具体可以为a-Si半导体层，所述欧姆接触层具体可以为n+a-Si半导体层；具体地，参照图6，依次进行a-Si半导体层8、n+a-Si半导体层9、SD210的镀膜；在沉积的SD210上涂覆光刻胶，形成无光刻胶区域、第三厚度光刻胶区域、以及第四厚度光刻胶区域；进行第三道掩模板工艺，形成TFT源极、所述TFT源极与漏极之间的半导体沟道；
其中，所述第三厚度光刻胶区域为所述TFT源极上方以及所述TFT源极和漏极之间区域上方的区域；所述第四厚度光刻胶区域为所述TFT漏极上方的区域；除去所述第三厚度光刻胶区域和所述第四厚度光刻胶区域的其他区域为无光刻胶区域。具体如图6所示，在所述TFT源极上方覆盖厚度为c的光刻胶14，在所述TFT源极与漏极之间区域和所述TFT漏极的上方覆盖厚度为d的光刻胶15；其中，所述c/3≤d≤c/2，所述c的取值范围可以为2.1um～2.7um；
所述进行第三道掩模板工艺，形成TFT源极、所述TFT源极与漏极之间的半导体沟道具体为：
进行SD210的湿法刻蚀，将无光刻胶区域的SD210刻蚀掉；然后对所述n+a-Si半导体层9、a-Si半导体层8进行干法刻蚀，保留下被光刻胶覆盖的膜层；进行光刻胶的灰化，将第四厚度光刻胶区域的光刻胶即厚度为d的光刻胶15灰化掉，露出所述厚度为d的光刻胶15覆盖的区域，并依次对所述区域的SD210和n+a-Si半导体层9分别进行刻蚀；这里，由于c/3≤d≤c/2，因此，厚度为d的光刻胶15灰化掉后，厚度为c的光刻胶14还会有部分剩余，将剩余的光刻胶进行剥离，得到TFT源极以及TFT源极和漏极之间的半导体沟道，如图7所示，此时，图7中的标注10即为TFT的源极，标注6为TFT的漏极，标注9、8、7构成源极10和漏极6之间的半导体沟道，由图7看出，半导体沟道中各层不在一个平面上，而为立体式分布关系。
本发明还提供一种像素结构，包括TFT和像素电极，且所述像素结构为利用如上所述方法制作得到的像素结构，其中，
所述TFT的半导体沟道包括位于TFT漏极上方的第一欧姆接触层、位于TFT源极下方的第二欧姆接触层、以及位于所述第一欧姆接触层和所述第二欧姆接触层之间的半导体层；其中，所述第一欧姆接触层和第二欧姆接触层具体可以为n+a-Si半导体层；所述半导体层具体可以为a-Si半导体层；
具体可参考图7，其中，上述第一欧姆接触层具体为图7中的n+a-Si半导体层7，第二欧姆接触层具体为图7中的n+a-Si半导体层9，半导体层具体可以为图7中的a-Si半导体层8；
n+a-Si半导体层7位于TFT漏极6的上方，n+a-Si半导体层9位于TFT源极10的下方，a-Si半导体层8位于n+a-Si半导体层7和n+a-Si半导体层9之间，因此，组成TFT半导体沟道中各层不在一个平面上，而为立体式分布关系。
本发明还提供一种阵列基板，所述阵列基板包括为如上所述的像素结构。
本发明还提供了一种显示装置，所述显示装置包括如上所述的阵列基板。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (7)

1.一种像素结构制造方法，其特征在于，所述方法包括：
在玻璃基板上沉积金属膜，通过第一道掩模板工艺形成栅极和栅极线，依次进行栅绝缘GI层、钝化PVX层的镀膜；
依次进行铟锡金属氧化物ITO层、第一源漏SD金属层、第一欧姆接触层的沉积，通过第二道掩模板工艺，形成薄膜晶体管TFT漏极、像素电极和位于所述TFT漏极之上的第一欧姆接触层；
依次进行半导体层、第二欧姆接触层、第二SD金属层的沉积，通过第三道掩模板工艺，形成TFT源极以及TFT源极和漏极之间的半导体沟道；其中，
所述通过第二道掩模板工艺，形成TFT漏极、像素电极和位于所述TFT漏极之上的第一欧姆接触层为：
在沉积的第一欧姆接触层上涂覆光刻胶，形成无光刻胶区域、第一厚度光刻胶区域、以及第二厚度光刻胶区域，
进行第二道掩模板工艺，形成TFT漏极、像素电极和位于所述TFT漏极之上的第一欧姆接触层，
其中，所述第一厚度光刻胶区域为所述TFT漏极上方的区域，所述第二厚度光刻胶区域为所述像素电极上方的区域，除去所述第一厚度光刻胶区域和所述第二厚度光刻胶区域的其他区域为无光刻胶区域；
所述通过第三道掩模板工艺，形成TFT源极以及TFT源极和漏极之间的半导体沟道为：
在沉积的第二SD金属层上涂覆光刻胶，形成无光刻胶区域、第三厚度光刻胶区域、以及第四厚度光刻胶区域，
进行第三道掩模板工艺，形成TFT源极、所述TFT源极与漏极之间的半导体沟道，
其中，所述第三厚度光刻胶区域为所述TFT源极上方的区域；所述第四厚度光刻胶区域为所述TFT漏极上方以及所述TFT源极和漏极之间区域上方的区域，除去所述第三厚度光刻胶区域和所述第四厚度光刻胶区域的其他区域为无光刻胶区域。
2.根据权利要求1所述的方法，其特征在于，所述光刻胶的第一厚度和第二厚度的关系a/3≤b≤a/2；其中，a为第一厚度，b为第二厚度；
所述进行第二道掩模板工艺，形成TFT漏极、像素电极和位于所述TFT漏极之上的第一欧姆接触层为：
进行干法刻蚀，将无光刻胶区域的第一欧姆接触层刻蚀掉；再进行第一源漏SD金属层的湿法刻蚀，将无光刻胶区域的第一源漏SD金属层刻蚀掉；最后进行ITO层湿法刻蚀，将像素电极以外的ITO层刻蚀掉；
进行光刻胶的灰化，将第二厚度光刻胶区域的光刻胶灰化掉，露出第二厚度光刻胶覆盖的区域，并依次对露出的所述第二厚度光刻胶覆盖的区域的第一欧姆接触层进行干法刻蚀掉，对第一源漏SD金属层进行湿法刻蚀；
将剩余的光刻胶进行剥离，得到TFT漏极、像素电极和位于所述TFT漏极之上的第一欧姆接触层。
3.根据权利要求1所述的方法，其特征在于，所述光刻胶的第三厚度和第四厚度的关系为c/3≤d≤c/2；其中，c为第三厚度，d为第四厚度；
所述进行第三道掩模板工艺，形成TFT源极、所述TFT源极与漏极之间的半导体沟道为：
进行第二SD金属层的湿法刻蚀，将无光刻胶区域的第二SD金属层刻蚀掉；然后对所述第二欧姆接触层、半导体层进行干法刻蚀，保留下被光刻胶覆盖的膜层；
进行光刻胶的灰化，将第四厚度光刻胶区域的光刻胶灰化掉，露出第四厚度光刻胶覆盖的区域，并依次对露出的所述第四厚度光刻胶覆盖的区域的第二SD金属层和第二欧姆接触层分别进行刻蚀；
将剩余的光刻胶进行剥离，得到TFT源极以及TFT源极和漏极之间的半导体沟道。
4.根据权利要求1至3中任一项所述的方法，其特征在于，a或c的取值范围为2.1um～2.7um。
5.一种像素结构，包括TFT和像素电极，其特征在于，所述像素结构是利用权利要求1至4中任一项所述方法制作得到的像素结构，其中，
所述TFT的半导体沟道包括位于TFT漏极上方的第一欧姆接触层、位于TFT源极下方的第二欧姆接触层、以及位于所述第一欧姆接触层和所述第二欧姆接触层之间的半导体层。
6.一种阵列基板，其特征在于，所述阵列基板包括像素结构，所述像素结构是如权利要求5所述的像素结构。
7.一种显示装置，其特征在于，所述显示装置包括如权利要求6所述的阵列基板。
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