CN103309095B - 一种阵列基板及其制作方法、显示装置 - Google Patents

一种阵列基板及其制作方法、显示装置 Download PDF

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CN103309095B
CN103309095B CN201310211125.4A CN201310211125A CN103309095B CN 103309095 B CN103309095 B CN 103309095B CN 201310211125 A CN201310211125 A CN 201310211125A CN 103309095 B CN103309095 B CN 103309095B
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CN103309095A (zh
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崔承镇
金熙哲
宋泳锡
刘聖烈
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BOE Technology Group Co Ltd
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Abstract

本发明实施例提供了一种阵列基板及其制作方法、显示装置，涉及液晶显示领域，可以实现公共电极和像素电极之间的零重叠，进而提高显示装置的显示质量。所述阵列基板，包括栅线、数据线以及所述栅线和所述数据线交叉限定的像素区域，所述像素区域包括薄膜晶体管，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极以及漏极；所述像素区域还包括：衬底基板；间隔设置在衬底基板上的凸起物；第一电极层，所述第一电极层包括至少一个电连接的第一电极条，所述第一电极条设置在所述凸起物的间隙中；第二电极层，所述第二电极层包括至少一个电连接的第二电极条，所述第二电极条设置在所述凸起物上方。

Description

一种阵列基板及其制作方法、显示装置
技术领域
本发明涉及液晶显示器领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
现有技术中常见的液晶显示装置主要有AD-SDS(Advanced-SuperDimensional Switching，简称为ADS，高级超维场开关)型、IPS(InPlane Switch，横向电场效应)型以及TN(Twist Nematic，扭曲向列)型。其中，ADS型显示装置通过同一平面内像素电极边缘所产生的平行电场以及像素电极层与公共电极层间产生的纵向电场形成多维电场，使液晶盒内像素电极间、电极正上方所有取向液晶分子都能够产生旋转转换。
现有的ADS型显示装置中由于像素电极和公共电极的重叠面积大且间距小，从而导致存储电容Cst非常大，因此在设计时会受到很多限制。目前为了解决Cst过大的问题，通常都采取像素电极和公共电极交错排列的方式，但一般情况下，由于像素电极和公共电极均采用透明电极材料制成交错排列的方式非常要求曝光工艺的精确度，这样无疑会增加设备以及工艺控制的难度和成本。
发明内容
本发明的实施例提供一种阵列基板及其制作方法、显示装置，可以降低制作成本和制作工艺的难度。
为达到上述目的，本发明的实施例采用如下技术方案：
一种阵列基板，包括栅线、数据线以及所述栅线和所述数据线交叉限定的像素区域，所述像素区域包括薄膜晶体管，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极以及漏极；所述像素区域还包括：
衬底基板；间隔设置在衬底基板上的凸起物；
第一电极层，所述第一电极层包括至少一个电连接的第一电极条，所述第一电极条设置在所述凸起物的间隙中；
第二电极层，所述第二电极层包括至少一个电连接的第二电极条，所述第二电极条设置在所述凸起物上方。
优选的，所述衬底基板上的凸起物是等间距设置的。
优选的，所述凸起物的材料为透明树脂材料，且所述凸起物的厚度大于所述第一电极层的厚度。
优选的，每个所述凸起物的间隙内都设置有所述第一电极条，每个所述凸起物的上方都设置有所述第二电极条。
可选的，所述栅绝缘层设置在所述第一电极层和所述第二电极层之间；
所述第一电极层通过所述栅绝缘层上的过孔与所述漏极连接。
可选的，所述阵列基板还包括钝化层，所述栅绝缘层设置在所述第一电极层的下方，所述钝化层设置在所述第一电极层和所述第二电极层之间；
所述第一电极层直接与所述漏极连接。
可选的，所述阵列基板还包括钝化层，所述钝化层设置在所述第一电极层和所述第二电极层之间；
所述第二电极层通过钝化层上的过孔与所述漏极连接。
可选的，所述阵列基板还包括钝化层，所述栅绝缘层设置在所述第一电极层和所述第二电极层之间，所述钝化层设置在所述第二电极层的上方；
所述第二电极层直接连接所述漏极。
一种阵列基板的制作方法，包括在所述阵列基板上制作栅线、数据线以及薄膜晶体管，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极以及漏极；其特征在于，所述阵列基板的制作方法还包括：
在衬底基板上制作间隔设置的凸起物；
在基板上制作第一透明导电薄膜，并在制作有所述第一透明导电薄膜的基板上涂敷第一光刻胶；
对所述第一光刻胶进行灰化处理，形成第一光刻胶图案，所述第一光刻胶图案只覆盖所述凸起物的间隙；
进行刻蚀工艺，除去所述第一光刻胶图案未覆盖的第一透明导电薄膜；
进行光刻胶剥离工艺，将所述第一光刻胶图案剥离，从而形成包括至少一个电连接的第一电极条的第一电极层；
在形成有所述第一电极层的基板上制作绝缘层；
在制作有所述绝缘层的基板上涂敷第二光刻胶，对所述光刻胶进行灰化处理，形成第二光刻胶图案，所述第二光刻胶图案只覆盖所述凸起物的间隙；
在所述形成有第二光刻胶图案的基板上制作第二透明导电薄膜，然后通过光刻胶剥离工艺，去除所述第二光刻胶图案以及位于所述第二光刻胶图案上的第二透明导电薄膜，从而形成包括多个电连接的第二电极条的第二电极层。
可选的，所述绝缘层包括栅绝缘层或钝化层中的至少一个；
制作成的所述第一电极层与所述漏极连接，或制作成的所述第二电极层与所述漏极连接。
优选的，制作在衬底基板上的凸起物是等间距的。
优选的，所述凸起物的材料为透明树脂材料，且所述凸起物的厚度大于所述第一电极层的厚度。
一种显示装置，所述显示装置包括上述的阵列基板。
本发明实施例提供的阵列基板及其制作方法、显示装置，通过在衬底基板上设置凸起物，并将第一电极层设置在凸起物形成的凹槽内，第二电极层设置在凸起物的上方，来实现公共电极和像素电极之间的零重叠；而现有技术中的阵列基板多如图1所示，所述公共电极1与像素电极2交错设置，由于像素电极1和公共电极2均采用透明电极材料，这就需要通过较复杂制作工艺和较高的制作成本来精确地保证了两个电极层之间的零重叠。与现有技术相比，本发明利用衬底基板上的凸起物，就可以精确地保证了两个电极层之间的零重叠，降低制作成本和制作工艺的难度。
附图说明
图1为现有技术中的一种阵列基板的剖面结构示意图；
图2为本发明实施例提供的一种阵列基板的剖面基板结构示意图；
图3为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第一种剖面结构的示意图；
图4为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第二种剖面结构的示意图；
图5为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第三种剖面结构的示意图；
图6为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第四种剖面结构的示意图；
图7为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第五种剖面结构的示意图；
图8为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第六种剖面结构的示意图；
图9为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第七种剖面结构的示意图；
图10为本发明实施例提供的阵列基板制作方法过程中的阵列基板的第八种剖面结构的示意图。
附图标记：
1-公共电极，2-像素电极；11-衬底基板，12-第一电极层，13-第二电极层，110-凸起物，120-第一电极条，130-第二电极条，12a-第一透明导电薄膜，12b-第一光刻胶，12c-第一光刻胶图案，13b-第二光刻胶，13a-第二透明导电薄膜，13c-第二光刻胶图案。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。
本发明实施例提供了一种阵列基板，所述阵列基板包括栅线、数据线以及所述栅线和所述数据线交叉限定的像素区域，所述像素区域包括薄膜晶体管，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极以及漏极。如图2所示，所述像素区域包括：衬底基板11，所述衬底基板11上设置有凸起物110；第一电极层12，所述第一电极层12包括至少一个电连接的第一电极条120，所述第一电极条120设置在所述凸起物110的间隙中；第二电极层13，所述第二电极层13包括至少一个电连接的第二电极条130，所述第二电极条130设置在所述凸起物110的上方。
本发明实施例提供的阵列基板，通过将阵列基板的衬底基板设置成带有凹槽的衬底基板，并将第一电极层设置在凹槽内，第二电极层设置在凹槽外，这样利用衬底基板上的凸起物，就可以精确地保证了两个电极层之间的零重叠，降低制作成本和制作工艺的难度。
优选的，所述衬底基板上设置的凸起物110是等间距的。
优选的，所述凸起物110的深度大于所述第一电极层的厚度。
优选的，如图2所示，各个凸起物110的间隙内都设置有所述第一电极条120，每个所述凸起物的上方都设置有所述第二电极条130。
本发明实施例提供的阵列基板中，所述第一电极层和所述第二电极层中有一个电极层要作为像素电极与漏极连接。可以是所述第一电极层与所述漏极连接，也可以是所述第二电极层与所述漏极连接。在这里需要说明的是，无论第一电极层还是第二电极层，只要与公共电极线电连接的电极就为公共电极，与薄膜晶体管的漏极电连接的电极就为像素电极。
可选的，所述第一电极层可以与所述漏极连接，即第一电极层为像素电极，所述第二电极层为公共电极，此时可以有以下两种情况：
一种情况为：所述第一电极层直接连接所述漏极，此种情况下，所述阵列基板上先制作有薄膜晶体管，再依次制作第一电极层、钝化层和第二电极层，所述第一电极层与所述第二电极层之间设置有钝化层。此时，所述第一电极层位于所述栅绝缘层的上方，所述第一电极层与所述漏极之间没有其他层级结构，所述第一电极层可以直接搭接在所述漏极上。另一种情况为：所述第一电极层通过所述栅绝缘层上的过孔与所述漏极连接，此种情况下，所述阵列基板上先制作第一电极层再制作薄膜晶体管，然后制作钝化层和第二电极层。所述第一电极层与所述第二电极层之间设置有栅绝缘层。此时，所述栅绝缘层位于所述第一电极层上方，在所述栅绝缘层上制作过孔，所述栅绝缘层上的过孔在所述第一电极层的上方，所述漏极可以通过所述栅绝缘层上的过孔与所述第一电极层连接。
可选的，所述第二电极层也可以与所述漏极连接，即第二电极层为像素电极，所述第一电极层为公共电极，此时可以有以下两种情况：
一种情况为：所述第二电极层通过钝化层上的过孔与所述漏极连接，此种情况下，所述阵列基板上先制作钝化层再制作第二电极层，所述第二电极层位于所述钝化层上方，所述钝化层上的过孔在所述漏极的上方，所述第二电极层可以通过所述钝化层上的过孔与所述第二电极层连接。另一种情况为：所述第二电极层直接连接所述漏极，此种情况下，所述阵列基板上先制作第一电极层再制作薄膜晶体管，然后依次制作第二电极层和钝化层，所述第二电极层位于所述钝化层下方，所述第二电极层与所述漏极之间没有其他层级结构，所述第二电极层可以直接搭接在所述漏极上。
本发明实施例还提供了一种阵列基板的制作方法，本发明实施例提供的阵列基板的非显示区域处的栅线、数据线以及薄膜晶体管的制作工艺可以参考现有的制作工艺；所述阵列基板的显示区域处的两个电极层的制作制作方法包括以下步骤：
S1、如图3所示，在衬底基板11上制作树脂层，然后通过一次构图工艺在衬底基板11上形成凸起物，优选的，所述衬底基板11上的凸起物110是等间距的。
S2、如图4所示，在基板上制作第一透明导电薄膜12a，并在制作有所述第一透明导电薄膜12a的基板上涂敷第一光刻胶12b。
S3、如图5所示，对所述第一光刻胶12b进行灰化处理，形成第一光刻胶图案12c，所述第一光刻胶图案12c只覆盖所述凸起物110的间隙。
S4、进行刻蚀工艺，除去所述第一光刻胶图案12c未覆盖的第一透明导电薄膜，如图6所示，在基板的凹槽内形成包括多个电连接的第一电极条120的第一电极层12。优选的，所述凸起物110的厚度大于所述第一电极层12的厚度。
S5、进行光刻胶剥离工艺，将所述第一光刻胶图案剥离，形成如图7所示的基板。
S6、在形成有所述第一电极层的基板上制作绝缘层，然后在制作有所述绝缘层的基板上涂敷第二光刻胶13b，形成如图8所示的基板。在这里需要说明的是，所述绝缘层包括栅绝缘层或钝化层中的至少一个。
S7、对所述第二光刻胶13b进行灰化处理，形成如图9所示的第二光刻胶图案13c，所述第二光刻胶图案13c只覆盖所述凸起物110的间隙。
S8、如图10所示，在所述形成有第二光刻胶图案13c的基板上制作第二透明导电薄膜13a。
S9、通过光刻胶剥离工艺，去除所述第二光刻胶图案13c以及所述第二光刻胶图案上的第二透明导电薄膜，从而形成如图2所示的包括多个电连接的第二电极条130的第二电极层13。
其中，制作成的所述第一电极层与所述漏极连接，或制作成的所述第二电极层与所述漏极连接。在这里需要说明的是，无论第一电极层还是第二电极层，只要与公共电极线电连接的电极就为公共电极，与薄膜晶体管的漏极电连接的电极就为像素电极。
若所述制作成的第一电极与所述漏极连接，且所述第一电极层直接连接所述漏极，则所述制作方法包括：在步骤S1后，参考现有的制作工艺在衬底基板的非显示区域制作薄膜晶体管，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极以及漏极。然后依次进行步骤S2-S5，制作第一电极层，所述第一电极层就可以直接制作在所述漏极上。最后可以先制作钝化层再依次进行步骤S6-S10，制作第二电极层。此时，所述绝缘层为钝化层。
若所述制作成的第一电极与所述漏极连接，且所述第一电极层通过所述栅绝缘层上的过孔与所述漏极连接，则所述制作方法包括：首先依次进行步骤S1-S5，制作第一电极层。然后参考现有的制作工艺在衬底基板的非显示区域制作薄膜晶体管，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极以及漏极。其中，在制作栅绝缘层时，可以通过构图工艺制作成包含有过孔的栅绝缘层，所述栅绝缘层的过孔形成在所述第一电极层的上方，制作成的漏极就可以通过所述栅绝缘层上的过孔与所述第一电极层连接。最后可以先制作钝化层再依次进行步骤S6-S10，制作第二电极层；或者先依次进行步骤S6-S10，制作第二电极层，在制作钝化层。此时，所述绝缘层为栅绝缘层，或者，所述所述绝缘层为栅绝缘层和钝化层。
若所述制作成的第二电极与所述漏极连接，且所述第二电极层直接连接所述漏极，则所述制作方法包括：首先依次进行步骤S1-S5，制作第一电极层，再参考现有的制作工艺在衬底基板的非显示区域制作薄膜晶体管，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极以及漏极。然后，依次进行步骤S6-S10，制作第二电极层，所述第二电极层就可以直接制作在所述漏极上。最后制作钝化层。此时，所述绝缘层为栅绝缘层。
若所述制作成的第二电极与所述漏极连接，且所述第二电极层通过钝化层上的过孔与所述漏极连接，则所述制作方法包括：先在衬底基板上制作第一电极层和薄膜晶体管，然后在基板上制作钝化层薄膜，并通过构图工艺制作成包含有过孔的钝化层，所述钝化层的过孔形成在所述漏极的上方。最后可以依次进行步骤S6-S10，制作第二电极层，制作成的第二电极层可以通过所述钝化层的过孔与所述漏极连接。此时，所述绝缘层为钝化层，或者，所述绝缘层为栅绝缘层和钝化层。
本发明实施例还提供了一种显示装置，所述显示装置包括上述的的阵列基板，所述显示装置可以为液晶显示器、液晶电视、数码相机、手机、平板电脑等具有任何显示功能的产品或者部件。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (13)

1.一种阵列基板，包括栅线、数据线以及所述栅线和所述数据线交叉限定的像素区域，所述像素区域包括薄膜晶体管，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极以及漏极，所述像素区域还包括衬底基板，间隔设置在衬底基板上的凸起物，第一电极层，所述第一电极层包括至少一个电连接的第一电极条，所述第一电极条设置在所述凸起物的间隙中；其特征在于，所述像素区域还包括：
第二电极层，所述第二电极层包括至少一个电连接的第二电极条，所述第二电极条设置在所述凸起物上方。
2.根据权利要求1所述的阵列基板，其特征在于，所述衬底基板上的凸起物是等间距设置的。
3.根据权利要求1所述的阵列基板，其特征在于，所述凸起物的材料为透明树脂材料，且所述凸起物的厚度大于所述第一电极层的厚度。
4.根据权利要求1-3任意一项所述的阵列基板，其特征在于，每个所述凸起物的间隙内都设置有所述第一电极条，每个所述凸起物的上方都设置有所述第二电极条。
5.根据权利要求1-3任意一项所述的阵列基板，其特征在于，所述栅绝缘层设置在所述第一电极层和所述第二电极层之间；
所述第一电极层通过所述栅绝缘层上的过孔与所述漏极连接。
6.根据权利要求1-3任意一项所述的阵列基板，其特征在于，所述阵列基板还包括钝化层，所述栅绝缘层设置在所述第一电极层的下方，所述钝化层设置在所述第一电极层和所述第二电极层之间；
所述第一电极层直接与所述漏极连接。
7.根据权利要求1-3任意一项所述的阵列基板，其特征在于，所述阵列基板还包括钝化层，所述钝化层设置在所述第一电极层和所述第二电极层之间；
所述第二电极层通过钝化层上的过孔与所述漏极连接。
8.根据权利要求1-3任意一项所述的阵列基板，其特征在于，所述阵列基板还包括钝化层，所述栅绝缘层设置在所述第一电极层和所述第二电极层之间，所述钝化层设置在所述第二电极层的上方；
所述第二电极层直接连接所述漏极。
9.一种阵列基板的制作方法，包括在所述阵列基板上制作栅线、数据线以及薄膜晶体管，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极以及漏极；其特征在于，所述阵列基板的制作方法还包括：
在衬底基板上制作间隔设置的凸起物；
在基板上制作第一透明导电薄膜，并在制作有所述第一透明导电薄膜的基板上涂敷第一光刻胶；
对所述第一光刻胶进行灰化处理，形成第一光刻胶图案，所述第一光刻胶图案只覆盖所述凸起物的间隙；
进行刻蚀工艺，除去所述第一光刻胶图案未覆盖的第一透明导电薄膜；
进行光刻胶剥离工艺，将所述第一光刻胶图案剥离，从而形成包括至少一个电连接的第一电极条的第一电极层；
在形成有所述第一电极层的基板上制作绝缘层；
在制作有所述绝缘层的基板上涂敷第二光刻胶,对所述光刻胶进行灰化处理，形成第二光刻胶图案，所述第二光刻胶图案只覆盖所述凸起物的间隙；
在所述形成有第二光刻胶图案的基板上制作第二透明导电薄膜，然后通过光刻胶剥离工艺，去除所述第二光刻胶图案以及位于所述第二光刻胶图案上的第二透明导电薄膜，从而形成包括多个电连接的第二电极条的第二电极层。
10.根据权利要求9所述的制作方法，其特征在于，
所述绝缘层包括栅绝缘层或钝化层中的至少一个；
制作成的所述第一电极层与所述漏极连接，或制作成的所述第二电极层与所述漏极连接。
11.根据权利要求9所述的制作方法，其特征在于，制作在衬底基板上的凸起物是等间距的。
12.根据权利要求9所述的制作方法，其特征在于，所述凸起物的材料为透明树脂材料，且所述凸起物的厚度大于所述第一电极层的厚度。
13.一种显示装置，其特征在于，所述显示装置包括权利要求1-8任一项所述的阵列基板。
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