CN104409483B - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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CN104409483B
CN104409483B CN201410549863.4A CN201410549863A CN104409483B CN 104409483 B CN104409483 B CN 104409483B CN 201410549863 A CN201410549863 A CN 201410549863A CN 104409483 B CN104409483 B CN 104409483B
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gate insulation
insulation layer
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CN104409483A (zh
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薛静
于洪俊
朱红
吴昊
崔子巍
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to PCT/CN2015/074565 priority patent/WO2016058330A1/zh
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Abstract

本发明实施例公开了一种阵列基板及其制造方法、显示装置，涉及显示领域，能够提高产品的透过率，同时对Crosstalk、Flicker等不良也有一定的改善效果。本发明提供一种阵列基板，包括：基板，形成于所述基板上的数据线、栅线、薄膜晶体管和像素电极，所述薄膜晶体管包括栅绝缘层，所述栅绝缘层上与像素中的透光区域相对应的部分被去除。

Description

阵列基板及其制造方法、显示装置
技术领域
本发明涉及显示领域，尤其涉及一种阵列基板及其制造方法、显示装置。
背景技术
液晶显示器发展迅猛，目前已经占据显示领域的主流，广泛应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等产品中。
高级超维场开关技术(Advanced-Super Dimensional Switching，简称：ADS)是液晶显示领域的新兴技术，其通过同一平面内像素电极或公共电极边缘所产生的平行电场以及像素电极与公共电极间产生的纵向电场形成多维电场，使液晶盒内像素电极或公共电极之间、像素电极或公共电极正上方所有取向液晶分子都能够产生旋转转换，从而提高了平面取向系液晶工作效率并增大了透光效率。ADS技术具有宽视角、高开口率、低色差、低响应时间、无挤压水波纹(push Mura)波纹等优点，但目前ADS产品同时也普遍存在透过率不高以及Crosstalk、Flicker(亮点串扰不良、闪烁不良)等不良，影响产品的显示品质。
发明内容
本发明的实施例提供一种阵列基板及其制造方法、显示装置，能够提高产品的透过率，同时对Crosstalk、Flicker等不良也有一定的改善效果。
为达到上述目的，本发明的实施例采用如下技术方案：
一方面，本发明的实施例提供一种阵列基板，包括：基板，形成于所述基板上的数据线、栅线、薄膜晶体管和像素电极，所述薄膜晶体管包括栅绝缘层，所述栅绝缘层上与像素中的透光区域相对应的部分被去除。
进一步地，所述阵列基板还包括：钝化层，所述钝化层上与像素中的透光区域相对应的部分也被去除。
优选地，所述栅绝缘层制作时采用了一种或多种增加膜层致密度的方法。
具体地，所述栅绝缘层、所述钝化层的分布区域包括所述数据线、所述栅线、所述薄膜晶体管的分布区域。
优选地，所述栅绝缘层和所述钝化层的边缘距离所述栅线均不小于2um，距离所述数据线也均不小于2um。
优选地，所述像素电极直接搭接在所述薄膜晶体管的漏极。
本发明实施例还提供一种显示装置，包括：任一项所述的阵列基板。
另一方面，本发明实施例还提供一种阵列基板的制造方法，包括：形成栅绝缘层的工序，所述形成栅绝缘层的工序中形成的栅绝缘层与像素中的透光区域相对应的部分被去除。
进一步地，所述阵列基板的制造方法还包括：形成钝化层的工序，所述形成钝化层的工序中形成的钝化层与像素中的透光区域相对应的部分被去除。
优选地，所述形成栅绝缘层的工序中采用了一种或多种增加膜层致密度的方法。
本发明实施例提供的阵列基板及其制造方法、显示装置，将栅绝缘层上与像素中的透光区域相对应的部分去除，使像素中透光区域的透过率增加，从而提高产品的透过率；透过率增加，还可以弥补充电水平不足。另一方面，Crosstalk、Flicker等不良主要是控制显示信号加载的薄膜晶体管的有源层受光照影响使得载流子增多所导致，本发明方案透过率增加可以使所需要的充电水平降低(充电水平受沟道的宽长比W/L影响)，这样在设计时可以有意减小有源层，从而避免有源层受光照影响载流子增多，因而本发明方案对Crosstalk、Flicker等不良也有一定的改善效果。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本发明实施例提供的TN型阵列基板的俯视结构示意图；
图2为本发明实施例提供的TN型阵列基板的剖面结构示意图；
图3为本发明实施例中栅绝缘层的俯视结构示意图；
图4为现有技术中TN型阵列基板在形成像素电极之前(左图)和之后(右图)的俯视结构示意图；
图5为现有技术中TN型阵列基板的剖面结构示意图；
图6为现有技术中ADS型阵列基板的剖面结构示意图；
图7为本发明实施例提供的ADS型阵列基板的剖面结构示意图；
附图标记：
10-基板，11-数据线，12-栅线，13-薄膜晶体管，14-像素电极，130-栅极，
131-栅绝缘层，132-有源层，133-漏极，15-钝化层，16-公共电极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。
本发明的实施例提供一种阵列基板，如图1～图3所示，该阵列基板包括：基板10，形成于基板10上的数据线11、栅线12、薄膜晶体管13和像素电极14，薄膜晶体管13包括栅绝缘层131，栅绝缘层131上与像素中的透光区域相对应的部分被去除。
薄膜晶体管13的结构包括栅极130、栅绝缘层131、有源层132和源极、漏极133。如图4和图5所示，现有技术在形成薄膜晶体管的栅绝缘层131时，往往形成的是覆盖整个基板的绝缘膜层，在薄膜晶体管13以外区域，栅绝缘层131主要用于隔开栅绝缘层131上方和下方膜层，使二者绝缘，例如在数据线11和栅线12交叠区域，上方膜层为栅金属层、下方膜层为源漏金属层，但实际上像素中的透光区域并不需要栅绝缘层131的绝缘功能，像素电极14可以直接形成于基板10上，因此本实施例将像素中透光区域的栅绝缘层131去除以提高透过率。
如图3所示，为本实施例中栅绝缘层131的俯视示意图。栅绝缘层131上各像素的透光区域被去除(或镂空)。像素中的透光区域指像素电极14的覆盖区域。当然本领域技术人员可以理解的是，具体设计时栅绝缘层131的剩余膜层应能保证像素电极14不与数据线11、栅线12、薄膜晶体管13的栅极131等不发生非设计要求上的电连接。本实施例还可以选择将全部或部分像素的透光区域进行栅绝缘层镂空的设计，以调整透过率在整个显示面板上的分布。
本实施例提供的阵列基板，将栅绝缘层上与像素中的透光区域相对应的部分去除，使像素中透光区域的透过率增加，从而提高产品的透过率；透过率增加，还可以弥补充电水平不足。另一方面，透过率增加可以使所需要的充电水平降低(充电水平受沟道的宽长比W/L影响)，这样在设计时可以有意减小有源层，从而避免有源层受光照影响载流子增多，因而本发明方案对Crosstalk、Flicker等不良也有一定的改善效果。
进一步地，上述阵列基板还包括：钝化层15，当像素中的透光区域不需要钝化层15的绝缘功能时，钝化层15上与像素中的透光区域相对应的部分也被去除(或镂空)，进一步提高产品的透过率。钝化层15的去除部分与栅绝缘层类似，可参照图3所示。
优选地，上述栅绝缘层131制作时采用了一种或多种增加膜层致密度的方法。增加膜层致密度的方法有很多种，比如改变沉积时的气体流量，沉积压力或沉积功率等等，本实施例对此不做限定，膜层致密度增加可以减小栅绝缘层131的透光率，假如有源层(Active)132发生微小移动(微Shift)，致密的栅绝缘层131可防止有源层132尾端受光照影响过大结果出现串扰现象(此处的光照主要指背光)，从而改善Crosstalk、Flicker等不良，提高产品的显示品质。
为了本领域技术人员更好的理解本发明实施例提供的阵列基板的结构，下面通过具体的实施例对本发明提供的阵列基板进行详细说明。
本实施例的第一种实施方式，提供一种适合TN(Twisted Nematic，扭曲向列型)产品的阵列基板，包括：基板10，形成于基板10上的数据线11、栅线12、薄膜晶体管13和像素电极14，薄膜晶体管13的结构包括栅极130、栅绝缘层131、有源层132和源极、漏极133。为便于理解，下面通过与图4和图5所示现有TN型阵列基板进行对比叙述。现有TN型阵列基板，栅绝缘层131与钝化层15覆盖整个基板，像素电极14通过贯穿栅绝缘层131与钝化层15的过孔进行像素电极14(ITO层)与薄膜晶体管13的漏极133(源漏金属层S/D)搭接。而本实施方式中将栅绝缘层131上与像素中的透光区域相对应的部分去除，栅绝缘层131、钝化层15至少覆盖栅线、数据线以及薄膜晶体管的分布区域，且栅绝缘层131、钝化层15的边缘距离数据线/栅线的边缘不小于2um。
例如，可以通过湿法或干法刻蚀方法将像素区(Pixel区)底层的栅绝缘层131与钝化层15(GI&PVX)刻蚀掉，刻蚀边缘距离数据线11或栅线12(Data线&Gate线)不小于2um，此限制可以保证数据线11或栅线12被完全保护住，避免短接导致的漏电，同时实现透过率的提高。薄膜晶体管13的漏极133可直接搭接像素电极，与现有技术中做过孔搭接的方法相比，连接更加可靠，避免了过孔搭接不良出现的异常显示现象(AD现象)。
上述栅绝缘层131、钝化层15图形一致，其中与像素中的透光区域相对应的部分均被去除，具体分布区域均包括数据线11、栅线12、薄膜晶体管13的分布区域。栅绝缘层131、钝化层15可以分别单独独立刻蚀制作，也可以在钝化层15成膜工序之后，通过刻蚀工艺将栅绝缘层131、钝化层15的图形一起制作出来。
另外，上述栅绝缘层131、钝化层15图形也可以不一致，制作时先形成包括栅极130和栅线12的栅金属层；栅金属层之上形成栅绝缘层131并图形化，图形化后的栅绝缘层131的分布区域至少要包括栅线12、薄膜晶体管13的有源层的分布区域；然后继续形成有源层132、包括源极和漏极133的源漏金属层；源漏金属层之上形成钝化层15并图形化，图形化后的钝化层15的分布区域至少要包括数据线11、薄膜晶体管13的源极和漏极133的分布区域。
本实施例的第二种实施方式提供一种适合ADS(高级超维场开关，Advanced-SuperDimensional Switching)产品的阵列基板。图6为现有技术中ADS型阵列基板剖面图，图7为本发明实施方式提及的ADS型阵列基板剖面图，同样，将栅绝缘层131上与像素中的透光区域相对应的部分刻蚀掉，刻蚀边缘距离数据线11(或栅线12)不小于2um，此距离可以保证数据线11(或栅线12)被完全保护住且能提高透过率。对于ADS型阵列基板，需要钝化层15隔开像素电极14和公共电极16，保证二者绝缘，因此，钝化层15不做刻蚀，保留原有的整层分布方式。
上述具体实施方式中提及的阵列基板其栅绝缘层131在成膜时还采用了一种或多种增加膜层致密度的方法，比如优化沉积时的气体流量、沉积压力或沉积功率等等，以减小栅绝缘层131的透光率，在有源层132发生微Shift时可防止Active尾端受光照影响过大而出现的串扰现象，从而改善Crosstalk、Flicker等不良，提高产品的显示品质。
上述为提高透过率而对栅绝缘层131(或者栅绝缘层131和钝化层15)进行的刻蚀，与提高栅绝缘层131致密度的方法二者相辅相成，共同解决显示产品普遍存在的透过率不高以及Crosstalk、Flicker等不良，提高产品的显示品质。
本发明实施例还提供一种显示装置，其包括上述任意一种阵列基板。所述显示装置透过率高，能改善Crosstalk、Flicker等不良，可获得更高的显示品质，并且所需充电水平低，易满足，节能省电。所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
另一方面，本发明实施例还提供一种阵列基板的制造方法，其中包括：形成栅绝缘层的工序，该工序中形成的栅绝缘层与像素中的透光区域相对应的部分被去除，提高产品的透过率，改善Crosstalk、Flicker等不良，从而提高产品的显示品质。
进一步地，阵列基板的制造方法还包括：形成钝化层的工序，形成钝化层的工序中形成的钝化层与像素中的透光区域相对应的部分被去除，进一步提高产品的透过率。
上述形成栅绝缘层或者形成钝化层的工序中可先成膜，再根据栅绝缘层或钝化层的膜材料选择通过湿法或干法刻蚀方法将像素中的透光区域的栅绝缘层或钝化层刻蚀掉(可以通过同一工序一次性刻蚀掉栅绝缘层和钝化层)，也可以通过印刷、遮挡成膜等方式直接形成符合要求的像素中的透光区域镂空的栅绝缘层或钝化层，本实施例对此不做限定，可以是本领域技术人员所熟知的任何方式。
优选地，形成栅绝缘层的工序中采用了一种或多种增加膜层致密度的方法。致密的栅绝缘层131改善因有源层132受光照影响载流子增多导致的Crosstalk、Flicker等不良，提高产品的显示品质。
本实施例提供的阵列基板的制造方法，将栅绝缘层、钝化层上与像素中的透光区域相对应的部分去除，以提高产品的透过率；另一方面，通过栅绝缘层131成膜工序中采用增加膜层致密度的方法，改善Crosstalk、Flicker等不良，从而提高产品的显示品质。
需要说明的是，在上面叙述中虽然以液晶显示为背景进行叙述，但本发明的应用并不应局限于此。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于设备实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (8)

1.一种阵列基板，包括：基板，形成于所述基板上的数据线、栅线、薄膜晶体管和像素电极，所述薄膜晶体管包括栅绝缘层，其特征在于，
所述栅绝缘层上与像素中的透光区域相对应的部分被去除，以增加透过率，从而减少有源层的分布面积；所述栅绝缘层制作时采用了一种或多种增加膜层致密度的方法，以减小栅绝缘层的透光率，改善亮点串扰不良和闪烁不良。
2.根据权利要求1所述的阵列基板，其特征在于，还包括：钝化层，
所述钝化层上与像素中的透光区域相对应的部分也被去除。
3.根据权利要求2所述的阵列基板，其特征在于，
所述栅绝缘层、所述钝化层的分布区域包括所述数据线、所述栅线、所述薄膜晶体管的分布区域。
4.根据权利要求3所述的阵列基板，其特征在于，
所述栅绝缘层和所述钝化层的边缘距离所述栅线均不小于2um，距离所述数据线也均不小于2um。
5.根据权利要求1或2所述的阵列基板，其特征在于，
所述像素电极直接搭接在所述薄膜晶体管的漏极。
6.一种显示装置，其特征在于，包括：权利要求1-5任一项所述的阵列基板。
7.一种阵列基板的制造方法，包括：形成栅绝缘层的工序，其特征在于，所述形成栅绝缘层的工序中形成的栅绝缘层与像素中的透光区域相对应的部分被去除以增加透过率，从而减少有源层的分布面积；且，
所述栅绝缘层的工序中采用了一种或多种增加膜层致密度的方法，以减小栅绝缘层的透光率，改善亮点串扰不良和闪烁不良。
8.根据权利要求7所述的制造方法，其特征在于，还包括：形成钝化层的工序，所述形成钝化层的工序中形成的钝化层与像素中的透光区域相对应的部分被去除。
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