CN102654703B - 一种阵列基板及其制造方法、以及显示设备 - Google Patents

一种阵列基板及其制造方法、以及显示设备 Download PDF

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CN102654703B
CN102654703B CN201210093375.8A CN201210093375A CN102654703B CN 102654703 B CN102654703 B CN 102654703B CN 201210093375 A CN201210093375 A CN 201210093375A CN 102654703 B CN102654703 B CN 102654703B
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electrode
public electrode
substrate
via hole
insulation course
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CN102654703A (zh
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白金超
刘耀
李梁梁
孙亮
郝昭慧
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US13/976,498 priority patent/US9146431B2/en
Priority to PCT/CN2012/084470 priority patent/WO2013143291A1/zh
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Abstract

本发明提供一种阵列基板，其包括：基板；依次形成在所述基板上且相互绝缘的公共电极和像素电极；薄膜晶体管，所述薄膜晶体管包括栅电极、有源层、源电极和漏电极；所述漏电极与所述像素电极电连接；以及，与所述栅电极同层设置的公共电极线；其中，所述阵列基板还包括绝缘层，所述绝缘层位于栅电极与公共电极之间，用于将栅电极与公共电极隔离；所述公共电极通过绝缘层过孔与所述公共电极线连接。相应地，提供一种上述阵列基板的制造方法以及采用该阵列基板的显示设备。本发明所述阵列基板能够克服现有技术中存在的单元像素的开口率较低的问题。

Description

一种阵列基板及其制造方法、以及显示设备
技术领域
本发明属于显示器制造技术领域，具体涉及一种阵列基板及其制造方法，以及使用所述阵列基板的显示设备。
背景技术
随着显示器制造技术的发展，液晶显示器技术发展迅速，已经逐渐取代了传统的显像管显示器而成为未来平板显示器的主流。在液晶显示器技术领域中，TFT-LCD(Thin Film TransistorLiquid Crystal Display，薄膜晶体管液晶显示器)以其大尺寸、高度集成、功能强大、工艺灵活、低成本等优势而广泛应用于电视机、电脑、手机等领域。
其中，ADSDS(高级超维场转换技术，ADvanced SuperDimension Switch，简称ADS)型TFT-LCD由于具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(push Mura)等优点，广泛应用于液晶显示器领域。ADS型TFT-LCD通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率，进而提高TFT-LCD产品的画面品质。
目前，ADS型TFT-LCD的阵列基板是通过多次光刻工艺来完成的，每一次光刻工艺又分别包括成膜、曝光、显影、刻蚀和剥离等工艺，其中刻蚀工艺包括干法刻蚀和湿法刻蚀。
现有技术中通过5次光刻工艺制造的ADS型TFT-LCD阵列基板是较为领先的技术。图1为现有的ADS型TFT-LCD的阵列基板像素结构示意图，如图1所示，所述5次光刻工艺包括：公共电极(1st ITO)光刻、栅电极(gate)光刻、半导体层/源漏电极(SDT)光刻、钝化层(PVX)光刻和像素电极(2nd ITO)光刻。其中，所述公共电极用于提供公共电压，所述像素电极用于提供单元像素显色所需电压。
上述公共电极光刻和栅电极光刻是在连续的工艺下完成的，如果公共电极2或栅电极4在刻蚀工艺过程中产生残留，容易造成公共电极2与栅电极4导通，从而导致公共电极2与栅电极4之间发生短路(Gate-Common Short)，这会严重危害薄膜晶体管的性能。为了避免短路现象的发生，一般采取的措施是增大公共电极2与栅电极4之间的距离，但这种做法势必会增大为了防止栅线漏光的黑矩阵(BM，Black Matrix)的宽度，同时减少单元像素透光区的面积，从而降低单元像素的开口率。
发明内容
本发明所要解决的技术问题是针对现有技术中存在的上述问题，提供一种阵列基板及其制造方法，以克服现有技术中存在的单元像素的开口率较低的问题。
解决本发明技术问题所采用的技术方案是：
所述阵列基板包括：基板；依次形成在所述基板上且相互绝缘的公共电极和像素电极；薄膜晶体管，所述薄膜晶体管包括栅电极、有源层、源电极和漏电极；所述漏电极与所述像素电极电连接；以及与所述栅电极同层设置的公共电极线；其中，所述阵列基板还包括绝缘层，所述绝缘层位于栅电极与公共电极之间，用于将栅电极与公共电极隔离；所述公共电极通过绝缘层过孔与所述公共电极线连接。
优选的是，所述绝缘层覆盖在所述公共电极上并延伸至基板上，所述公共电极线和栅电极位于绝缘层上；绝缘层覆盖公共电极的部分开有第一过孔，公共电极通过第一过孔与公共电极线连接。
优选的是，所述公共电极线和栅电极位于基板上，所述绝缘层位于基板上并覆盖公共电极线和栅电极，所述公共电极位于绝缘层上方；所述绝缘层覆盖公共电极线的部分开有第一过孔，所述公共电极通过第一过孔与公共电极线连接。
优选的是，所述绝缘层采用高透光性的绝缘材料制成。
本发明同时提供一种如上所述的阵列基板的制造方法，包括在基板上制作公共电极线、公共电极、薄膜晶体管的过程，所述薄膜晶体管包括栅电极、源电极和漏电极；其中，所述制造方法还包括：制作绝缘层，所述绝缘层位于栅电极与公共电极之间，用于将栅电极与公共电极隔离。
优选的是，所述制造方法具体包括下列步骤：
A.在基板上形成公共电极、绝缘层、栅电极与公共电极线的图形；
B.在完成步骤A的基板上形成栅电极保护层、有源层、源电极和漏电极的图形；
C.在完成步骤B的基板上形成钝化层的图形，并在钝化层上形成有第二过孔；
D.在完成步骤C的基板上形成像素电极的图形，所述像素电极通过第二过孔与漏电极连接。
进一步优选的是，所述步骤A包括：
A11.在基板上形成公共电极的图形；
A12.在完成步骤A11的基板上形成绝缘层的图形，在绝缘层上形成有第一过孔，使绝缘层覆盖在公共电极上并延伸至基板上，并使所述第一过孔位于公共电极上方；
A13.在绝缘层上形成栅电极与公共电极线的图形，使公共电极线位于第一过孔上方，公共电极线通过第一过孔与公共电极连接。
或者，所述步骤A包括：
A21.在基板上形成栅电极与公共电极线的图形；
A22.在完成步骤A21的基板上形成绝缘层的图形，在绝缘层上形成有第一过孔，使所述绝缘层位于基板上并覆盖公共电极线和栅电极，并使第一过孔位于公共电极线的上方；
A23.在绝缘层上形成公共电极的图形，使公共电极位于第一过孔上方，所述公共电极通过第一过孔与公共电极线连接。
或者，所述步骤A包括：
A31.在基板上形成栅电极与公共电极线的图形；
A32.在完成步骤A31的基板上形成绝缘层及公共电极的图形，使绝缘层位于基板上并覆盖公共电极线和栅电极，并使公共电极位于公共电极线的上方；
所述步骤C包括：
在完成步骤B的基板上形成钝化层的图形，并形成贯穿钝化层的第二过孔以露出所述漏电极，以及形成贯穿钝化层、栅电极保护层、公共电极与绝缘层的第一过孔以露出所述公共电极线；
所述步骤D包括：在完成步骤C的基板上形成像素电极的图形，所述像素电极通过第二过孔与所述漏电极连接，同时公共电极通过第一过孔与公共电极线连接。
或者，所述步骤A包括：
A41.在基板上形成公共电极的图形；
A42.在完成步骤A41的基板上形成绝缘层、栅电极及公共电极线的图形，使绝缘层覆盖在公共电极上并延伸至基板上，并使公共电极线位于公共电极上方；
所述步骤C包括：
在完成步骤B的基板上形成钝化层的图形，并形成贯穿钝化层的第二过孔以露出所述漏电极，以及形成贯穿钝化层、栅电极保护层、公共电极线与绝缘层的第一过孔以露出所述公共电极；
所述步骤D包括：在完成步骤C的基板上形成像素电极的图形，所述像素电极通过第二过孔与所述漏电极连接，同时公共电极通过第一过孔与公共电极线连接。
本发明同时还提供一种显示设备，包括阵列基板，所述阵列基板采用上述的阵列基板。
有益效果：
本发明所述阵列基板由于在公共电极和栅电极之间增加了一层采用高透光率的绝缘材料制成的绝缘层，将公共电极与栅电极完全隔离，即使公共电极或栅电极在刻蚀工艺过程中产生残留，也不会导致公共电极与栅电极之间发生短路；进一步可以缩短公共电极与栅电极之间的水平距离；本发明中公共电极与栅电极之间的水平距离与现有技术中公共电极与栅电极之间的水平距离相比，缩短至现有水平距离的0.5～0.8倍，从而可以减小为防止栅线漏光的黑矩阵的宽度，增大了单元像素透光区的面积，因而有效提高了单元像素的开口率。
附图说明
图1为现有的ADS模式的阵列基板的结构示意图；
图2为本发明实施例1中阵列基板的结构示意图；
图3为本发明实施例2中阵列基板的结构示意图；
图4为本发明实施例3中阵列基板的结构示意图；
图5为本发明实施例4中阵列基板的结构示意图；
图6为本发明所述阵列基板中公共电极与栅电极的间距和现有技术中公共电极与栅电极的间距对比示意图。
图中：1-基板；2-公共电极；3-绝缘层；4-栅电极；5-公共电极线；6-栅电极保护层；7-有源层；8a-源电极；8b-漏电极；9-钝化层；10-像素电极；11-第一过孔；12-第二过孔。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所述阵列基板、该阵列基板的制造方法、以及包括所述阵列基板的显示设备作进一步详细描述。
所述阵列基板包括基板1；依次形成在所述基板1上且相互绝缘的公共电极2和像素电极10，其中像素电极10上形成有狭缝结构；薄膜晶体管，所述薄膜晶体管包括栅电极4、有源层7、源电极8a和漏电极8b；所述漏电极8b与所述像素电极10电连接；以及所述栅电极4同层设置的公共电极线5；其中，所述阵列基板还包括绝缘层3，所述绝缘层3位于栅电极4与公共电极2之间，用于将栅电极4与公共电极2隔离；所述公共电极2通过绝缘层过孔与所述公共电极线5连接。
所述阵列基板的制作方法包括在基板1上制作公共电极线5、公共电极2、薄膜晶体管的过程，所述薄膜晶体管包括栅电极4、源电极8a和漏电极8b；其中，所述制造方法还包括：制作绝缘层3，所述绝缘层3位于栅电极4与公共电极2之间，用于将栅电极4与公共电极2隔离。
所述显示设备包括阵列基板，所述阵列基板采用上述的阵列基板。所述显示装置可以为：液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
图6为本发明所述阵列基板中公共电极2与栅电极4的间距和现有技术中公共电极与栅电极的间距示意图，图a为现有技术阵列基板中公共电极2与栅电极4之间的间距示意图，其中d1表示现有技术中公共电极2与栅电极4的间距，图b为本发明公共电极2与栅电极4之间的间距示意图，其中d2表示本发明中公共电极2与栅电极4的间距；所述d2/d1约为0.5～0.8。从图6可以看出，由于本发明所述阵列基板在公共电极2和栅电极4之间增加了一层高透光率的绝缘层3，使得本发明所述阵列基板与现有技术的阵列基板相比，缩短了公共电极2与栅电极4之间的距离，从而增大了单元像素的开口率。
实施例1：
如图2所示，本实施例中，所述阵列基板包括：基板1；形成在基板上的公共电极2；覆盖在公共电极2上并延伸至基板1上的绝缘层3，绝缘层3覆盖公共电极2的部分开有第一过孔11；形成在绝缘层3上的栅电极4与公共电极线5，即公共电极线5与栅电极4同层设置，所述公共电极线5位于第一过孔11上方，公共电极线5通过第一过孔11与公共电极2连接；栅电极保护层(即栅绝缘层)6，所述栅电极保护层6将栅电极4、公共电极线5以及绝缘层3完全覆盖；在栅电极保护层6上形成的有源层7；形成在有源层7上的源电极8a与漏电极8b；覆盖源电极8a与漏电极8b并延伸至栅电极保护层6上的钝化层9，所述钝化层9覆盖漏电极8b的部分开有第二过孔12；在钝化层9上形成的像素电极10，所述像素电极10上形成有狭缝结构而且像素电极10通过第二过孔12与漏电极8b电连接。可以看出，公共电极2与像素电极10相互绝缘；绝缘层3位于栅电极4与公共电极2之间，用于将栅电极4与公共电极2隔离。
优选所述第一过孔11与第二过孔12通过干刻技术形成。
优选的是，所述基板1采用玻璃制成；所述绝缘层3与钝化层9均采用高透光率的绝缘材料制成，例如可采用SiNx、SiOx或SiOxNy中的任一所形成的单层膜制成，或者采用SiNx、SiOx或SiOxNy的任意组合所形成的复合膜制成，或者采用聚酰胺与环氧树脂中的任一所形成的单层膜制成，或者采用聚酰胺与环氧树脂的组合所形成的复合膜制成，或者采用其他绝缘材料的单层膜或复合膜制成；所述源电极8a、漏电极8b、栅电极4与公共电极线5采用钼、铝、铝钕合金、钨、铬或铜的单层膜制成，或者采用以上金属多层沉积形成的多层膜制成，或者采用其他金属材料的单层膜或多层膜制成；所述有源层7包括半导体层和欧姆接触层，其中半导体层采用a-Si(非晶硅)制成，或者采用其他半导体材料制成；所述欧姆接触层采用n+a-Si(掺杂P非晶硅)制成，或者采用其他半导体掺杂材料制成；所述公共电极2与像素电极10采用铟锡氧化物或者铟锌氧化物制成。
本实施例同时提供一种阵列基板的制造方法，其采用六次光刻工艺完成，具体工艺流程如下：
步骤①，在基板1上沉积透明导电薄膜，通过第一次光刻工艺形成公共电极2的图形；
步骤②，在完成步骤①的基板上沉积绝缘薄膜，通过第二次光刻工艺形成绝缘层3的图形，在绝缘层3上形成有第一过孔11，使所述绝缘层3覆盖在公共电极2上并延伸至基板1上，并使所述第一过孔11位于公共电极2上方；
步骤③，在完成步骤②的基板上沉积栅极金属薄膜，通过第三次光刻工艺在绝缘层3上形成栅电极4与公共电极线5的图形，使所述公共电极线5位于第一过孔11上方，并使公共电极线5通过第一过孔11与公共电极2连接；
步骤④，在完成步骤③的基板上依次沉积栅电极保护薄膜、半导体薄膜、欧姆接触薄膜、漏源极金属薄膜，并利用半色调掩模或者灰色调掩模进行第四次光刻工艺形成栅电极保护层6、有源层7、源电极8a和漏电极8b的图形，使所述栅电极保护层6完全覆盖栅电极4、公共电极线5以及绝缘层3，并使有源层7、源电极8a和漏电极8b位于栅电极4上方的栅电极保护层6上；
步骤⑤，在完成步骤④的基板上沉积绝缘薄膜，通过第五次光刻工艺形成钝化层9的图形，在钝化层9上形成有第二过孔12，使所述钝化层9完全覆盖源电极8a、漏电极8b与栅电极保护层6，并使第二过孔12位于漏电极8b上方；
步骤⑥，在完成步骤⑤的基板上沉积第二透明导电薄膜，通过第六次光刻工艺形成像素电极10的图形，使所述像素电极10通过第二过孔12与漏电极8b连接。
实施例2：
如图3所示，本实施例中，所述阵列基板包括：基板1；形成在基板1上的栅电极4与公共电极线5，即公共电极线5与栅电极4同层设置；形成在基板1上并覆盖栅电极4与公共电极线5的绝缘层3，所述绝缘层3覆盖公共电极线5的部分开有第一过孔11，所述第一过孔11位于公共电极线5的上方；形成在绝缘层3上的公共电极2，所述公共电极2位于第一过孔11上方，公共电极2通过第一过孔11与公共电极线5连接；完全覆盖公共电极2以及绝缘层3的栅电极保护层6；在栅电极4上方的栅电极保护层6上形成的有源层7；形成在有源层7上的源电极8a与漏电极8b；覆盖源电极8a与漏电极8b并延伸至栅电极保护层6上的钝化层9，所述钝化层9覆盖漏电极8b的部分开有第二过孔12；在钝化层9上形成的像素电极10，所述像素电极10上形成有狭缝结构而且像素电极10通过第二过孔12与漏电极8b连接。可以看出，公共电极2与像素电极10相互绝缘；绝缘层3位于栅电极4与公共电极2之间，用于将栅电极4与公共电极2隔离。
优选所述第一过孔11与第二过孔12通过干刻技术形成。
组成本实施例中的阵列基板的各层材质与实施例1中相同。
本实施例同时提供一种阵列基板的制造方法，其采用六次光刻工艺完成，具体工艺流程如下：
步骤①，在基板1上沉积栅极金属薄膜，通过第一次光刻工艺形成栅电极4与公共电极线5的图形；
步骤②，在完成步骤①的基板上沉积绝缘薄膜，通过第二次光刻工艺形成绝缘层3的图形，在绝缘层3上形成有第一过孔11，使所述绝缘层3位于基板1上并覆盖公共电极线5和栅电极4，并使第一过孔11位于公共电极线5的上方；
步骤③，在完成步骤②的基板上沉积第一透明导电薄膜，通过第三次光刻工艺形成公共电极2的图形，使公共电极2位于第一过孔11上方，所述公共电极2通过第一过孔11与公共电极线5连接；
步骤④～⑥与实施例1的步骤④～⑥相同，这里不再赘述。
实施例3：
如图4所示，本实施例中，所述阵列基板包括：基板1；形成在基板1上的栅电极4与公共电极线5，即公共电极线5与栅电极4同层设置；形成在基板1上并覆盖栅电极4与公共电极线5的绝缘层3；形成在绝缘层3上的公共电极2，所述公共电极2位于公共电极线5上方；完全覆盖公共电极2以及绝缘层3的栅电极保护层6；在栅电极4上方的栅电极保护层6上形成的有源层7；形成在有源层7上的源电极8a与漏电极8b；覆盖源电极8a与漏电极8b并延伸至栅电极保护层6上的钝化层9，所述钝化层9覆盖漏电极8b的部分开有第二过孔12；公共电极线5上方设置有第一过孔11，所述第一过孔11依次穿过钝化层9、栅电极保护层6、公共电极2与绝缘层3，公共电极2通过第一过孔11与公共电极线5连接；在钝化层9上形成的像素电极10，所述像素电极10上形成有狭缝结构而且像素电极10通过第二过孔12与漏电极8b连接。可以看出，公共电极2与像素电极10相互绝缘；绝缘层3位于栅电极4与公共电极2之间，用于将栅电极4与公共电极2隔离。
优选所述第一过孔11与第二过孔12通过干刻技术形成。
组成本实施例阵列基板的各层材质与实施例1相同。
本实施例同时提供一种阵列基板的制造方法，其采用五次光刻工艺完成，具体工艺流程如下：
步骤①，在基板1上沉积栅极金属薄膜，通过第一次光刻工艺形成栅电极4与公共电极线5的图形；
步骤②，在完成步骤①的基板上依次沉积绝缘薄膜、第一透明导电薄膜，通过第二次光刻工艺形成绝缘层3及公共电极2的图形，使绝缘层3位于基板1上并覆盖公共电极线5和栅电极4，并使公共电极2位于公共电极线5的上方；
步骤③，在完成步骤②的基板上依次沉积栅电极保护薄膜、半导体薄膜、欧姆接触薄膜、漏源极金属薄膜，并利用半色调掩模或者灰色调掩模进行第三次光刻工艺形成栅电极保护层6、有源层7、源电极8a与漏电极8b的图形，使所述栅电极保护层6完全覆盖公共电极2以及绝缘层3，并使有源层7、源电极8a和漏电极8b位于栅电极4上方的栅电极保护层6上方；
步骤④，在完成步骤③的基板上沉积绝缘薄膜，通过第四次光刻工艺形成钝化层9的图形，在钝化层9上形成有第二过孔12，并使第二过孔12位于漏电极8b上方，即第二过孔12贯穿钝化层9以露出所述漏电极8b，所述钝化层9完全覆盖源电极8a、漏电极8b与栅电极保护层6；以及形成贯穿钝化层9、栅电极保护层6、公共电极2与绝缘层3的第一过孔11以露出所述公共电极线5；
步骤⑤，在完成步骤④的基板上沉积第二透明导电薄膜，通过第五次光刻工艺形成像素电极10的图形，使所述像素电极10通过第二过孔12与漏电极8b连接，同时沉积在所述第一过孔11处的像素电极材料(即第二透明导电薄膜材料)使公共电极2通过第一过孔11与公共电极线5连接。
实施例4：
如图5所示，本实施例中，所述阵列基板包括：基板1；形成在基板1上的公共电极2；形成在基板1上并覆盖公共电极2的绝缘层3；形成在绝缘层3上的栅电极4与公共电极线5，即公共电极线5与栅电极4同层设置，且所述公共电极线5位于公共电极2上方；完全覆盖栅电极4、公共电极线5以及绝缘层3的栅电极保护层6；在栅电极4上方的栅电极保护层6上形成的有源层7；形成在有源层7上的源电极8a与漏电极8b；覆盖源电极8a与漏电极8b并延伸至栅电极保护层6上的钝化层9，所述钝化层9覆盖漏电极8b的部分开有第二过孔12；公共电极2上方设置有第一过孔11，所述第一过孔11依次穿过钝化层9、栅电极保护层6、公共电极线5与绝缘层3，公共电极2通过第一过孔11与公共电极线5连接；在钝化层9上形成的像素电极10，所述像素电极10上形成有狭缝结构而且像素电极10通过第二过孔12与漏电极8b电连接。可以看出，公共电极2与像素电极10相互绝缘；绝缘层3位于栅电极4与公共电极2之间，用于将栅电极4与公共电极2隔离。
优选所述第一过孔11与第二过孔12通过干刻技术形成。
组成本实施例阵列基板的各层材质与实施例1相同。
本实施例同时提供一种阵列基板的制造方法，其采用五次光刻工艺完成，具体工艺流程如下：
步骤①，在基板1上沉积第一透明导电薄膜，通过第一次光刻工艺形成公共电极2的图形；
步骤②，在完成步骤①的基板上依次沉积绝缘薄膜、栅极金属薄膜，通过第二次光刻工艺形成绝缘层3、栅电极4与公共电极线5的图形，使绝缘层3位于基板1上并覆盖公共电极2，并使公共电极线5位于公共电极2的上方；
步骤③，在完成步骤②的基板上依次沉积栅电极保护薄膜、半导体薄膜、欧姆接触薄膜、漏源极金属薄膜，并利用半色调掩模或者灰色调掩模进行第三次光刻工艺形成栅电极保护层6、有源层7、源电极8a与漏电极8b的图形，使所述栅电极保护层6完全覆盖栅电极4、公共电极线5以及绝缘层3，并使有源层7、源电极8a与漏电极8b位于栅电极4上方的栅电极保护层6上；
步骤④，在完成步骤③的基板上沉积绝缘薄膜，通过第四次光刻工艺形成钝化层9的图形，在钝化层9上形成有第二过孔12，并使第二过孔12位于漏电极8b上方，即第二过孔12贯穿钝化层9以露出所述漏电极8b，所述钝化层9完全覆盖源电极8a、漏电极8b与栅电极保护层6；以及形成贯穿钝化层9、栅电极保护层6、公共电极线5与绝缘层3的第一过孔11以露出所述公共电极2；
步骤⑤，在完成步骤④的基板上沉积第二透明导电薄膜，通过第五次光刻工艺形成像素电极10的图形，使所述像素电极10通过第二过孔12与漏电极8b连接，同时沉积在所述第一过孔11处的像素电极材料(即第二透明导电薄膜材料)使公共电极2通过第一过孔11与公共电极线5连接。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (8)

1.一种阵列基板，包括：
基板(1)；
依次形成在所述基板(1)上且相互绝缘的公共电极(2)和像素电极(10)；
薄膜晶体管，所述薄膜晶体管包括栅电极(4)、栅电极保护层(6)和有源层(7)、源电极(8a)和漏电极(8b)；所述漏电极(8b)与所述像素电极(10)电连接；以及，
与所述栅电极(4)同层设置的公共电极线(5)；
钝化层(9)，所述钝化层9覆盖所述源极(8a)与所述漏极(8b)并延伸至所述栅电极保护层(6)上；
其特征在于，所述阵列基板还包括绝缘层(3)，所述绝缘层(3)位于栅电极(4)与公共电极(2)之间，用于将栅电极(4)与公共电极(2)隔离；所述公共电极(2)通过依次贯穿所述钝化层(9)、所述栅电极保护层(6)和所述绝缘层(3)的第一过孔(11)与所述公共电极线(5)连接，填充所述第一过孔(11)的材料为形成所述像素电极(10)的材料。
2.根据权利要求1所述的阵列基板，其特征在于，所述公共电极(2)位于基板(1)上，所述绝缘层(3)覆盖在所述公共电极(2)上并延伸至基板(1)上，所述公共电极线(5)和栅电极(4)位于绝缘层(3)上，所述第一过孔(11)位于所述绝缘层覆盖所述公共电极(2)的部分上。
3.根据权利要求1所述的阵列基板，其特征在于，所述公共电极线(5)和栅电极(4)位于基板(1)上，所述绝缘层(3)位于基板(1)上并覆盖公共电极线(5)和栅电极(4)，所述公共电极(2)位于绝缘层(3)上方，所述第一过孔(11)位于所述绝缘层(3)覆盖所述公共电极线(5)的部分上。
4.根据权利要求1-3之一所述的阵列基板，其特征在于，所述绝缘层(3)采用高透光性的绝缘材料制成。
5.一种如权利要求1所述的阵列基板的制造方法，所述制造方法包括下列步骤：
A.在基板(1)上形成公共电极(2)、绝缘层(3)、栅电极(4)与公共电极线(5)的图形；
B.在完成步骤A的基板上形成栅电极保护层(6)、有源层(7)、源电极(8a)和漏电极(8b)的图形；
C.在完成步骤B的基板上形成钝化层(9)的图形，在钝化层(9)上形成有第一过孔(11)和第二过孔(12)；
D.在完成步骤C的基板上形成像素电极(10)的图形，所述像素电极(10)通过第二过孔(12)与漏电极(8b)连接；所述第一过孔(11)中填充像素电极材料以连接所述公共电极(2)和所述公共电极线(5)。
6.根据权利要求5所述的制造方法，其特征在于，
所述步骤A包括：
A31.在基板(1)上形成栅电极(4)与公共电极线(5)的图形；
A32.在完成步骤A31的基板上形成绝缘层(3)及公共电极(2)的图形，使绝缘层(3)位于基板(1)上并覆盖公共电极线(5)和栅电极(4)，并使公共电极(2)位于公共电极线(5)的上方；
所述步骤C包括：
在完成步骤B的基板上形成钝化层(9)的图形，并形成贯穿钝化层(9)的第二过孔(12)以露出所述漏电极(8b)，以及形成贯穿钝化层(9)、栅电极保护层(6)、公共电极(2)与绝缘层(3)的第一过孔(11)以露出所述公共电极线(5)；
所述步骤D包括：在完成步骤C的基板上形成像素电极(10)的图形，所述像素电极(10)通过第二过孔(12)与所述漏电极(8b)连接，同时公共电极(2)通过第一过孔(11)与公共电极线(5)连接。
7.根据权利要求5所述的制造方法，其特征在于，
所述步骤A包括：
A41.在基板(1)上形成公共电极(2)的图形；
A42.在完成步骤A41的基板上形成绝缘层(3)、栅电极(4)及公共电极线(5)的图形，使绝缘层(3)覆盖在公共电极(2)上并延伸至基板(1)上，并使公共电极线(5)位于公共电极(2)上方；
所述步骤C包括：
在完成步骤B的基板上形成钝化层(9)的图形，并形成贯穿钝化层(9)的第二过孔(12)以露出所述漏电极(8b)，以及形成贯穿钝化层(9)、栅电极保护层(6)、公共电极线(5)与绝缘层(3)的第一过孔(11)以露出所述公共电极(2)；
所述步骤D包括：在完成步骤C的基板上形成像素电极(10)的图形，所述像素电极(10)通过第二过孔(12)与所述漏电极(8b)连接，同时公共电极(2)通过第一过孔(11)与公共电极线(5)连接。
8.一种显示设备，包括阵列基板，其特征在于所述阵列基板采用权利要求1-4之一所述的阵列基板。
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