WO2018184279A1 - Tft基板的制作方法及tft基板 - Google Patents

Tft基板的制作方法及tft基板 Download PDF

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Publication number
WO2018184279A1
WO2018184279A1 PCT/CN2017/084601 CN2017084601W WO2018184279A1 WO 2018184279 A1 WO2018184279 A1 WO 2018184279A1 CN 2017084601 W CN2017084601 W CN 2017084601W WO 2018184279 A1 WO2018184279 A1 WO 2018184279A1
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layer
interlayer dielectric
gate insulating
via holes
dielectric layer
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PCT/CN2017/084601
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English (en)
French (fr)
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张海杰
张占东
杨玲
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武汉华星光电技术有限公司
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Priority to KR1020197032764A priority Critical patent/KR102314509B1/ko
Priority to EP17904463.1A priority patent/EP3608950A4/en
Priority to US15/544,023 priority patent/US10181484B2/en
Publication of WO2018184279A1 publication Critical patent/WO2018184279A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate and a TFT substrate.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • a liquid crystal display panel comprises a CF (Color Filter) substrate, a thin film transistor (TFT) substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor substrate, and a sealant frame ( Sealant) composition.
  • the TFT substrate is the main driving component in the liquid crystal display panel, which is directly related to the development direction of the high performance liquid crystal display device.
  • a method for fabricating a conventional TFT substrate includes the following steps:
  • Step 1 as shown in FIG. 1, a base substrate 100 is provided on which a buffer layer 200, an active layer 300, a gate insulating layer 400, a gate 500, and a layer are sequentially formed from bottom to top.
  • Step 2 As shown in FIG. 2, the interlayer dielectric layer 600 and the gate insulating layer 400 are simultaneously etched, and the interlayer dielectric layer 600 and the gate insulating layer 400 are respectively formed corresponding to the active layer. Through holes at both ends of layer 300;
  • Step 3 as shown in FIG. 3, a source 700 and a drain 800, a flat layer 900, a common electrode 1000, a passivation layer 1100, and a pixel electrode 1200 are sequentially formed on the interlayer dielectric layer 600 from bottom to top. .
  • step 2 of the method for fabricating the TFT substrate since the total thickness of the interlayer dielectric layer 600 and the gate insulating layer 400 is large, the process of simultaneously etching the two is relatively difficult to control.
  • the system is prone to inconsistency in the through hole or the over-etching of the via hole causes the loss of the active layer 300 to be inconsistent, resulting in abnormality of the product. Therefore, it is necessary to provide an improved TFT substrate fabrication method to solve the above problems.
  • An object of the present invention is to provide a method for fabricating a TFT substrate, which can improve the uniformity of the active layer, reduce the difficulty of the process, avoid the problem of etching stop caused by thick etching, and improve product quality.
  • Another object of the present invention is to provide a TFT substrate, which can improve the uniformity of the active layer, reduce the difficulty of the process, avoid the problem of etching stop caused by thick etching, and improve product quality.
  • the present invention first provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 providing a base substrate on which a buffer layer and an active layer are sequentially formed from bottom to top; ion doping is performed on both ends of the active layer to form a two-ion heavily doped region; Forming a gate insulating layer on the active layer and the buffer layer;
  • Step 2 forming a photoresist layer on the gate insulating layer, exposing and developing the photoresist layer by using a halftone mask, and forming a first recess and two first via holes in the photoresist layer
  • the first recess is located above the channel region to be formed between the two ion heavily doped regions, and the two first via holes are respectively located above the two ion heavily doped regions;
  • Step 3 etch the gate insulating layer with the remaining photoresist layer as an occlusion, and form two first via holes corresponding to the regions below the two first via holes respectively on the gate insulating layer;
  • Step 4 performing overall thinning treatment on the photoresist layer, so that the first groove is converted into a second through hole;
  • the active layer is ion-doped with the remaining photoresist layer as an occlusion, and a channel region is formed in a region of the active layer corresponding to the second via hole;
  • Step 5 stripping the remaining photoresist layer, depositing a first metal layer on the gate insulating layer, patterning the first metal layer to obtain a gate corresponding to the channel region, and Two jumper metal blocks respectively located in the two first via holes;
  • Step 6 Ion doping the active layer with the gate as an occlusion, and obtaining a two-ion lightly doped region respectively located between the channel region and the two-ion heavily doped region;
  • Step 7 forming an interlayer dielectric layer on the gate insulating layer, etching the interlayer dielectric layer, and forming the interlayer dielectric layer on the interlayer dielectric layer Two second vias;
  • Step 8 Depositing a second metal layer on the interlayer dielectric layer, and patterning the second metal layer to form a spacer layer on the interlayer dielectric layer and passing through the two second via holes respectively. a source and a drain in contact with the two jumper metal blocks;
  • Step 9 On the interlayer dielectric layer, a flat layer, a common electrode, a passivation layer and a pixel electrode are sequentially formed from bottom to top.
  • the method of etching the gate insulating layer and the interlayer dielectric layer in the step 7 in the step 3 is dry etching.
  • the photoresist layer is integrally thinned by a method of photoresist ashing.
  • the pixel electrode is in contact with the drain through a third via penetrating through the planarization layer and the passivation layer.
  • the base substrate is a glass substrate; the buffer layer, the gate insulating layer, the interlayer dielectric layer, and the passivation layer are made of a combination of one or more of silicon nitride and silicon oxide;
  • the material of the source layer is polysilicon; the material of the gate and the bridging metal block comprises at least one of molybdenum, aluminum, copper, titanium, tungsten, and an alloy of the above metals; the material of the flat layer is transparent organic insulation Material; the material of the common electrode and the pixel electrode is indium tin oxide.
  • the present invention also provides a TFT substrate, comprising: a base substrate, a buffer layer covering the base substrate, an active layer disposed on the buffer layer, covering the active layer and the buffer layer a gate insulating layer, two first via holes penetrating the gate insulating layer, two jumper metal blocks respectively located in the two first via holes, a gate electrode disposed on the gate insulating layer, and covering An interlayer dielectric layer on the gate and the gate insulating layer, two second vias penetrating the interlayer dielectric layer, and source and drain electrodes spaced apart from the interlayer dielectric layer, And a flat layer, a common electrode, a passivation layer and a pixel electrode which are disposed on the source, the drain and the interlayer dielectric layer from bottom to top;
  • the active layer includes: a channel region, two ion heavily doped regions respectively located on both sides of the channel region, and two ion lightly doped regions respectively located between the channel region and the two ion heavily doped regions;
  • the two first via holes are respectively located above the two ion heavily doped regions, and the two jumper metal blocks are respectively in contact with the two ion heavily doped regions, and the gate is located on the gate insulating layer on the channel region ;
  • the two second via holes are respectively connected to the two first via holes, and the source and the drain are respectively in contact with the two jumper metal blocks through the two second via holes.
  • the pixel electrode is in contact with the drain through a third via penetrating through the planarization layer and the passivation layer.
  • the first via is obtained by dry etching a gate insulating layer separately, and the second via is obtained by dry etching a separate interlayer dielectric layer.
  • the base substrate is a glass substrate; the buffer layer, the gate insulating layer, the interlayer dielectric layer, and the passivation layer are made of a combination of one or more of silicon nitride and silicon oxide; Source layer The material is polysilicon; the material of the gate and the bridging metal block comprises at least one of molybdenum, aluminum, copper, titanium, tungsten, and an alloy of the above metals; the material of the flat layer is a transparent organic insulating material; The materials of the common electrode and the pixel electrode are both indium tin oxide.
  • the invention also provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 providing a base substrate on which a buffer layer and an active layer are sequentially formed from bottom to top; ion doping is performed on both ends of the active layer to form a two-ion heavily doped region; Forming a gate insulating layer on the active layer and the buffer layer;
  • Step 2 forming a photoresist layer on the gate insulating layer, exposing and developing the photoresist layer by using a halftone mask, and forming a first recess and two first via holes in the photoresist layer
  • the first recess is located above the channel region to be formed between the two ion heavily doped regions, and the two first via holes are respectively located above the two ion heavily doped regions;
  • Step 3 etch the gate insulating layer with the remaining photoresist layer as an occlusion, and form two first via holes corresponding to the regions below the two first via holes respectively on the gate insulating layer;
  • Step 4 performing overall thinning treatment on the photoresist layer, so that the first groove is converted into a second through hole;
  • the active layer is ion-doped with the remaining photoresist layer as an occlusion, and a channel region is formed in a region of the active layer corresponding to the second via hole;
  • Step 5 stripping the remaining photoresist layer, depositing a first metal layer on the gate insulating layer, patterning the first metal layer to obtain a gate corresponding to the channel region, and Two jumper metal blocks respectively located in the two first via holes;
  • Step 6 Ion doping the active layer with the gate as an occlusion, and obtaining a two-ion lightly doped region respectively located between the channel region and the two-ion heavily doped region;
  • Step 7 forming an interlayer dielectric layer on the gate insulating layer, etching the interlayer dielectric layer, and forming the interlayer dielectric layer on the interlayer dielectric layer Two second vias;
  • Step 8 Depositing a second metal layer on the interlayer dielectric layer, and patterning the second metal layer to form a spacer layer on the interlayer dielectric layer and passing through the two second via holes respectively. a source and a drain in contact with the two jumper metal blocks;
  • Step 9 forming a flat layer, a common electrode, a passivation layer, and a pixel electrode in sequence from the bottom to the top on the interlayer dielectric layer;
  • the method for etching the gate insulating layer and the interlayer dielectric layer in the step 7 in the step 3 is dry etching
  • the photoresist layer is subjected to overall thinning treatment by a method of photoresist ashing.
  • the present invention provides a method for fabricating a TFT substrate by first etching a gate insulating layer to form two first via holes, and forming a two-span metal block in the two first via holes, and etching the interlayer.
  • the dielectric layer forms two second vias respectively communicating with the two first vias, and the source and the drain are respectively in contact with the two jumper metal blocks through the two second via holes, and the gate is formed by a conventional one-time etching process.
  • the via structure of the insulating layer and the interlayer dielectric layer is improved into two etching processes, which can improve the uniformity of the active layer, reduce the difficulty of the process, avoid the problem of etching stop caused by thick etching, and improve product quality.
  • the invention also provides a TFT substrate, which can improve the uniformity of the active layer, reduce the difficulty of the process, avoid the problem of etching stop caused by the thick etching thickness, and improve the product quality.
  • FIG. 1 is a schematic view showing a step 1 of a method of fabricating a conventional TFT substrate
  • FIG. 2 is a schematic view showing a step 2 of a method for fabricating a conventional TFT substrate
  • FIG. 3 is a schematic view showing a step 3 of a method for fabricating a conventional TFT substrate
  • FIG. 4 is a flow chart showing a method of fabricating a TFT substrate of the present invention.
  • FIG. 5 is a schematic view showing a step 1 of a method of fabricating a TFT substrate of the present invention
  • FIG. 6 is a schematic view showing a step 2 of a method of fabricating a TFT substrate of the present invention
  • FIG. 7 is a schematic view showing a step 3 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 8 is a schematic view showing a step 4 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 9 is a schematic view showing a step 5 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 10 is a schematic view showing a step 6 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 11 is a schematic view showing a step 7 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 12 is a schematic view showing a step 8 of a method of fabricating a TFT substrate of the present invention.
  • Fig. 13 is a schematic view showing the step 9 of the method for fabricating the TFT substrate of the present invention and a schematic structural view of the TFT substrate of the present invention.
  • the present invention provides a method for fabricating a TFT substrate, including the following steps:
  • Step 1 as shown in FIG. 5, providing a substrate 10, on which the buffer layer 20 and the active layer 30 are sequentially formed from bottom to top;
  • a gate insulating layer 40 is formed on the active layer 30 and the buffer layer 20.
  • the base substrate 10 is a glass substrate.
  • the material of the buffer layer 20 is a combination of one or more of silicon nitride (SiN x ) and silicon oxide (SiO x ), respectively.
  • the material of the active layer 30 is polysilicon.
  • the two ends of the active layer 30 are ion doped by using a photomask.
  • Step 2 as shown in FIG. 6, a photoresist layer 50 is formed on the gate insulating layer 40, and the photoresist layer 50 is exposed and developed by a halftone mask to form in the photoresist layer 50.
  • a first groove 51 and two first through holes 52 the first groove 51 is located above the channel region to be formed between the two ion heavily doped regions 31, and the two first through holes 52 respectively Located above the two ion heavily doped region 31;
  • the material of the gate insulating layer 40 is a combination of one or more of silicon nitride and silicon oxide, respectively.
  • Step 3 as shown in FIG. 7, the gate insulating layer 40 is etched with the remaining photoresist layer 50 as an occlusion, and the gate insulating layer 40 corresponds to the two first via holes 52, respectively.
  • the area forms two first vias 41.
  • the method of etching the gate insulating layer 40 is dry etching.
  • the process for performing etching is easy to control, the process uniformity is better, and the problem that the loss of the active layer 30 is inconsistent due to the un-perforated via hole or the over-hole over-etching is not easy to occur.
  • Product quality since the thickness of the gate insulating layer is thin, the process for performing etching is easy to control, the process uniformity is better, and the problem that the loss of the active layer 30 is inconsistent due to the un-perforated via hole or the over-hole over-etching is not easy to occur.
  • Step 4 as shown in Figure 8, the photoresist layer 50 is thinned as a whole, so that the first groove 51 is converted into a second through hole 53;
  • the active layer 30 is ion-doped with the remaining photoresist layer 50 as an occlusion, and a channel region 32 is formed in a region of the active layer 30 corresponding to the lower portion of the second via hole 53.
  • the photoresist layer 50 is subjected to overall thinning treatment by a method of photoresist ashing.
  • Step 5 peeling off the remaining photoresist layer 50 on the gate insulating layer 40 Depositing a first metal layer, and patterning the first metal layer to obtain a gate 60 corresponding to the upper portion of the channel region 32 and two jumper metals respectively located in the two first via holes 41 Block 61.
  • the material of the gate 60 and the two bridging metal blocks 61 include alloys of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), and the above metals. At least one.
  • Step 6 as shown in FIG. 10, the entire active layer 30 is ion-doped with the gate 60 as an occlusion without using a photomask, and the channel region 32 and the two-ion heavily doped region are obtained.
  • Step 7 as shown in FIG. 11, an interlayer dielectric layer 70 is formed on the gate insulating layer 40, and the interlayer dielectric layer 70 is etched, and the interlayer dielectric layer 70 is formed separately.
  • the two bridges the two second via holes 71 above the metal block 61.
  • the method of etching the interlayer dielectric layer 70 is dry etching.
  • the bottom layer of the second via hole 71 is a jumper metal block 61, there is no need to worry about the loss of the underlying active layer 30 (Loss) during etching, and the process limit (Window) is large, which can effectively reduce the process. Difficulty, avoiding the problem of etching stop due to thick etching thickness and improving product quality.
  • the material of the interlayer dielectric layer 70 is a combination of one or more of silicon nitride (SiN x ) and silicon oxide (SiO x ), respectively.
  • Step 8 As shown in FIG. 12, a second metal layer is deposited on the interlayer dielectric layer 70, and the second metal layer is patterned to obtain a spacer distribution on the interlayer dielectric layer 70. And the source 81 and the drain 82 which are in contact with the two bridging metal blocks 61 through the two second via holes 71, respectively.
  • Step 9 As shown in FIG. 13, a flat layer 90, a common electrode 101, a passivation layer 110, and a pixel electrode 102 are sequentially formed on the interlayer dielectric layer 70 from bottom to top.
  • a third via hole 111 above the drain electrode 82 is formed on the passivation layer 110 and the flat layer 90, and the pixel electrode 102 passes through the third via hole 111. Contact with the drain 82.
  • the material of the flat layer 90 is a transparent organic insulating material.
  • the materials of the common electrode 101 and the pixel electrode 102 are both indium tin oxide.
  • the material of the passivation layer 110 is a combination of one or more of silicon nitride (SiN x ) and silicon oxide (SiO x ), respectively.
  • the method for fabricating the TFT substrate described above is to improve the via structure of the gate insulating layer 40 and the interlayer dielectric layer 70 by a conventional one-time etching process to two etching processes, first etching the gate insulating layer 40, due to gate insulation.
  • the thickness of the layer 40 is thin, and the process uniformity is better, which can effectively avoid etching
  • the active layer 30 is unevenly distributed, and the interlayer dielectric layer 70 is etched.
  • the bottom of the second via 71 is bridged over the metal block 61, which avoids the influence of etching on the active layer 30, and the process boundary is large. It can effectively reduce the difficulty of the process, avoid the problem of etching stop due to thick etching thickness, and improve product quality.
  • the present invention further provides a TFT substrate, comprising: a substrate substrate 10 , a buffer layer 20 covering the substrate substrate 10 , and a buffer layer 20 disposed on the buffer layer 20 .
  • the upper active layer 30, the gate insulating layer 40 covering the active layer 30 and the buffer layer 20, and the two first via holes 41 penetrating the gate insulating layer 40 are respectively located in the two first via holes a two-span metal block 61 in the 41, a gate 60 disposed on the gate insulating layer 40, an interlayer dielectric layer 70 overlying the gate 60 and the gate insulating layer 40,
  • Two second vias 71 of the interlayer dielectric layer 70, a source 81 and a drain 82 spaced apart from the interlayer dielectric layer 70, and a source 81, a drain 82 and an interlayer a flat layer 90, a common electrode 101, a passivation layer 110, and a pixel electrode 102 are stacked on the dielectric layer 70 from bottom to top;
  • the active layer 30 includes a channel region 32, two ion heavily doped regions 31 respectively located on both sides of the channel region 32, and two ions lightly located between the channel region 32 and the two ion heavily doped regions 31, respectively.
  • the two first via holes 41 are respectively located above the two ion heavily doped regions 31, and the two jumper metal blocks 61 are respectively in contact with the two ion heavily doped regions 31, and the gate electrodes 60 are located on the channel region 32.
  • the gate insulating layer 40 On the gate insulating layer 40;
  • the two second via holes 71 are respectively connected to the two first via holes 41 , and the source electrode 81 and the drain electrode 82 are respectively in contact with the two jumper metal blocks 61 through the two second via holes 71 .
  • the first via hole 41 is obtained by dry etching the gate insulating layer 40 alone.
  • the second via 71 is obtained by dry etching the interlayer dielectric layer 70 separately.
  • the pixel electrode 102 is in contact with the drain 82 through the third via 111 penetrating the passivation layer 110 and the planar layer 90.
  • the base substrate 10 is a glass substrate.
  • the materials of the buffer layer 20, the gate insulating layer 40, the interlayer dielectric layer 70, and the passivation layer 110 are one or more of silicon nitride (SiN x ) and silicon oxide (SiO x ), respectively. Combination of species.
  • the material of the active layer 30 is polysilicon.
  • the material of the gate 60 and the bridging metal block 61 includes at least at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), and an alloy of the above metals.
  • Mo molybdenum
  • Al aluminum
  • Cu copper
  • Ti titanium
  • W tungsten
  • the material of the flat layer 90 is a transparent organic insulating material.
  • the materials of the common electrode 101 and the pixel electrode 102 are both indium tin oxide.
  • a conventional via insulating layer 40 and a via structure of the interlayer dielectric layer 70 are divided into two via structures, and the gate insulating layer 40 is first etched. Since the gate insulating layer 40 is thin, The uniformity of the process is better, and the loss of the active layer 30 due to the etching is effectively avoided, and the interlayer dielectric layer 70 is etched, and the bottom of the second via 71 is bridged over the metal block 61, thereby avoiding etching.
  • the influence of the source layer 30 has a large process limit, which can effectively reduce the difficulty of the process, avoid the problem of etching stop due to thick etching thickness, and improve product quality.
  • the gate insulating layer is first etched to form two first via holes, and the two first via holes are formed in the first via holes, and then the interlayer is etched.
  • the dielectric layer forms two second vias respectively communicating with the two first vias, and the source and the drain are respectively in contact with the two jumper metal blocks through the two second via holes, and the gate is formed by a conventional one-time etching process.
  • the via structure of the insulating layer and the interlayer dielectric layer is improved into two etching processes, which can improve the uniformity of the active layer, reduce the difficulty of the process, avoid the problem of etching stop caused by thick etching, and improve product quality.

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Abstract

一种TFT基板的制作方法及TFT基板。TFT基板的制作方法包括：先蚀刻栅极绝缘层（40）形成两第一过孔（41），并在两第一过孔（41）内形成两跨接金属块（61），再蚀刻层间介电层（70）形成分别与两第一过孔（41）连通的两第二过孔（71），源极（81）和漏极（82）分别通过两第二过孔（71）与两跨接金属块（61）接触。通过将传统的一次蚀刻工艺制作出栅极绝缘层与层间介电层的过孔结构改进为两次蚀刻工艺，能够提升有源层的均一性，降低制程难度，避免因蚀刻厚度较厚而造成的蚀刻停止的问题，提升产品品质。

Description

TFT基板的制作方法及TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及TFT基板。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF，Color Filter)基板、薄膜晶体管(TFT，Thin Film Transistor)基板、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成。其中，TFT基板是液晶显示面板中的主要驱动元件，直接关系到高性能液晶显示装置的发展方向。
如图1至图3所示，现有的TFT基板的制作方法包括如下步骤：
步骤1、如图1所示，提供衬底基板100，在所述衬底基板100上从下到上依次制作缓冲层200、有源层300、栅极绝缘层400、栅极500、及层间介电层600；
步骤2、如图2所示，对所述层间介电层600与栅极绝缘层400同时进行蚀刻，在所述层间介电层600与栅极绝缘层400上形成分别对应于有源层300两端的通孔；
步骤3、如图3所示，在所述层间介电层600上从下到上依次制作源极700与漏极800、平坦层900、公共电极1000、钝化层1100、及像素电极1200。
上述TFT基板的制作方法的步骤2中，由于所述层间介电层600与栅极绝缘层400的总厚度较大，因此对二者同时进行蚀刻的制程比较难以控 制，容易出现通孔未刻穿或者通孔过蚀刻导致有源层300损失量不一致的情况，造成产品异常。因此有必要提供一种改进的TFT基板的制作方法，以解决上述问题。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，能够提升有源层的均一性，降低制程难度，避免因蚀刻厚度较厚而造成的蚀刻停止的问题，提升产品品质。
本发明的目的还在于提供一种TFT基板，能够提升有源层的均一性，降低制程难度，避免因蚀刻厚度较厚而造成的蚀刻停止的问题，提升产品品质。
为实现上述目的，本发明首先提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供衬底基板，在所述衬底基板上从下到上依次制作缓冲层与有源层；对所述有源层两端进行离子掺杂，形成两离子重掺杂区；在所述有源层与缓冲层上形成栅极绝缘层；
步骤2、在所述栅极绝缘层上形成光阻层，采用半色调光罩对所述光阻层进行曝光、显影，在所述光阻层中形成第一凹槽和两第一通孔；所述第一凹槽位于所述两离子重掺杂区之间待形成的沟道区的上方，所述两第一通孔分别位于所述两离子重掺杂区的上方；
步骤3、以剩余光阻层为遮挡，对所述栅极绝缘层进行蚀刻，在所述栅极绝缘层分别对应于所述两第一通孔下方的区域形成两第一过孔；
步骤4、对所述光阻层进行整体薄化处理，使得所述第一凹槽转化为第二通孔；
以剩余的光阻层为遮挡，对所述有源层进行离子掺杂，在有源层对应位于所述第二通孔下方的区域形成沟道区；
步骤5、剥离剩余的光阻层，在所述栅极绝缘层上沉积第一金属层，对所述第一金属层进行图形化处理，得到对应于所述沟道区上方的栅极、以及分别位于两第一过孔内的两跨接金属块；
步骤6、以所述栅极为遮挡对有源层进行离子掺杂，得到分别位于沟道区与两离子重掺杂区之间的两离子轻掺杂区；
步骤7、在所述栅极绝缘层上形成层间介电层，对所述层间介电层进行蚀刻，在所述层间介电层上形成分别位于所述两跨接金属块上方的两第二过孔；
步骤8、在所述层间介电层上沉积第二金属层，对所述第二金属层进行图形化处理，得到间隔分布于所述层间介电层上并分别通过两第二过孔与两跨接金属块接触的源极与漏极；
步骤9、在所述层间介电层上从下到上依次制作平坦层、公共电极、钝化层及像素电极。
所述步骤3中对所述栅极绝缘层和所述步骤7中对所述层间介电层进行蚀刻的方法均为干蚀刻。
所述步骤4中，采用光阻灰化的方法对所述光阻层进行整体薄化处理。
所述像素电极通过贯穿所述平坦层和钝化层中的第三过孔与所述漏极接触。
所述衬底基板为玻璃基板；所述缓冲层、栅极绝缘层、层间介电层、钝化层的材料为氮化硅和氧化硅中的一种或多种的组合；所述有源层的材料为多晶硅；所述栅极与跨接金属块的材料包括钼、铝、铜、钛、钨、及以上金属的合金中的至少一种；所述平坦层的材料为透明有机绝缘材料；所述公共电极与像素电极的材料均为氧化铟锡。
本发明还提供一种TFT基板，包括：衬底基板、覆盖于所述衬底基板上的缓冲层、设于所述缓冲层上的有源层、覆盖于所述有源层和缓冲层上的栅极绝缘层、贯穿所述栅极绝缘层的两第一过孔、分别位于两第一过孔内的两跨接金属块、设于所述栅极绝缘层上的栅极、覆盖于所述栅极以及栅极绝缘层上的层间介电层、贯穿所述层间介电层的两第二过孔、间隔分布于所述层间介电层上的源极与漏极、以及设于所述源极、漏极和层间介电层上自下而上层叠设置的平坦层、公共电极、钝化层和像素电极；
所述有源层包括：沟道区、分别位于沟道区两侧的两离子重掺杂区和分别位于沟道区与两离子重掺杂区之间的两离子轻掺杂区；
所述两第一过孔分别位于两离子重掺杂区的上方，所述两跨接金属块分别与两离子重掺杂区接触，所述栅极位于沟道区上的栅极绝缘层上；
所述两第二过孔分别与两第一过孔连通，所述源极和漏极分别通过两第二过孔与两跨接金属块接触。
所述像素电极通过贯穿所述平坦层和钝化层中的第三过孔与所述漏极接触。
所述第一过孔通过对栅极绝缘层单独进行干蚀刻得到，所述第二过孔通过对层间介电层单独进行干蚀刻得到。
所述衬底基板为玻璃基板；所述缓冲层、栅极绝缘层、层间介电层、钝化层的材料为氮化硅和氧化硅中的一种或多种的组合；所述有源层的材 料为多晶硅；所述栅极与跨接金属块的材料包括钼、铝、铜、钛、钨、及以上金属的合金中的至少一种；所述平坦层的材料为透明有机绝缘材料；所述公共电极与像素电极的材料均为氧化铟锡。
本发明还提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供衬底基板，在所述衬底基板上从下到上依次制作缓冲层与有源层；对所述有源层两端进行离子掺杂，形成两离子重掺杂区；在所述有源层与缓冲层上形成栅极绝缘层；
步骤2、在所述栅极绝缘层上形成光阻层，采用半色调光罩对所述光阻层进行曝光、显影，在所述光阻层中形成第一凹槽和两第一通孔；所述第一凹槽位于所述两离子重掺杂区之间待形成的沟道区的上方，所述两第一通孔分别位于所述两离子重掺杂区的上方；
步骤3、以剩余的光阻层为遮挡，对所述栅极绝缘层进行蚀刻，在所述栅极绝缘层分别对应于所述两第一通孔下方的区域形成两第一过孔；
步骤4、对所述光阻层进行整体薄化处理，使得所述第一凹槽转化为第二通孔；
以剩余的光阻层为遮挡，对所述有源层进行离子掺杂，在有源层对应位于所述第二通孔下方的区域形成沟道区；
步骤5、剥离剩余的光阻层，在所述栅极绝缘层上沉积第一金属层，对所述第一金属层进行图形化处理，得到对应于所述沟道区上方的栅极、以及分别位于两第一过孔内的两跨接金属块；
步骤6、以所述栅极为遮挡对有源层进行离子掺杂，得到分别位于沟道区与两离子重掺杂区之间的两离子轻掺杂区；
步骤7、在所述栅极绝缘层上形成层间介电层，对所述层间介电层进行蚀刻，在所述层间介电层上形成分别位于所述两跨接金属块上方的两第二过孔；
步骤8、在所述层间介电层上沉积第二金属层，对所述第二金属层进行图形化处理，得到间隔分布于所述层间介电层上并分别通过两第二过孔与两跨接金属块接触的源极与漏极；
步骤9、在所述层间介电层上从下到上依次制作平坦层、公共电极、钝化层及像素电极；
其中，所述步骤3中对所述栅极绝缘层和所述步骤7中对所述层间介电层进行蚀刻的方法均为干蚀刻；
其中，所述步骤4中，采用光阻灰化的方法对所述光阻层进行整体薄化处理。
本发明的有益效果：本发明提供一种TFT基板的制作方法，先蚀刻栅极绝缘层形成两第一过孔，并在两第一过孔内形成与两跨接金属块，再蚀刻层间介电层形成分别与两第一过孔连通的两第二过孔，源极和漏极分别通过两第二过孔与两跨接金属块接触，通过将传统的一次蚀刻工艺制作出栅极绝缘层与层间介电层的过孔结构改进为两次蚀刻工艺，能够提升有源层的均一性，降低制程难度，避免因蚀刻厚度较厚而造成的蚀刻停止的问题，提升产品品质。本发明还提供一种TFT基板，能够提升有源层的均一性，降低制程难度，避免因蚀刻厚度较厚而造成的蚀刻停止的问题，提升产品品质。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的TFT基板的制作方法的步骤1的示意图；
图2为现有的TFT基板的制作方法的步骤2的示意图；
图3为现有的TFT基板的制作方法的步骤3的示意图；
图4为本发明的TFT基板的制作方法的流程图；
图5为本发明的TFT基板的制作方法的步骤1的示意图；
图6为本发明的TFT基板的制作方法的步骤2的示意图；
图7为本发明的TFT基板的制作方法的步骤3的示意图；
图8为本发明的TFT基板的制作方法的步骤4的示意图；
图9为本发明的TFT基板的制作方法的步骤5的示意图；
图10为本发明的TFT基板的制作方法的步骤6的示意图；
图11为本发明的TFT基板的制作方法的步骤7的示意图；
图12为本发明的TFT基板的制作方法的步骤8的示意图；
图13为本发明的TFT基板的制作方法的步骤9的示意图暨本发明的TFT基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图4，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、如图5所示，提供衬底基板10，在所述衬底基板10上从下到上依次制作缓冲层20与有源层30；
对所述有源层30两端进行离子掺杂，形成两离子重掺杂区31；
在所述有源层30与缓冲层20上形成栅极绝缘层40。
具体地，所述衬底基板10为玻璃基板。
具体地，所述缓冲层20的材料分别为氮化硅(SiNx)和氧化硅(SiOx)中的一种或多种的组合。
具体地，所述有源层30的材料为多晶硅。
具体地，所述步骤1中，采用一道光罩对所述有源层30两端进行离子掺杂。
步骤2、如图6所示，在所述栅极绝缘层40上形成光阻层50，采用半色调光罩对所述光阻层50进行曝光、显影，在所述光阻层50中形成第一凹槽51和两第一通孔52；所述第一凹槽51位于所述两离子重掺杂区31之间待形成的沟道区的上方，所述两第一通孔52分别位于所述两离子重掺杂区31的上方；
具体地，所述栅极绝缘层40的材料分别为氮化硅和氧化硅中的一种或多种的组合。
步骤3、如图7所示，以剩余的光阻层50为遮挡，对所述栅极绝缘层40进行蚀刻，在所述栅极绝缘层40分别对应于所述两第一通孔52下方的区域形成两第一过孔41。
具体地，所述步骤3中，对所述栅极绝缘层40进行蚀刻的方法为干蚀刻。
具体地，由于栅极绝缘层厚度较薄，进行蚀刻的制程容易控制，制程均一性较佳，不容易出现过孔未刻穿或者过孔过蚀刻导致有源层30损失量不一致的问题，提升了产品品质。
步骤4、如图8所示，对所述光阻层50进行整体薄化处理，使得所述第一凹槽51转化为第二通孔53；
以剩余的光阻层50为遮挡，对所述有源层30进行离子掺杂，在有源层30对应位于所述第二通孔53下方的区域形成沟道区32。
具体地，所述步骤4中，采用光阻灰化的方法对所述光阻层50进行整体薄化处理。
步骤5、如图9所示，剥离剩余的光阻层50，在所述栅极绝缘层40上 沉积第一金属层，对所述第一金属层进行图形化处理，得到对应于所述沟道区32上方的栅极60、以及分别位于所述两第一过孔41内的两跨接金属块61。
具体的，所述栅极60与两跨接金属块61的材料包括钼(Mo)、铝(Al)、铜(Cu)、钛(Ti)、钨(W)、及以上金属的合金中的至少一种。
步骤6、如图10所示，在不采用光罩的情况下，以所述栅极60为遮挡对整个有源层30进行离子掺杂，得到位于沟道区32与两离子重掺杂区31之间的两离子轻掺杂区34。
步骤7、如图11所示，在所述栅极绝缘层40上形成层间介电层70，对所述层间介电层70进行蚀刻，在所述层间介电层70形成分别位于所述两跨接金属块61上方的两第二过孔71。
具体地，所述步骤7中，对所述层间介电层70进行蚀刻的方法为干蚀刻。
具体地，由于所述第二过孔71的底层为跨接金属块61，因此在蚀刻的时候不用担心底层有源层30损失量(Loss)，制程界限(Window)较大，可有效降低制程难度，避免因蚀刻厚度较厚而造成蚀刻停止的问题，提升产品品质。
具体地，所述层间介电层70的材料分别为氮化硅(SiNx)和氧化硅(SiOx)中的一种或多种的组合。
步骤8、如图12所示，在所述层间介电层70上沉积第二金属层，对所述第二金属层进行图形化处理，得到间隔分布于所述层间介电层70上并分别通过两第二过孔71与两跨接金属块61接触的源极81与漏极82。
步骤9、如图13所示，在所述层间介电层70上从下到上依次制作平坦层90、公共电极101、钝化层110及像素电极102。
具体地，所述步骤9中，在所述钝化层110以及平坦层90上形成位于所述漏极82的上方的第三过孔111，所述像素电极102通过所述第三过孔111与漏极82接触。
具体地，所述平坦层90的材料为透明有机绝缘材料。
具体地，所述公共电极101与像素电极102的材料均为氧化铟锡。
具体地，所述钝化层110的材料分别为氮化硅(SiNx)和氧化硅(SiOx)中的一种或多种的组合。
上述TFT基板的制作方法，将传统的一次蚀刻工艺制作出栅极绝缘层40与层间介电层70的过孔结构改进为两次蚀刻工艺，先蚀刻栅极绝缘层40，由于栅极绝缘层40厚度较薄，制程均一性较佳，可有效避免因蚀刻造 成的有源层30损失不均，再蚀刻层间介电层70，其第二过孔71的底部为跨接金属块61，避免了蚀刻对有源层30的影响，制程界限较大，可有效降低制程难度，避免因蚀刻厚度较厚而造成蚀刻停止的问题，提升产品品质。
请参阅图13，基于上述TFT基板的制作方法，本发明还提供一种TFT基板，包括：衬底基板10、覆盖于所述衬底基板10上的缓冲层20、设于所述缓冲层20上的有源层30、覆盖于所述有源层30和缓冲层20上的栅极绝缘层40、贯穿所述栅极绝缘层40的两第一过孔41、分别位于两第一过孔41内的两跨接金属块61、设于所述栅极绝缘层40上的栅极60、覆盖于所述栅极60以及栅极绝缘层40上的层间介电层70、贯穿所述层间介电层70的两第二过孔71、间隔分布于所述层间介电层70上的源极81与漏极82、以及设于所述源极81、漏极82和层间介电层70上自下而上层叠设置的平坦层90、公共电极101、钝化层110和像素电极102；
所述有源层30包括：沟道区32、分别位于沟道区32两侧的两离子重掺杂区31和分别位于沟道区32与两离子重掺杂区31之间的两离子轻掺杂区34；
所述两第一过孔41分别位于两离子重掺杂区31的上方，所述两跨接金属块61分别与两离子重掺杂区31接触，所述栅极60位于沟道区32上的栅极绝缘层40上；
所述两第二过孔71分别与两第一过孔41连通，所述源极81和漏极82分别通过两第二过孔71与两跨接金属块61接触。
具体地，所述第一过孔41通过对栅极绝缘层40单独进行干蚀刻得到。
具体地，所述第二过孔71通过对层间介电层70单独进行干蚀刻得到。
具体地，所述像素电极102通过贯穿所述钝化层110以及平坦层90的第三过孔111与漏极82接触。
具体地，所述衬底基板10为玻璃基板。
具体地，所述缓冲层20、栅极绝缘层40、层间介电层70、钝化层110的材料分别为氮化硅(SiNx)和氧化硅(SiOx)中的一种或多种的组合。
具体地，所述有源层30的材料为多晶硅。
具体地，所述栅极60与跨接金属块61的材料包括钼(Mo)、铝(Al)、铜(Cu)、钛(Ti)、钨(W)、及以上金属的合金中的至少一种。
具体地，所述平坦层90的材料为透明有机绝缘材料。
具体地，所述公共电极101与像素电极102的材料均为氧化铟锡。
上述TFT基板，将传统的栅极绝缘层40与层间介电层70的一过孔结构分为两个过孔结构，先蚀刻栅极绝缘层40，由于栅极绝缘层40厚度较薄， 制程均一性较佳，可有效避免因蚀刻造成的有源层30损失不均，再蚀刻层间介电层70，其第二过孔71的底部为跨接金属块61，避免了蚀刻对有源层30的影响，制程界限较大，可有效降低制程难度，避免因蚀刻厚度较厚而造成蚀刻停止的问题，提升产品品质。
综上所述，本发明的TFT基板的制作方法及TFT基板，先蚀刻栅极绝缘层形成两第一过孔，并在两第一过孔内形成与两跨接金属块，再蚀刻层间介电层形成分别与两第一过孔连通的两第二过孔，源极和漏极分别通过两第二过孔与两跨接金属块接触，通过将传统的一次蚀刻工艺制作出栅极绝缘层与层间介电层的过孔结构改进为两次蚀刻工艺，能够提升有源层的均一性，降低制程难度，避免因蚀刻厚度较厚而造成的蚀刻停止的问题，提升产品品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供衬底基板，在所述衬底基板上从下到上依次制作缓冲层与有源层；对所述有源层两端进行离子掺杂，形成两离子重掺杂区；在所述有源层与缓冲层上形成栅极绝缘层；
    步骤2、在所述栅极绝缘层上形成光阻层，采用半色调光罩对所述光阻层进行曝光、显影，在所述光阻层中形成第一凹槽和两第一通孔；所述第一凹槽位于所述两离子重掺杂区之间待形成的沟道区的上方，所述两第一通孔分别位于所述两离子重掺杂区的上方；
    步骤3、以剩余的光阻层为遮挡，对所述栅极绝缘层进行蚀刻，在所述栅极绝缘层分别对应于所述两第一通孔下方的区域形成两第一过孔；
    步骤4、对所述光阻层进行整体薄化处理，使得所述第一凹槽转化为第二通孔；
    以剩余的光阻层为遮挡，对所述有源层进行离子掺杂，在有源层对应位于所述第二通孔下方的区域形成沟道区；
    步骤5、剥离剩余的光阻层，在所述栅极绝缘层上沉积第一金属层，对所述第一金属层进行图形化处理，得到对应于所述沟道区上方的栅极、以及分别位于两第一过孔内的两跨接金属块；
    步骤6、以所述栅极为遮挡对有源层进行离子掺杂，得到分别位于沟道区与两离子重掺杂区之间的两离子轻掺杂区；
    步骤7、在所述栅极绝缘层上形成层间介电层，对所述层间介电层进行蚀刻，在所述层间介电层上形成分别位于所述两跨接金属块上方的两第二过孔；
    步骤8、在所述层间介电层上沉积第二金属层，对所述第二金属层进行图形化处理，得到间隔分布于所述层间介电层上并分别通过两第二过孔与两跨接金属块接触的源极与漏极；
    步骤9、在所述层间介电层上从下到上依次制作平坦层、公共电极、钝化层及像素电极。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤3中对所述栅极绝缘层和所述步骤7中对所述层间介电层进行蚀刻的方法均为干蚀刻。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤4中， 采用光阻灰化的方法对所述光阻层进行整体薄化处理。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述像素电极通过贯穿所述平坦层和钝化层中的第三过孔与所述漏极接触。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述衬底基板为玻璃基板；所述缓冲层、栅极绝缘层、层间介电层、钝化层的材料为氮化硅和氧化硅中的一种或多种的组合；所述有源层的材料为多晶硅；所述栅极与跨接金属块的材料包括钼、铝、铜、钛、钨、及以上金属的合金中的至少一种；所述平坦层的材料为透明有机绝缘材料；所述公共电极与像素电极的材料均为氧化铟锡。
  6. 一种TFT基板，包括：衬底基板、覆盖于所述衬底基板上的缓冲层、设于所述缓冲层上的有源层、覆盖于所述有源层和缓冲层上的栅极绝缘层、贯穿所述栅极绝缘层的两第一过孔、分别位于两第一过孔内的两跨接金属块、设于所述栅极绝缘层上的栅极、覆盖于所述栅极以及栅极绝缘层上的层间介电层、贯穿所述层间介电层的两第二过孔、间隔分布于所述层间介电层上的源极与漏极、以及设于所述源极、漏极和层间介电层上自下而上层叠设置的平坦层、公共电极、钝化层和像素电极；
    所述有源层包括：沟道区、分别位于沟道区两侧的两离子重掺杂区和分别位于沟道区与两离子重掺杂区之间的两离子轻掺杂区；
    所述两第一过孔分别位于两离子重掺杂区的上方，所述两跨接金属块分别与两离子重掺杂区接触，所述栅极位于沟道区上的栅极绝缘层上；
    所述两第二过孔分别与两第一过孔连通，所述源极和漏极分别通过两第二过孔与两跨接金属块接触。
  7. 如权利要求6所述的TFT基板，其中，所述像素电极通过贯穿所述平坦层和钝化层中的第三过孔与所述漏极接触。
  8. 如权利要求6所述的TFT基板，其中，所述第一过孔通过对栅极绝缘层单独进行干蚀刻得到，所述第二过孔通过对层间介电层单独进行干蚀刻得到。
  9. 如权利要求6所述的TFT基板，其中，所述衬底基板为玻璃基板；所述缓冲层、栅极绝缘层、层间介电层、钝化层的材料为氮化硅和氧化硅中的一种或多种的组合；所述有源层的材料为多晶硅；所述栅极与跨接金属块的材料包括钼、铝、铜、钛、钨、及以上金属的合金中的至少一种；所述平坦层的材料为透明有机绝缘材料；所述公共电极与像素电极的材料均为氧化铟锡。
  10. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供衬底基板，在所述衬底基板上从下到上依次制作缓冲层与有源层；对所述有源层两端进行离子掺杂，形成两离子重掺杂区；在所述有源层与缓冲层上形成栅极绝缘层；
    步骤2、在所述栅极绝缘层上形成光阻层，采用半色调光罩对所述光阻层进行曝光、显影，在所述光阻层中形成第一凹槽和两第一通孔；所述第一凹槽位于所述两离子重掺杂区之间待形成的沟道区的上方，所述两第一通孔分别位于所述两离子重掺杂区的上方；
    步骤3、以剩余的光阻层为遮挡，对所述栅极绝缘层进行蚀刻，在所述栅极绝缘层分别对应于所述两第一通孔下方的区域形成两第一过孔；
    步骤4、对所述光阻层进行整体薄化处理，使得所述第一凹槽转化为第二通孔；
    以剩余的光阻层为遮挡，对所述有源层进行离子掺杂，在有源层对应位于所述第二通孔下方的区域形成沟道区；
    步骤5、剥离剩余的光阻层，在所述栅极绝缘层上沉积第一金属层，对所述第一金属层进行图形化处理，得到对应于所述沟道区上方的栅极、以及分别位于两第一过孔内的两跨接金属块；
    步骤6、以所述栅极为遮挡对有源层进行离子掺杂，得到分别位于沟道区与两离子重掺杂区之间的两离子轻掺杂区；
    步骤7、在所述栅极绝缘层上形成层间介电层，对所述层间介电层进行蚀刻，在所述层间介电层上形成分别位于所述两跨接金属块上方的两第二过孔；
    步骤8、在所述层间介电层上沉积第二金属层，对所述第二金属层进行图形化处理，得到间隔分布于所述层间介电层上并分别通过两第二过孔与两跨接金属块接触的源极与漏极；
    步骤9、在所述层间介电层上从下到上依次制作平坦层、公共电极、钝化层及像素电极；
    其中，所述步骤3中对所述栅极绝缘层和所述步骤7中对所述层间介电层进行蚀刻的方法均为干蚀刻；
    其中，所述步骤4中，采用光阻灰化的方法对所述光阻层进行整体薄化处理。
  11. 如权利要求10所述的TFT基板的制作方法，其中，所述像素电极通过贯穿所述平坦层和钝化层中的第三过孔与所述漏极接触。
  12. 如权利要求10所述的TFT基板的制作方法，其中，所述衬底基板为玻璃基板；所述缓冲层、栅极绝缘层、层间介电层、钝化层的材料为氮 化硅和氧化硅中的一种或多种的组合；所述有源层的材料为多晶硅；所述栅极与跨接金属块的材料包括钼、铝、铜、钛、钨、及以上金属的合金中的至少一种；所述平坦层的材料为透明有机绝缘材料；所述公共电极与像素电极的材料均为氧化铟锡。
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