WO2023004844A1 - 阵列基板的制备方法、阵列基板和显示面板 - Google Patents

阵列基板的制备方法、阵列基板和显示面板 Download PDF

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Publication number
WO2023004844A1
WO2023004844A1 PCT/CN2021/110289 CN2021110289W WO2023004844A1 WO 2023004844 A1 WO2023004844 A1 WO 2023004844A1 CN 2021110289 W CN2021110289 W CN 2021110289W WO 2023004844 A1 WO2023004844 A1 WO 2023004844A1
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Prior art keywords
layer
metal
buffer
opening
array substrate
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PCT/CN2021/110289
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English (en)
French (fr)
Inventor
罗传宝
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/440,186 priority Critical patent/US20240055438A1/en
Publication of WO2023004844A1 publication Critical patent/WO2023004844A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present application relates to the display field, in particular to a method for preparing an array substrate, the array substrate and a display panel.
  • MLED Mini/Micro Light Emitting Diodes
  • OLED Organic Light Emitting Diode
  • MLED display technology array substrate technology controls the display of MLED as a key technology.
  • the preparation method of the array substrate used to control the MLED display is complicated at present.
  • the present application provides a method for preparing an array substrate, the array substrate and a display panel, so as to improve the production efficiency of the array substrate.
  • the present application provides a method for preparing an array substrate, including:
  • a first metal layer, a buffer layer and a semiconductor layer are sequentially formed on the substrate, and the first metal layer, the buffer layer and the semiconductor layer are patterned, and the first metal layer forms a first pole plate, the first light-shielding part and the first metal part, the buffer layer forms the first buffer part, the second buffer part and the third buffer part, the semiconductor layer forms the second electrode plate and the active part, and the The first pole plate, the first buffer part and the second pole plate are arranged correspondingly, the first light-shielding part, the second buffer part and the active part are arranged correspondingly, and the third buffer part is located at a side of the first metal part away from the substrate;
  • a second metal layer is formed on the side of the semiconductor layer away from the substrate, and the second metal layer is patterned to form a third plate, a drain, a gate, a source, and a connecting portion, and the connecting The part is connected with the first metal part.
  • the sequentially forming a first metal layer, a buffer layer, and a semiconductor layer on the substrate, after patterning the first metal layer, the buffer layer, and the semiconductor layer further includes:
  • a gate insulating layer covering the first metal layer, the buffer layer and the semiconductor layer, and patterning the gate insulating layer to form a first opening, a second opening, a third opening and The fourth opening, the first opening and the second opening expose the active portion, the third opening exposes the first light shielding portion, and the fourth opening exposes the first metal department.
  • the second metal layer is formed on the side of the semiconductor layer away from the substrate, and the second metal layer is patterned to form a third electrode plate, a drain electrode, a gate electrode, and a source electrode.
  • poles and connections also include:
  • first passivation layer covering the second metal layer, patterning the first passivation layer to form a first opening and a second opening, the first opening exposing the source, the first The two openings expose the connecting portion.
  • patterning the first passivation layer to form the first opening and the second opening further includes:
  • a protective layer is formed within the second opening.
  • the protective layer in the second opening after forming the protective layer in the second opening, it further includes:
  • a second passivation layer and a second light shielding portion are sequentially formed on a side of the first passivation layer away from the second metal layer.
  • a light emitting diode is arranged in the first opening.
  • the sequentially forming a first metal layer, a buffer layer, and a semiconductor layer on the substrate, and patterning the first metal layer, the buffer layer, and the semiconductor layer include:
  • the present application provides an array substrate, which is prepared by using the method for preparing an array substrate as described above, and the array substrate includes:
  • the first metal layer includes a first electrode plate, a first light shielding portion, and a first metal portion
  • the buffer layer includes a first buffer layer portion, a second buffer portion, and a third buffer portion
  • the semiconductor layer includes a second plate and an active portion, and the first plate, the first buffer portion, and the second plate are correspondingly arranged, so The first light-shielding part, the second buffer part and the active part are arranged correspondingly, and the third buffer part is located on a side of the first metal part away from the substrate;
  • a second metal layer is arranged on the side of the semiconductor layer away from the substrate, the second metal layer includes a third plate, a drain, a gate, a source and a connecting part, so The connection part is connected to the first metal part.
  • the second metal layer is a three-layer metal structure of indium zinc oxide/molybdenum/copper or a double-layer metal structure of molybdenum oxide/copper.
  • the thickness of the indium zinc oxide layer is 15 nm to 30 nm, and the thickness of the molybdenum oxide layer is 20 nm to 30 nm.
  • the array substrate further includes a first passivation layer covering the second metal layer, the first passivation layer includes a first opening and a second opening, so The first opening exposes the source electrode, and the second opening exposes the connecting portion.
  • a light emitting diode is disposed in the first opening, the light emitting diode is connected to the source, a protective layer is disposed in the second opening, and the protective layer covers the connecting portion.
  • the array substrate further includes a second passivation layer and a second light shielding portion, the second passivation layer is disposed on a side of the first passivation layer away from the second metal layer, The second light shielding portion is disposed on a side of the second passivation layer away from the first passivation layer.
  • a display panel comprising an array substrate, the array substrate comprising:
  • the first metal layer includes a first electrode plate, a first light shielding portion, and a first metal portion
  • the buffer layer includes a first buffer layer portion, a second buffer portion, and a third buffer portion
  • the semiconductor layer includes a second plate and an active portion, and the first plate, the first buffer portion, and the second plate are correspondingly arranged, so The first light-shielding part, the second buffer part and the active part are arranged correspondingly, and the third buffer part is located on a side of the first metal part away from the substrate;
  • a second metal layer is arranged on the side of the semiconductor layer away from the substrate, the second metal layer includes a third plate, a drain, a gate, a source and a connecting part, so The connection part is connected to the first metal part.
  • the second metal layer is a three-layer metal structure of indium zinc oxide/molybdenum/copper or a double-layer metal structure of molybdenum oxide/copper.
  • the thickness of the indium zinc oxide layer is 15 nm to 30 nm, and the thickness of the molybdenum oxide layer is 20 nm to 30 nm.
  • the array substrate further includes a first passivation layer covering the second metal layer, the first passivation layer includes a first opening and a second opening, so The first opening exposes the source electrode, and the second opening exposes the connecting portion.
  • a light emitting diode is disposed in the first opening, the light emitting diode is connected to the source, a protective layer is disposed in the second opening, and the protective layer covers the connecting portion.
  • the array substrate further includes a second passivation layer and a second light shielding portion, the second passivation layer is disposed on a side of the first passivation layer away from the second metal layer, The second light shielding portion is disposed on a side of the second passivation layer away from the first passivation layer.
  • the present application provides a method for preparing an array substrate, the array substrate and a display panel.
  • the preparation method of the array substrate provided by this application saves a photolithography process by patterning the first metal layer, buffer layer and semiconductor layer in the same process, and realizes the same process by patterning the second metal layer.
  • the preparation of the third plate, the drain, the gate, the source and the connecting part also saves a photolithography process. Therefore, the preparation method of the array substrate provided by the present application can reduce two photolithography processes in the manufacturing process, and the preparation method is simple, which is conducive to improving the production efficiency of the array substrate.
  • FIG. 1 is a flow chart of the first embodiment of the method for manufacturing an array substrate provided by the present application.
  • FIG. 2 is a flow chart of a second embodiment of the method for preparing an array substrate provided by the present application.
  • 3a-3i are schematic diagrams of a second embodiment of the method for preparing an array substrate provided in the present application.
  • FIG. 4 is a schematic structural diagram of the first embodiment of the array substrate provided by the present application.
  • FIG. 5 is a schematic structural diagram of a second embodiment of the array substrate provided by the present application.
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • An embodiment of the present application provides a method for preparing an array substrate, and the present application will be described in detail below in conjunction with specific embodiments.
  • FIG. 1 is a flow chart of the first embodiment of the method for preparing an array substrate provided by the present application.
  • Step B10 providing a substrate.
  • the substrate may be a glass substrate or a flexible substrate.
  • the present application does not limit the substrate here.
  • Step B20 sequentially forming a first metal layer, buffer layer and semiconductor layer on the substrate, patterning the first metal layer, buffer layer and semiconductor layer, the first metal layer forms the first plate, the first light shielding part and The first metal part, the buffer layer forms the first buffer part, the second buffer part and the third buffer part, the semiconductor layer forms the second pole plate and the active part, the first pole plate, the first buffer part and the second pole
  • the boards are arranged correspondingly, the first light-shielding part, the second buffer part and the active part are arranged correspondingly, and the third buffer part is located on the side of the first metal part away from the substrate.
  • the first metal layer may be formed of molybdenum (Mo) or a stacked metal of molybdenum (Mo)/copper (Cu).
  • the first metal layer can be formed by physical vapor deposition.
  • the buffer layer may be formed of silicon oxide (SiO x ) or a stack of silicon oxide (SiO x )/silicon nitride (SiN x ).
  • the buffer layer can be formed by chemical vapor deposition.
  • the semiconductor layer 13 may be formed of one or more of gallium indium zinc oxide (IGZO), gallium zinc indium tin oxide (IGZTO) or gallium indium tin oxide (IGTO).
  • Step B30 Forming a second metal layer on the side of the semiconductor layer away from the substrate, patterning the second metal layer to form a third plate, drain, gate, source and connection part, the connection part and the first metal layer department connection.
  • the second metal layer may be formed of a three-layer metal of indium zinc oxide (IZO)/molybdenum (Mo)/copper (Cu) or a double-layer metal of molybdenum oxide (MoO x )/copper (Cu).
  • IZO indium zinc oxide
  • Mo molybdenum
  • Cu molybdenum oxide
  • Cu molybdenum oxide
  • the method for forming the second metal layer is the same as that of the first metal layer, and will not be repeated here.
  • the preparation method of the array substrate provided by the present application saves a photolithography process by patterning the first metal layer, the buffer layer and the semiconductor layer in the same process.
  • the second metal layer, the third electrode plate, the drain electrode, the gate electrode, the source electrode and the connection part are prepared in the same manufacturing process, which also saves a photolithography process. Therefore, the preparation method of the array substrate provided by the present application can reduce two photolithography processes in the manufacturing process, and the preparation method is simple, which is conducive to improving the production efficiency of the array substrate.
  • FIG. 2 is a flow chart of a second embodiment of the method for preparing an array substrate provided by the present application.
  • 3a-3i are schematic diagrams of a second embodiment of the method for preparing an array substrate provided in the present application.
  • the present application also provides a flow chart of the second embodiment of the method for manufacturing the array substrate.
  • Step B10 providing a substrate.
  • the substrate 10 may be a glass substrate or a flexible substrate.
  • the present application does not limit the substrate 10 here.
  • Step B20 sequentially forming a first metal layer, buffer layer and semiconductor layer on the substrate, patterning the first metal layer, buffer layer and semiconductor layer, the first metal layer forms the first plate, the first light shielding part and The first metal part, the buffer layer forms the first buffer part, the second buffer part and the third buffer part, the semiconductor layer forms the second pole plate and the active part, the first pole plate, the first buffer part and the second pole
  • the boards are arranged correspondingly, the first light-shielding part, the second buffer part and the active part are arranged correspondingly, and the third buffer part is located on the side of the first metal part away from the substrate.
  • the materials and methods for forming the first metal layer, the buffer layer and the semiconductor layer are the same as those in the first embodiment of the array substrate manufacturing method provided in this application, and will not be repeated here.
  • the sequentially forming a first metal layer, a buffer layer, and a semiconductor layer on the substrate, and patterning the first metal layer, the buffer layer, and the semiconductor layer include:
  • Step B21 sequentially forming a first metal layer, a buffer layer, a semiconductor layer and a photoresist layer on the substrate.
  • a first metal layer 11 , a buffer layer 12 , a semiconductor layer 13 and a photoresist layer 21 are sequentially formed on the substrate 10 .
  • the materials and methods for forming the first metal layer 11 , the buffer layer 12 and the semiconductor layer 13 are the same as those in the first embodiment of the array substrate manufacturing method provided in this application, and will not be repeated here.
  • the buffer layer after forming the buffer layer, it may also include:
  • TA Thermal annealing
  • the thermal annealing treatment can reduce the stress of the buffer layer 12 , thereby reducing the occurrence of strain and reducing the occurrence of film peeling, thereby improving the stability of the array substrate 100 .
  • Step B22 providing a halftone mask or a grayscale mask to expose the photoresist layer.
  • a Half Tone Mask (HTM) or a Gray Tone Mask (GTM) includes: a semi-transparent area, an opaque area and a completely transparent area.
  • the thickness of the photoresist layer at the corresponding position is thinned by using the semi-transparent region.
  • the photoresist layer at the corresponding position is completely removed by using the completely transparent area, and the photoresist layer at the corresponding position in the non-transparent area will be completely retained. It can be understood that, according to the difference of the positive and negative properties of the photoresist, the positions corresponding to the opaque area and the completely transparent area can be interchanged. As shown in FIG.
  • HTM or GTM is used to expose the photoresist layer 21 to completely remove the photoresist layer 21 in areas other than the thin film transistors, capacitors and data lines to be formed, and simultaneously form the photoresist layer 21 with two thicknesses.
  • Step B23 patterning the first metal layer, the buffer layer and the semiconductor layer.
  • the first metal layer 11 , the buffer layer 12 and the semiconductor layer 13 are etched by using the photoresist layer 21 as a shield. Wherein, the film layers not covered by the photoresist layer 21 are removed by etching. Specifically, the first metal layer 11 is etched by wet etching. The first metal layer 11 forms a first pole plate 111 , a first light shielding portion 112 and a first metal portion 113 . The buffer layer 12 is etched by dry etching. The buffer layer 12 forms a first buffer part 121 , a second buffer part 122 and a third buffer part 123 . The semiconductor layer 13 is wet etched by wet etching.
  • the semiconductor layer 13 forms the second pole plate 131 and the active portion 132 , the first pole plate 111 , the first buffer portion 121 and the second pole plate 131 are arranged correspondingly.
  • the first light shielding portion 112 , the second buffer portion 122 and the active portion 132 are disposed correspondingly.
  • the third buffer portion 123 is located on a side of the first metal portion 113 away from the substrate 10 .
  • the buffer layer and the semiconductor layer after patterning the first metal layer, the buffer layer and the semiconductor layer, it may further include:
  • Step B24 Perform ashing treatment on the photoresist layer.
  • dry ashing is used to ash the photoresist layer 21 .
  • the thinner photoresist layer 21 is removed by ashing.
  • the thick photoresist layer 21 is thinned. Dry ashing can be done using localized heating, laser irradiation or oxygen plasma ashing (Oxygen plasma ashing).
  • the photoresist layer may further include:
  • Step B25 performing a second patterning treatment on the semiconductor layer.
  • the semiconductor layer 13 is patterned by using the photoresist layer 21 remaining after the ashing treatment as a shield. Specifically, the semiconductor layer 13 is etched by wet etching.
  • Step B26 peeling off the photoresist layer.
  • the photoresist layer 21 is peeled off.
  • Step B40 forming a gate insulating layer covering the first metal layer, the buffer layer and the semiconductor layer, patterning the gate insulating layer to form a first opening, a second opening, a third opening and a fourth opening, The first opening and the second opening expose the active portion, the third opening exposes the first light shielding portion, and the fourth opening exposes the first metal portion.
  • a gate insulating layer 15 covering the first metal layer 11 , the buffer layer 12 and the semiconductor layer 13 is formed.
  • the gate insulating layer 15 is patterned to form a first opening 151 , a second opening 152 , a third opening 153 and a fourth opening 154 .
  • the first opening 151 and the second opening 152 expose the semiconductor layer 13 .
  • the third opening 153 exposes the first light shielding portion 112 .
  • the fourth opening 154 exposes the first metal part 113 .
  • the gate insulating layer 15 can be formed by chemical vapor deposition.
  • the gate insulating layer 15 may be formed of SiOx or a stack of SiOx / SiNx .
  • the first opening 151 and the second opening 152 are plasma treated to form a channel region and a non-channel region of the thin film transistor.
  • Conducting the active part 132 corresponding to the plasma treatment of the first opening 151 and the second opening 152 is achieved by plasma processing the first opening 151 and the second opening 152 .
  • the conductorized region of the active portion 132 may serve as a channel region of the thin film transistor.
  • the non-conductorized region of the active portion 132 may serve as a non-channel region of the thin film transistor.
  • Step B30 Forming a second metal layer on the side of the semiconductor layer away from the substrate, patterning the second metal layer to form a third plate, drain, gate, source and connection part, the connection part and the first metal layer department connection.
  • the second metal layer 14 is formed on the side of the gate insulating layer 15 away from the substrate 10 .
  • the second metal layer 14 is patterned to form a third plate 141 , a drain 142 , a gate 143 , a source 144 and a connecting portion 145 .
  • the connection part 145 is connected to the first metal part 113 .
  • the source electrode 144 is located in the second opening 152 and the third opening 153 .
  • the source electrode 144 is connected to the active part 132 and the first light shielding part 112 . Specifically, the source electrode 144 is connected to the channel region of the active portion 132 .
  • the drain 142 is located in the first opening 151 .
  • the drain 142 is connected to the active part 132 . Specifically, the drain 142 is connected to the channel region of the active portion 132 .
  • the connecting portion 145 is located in the fourth opening 154 .
  • the connection part 145 is connected to the first metal part 113 .
  • the second metal layer 14 can be formed by physical vapor deposition.
  • first pole plate 111 , the first buffer portion 121 and the second pole plate 131 form a first capacitor.
  • the second plate 131 , the gate insulating layer 15 and the third plate 141 form a second capacitor.
  • the first capacitor and the second capacitor are connected in parallel.
  • a larger charge storage capacity can be obtained in a smaller space, and the performance of the array substrate 100 is improved.
  • the material and method for forming the second metal layer 14 are the same as those of the first embodiment of the array substrate manufacturing method provided in this application, and will not be repeated here.
  • Step B50 forming a first passivation layer covering the second metal layer, patterning the first passivation layer to form a first opening and a second opening, the first opening exposes the source, and the second opening exposes the connection department.
  • a first passivation layer 16 covering the second metal layer 14 is formed.
  • the first opening 161 and the second opening 162 are formed by patterning the first passivation layer 16 .
  • the first opening 161 exposes the source electrode 144 .
  • the second opening 162 exposes the connection part 145 .
  • the first passivation layer 16 can be formed by chemical vapor deposition.
  • the first passivation layer 16 may be formed of SiOx or a stack of SiOx / SiNx .
  • Step B60 forming a protective layer in the second opening.
  • the protective layer 17 is formed in the second opening 162 .
  • the protective layer 17 can be formed by physical vapor deposition.
  • the protective layer 17 can be formed of a metal oxide such as ITO or IZO.
  • the protective layer 17 has a thickness of 50 nm to 100 nm. Specifically, the thickness of the protective layer 17 may be 50 nanometers, 60 nanometers, 70 nanometers, 80 nanometers, 90 nanometers or 100 nanometers.
  • the protective layer 17 is provided on the connecting portion 145 to prevent the connecting portion 145 from being corroded by external water vapor, and to prevent thermal oxidation of the connecting portion 145 caused by high temperature in subsequent processes, resulting in poor connection.
  • ITO and IZO have good film-forming properties, the flatness of the connection portion 145 can be improved by disposing the protective layer 17 on the connection portion 145 , thereby improving connection reliability.
  • Step B70 sequentially forming a second passivation layer and a second light shielding portion on the side of the first passivation layer away from the second metal layer.
  • a second passivation layer 18 and a second light shielding portion 19 are sequentially formed on the side of the first passivation layer 16 away from the second metal layer 14 .
  • the second passivation layer 18 can be formed by chemical vapor deposition.
  • the second passivation layer 18 may be formed of SiOx or a stack of SiOx / SiNx .
  • the second light shielding portion 19 can be formed by chemical vapor deposition.
  • the second light-shielding portion 19 may be formed of a highly light-shielding photoresist material.
  • the second passivation layer 18 between the second light shielding portion 19 and the first passivation layer 16 , it is possible to prevent high temperature from affecting the second metal layer 14 when the second light shielding portion 19 is formed.
  • the influence of external light on the thin film transistor can be blocked, thereby improving the stability of the array substrate 100 .
  • Step B80 disposing light emitting diodes in the first opening.
  • the light emitting diode 20 is disposed in the first opening 161 .
  • the light emitting diode 20 can be one of Mini LED or Micro LED.
  • the light emitting diode 20 prior to disposing the light emitting diode 20 in the first opening 161 , it may further include: solder paste printing and anisotropic conductive glue (ACF glue) bonding.
  • ACF glue anisotropic conductive glue
  • the preparation method of the array substrate provided by this application saves a photolithography process by patterning the first metal layer, buffer layer and semiconductor layer in the same process, and realizes the same process by patterning the second metal layer.
  • the preparation of the third plate, the drain, the gate, the source and the connecting part also saves a photolithography process. Therefore, the preparation method of the array substrate provided by the present application can reduce two photolithography processes in the manufacturing process, and the preparation method is simple, which is conducive to improving the production efficiency of the array substrate.
  • FIG. 4 is a schematic structural diagram of the first embodiment of the array substrate provided by the present application.
  • the present application provides an array substrate 100 .
  • the array substrate 100 includes a substrate 10 , a first metal layer 11 , a buffer layer 12 , a semiconductor layer 13 and a second metal layer 14 .
  • the first metal layer 11 , the buffer layer 12 , and the semiconductor layer 13 are sequentially stacked on the substrate 10 .
  • the second metal layer 14 is disposed on a side of the semiconductor layer 13 away from the substrate 10 .
  • the first metal layer 11 includes a first pole plate 111 , a first light shielding portion 112 and a first metal portion 113 .
  • the buffer layer 12 includes a first buffer portion 121 , a second buffer portion 122 and a third buffer portion 123 .
  • the semiconductor layer 13 includes a second plate 131 and an active portion 132 .
  • the first pole plate 111, the first buffer portion 121 and the second pole plate 131 are arranged correspondingly.
  • the first light shielding portion 112 , the second buffer portion 122 and the active portion 132 are disposed correspondingly.
  • the third buffer portion 123 is located on a side of the first metal portion 113 away from the substrate 10 .
  • the second metal layer 14 includes a third plate 141 , a drain 142 , a gate 143 , a source 144 and a connecting portion 145 .
  • the connection part 145 is connected to the first metal part 113 .
  • the array substrate provided in this application includes a substrate 10 , a first metal layer 11 , a buffer layer 12 , a semiconductor layer 13 and a second metal layer 14 .
  • This application saves a photolithography process by patterning the first metal layer 11, buffer layer 12 and semiconductor layer 13 in the same process, and realizes the preparation of the third metal layer 14 in the same process by patterning the second metal layer 14.
  • the plate 141 , the drain 142 , the gate 143 , the source 144 and the connecting portion 145 also save a photolithography process. Therefore, the array substrate 100 provided by the present application can reduce two photolithography processes in the manufacturing process, and the manufacturing method is simple, which is beneficial to improve the production efficiency of the array substrate 100 .
  • the second metal layer 14 is a three-layer metal structure of IZO/Mo/Cu.
  • the IZO layer 14a serves as a low reflection function layer.
  • Cu serves as the electrode layer.
  • Mo between the IZO layer 14a and Cu, the adhesion between the IZO layer 14a and Cu can be improved.
  • the thickness of the IZO layer 14a is 15 nm to 30 nm. Specifically, the thickness of the IZO layer 14a may be 15 nm, 20 nm, 25 nm or 30 nm.
  • the array substrate 100 further includes a gate insulating layer 15 .
  • the gate insulating layer 15 covers the first metal layer 11 , the buffer layer 12 and the semiconductor layer 13 .
  • the gate insulating layer 15 may be formed of SiOx or a stack of SiOx / SiNx .
  • the array substrate 100 further includes a first passivation layer 16 .
  • the first passivation layer 16 covers the second metal layer 14 .
  • the first passivation layer 16 includes a first opening 161 and a second opening 162 .
  • the first opening 161 exposes the source electrode 144 .
  • the second opening 162 exposes the connection part 145 .
  • the protective layer 17 is disposed in the second opening 162 .
  • the protective layer 17 covers the connection portion 145 .
  • the protective layer 17 can be formed of a metal oxide such as ITO or IZO.
  • the protective layer 17 can be formed by physical vapor deposition.
  • the protective layer 17 has a thickness of 50 nm to 100 nm. Specifically, the thickness of the protective layer 17 may be 50 nanometers, 60 nanometers, 70 nanometers, 80 nanometers, 90 nanometers or 100 nanometers.
  • the protective layer 17 is provided on the connecting portion 145 to prevent the connecting portion 145 from being corroded by external water vapor, and to prevent thermal oxidation of the connecting portion 145 caused by high temperature in subsequent processes, resulting in poor connection.
  • ITO and IZO have good film-forming properties, the flatness of the connection portion 145 can be improved by disposing the protective layer 17 on the connection portion 145 , thereby improving connection reliability.
  • a light emitting diode 20 is disposed in the first opening 161 .
  • the LED 20 is connected to the source 144 .
  • the light emitting diode 20 can be one of Mini LED or Micro LED.
  • the array substrate 100 further includes a second passivation layer 18 and a second light shielding portion 19 .
  • the second passivation layer 18 is disposed on a side of the first passivation layer 16 away from the second metal layer 14 .
  • the second light shielding portion 19 is disposed on a side of the second passivation layer 18 away from the first passivation layer 16 .
  • the second passivation layer 18 may be formed of SiOx or a stack of SiOx / SiNx .
  • the second passivation layer 18 can be formed by chemical vapor deposition.
  • the second light-shielding portion 19 may be formed of a highly light-shielding photoresist material.
  • the second light-shielding portion 19 may serve as a light-shielding layer for the channel region of the thin film transistor.
  • the second passivation layer 18 between the second light shielding portion 19 and the first passivation layer 16 , it is possible to prevent high temperature from affecting the second metal layer 14 when the second light shielding portion 19 is formed.
  • the influence of external light on the thin film transistor can be blocked, thereby improving the stability of the array substrate 100 .
  • FIG. 5 is a schematic structural diagram of a second embodiment of the array substrate provided by the present application.
  • the second metal layer 14 is a double-layer metal structure of MoO x /Cu.
  • the MoO X layer 14b serves as a low reflection functional layer.
  • Cu serves as the electrode layer.
  • the thickness of the MoO X layer 14b is 20 nm to 30 nm. Specifically, the thickness of the MoO X layer 14b may be 20 nanometers, 25 nanometers or 30 nanometers.
  • the second metal layer 14 is set as a three-layer metal structure of IZO/Mo/Cu or a double-layer metal structure of MoO X /Cu.
  • the IZO layer 14a and the MoO X layer 14b are low-reflection functional layers, which can reduce the reflection of scattered light into the active part 132 through the drain 142 , the gate 143 and the source 144 and affect the stability of the array substrate 100 .
  • the present application sets the thickness of the IZO layer 14a to 15 nanometers to 30 nanometers, and the thickness of the MoO X layer 14b to 20 nanometers to 30 nanometers, which facilitates the removal of the IZO layer 14a and the MoO X layer 14b in the corresponding area to achieve the second metal Patterning of layer 14.
  • the other structures of the array substrate provided by the second embodiment are the same as those of the array substrate provided by the first embodiment, and will not be repeated here.
  • FIG. 6 is a schematic diagram of a display panel provided by an embodiment of the present application.
  • the display panel 1000 includes the array substrate 100 as described in any previous embodiment.
  • the display panel 1000 provided in this application includes an array substrate 100 .
  • the array substrate includes a substrate, a first metal layer, a buffer layer, a semiconductor layer and a second metal layer.
  • a photolithography process is saved.
  • the second metal layer, the third electrode plate, the drain electrode, the gate electrode, the source electrode and the connection part are prepared in the same manufacturing process, which also saves a photolithography process.
  • the display panel 1000 and the array substrate 100 provided in the present application can reduce two photolithography processes in the manufacturing process, and the manufacturing method is simple, which is beneficial to improve the production efficiency of the array substrate 100 and the display panel 1000 .

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Abstract

本申请提供一种阵列基板的制备方法、阵列基板和显示面板。本申请在同一制程中对第一金属层、缓冲层和半导体层图案化处理，节省一道光刻工艺，在同一制程中制备第三极板、漏极、栅极、源极和连接部，也节省一道光刻工艺。因此本申请提供的阵列基板的制备方法在制程上可以减少两道光刻工艺，有利于提高阵列基板的生产效率。

Description

阵列基板的制备方法、阵列基板和显示面板 技术领域
本申请涉及显示领域，尤其涉及一种阵列基板的制备方法、阵列基板和显示面板。
 背景技术
目前迷你/微发光二极管（Mini/Micro Light Emitting Diode，MLED）显示技术进入加速发展阶段，MLED可以应用于中小型显示器。相较有机发光二极管（Organic Light Emitting Diode，OLED）显示器，MLED显示器在成本、对比度、高亮度和轻薄外形上表现出更佳性能。在MLED显示技术中，阵列基板技术作为关键技术控制着MLED的显示。但是目前用于控制MLED显示器的阵列基板的制备方法复杂。
 技术问题
本申请提供一种阵列基板的制备方法、阵列基板和显示面板，以提高阵列基板的生产效率。
 技术解决方案
本申请提供一种阵列基板的制备方法，包括：
提供一基板；
在所述基板上依次形成第一金属层、缓冲层和半导体层，对所述第一金属层、所述缓冲层和所述半导体层图案化处理，所述第一金属层形成了第一极板、第一遮光部和第一金属部，所述缓冲层形成了第一缓冲部、第二缓冲部和第三缓冲部，所述半导体层形成了第二极板和有源部，所述第一极板、所述第一缓冲部和所述第二极板对应设置，所述第一遮光部、所述第二缓冲部和所述有源部对应设置，所述第三缓冲部位于所述第一金属部远离所述基板的一侧；
在所述半导体层远离所述基板的一侧形成第二金属层，对所述第二金属层图案化处理以形成第三极板、漏极、栅极、源极和连接部，所述连接部与所述第一金属部连接。
在一些实施例中，所述在所述基板上依次形成第一金属层、缓冲层和半导体层，对所述第一金属层、所述缓冲层和所述半导体层图案化处理之后还包括：
形成覆盖所述第一金属层、所述缓冲层和所述半导体层的栅极绝缘层，对所述栅极绝缘层图案化以形成第一开孔、第二开孔、第三开孔和第四开孔，所述第一开孔和所述第二开孔暴露出所述有源部，所述第三开孔暴露出第一遮光部，所述第四开孔暴露出第一金属部。
在一些实施例中，所述在所述半导体层远离所述基板的一侧形成第二金属层，对所述第二金属层图案化处理以形成第三极板、漏极、栅极、源极和连接部之后还包括：
形成覆盖所述第二金属层的第一钝化层，对所述第一钝化层图案化以形成第一开口和第二开口，所述第一开口暴露出所述源极，所述第二开口暴露出所述连接部。
在一些实施例中，所述形成覆盖所述第二金属层的第一钝化层，对所述第一钝化层图案化以形成第一开口和第二开口之后还包括：
在所述第二开口内形成保护层。
在一些实施例中，所述在所述第二开口内形成保护层之后还包括：
在所述第一钝化层远离所述第二金属层的一侧依次形成第二钝化层和第二遮光部。
在一些实施例中，所述在所述第一钝化层远离所述第二金属层的一侧依次形成第二钝化层和第二遮光部之后还包括：
在所述第一开口内设置发光二极管。
在一些实施例中，所述在所述基板上依次形成第一金属层、缓冲层和半导体层，对所述第一金属层、所述缓冲层和所述半导体层图案化处理包括：
在所述基板上依次形成第一金属层、缓冲层、半导体层和光阻层；
提供一半色调光罩或灰阶光罩对所述光阻层曝光处理；
对所述第一金属层、缓冲层和半导体层图案化处理。
本申请提供一种阵列基板，采用如前所述的阵列基板的制备方法制备所述阵列基板，所述阵列基板包括：
基板；
依次层叠设置在所述基板上的第一金属层、缓冲层和半导体层，所述第一金属层包括第一极板、第一遮光部和第一金属部，所述缓冲层包括第一缓冲部、第二缓冲部和第三缓冲部，所述半导体层包括第二极板和有源部，所述第一极板、所述第一缓冲部和所述第二极板对应设置，所述第一遮光部、所述第二缓冲部和所述有源部对应设置，所述第三缓冲部位于所述第一金属部远离所述基板的一侧；
第二金属层，所述第二金属层设置在所述半导体层远离所述基板的一侧，所述第二金属层包括第三极板、漏极、栅极、源极和连接部，所述连接部与所述第一金属部连接。
在一些实施例中，所述第二金属层为氧化铟锌/钼/铜的三层金属结构或氧化钼/铜的双层金属结构。
在一些实施例中，所述氧化铟锌层的厚度为15纳米至30纳米，所述氧化钼层的厚度为20纳米至30纳米。
在一些实施例中，所述阵列基板还包括第一钝化层，所述第一钝化层覆盖所述第二金属层，所述第一钝化层包括第一开口和第二开口，所述第一开口暴露出所述源极，所述第二开口暴露出所述连接部。
在一些实施例中，所述第一开口内设置有发光二极管，所述发光二极管与所述源极连接，所述第二开口内设置有保护层，所述保护层覆盖所述连接部。
在一些实施例中，所述阵列基板还包括第二钝化层和第二遮光部，所述第二钝化层设置在所述第一钝化层远离所述第二金属层的一侧，所述第二遮光部设置在所述第二钝化层远离所述第一钝化层的一侧。
一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
基板；
依次层叠设置在所述基板上的第一金属层、缓冲层和半导体层，所述第一金属层包括第一极板、第一遮光部和第一金属部，所述缓冲层包括第一缓冲部、第二缓冲部和第三缓冲部，所述半导体层包括第二极板和有源部，所述第一极板、所述第一缓冲部和所述第二极板对应设置，所述第一遮光部、所述第二缓冲部和所述有源部对应设置，所述第三缓冲部位于所述第一金属部远离所述基板的一侧；
第二金属层，所述第二金属层设置在所述半导体层远离所述基板的一侧，所述第二金属层包括第三极板、漏极、栅极、源极和连接部，所述连接部与所述第一金属部连接。
在一些实施例中，所述第二金属层为氧化铟锌/钼/铜的三层金属结构或氧化钼/铜的双层金属结构。
在一些实施例中，所述氧化铟锌层的厚度为15纳米至30纳米，所述氧化钼层的厚度为20纳米至30纳米。
在一些实施例中，所述阵列基板还包括第一钝化层，所述第一钝化层覆盖所述第二金属层，所述第一钝化层包括第一开口和第二开口，所述第一开口暴露出所述源极，所述第二开口暴露出所述连接部。
在一些实施例中，所述第一开口内设置有发光二极管，所述发光二极管与所述源极连接，所述第二开口内设置有保护层，所述保护层覆盖所述连接部。
在一些实施例中，所述阵列基板还包括第二钝化层和第二遮光部，所述第二钝化层设置在所述第一钝化层远离所述第二金属层的一侧，所述第二遮光部设置在所述第二钝化层远离所述第一钝化层的一侧。
 有益效果
本申请提供一种阵列基板的制备方法、阵列基板和显示面板。本申请提供的阵列基板的制备方法通过在同一制程中对第一金属层、缓冲层和半导体层图案化处理，节省了一道光刻工艺，通过对第二金属层图案化，实现在同一制程中制备第三极板、漏极、栅极、源极和连接部，也节省了一道光刻工艺。因此本申请提供的阵列基板的制备方法在制程上可以减少两道光刻工艺，制备方法简单，有利于提高阵列基板的生产效率。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请提供的阵列基板的制备方法的第一种实施例的流程图。
图2为本申请提供的阵列基板的制备方法的第二种实施例的流程图。
图3a-3i为本申请提供的阵列基板的制备方法的第二种实施例的示意图。
图4为本申请提供的阵列基板的第一种实施例的结构示意图。
图5为本申请提供的阵列基板的第二种实施例的结构示意图。
图6 为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。需要说明的是，在本发明实施例中，应理解，诸如“包括”或“具有”等的术语旨在指示本说明书中所公开的特征、数字、步骤、行为、部件、部分或其组合的存在，并且不欲排除一个或多个其他特征、数字、步骤、行为、部件、部分或其组合存在或被添加的可能性。在本发明的各种实施例中，应理解，下述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
本申请实施例提供一种阵列基板的制备方法，下面将结合具体实施例对本申请进行详细说明。
请参阅图1，图1为本申请提供的阵列基板的制备方法的第一种实施例的流程图。
步骤B10：提供一基板。
基板可以是玻璃基板或柔性基板。本申请在此对基板不作限定。
步骤B20：在基板上依次形成第一金属层、缓冲层和半导体层，对第一金属层、缓冲层和半导体层图案化处理，第一金属层形成了第一极板、第一遮光部和第一金属部，缓冲层形成了第一缓冲部、第二缓冲部和第三缓冲部，半导体层形成了第二极板和有源部，第一极板、第一缓冲部和第二极板对应设置，第一遮光部、第二缓冲部和有源部对应设置，第三缓冲部位于第一金属部远离基板的一侧。
第一金属层可以由钼（Mo）或钼（Mo）/铜（Cu）的叠层金属形成。第一金属层可以通过物理气相沉积的方式形成。缓冲层可以由氧化硅（SiO X）或氧化硅（SiO X）/氮化硅（SiN X）的叠层形成。缓冲层可以通过化学气相沉积的方式形成。半导体层13可以由氧化镓铟锌（IGZO）、氧化镓锌铟锡（IGZTO）或氧化镓铟锡（IGTO）中的一种或多种形成。
步骤B30：在半导体层远离基板的一侧形成第二金属层，对第二金属层图案化处理以形成第三极板、漏极、栅极、源极和连接部，连接部与第一金属部连接。
在一些实施例中，第二金属层可以由氧化铟锌（IZO）/钼（Mo）/铜（Cu）的三层金属或氧化钼（MoO X）/铜（Cu）的双层金属形成。形成第二金属层的方法与第一金属层的相同，在此不再赘述。
本申请提供的阵列基板的制备方法通过在同一制程中对第一金属层、缓冲层和半导体层图案化处理，节省了一道光刻工艺。通过对第二金属层图案化，实现在同一制程中制备第三极板、漏极、栅极、源极和连接部，也节省了一道光刻工艺。因此本申请提供的阵列基板的制备方法在制程上可以减少两道光刻工艺，制备方法简单，有利于提高阵列基板的生产效率。
请参阅图2和图3a-3i，图2为本申请提供的阵列基板的制备方法的第二种实施例的流程图。图3a-3i为本申请提供的阵列基板的制备方法的第二种实施例的示意图。
本申请还提供了阵列基板的制备方法的第二种实施例的流程图。
步骤B10：提供一基板。
如图3a所示，基板10可以是玻璃基板或柔性基板。本申请在此对基板10不作限定。
步骤B20：在基板上依次形成第一金属层、缓冲层和半导体层，对第一金属层、缓冲层和半导体层图案化处理，第一金属层形成了第一极板、第一遮光部和第一金属部，缓冲层形成了第一缓冲部、第二缓冲部和第三缓冲部，半导体层形成了第二极板和有源部，第一极板、第一缓冲部和第二极板对应设置，第一遮光部、第二缓冲部和有源部对应设置，第三缓冲部位于第一金属部远离基板的一侧。
形成第一金属层、缓冲层和半导体层的材料和方法与本申请提供的阵列基板的制备方法的第一种实施例中的相同，在此不再赘述。
在一些实施例中，所述在所述基板上依次形成第一金属层、缓冲层和半导体层，对所述第一金属层、所述缓冲层和所述半导体层图案化处理包括：
步骤B21：在基板上依次形成第一金属层、缓冲层、半导体层和光阻层。
如图3b所示，在基板10上依次形成第一金属层11、缓冲层12、半导体层13和光阻层21。
形成第一金属层11、缓冲层12和半导体层13的材料和方法与本申请提供的阵列基板的制备方法的第一种实施例中的相同，在此不再赘述。
在一些实施例中，在形成缓冲层之后还可以包括：
对缓冲层进行热退火（Thermal annealing，TA）处理。
通过热退火处理可以减小缓冲层12的应力，从而减少应变的发生，减少发生膜层剥离，从而提高阵列基板100的稳定性。
步骤B22：提供一半色调光罩或灰阶光罩对光阻层曝光处理。
半色调光罩（Half Tone Mask，HTM）或灰阶光罩（Gray Tone Mask，GTM）包括：半透光区域、不透光区域和完全透光区域。利用半透光区域减薄对应位置的光阻层的厚度。利用完全透光区域完全去除对应位置的光阻层，而不透光区域对应位置的光阻层将被全部保留下来。可以理解的是，根据光阻的正负性质的不同，不透光区域和完全透光区域对应的位置可以互换。如图3b所示，采用HTM或GTM对光阻层21曝光处理，完全去除待形成薄膜晶体管、电容和数据线以外区域的光阻层21，同时形成具有两种厚度的光阻层21。
步骤B23：对第一金属层、缓冲层和半导体层图案化处理。
如图3c所示，利用光阻层21做遮挡，对第一金属层11、缓冲层12和半导体层13刻蚀处理。其中，没有光阻层21覆盖的膜层被蚀刻而除去。具体的，采用湿法蚀刻的方式对第一金属层11进行蚀刻。第一金属层11形成了第一极板111、第一遮光部112和第一金属部113。采用干法蚀刻的方式对缓冲层12进行蚀刻。缓冲层12形成了第一缓冲部121、第二缓冲部122和第三缓冲部123。采用湿法蚀刻的方式对半导体层13进行湿法蚀刻。半导体层13形成了第二极板131和有源部132第一极板111、第一缓冲部121和第二极板131对应设置。第一遮光部112、第二缓冲部122和有源部132对应设置。第三缓冲部123位于第一金属部113远离基板10的一侧。
在一些实施例中，对第一金属层、缓冲层和半导体层图案化处理之后还可以包括：
步骤B24：对光阻层进行灰化处理。
如图3c所示，具体的，采用干法灰化的方式对光阻层21进行灰化处理。其中，厚度较薄的光阻层21被灰化而除去。厚度较厚的光阻层21被减薄。干法灰化可以是利用局部加热、激光照射或氧电浆灰化工艺(Oxygen plasma ashing)的方式。
在一些实施例中，对光阻层进行灰化处理之后还可以包括：
步骤B25：对半导体层进行第二次图案化处理。
如图3d所示，利用灰化处理后剩余的光阻层21做遮挡，对半导体层13图案化处理。具体的，采用湿法蚀刻的方式对半导体层13进行蚀刻。
在一些实施例中，对半导体层进行第二次图案化处理之后还包括：
步骤B26：剥离光阻层。
如图3d所示，剥离光阻层21。
步骤B40：形成覆盖第一金属层、缓冲层和半导体层的栅极绝缘层，对栅极绝缘层图案化以形成第一开孔、第二开孔、第三开孔和第四开孔，第一开孔和第二开孔暴露出有源部，第三开孔暴露出第一遮光部，第四开孔暴露出第一金属部。
如图3e所示，形成覆盖第一金属层11、缓冲层12和半导体层13的栅极绝缘层15。对栅极绝缘层15图案化以形成第一开孔151、第二开孔152、第三开孔153和第四开孔154。第一开孔151和第二开孔152暴露出半导体层13。第三开孔153暴露出第一遮光部112。第四开孔154暴露出第一金属部113。栅极绝缘层15可以通过化学气相沉积的方式形成。栅极绝缘层15可以由SiO X或SiO X/SiN X的叠层形成。
在一些实施例中，对第一开孔151和第二开孔152等离子体处理，以形成薄膜晶体管的沟道区和非沟道区。
通过对第一开孔151和第二开孔152等离子体处理，以实现对应第一开孔151和第二开孔152等离子体处理的有源部132导体化。有源部132被导体化的区域可以作为薄膜晶体管的沟道区。有源部132没有被导体化的区域可以作为薄膜晶体管的非沟道区。
步骤B30：在半导体层远离基板的一侧形成第二金属层，对第二金属层图案化处理以形成第三极板、漏极、栅极、源极和连接部，连接部与第一金属部连接。
如图3f所示，具体的，在栅极绝缘层15远离基板10的一侧形成第二金属层14。对第二金属层14图案化处理形成第三极板141、漏极142、栅极143、源极144和连接部145。连接部145与第一金属部113连接。其中源极144位于第二开孔152和第三开孔153内。源极144与有源部132和第一遮光部112连接。具体的，源极144与有源部132的沟道区连接。漏极142位于第一开孔151内。漏极142与有源部132连接。具体的，漏极142与有源部132的沟道区连接。连接部145位于第四开孔154内。连接部145与第一金属部113连接。第二金属层14可以通过物理气相沉积的方式形成。
其中，第一极板111、第一缓冲部121和第二极板131构成了第一电容。第二极板131、栅极绝缘层15和第三极板141构成了第二电容。第一电容和第二电容并联连接。本申请通过将第一电容和第二电容共用第二极板131，可以实现在较小空间内获得更大的电荷存储量，改善了阵列基板100的性能。
形成第二金属层14的材料和方式和本申请提供的阵列基板的制备方法的第一种实施例的相同，在此不再赘述。
步骤B50：形成覆盖第二金属层的第一钝化层，对第一钝化层图案化以形成第一开口和第二开口，第一开口暴露出所述源极，第二开口暴露出连接部。
如图3g所示，形成覆盖第二金属层14的第一钝化层16。对第一钝化层16图案化形成第一开口161和第二开口162。第一开口161暴露出源极144。第二开口162暴露出连接部145。第一钝化层16可以通过化学气相沉积的方式形成。第一钝化层16可以由SiO X或SiO X/SiN X的叠层形成。
步骤B60：在第二开口内形成保护层。
如图3h所示，在第二开口162内形成保护层17。保护层17可以通过物理气相沉积的方式形成。保护层17可以由ITO或IZO等金属氧化物形成。保护层17的厚度为50纳米至100纳米。具体的，保护层17的厚度可以为50纳米、60纳米、70纳米、80纳米、90纳米或100纳米。
本申请通过在连接部145上设置保护层17，可以防止连接部145被外界水汽侵蚀，还可以防止在后续制程中，高温引起连接部145发生热氧化，造成连接不良。此外，由于ITO和IZO的成膜性好，通过在连接部145上设置保护层17，还可以提高连接部145的平整度，从而提高连接的可靠性。
步骤B70：在第一钝化层远离第二金属层的一侧依次形成第二钝化层和第二遮光部。
如图3i所示，在第一钝化层16远离第二金属层14的一侧依次形成第二钝化层18和第二遮光部19。第二钝化层18可以通过化学气相沉积的方式形成。第二钝化层18可以由SiO X或SiO X/SiN X的叠层形成。第二遮光部19可以通过化学气相沉积的方式形成。第二遮光部19可以由高遮光的光阻材料形成。
本申请通过在第二遮光部19与第一钝化层16之间设置第二钝化层18，可以防止在形成第二遮光部19时，高温对第二金属层14产生影响。此外，本申请通过设置第二遮光部19，可以阻挡外界光线对薄膜晶体管的影响，从而提高阵列基板100的稳定性。
步骤B80：在第一开口内设置发光二极管。
如图4所示，在第一开口161内设置发光二极管20。发光二极管20可以是Mini LED或Micro LED中的一种。
在一些实施例中，在第一开口161内设置发光二极管20之前还可以包括：锡膏印刷和异方性导电胶（ACF胶）贴合。
本申请提供的阵列基板的制备方法通过在同一制程中对第一金属层、缓冲层和半导体层图案化处理，节省了一道光刻工艺，通过对第二金属层图案化，实现在同一制程中制备第三极板、漏极、栅极、源极和连接部，也节省了一道光刻工艺。因此本申请提供的阵列基板的制备方法在制程上可以减少两道光刻工艺，制备方法简单，有利于提高阵列基板的生产效率。
请参阅图4，图4为本申请提供的阵列基板的第一种实施例的结构示意图。
本申请提供一种阵列基板100。阵列基板100包括基板10、第一金属层11、缓冲层12、半导体层13和第二金属层14。第一金属层11、缓冲层12、半导体层13依次层叠设置在基板10上。第二金属层14设置在半导体层13远离基板10的一侧。第一金属层11包括第一极板111、第一遮光部112和第一金属部113。缓冲层12包括第一缓冲部121、第二缓冲部122和第三缓冲部123。半导体层13包括第二极板131和有源部132。第一极板111、第一缓冲部121第二极板131对应设置。第一遮光部112、第二缓冲部122和有源部132对应设置。第三缓冲部123位于第一金属部113远离基板10的一侧。第二金属层14包括第三极板141、漏极142、栅极143、源极144和连接部145。连接部145与第一金属部113连接。
本申请提供的阵列基板包括基板10、第一金属层11、缓冲层12、半导体层13和第二金属层14。本申请通过在同一制程中对第一金属层11、缓冲层12和半导体层13图案化处理，节省了一道光刻工艺，通过对第二金属层14图案化，实现在同一制程中制备第三极板141、漏极142、栅极143、源极144和连接部145，也节省了一道光刻工艺。因此本申请提供的阵列基板100在制程上可以减少两道光刻工艺，制备方法简单，有利于提高阵列基板100的生产效率。
第二金属层14为IZO/Mo/Cu的三层金属结构。其中，IZO层14a作为低反射功能层。Cu作为电极层。通过将Mo设置在IZO层14a与Cu之间，可以提高IZO层14a与Cu的贴合性。IZO层14a的厚度为15纳米至30纳米，具体的，IZO层14a的厚度可以为15纳米、20纳米、25纳米或30纳米。
在一些实施例中，阵列基板100还包括栅极绝缘层15。栅极绝缘层15覆盖第一金属层11、缓冲层12和半导体层13。
栅极绝缘层15可以由SiO X或SiO X/SiN X的叠层形成。
在一些实施例中，阵列基板100还包括第一钝化层16。第一钝化层16覆盖第二金属层14。第一钝化层16包括第一开口161和第二开口162。第一开口161暴露出源极144。第二开口162暴露出连接部145。
在一些实施例中，第二开口162内设置有保护层17。保护层17覆盖连接部145。
保护层17可以由ITO或IZO等金属氧化物形成。保护层17可以通过物理气相沉积的方式形成。保护层17的厚度为50纳米至100纳米。具体的，保护层17的厚度可以为50纳米、60纳米、70纳米、80纳米、90纳米或100纳米。
本申请通过在连接部145上设置保护层17，可以防止连接部145被外界水汽侵蚀，还可以防止在后续制程中，高温引起连接部145发生热氧化，造成连接不良。此外，由于ITO和IZO的成膜性好，通过在连接部145上设置保护层17，还可以提高连接部145的平整度，从而提高连接的可靠性。
在一些实施例中，第一开口161内设置有发光二极管20。发光二极管20与源极144连接。
发光二极管20可以是Mini LED或Micro LED中的一种。
在一些实施例中，阵列基板100还包括第二钝化层18和第二遮光部19。第二钝化层18设置在第一钝化层16远离第二金属层14的一侧。第二遮光部19设置在第二钝化层18远离第一钝化层16的一侧。
第二钝化层18可以由SiO X或SiO X/SiN X的叠层形成。第二钝化层18可以通过化学气相沉积的方式形成。第二遮光部19可以由高遮光的光阻材料形成。第二遮光部19可以作为薄膜晶体管沟道区的遮光层。
本申请通过在第二遮光部19与第一钝化层16之间设置第二钝化层18，可以防止在形成第二遮光部19时，高温对第二金属层14产生影响。此外，本申请通过设置第二遮光部19，可以阻挡外界光线对薄膜晶体管的影响，从而提高阵列基板100的稳定性。
请参阅图5，图5为本申请提供的阵列基板的第二种实施例的结构示意图。
第二种实施例提供的阵列基板与第一种实施例提供的阵列基板不同之处在于：
第二金属层14为MoO X/Cu的双层金属结构。
其中，MoO X层14b作为低反射功能层。Cu作为电极层。MoO X层14b的厚度为20纳米至30纳米。具体的，MoO X层14b的厚度可以为20纳米、25纳米或30纳米。
本申请通过将第二金属层14设置为IZO/Mo/Cu的三层金属结构或MoO X/Cu的双层金属结构。其中，IZO层14a和MoO X层14b作为低反射功能层，可以减少散射光经过漏极142、栅极143和源极144再次反射进入有源部132而影响阵列基板100的稳定性。
本申请通过将IZO层14a的厚度设置为15纳米至30纳米，MoO X层14b的厚度设置为20纳米至30纳米，有利于去除对应区域的IZO层14a和MoO X层14b以实现第二金属层14的图案化。
第二种实施例提供的阵列基板与第一种实施例提供的阵列基板的其他结构都相同，在此不再赘述。
请参阅图6，图6为本申请实施例提供的显示面板的示意图。
显示面板1000包括如前任一实施例所述的阵列基板100。
本申请提供的显示面板1000包括阵列基板100。阵列基板包括基板、第一金属层、缓冲层、半导体层和第二金属层。通过在同一制程中对第一金属层、缓冲层和半导体层图案化处理，节省了一道光刻工艺。通过对第二金属层图案化，实现在同一制程中制备第三极板、漏极、栅极、源极和连接部，也节省了一道光刻工艺。本申请提供的显示面板1000和阵列基板100在制程上可以减少两道光刻工艺，制备方法简单，有利于提高阵列基板100和显示面板1000的生产效率。
综上所述，虽然本申请实施例的详细介绍如上，但上述实施例并非用以限制本申请，本领域的普通技术人员应当理解：其依然可以对前述实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请实施例的技术方案的范围。

Claims (19)

  1. 一种阵列基板的制备方法，其中，包括：
    提供一基板；
    在所述基板上依次形成第一金属层、缓冲层和半导体层，对所述第一金属层、所述缓冲层和所述半导体层图案化处理，所述第一金属层形成了第一极板、第一遮光部和第一金属部，所述缓冲层形成了第一缓冲部、第二缓冲部和第三缓冲部，所述半导体层形成了第二极板和有源部，所述第一极板、所述第一缓冲部和所述第二极板对应设置，所述第一遮光部、所述第二缓冲部和所述有源部对应设置，所述第三缓冲部位于所述第一金属部远离所述基板的一侧；
    在所述半导体层远离所述基板的一侧形成第二金属层，对所述第二金属层图案化处理以形成第三极板、漏极、栅极、源极和连接部，所述连接部与所述第一金属部连接。
  2. 根据权利要求1所述的阵列基板的制备方法，其中，所述在所述基板上依次形成第一金属层、缓冲层和半导体层，对所述第一金属层、所述缓冲层和所述半导体层图案化处理之后还包括：
    形成覆盖所述第一金属层、所述缓冲层和所述半导体层的栅极绝缘层，对所述栅极绝缘层图案化以形成第一开孔、第二开孔、第三开孔和第四开孔，所述第一开孔和所述第二开孔暴露出所述有源部，所述第三开孔暴露出第一遮光部，所述第四开孔暴露出第一金属部。
  3. 根据权利要求1所述的阵列基板的制备方法，其中，所述在所述半导体层远离所述基板的一侧形成第二金属层，对所述第二金属层图案化处理以形成第三极板、漏极、栅极、源极和连接部之后还包括：
    形成覆盖所述第二金属层的第一钝化层，对所述第一钝化层图案化以形成第一开口和第二开口，所述第一开口暴露出所述源极，所述第二开口暴露出所述连接部。
  4. 根据权利要求3所述的阵列基板的制备方法，其中，所述形成覆盖所述第二金属层的第一钝化层，对所述第一钝化层图案化以形成第一开口和第二开口之后还包括：
    在所述第二开口内形成保护层。
  5. 根据权利要求4所述的阵列基板的制备方法，其中，所述在所述第二开口内形成保护层之后还包括：
    在所述第一钝化层远离所述第二金属层的一侧依次形成第二钝化层和第二遮光部。
  6. 根据权利要求5所述的阵列基板的制备方法，其中，所述在所述第一钝化层远离所述第二金属层的一侧依次形成第二钝化层和第二遮光部之后还包括：
    在所述第一开口内设置发光二极管。
  7. 根据权利要求1所述的阵列基板的制备方法，其中，所述在所述基板上依次形成第一金属层、缓冲层和半导体层，对所述第一金属层、所述缓冲层和所述半导体层图案化处理包括：
    在所述基板上依次形成第一金属层、缓冲层、半导体层和光阻层；
    提供一半色调光罩或灰阶光罩对所述光阻层曝光处理；
    对所述第一金属层、缓冲层和半导体层图案化处理。
  8. 一种阵列基板，其中，采用阵列基板的制备方法制备所述阵列基板，所述阵列基板包括：
    基板；
    依次层叠设置在所述基板上的第一金属层、缓冲层和半导体层，所述第一金属层包括第一极板、第一遮光部和第一金属部，所述缓冲层包括第一缓冲部、第二缓冲部和第三缓冲部，所述半导体层包括第二极板和有源部，所述第一极板、所述第一缓冲部和所述第二极板对应设置，所述第一遮光部、所述第二缓冲部和所述有源部对应设置，所述第三缓冲部位于所述第一金属部远离所述基板的一侧；
    第二金属层，所述第二金属层设置在所述半导体层远离所述基板的一侧，所述第二金属层包括第三极板、漏极、栅极、源极和连接部，所述连接部与所述第一金属部连接。
  9. 根据权利要求8所述的阵列基板，其中，所述第二金属层为氧化铟锌/钼/铜的三层金属结构或氧化钼/铜的双层金属结构。
  10. 根据权利要求9所述的阵列基板，其中，所述氧化铟锌层的厚度为15纳米至30纳米，所述氧化钼层的厚度为20纳米至30纳米。
  11. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括第一钝化层，所述第一钝化层覆盖所述第二金属层，所述第一钝化层包括第一开口和第二开口，所述第一开口暴露出所述源极，所述第二开口暴露出所述连接部。
  12. 根据权利要求11所述的阵列基板，其中，所述第一开口内设置有发光二极管，所述发光二极管与所述源极连接，所述第二开口内设置有保护层，所述保护层覆盖所述连接部。
  13. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括第二钝化层和第二遮光部，所述第二钝化层设置在所述第一钝化层远离所述第二金属层的一侧，所述第二遮光部设置在所述第二钝化层远离所述第一钝化层的一侧。
  14. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括：
    基板；
    依次层叠设置在所述基板上的第一金属层、缓冲层和半导体层，所述第一金属层包括第一极板、第一遮光部和第一金属部，所述缓冲层包括第一缓冲部、第二缓冲部和第三缓冲部，所述半导体层包括第二极板和有源部，所述第一极板、所述第一缓冲部和所述第二极板对应设置，所述第一遮光部、所述第二缓冲部和所述有源部对应设置，所述第三缓冲部位于所述第一金属部远离所述基板的一侧；
    第二金属层，所述第二金属层设置在所述半导体层远离所述基板的一侧，所述第二金属层包括第三极板、漏极、栅极、源极和连接部，所述连接部与所述第一金属部连接。
  15. 根据权利要求14所述的显示面板，其中，所述第二金属层为氧化铟锌/钼/铜的三层金属结构或氧化钼/铜的双层金属结构。
  16. 根据权利要求15所述的显示面板，其中，所述氧化铟锌层的厚度为15纳米至30纳米，所述氧化钼层的厚度为20纳米至30纳米。
  17. 根据权利要求14所述的显示面板，其中，所述阵列基板还包括第一钝化层，所述第一钝化层覆盖所述第二金属层，所述第一钝化层包括第一开口和第二开口，所述第一开口暴露出所述源极，所述第二开口暴露出所述连接部。
  18. 根据权利要求17所述的显示面板，其中，所述第一开口内设置有发光二极管，所述发光二极管与所述源极连接，所述第二开口内设置有保护层，所述保护层覆盖所述连接部。
  19. 根据权利要求17所述的显示面板，其中，所述阵列基板还包括第二钝化层和第二遮光部，所述第二钝化层设置在所述第一钝化层远离所述第二金属层的一侧，所述第二遮光部设置在所述第二钝化层远离所述第一钝化层的一侧。
PCT/CN2021/110289 2021-07-27 2021-08-03 阵列基板的制备方法、阵列基板和显示面板 WO2023004844A1 (zh)

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