WO2021203501A1 - 阵列基板的制造方法、阵列基板和显示装置 - Google Patents

阵列基板的制造方法、阵列基板和显示装置 Download PDF

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WO2021203501A1
WO2021203501A1 PCT/CN2020/088957 CN2020088957W WO2021203501A1 WO 2021203501 A1 WO2021203501 A1 WO 2021203501A1 CN 2020088957 W CN2020088957 W CN 2020088957W WO 2021203501 A1 WO2021203501 A1 WO 2021203501A1
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Prior art keywords
layer
insulating layer
pad
array substrate
transparent electrode
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PCT/CN2020/088957
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English (en)
French (fr)
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赵斌
赵锐
李嘉
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2021203501A1 publication Critical patent/WO2021203501A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • This application relates to the field of display technology, and in particular to a manufacturing method of an array substrate, an array substrate, and a display device.
  • Mini Light Emitting Diode (Mini LED) display panels have the advantages of high brightness, long life, low power consumption, fast response speed, and good stability, and are widely used in many areas of social life.
  • MiniLED can be mounted through the surface mount process (Surface Mounted Technology, SMT) are soldered on the pads of the MiniLED array substrate to obtain the MiniLED display panel.
  • SMT Surface Mounted Technology
  • the thickness of the pad is generally not more than 1 mm. Because the pad is too thin, when the MiniLED is soldered on the pad of the MiniLED array substrate through SMT, the pad is easily corroded by the solder paste.
  • the pad is too thin, when the MiniLED is soldered on the pad of the MiniLED array substrate through SMT, the pad is easily corroded by the solder paste.
  • the embodiments of the present application provide a manufacturing method of an array substrate, an array substrate, and a display device, which can increase the thickness of the bonding pad.
  • an embodiment of the present application provides a manufacturing method of an array substrate, including:
  • the patterned first metal layer including a gate, a first pad and a conductive metal
  • a patterned second metal layer is formed on the semiconductor layer, the patterned second metal layer includes a source electrode, a drain electrode, and a second pad, and the second pad passes through the first through hole and The first pad is connected;
  • a second insulating layer, a transparent electrode layer, a third insulating layer and a light shielding layer are sequentially formed on the patterned second metal layer.
  • the method further includes :
  • a second through hole penetrating the light shielding layer, the third insulating layer, and the second insulating layer is formed on the light shielding layer, the second through hole corresponds to the second pad, and the The second through hole exposes the second pad.
  • the method further includes :
  • a light emitting unit is provided at the second through hole, and the light emitting unit is connected to the second pad through the second through hole.
  • the step of sequentially forming a second insulating layer, a transparent electrode layer, a third insulating layer and a light-shielding layer on the patterned second metal layer includes:
  • a light shielding layer is formed on the third insulating layer.
  • a transparent electrode layer is formed on the second insulating layer before, it also included:
  • a third through hole exposing the conductive metal is formed on the second insulating layer.
  • the method further includes :
  • the transparent electrode layer is etched to form a patterned transparent electrode layer, the patterned transparent electrode layer includes a transparent electrode, and the transparent electrode is connected to the conductive metal through the third through hole.
  • the material of the first metal layer includes aluminum, molybdenum, copper or silver.
  • the thickness of the first metal layer is 3000 ⁇ to 15000 ⁇ .
  • the thickness of the first pad is 3000 ⁇ -15000 ⁇ .
  • the thickness of the second metal layer is 3000 ⁇ to 15000 ⁇ .
  • the thickness of the second pad is 3000 ⁇ -15000 ⁇ .
  • an array substrate including:
  • a first metal layer including a gate, a first pad and a conductive metal
  • a first insulating layer, the first insulating layer is disposed on the first metal layer, and a first through hole exposing the first pad is disposed on the first insulating layer;
  • a semiconductor layer the semiconductor layer being disposed on the first insulating layer
  • a second metal layer is disposed on the semiconductor layer, the second metal layer includes a source electrode, a drain electrode, and a second pad, and the second pad passes through the first through hole Connected to the first pad;
  • a second insulating layer the second insulating layer being disposed on the second metal layer
  • a transparent electrode layer, the transparent electrode layer is disposed on the second insulating layer
  • a third insulating layer is disposed on the transparent electrode layer
  • a light-shielding layer, the light-shielding layer is disposed on the third insulating layer.
  • the light shielding layer is provided with a second through hole penetrating the light shielding layer, the third insulating layer, and the second insulating layer, and the second through hole is connected to the The second pad corresponds to, and the second through hole exposes the second pad.
  • the transparent electrode layer includes a transparent electrode
  • the second insulating layer is provided with a third through hole exposing the conductive metal
  • the transparent electrode passes through the third through hole.
  • the hole is connected to the conductive metal.
  • the material of the first metal layer includes aluminum, molybdenum, copper or silver.
  • the thickness of the first metal layer is 3000 ⁇ to 15000 ⁇ .
  • the thickness of the first pad is 3000 ⁇ -15000 ⁇ .
  • the thickness of the second metal layer is 3000 ⁇ -15000 ⁇ .
  • the thickness of the second pad is 3000 ⁇ -15000 ⁇ .
  • an embodiment of the present application also provides a display device, which includes the above-mentioned array substrate.
  • the manufacturing method of the array substrate includes providing a substrate; forming a patterned first metal layer on the substrate, and the patterned first metal layer includes a gate, a first pad, and a conductive metal Forming a patterned first insulating layer on the patterned first metal layer, the patterned first insulating layer having a first through hole exposing the first pad; on the patterned A semiconductor layer is formed on the first insulating layer; a patterned second metal layer is formed on the semiconductor layer, the patterned second metal layer includes a source electrode, a drain electrode and a second pad, and the second solder The disk is connected to the first pad through the first through hole; a second insulating layer, a transparent electrode layer, a third insulating layer and a light shielding layer are sequentially formed on the patterned second metal layer.
  • This solution can increase the thickness of the pad.
  • FIG. 1 is a schematic flowchart of a manufacturing method of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a first intermediate product of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a first intermediate product of an array substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a second intermediate product of the array substrate provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a third intermediate product of the array substrate provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a fourth intermediate product of the array substrate provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • the embodiments of the present application provide a method for manufacturing an array substrate and an array substrate, which will be described in detail below.
  • FIG. 1 is a schematic flowchart of a manufacturing method of an array substrate provided by an embodiment of the present application. It can be understood that the array substrate 1 as shown in FIG. 7 can be formed by the manufacturing method of the array substrate 1.
  • the specific process of the manufacturing method of the array substrate 1 may be as follows:
  • the material of the substrate 10 may include glass, quartz or sapphire, etc. It should be noted that the material of the substrate 10 includes but is not limited to the above materials, and it may also include other materials, such as polyimide. List one by one.
  • a patterned first metal layer 20 is formed on the substrate 10, and the patterned first metal layer 20 includes a gate 21, a first pad 22 and a conductive metal 23.
  • the first metal layer 20 may be deposited on the substrate 10 by physical vapor deposition technology, and then the first metal layer 20 may be etched to form the gate 21, the first pad 22 and the conductive material. Metal 23. That is, the patterned first metal layer 20 is formed.
  • the material of the first metal layer 20 may include metals such as aluminum (Al), molybdenum (Mo), copper (Cu), or silver (Ag).
  • the thickness of the first metal layer 20 is 3000 ⁇ (Angstrom) to 15000 ⁇ (Angstrom). That is, the thickness of the first pad 22 is 3000 ⁇ (Angstrom) to 15000 ⁇ (Angstrom).
  • a patterned first insulating layer 30 is formed on the patterned first metal layer 20, and the patterned first insulating layer 30 has a first through hole 31 exposing the first pad 22.
  • a first insulating layer 30 may be deposited on the patterned first metal layer 20 by a chemical vapor deposition technique, and then the first insulating layer 30 may be etched to form a patterned first metal layer. Insulation layer 30. That is, a first through hole 31 exposing the first pad 22 is formed on the first insulating layer 30.
  • the first insulating layer 30 is a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • a semiconductor layer 40 may be deposited on the patterned first insulating layer by physical vapor deposition technology, and then the semiconductor layer 40 may be patterned so that the patterned semiconductor layer 40 is located on the gate. Right above pole 21.
  • the material of the semiconductor layer 40 may include one or more of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), and indium gallium zinc tin oxide (IGZTO).
  • IGZO indium gallium zinc oxide
  • IZTO indium zinc tin oxide
  • IGZTO indium gallium zinc tin oxide
  • a patterned second metal layer 50 is formed on the semiconductor layer 40.
  • the patterned second metal layer 50 includes a source 51, a drain 52 and a second pad 53, the second pad 53 passes through the first through hole 31 is connected to the first pad 22.
  • the second metal layer 50 may be deposited on the semiconductor layer 40 by physical vapor deposition technology, and then the second metal layer 50 may be etched to form the source electrode 51, the drain electrode 52, and the second metal layer. ⁇ 53 ⁇ 53. That is, the patterned second metal layer 50 is formed.
  • the source 51 and the drain 52 are located on the semiconductor layer 40.
  • the second pad 53 corresponds to the first through hole 31, and the second pad 53 may be connected to the first pad 22 through the first through hole 31. That is, the second pad 53 is disposed on the first pad 22.
  • the material of the second metal layer 50 may include metals such as aluminum (Al), molybdenum (Mo), copper (Cu), or silver (Ag).
  • the thickness of the second metal layer 50 is 3000 ⁇ (Angstrom) to 15000 ⁇ (Angstrom). That is, the thickness of the second pad 53 is 3000 ⁇ (Angstrom) to 15000 ⁇ (Angstrom).
  • a second insulating layer 60, a transparent electrode layer 70, a third insulating layer 80, and a light shielding layer 90 are sequentially formed on the patterned second metal layer 50.
  • a second insulating layer 60 is formed on the patterned second metal layer 50; a transparent electrode layer 70 is formed on the second insulating layer 60; a third insulating layer is formed on the transparent electrode layer 70. Layer 80; a light-shielding layer 90 is formed on the third insulating layer 80.
  • the material of the second insulating layer 60 may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • the material of the transparent electrode layer 70 may include indium tin oxide (ITO).
  • the third insulating layer 80 may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.
  • the light shielding layer 90 may be a black matrix.
  • a second through hole 91 penetrating the light-shielding layer 90, the third insulating layer 80, and the second insulating layer 60 may be formed on the light-shielding layer 90. It should be noted that the second through hole 91 corresponds to the second pad 53, and the second through hole 91 may expose the second pad 53.
  • the light-emitting unit 100 may be disposed at the second through hole 91. It can be understood that the light emitting unit 100 may be connected to the second pad 53 through the second through hole 91. Specifically, the light-emitting unit 100 can be soldered on the second pad 53 by SMT.
  • the step “form the second insulating layer 60 on the patterned second metal layer 50" and before the step “form the transparent electrode layer 70 on the second insulating layer 60" it may further include:
  • a third through hole 61 exposing the conductive metal 23 is formed on the second insulating layer 60.
  • the third through hole 61 exposing the conductive metal 23 may be formed on the second insulating layer 60 by etching.
  • the step of "forming the transparent electrode layer 70 on the second insulating layer 60" and before the step of "forming the third insulating layer 80 on the transparent electrode layer 70" it may further include:
  • the transparent electrode layer 70 is etched to form a patterned transparent electrode layer 70.
  • the patterned transparent electrode layer 70 may include a transparent electrode 71, and the transparent electrode 71 may be connected to the conductive metal 23 through the third through hole 61.
  • the manufacturing method of the array substrate 1 forms the first pad 22 through the patterned first metal layer 20, and then forms the first pad 22 exposing the first pad 22 on the first insulating layer 30.
  • the through hole 31 allows the second pad 53 formed after patterning the second metal layer 50 to be connected to the first pad 22 through the first through hole 31.
  • the pad thickness of the array substrate 1 is the sum of the thickness of the first pad 22 and the thickness of the second pad 53. That is, this solution can increase the thickness of the pad of the array substrate 1.
  • the array substrate 1 may include a substrate 10, a first metal layer 20, a first insulating layer 30, a semiconductor layer 40, a second metal layer 50, a second insulating layer 60, a transparent electrode layer 70, a third insulating layer 80, and a light-shielding layer. 90.
  • the first metal layer 20 may include a gate 21, a first pad 22 and a conductive metal 23.
  • the first insulating layer 30 is disposed on the first metal layer 20, and a first through hole 31 exposing the first pad 22 is disposed on the first insulating layer 30.
  • the semiconductor layer 40 is disposed on the first insulating layer 30.
  • the second metal layer 50 is disposed on the semiconductor layer 40.
  • the second metal layer 50 may include a source electrode 51, a drain electrode 52 and a second pad 53.
  • the second pad 53 may be connected to the first pad 22 through the first through hole 31.
  • the second insulating layer 60 is disposed on the second metal layer 50.
  • the transparent electrode layer 70 is disposed on the second insulating layer 60.
  • the third insulating layer 80 is disposed on the transparent electrode layer 70.
  • the light shielding layer 90 is disposed on the third insulating layer 80.
  • the light shielding layer 90 is provided with a second through hole 91 penetrating the light shielding layer 90, the third insulating layer 80 and the second insulating layer 60. It should be noted that the second through hole 91 corresponds to the second pad 53 and can be used to expose the second pad 53.
  • the array substrate 1 may further include a light-emitting unit 100.
  • the light emitting unit 100 may be connected to the second pad 53 through the second through hole 91.
  • the light-emitting unit 100 can be soldered on the second pad 53 by SMT.
  • the transparent electrode layer 70 may include a transparent electrode 71.
  • a third through hole 61 exposing the conductive metal 23 may be provided on the second insulating layer 60.
  • the transparent electrode 71 can be connected to the conductive metal 23 through the third through hole 61.
  • the array substrate 1 provided by the embodiment of the present application is provided with a first pad 22 on the substrate 10, and a first through hole 31 exposing the first pad 22 is provided on the first insulating layer 30, so that the second The pad 53 may be connected to the first pad 22 through the first through hole 31. That is, the second pad 53 is disposed on the first pad 22.
  • the pad thickness of the array substrate 1 is the sum of the thickness of the first pad 22 and the thickness of the second pad 53. That is, this solution can increase the thickness of the pad of the array substrate 1.
  • the embodiment of the present application also provides a display device, which may include the array substrate 1 in the above-mentioned embodiment.

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Abstract

一种阵列基板的制造方法、阵列基板和显示装置，该阵列基板的制造方法通过在基板（10）上设置第一焊盘（22），在第一绝缘层（30）上设置暴露该第一焊盘（22）的第一通孔（31），以使第二焊盘（53）通过该第一通孔（31）与第一焊盘（22）相连，从而增加焊盘的厚度。

Description

阵列基板的制造方法、阵列基板和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板的制造方法、阵列基板和显示装置。
 背景技术
迷你发光二极管(Mini Light Emitting Diode，MiniLED)显示面板具有高亮度、寿命长、功耗低、反应速度快以及稳定性好等优点，被广泛应用于社会生活中的诸多领域。
通常，MiniLED可以通过表面贴装工艺（Surface Mounted Technology，SMT）焊接在MiniLED阵列基板的焊盘上，从而得到MiniLED显示面板。
然而，由于受到MiniLED阵列基板的制程限制，焊盘的厚度一般不超过1毫米。由于焊盘过薄，在将MiniLED通过SMT焊接在MiniLED阵列基板的焊盘上时，焊盘易被锡膏腐蚀透。
 技术问题
由于焊盘过薄，在将MiniLED通过SMT焊接在MiniLED阵列基板的焊盘上时，焊盘易被锡膏腐蚀透。
 技术解决方案
本申请实施例提供了一种阵列基板的制造方法、阵列基板和显示装置，可以增加焊盘的厚度。
第一方面，本申请实施例提供了一种阵列基板的制造方法，包括：
提供一基板；
在所述基板上形成图案化的第一金属层，所述图案化的第一金属层包括栅极、第一焊盘和导电金属；
在所述图案化的第一金属层上形成图案化的第一绝缘层，所述图案化的第一绝缘层具有暴露所述第一焊盘的第一通孔；
在所述图案化的第一绝缘层上形成半导体层；
在所述半导体层上形成图案化的第二金属层，所述图案化的第二金属层包括源极、漏极和第二焊盘，所述第二焊盘通过所述第一通孔与所述第一焊盘相连；
在所述图案化的第二金属层上依次形成第二绝缘层、透明电极层、第三绝缘层和遮光层。
在本申请实施例提供的阵列基板的制造方法中，在所述在所述图案化的第二金属层上依次形成第二绝缘层、透明电极层、第三绝缘层和遮光层之后，还包括：
在所述遮光层上形成一贯穿所述遮光层、所述第三绝缘层和所述第二绝缘层的第二通孔，所述第二通孔与所述第二焊盘对应，所述第二通孔暴露所述第二焊盘。
在本申请实施例提供的阵列基板的制造方法中，在所述遮光层上形成一贯穿所述遮光层、所述第三绝缘层和所述第二绝缘层的第二通孔之后，还包括：
在所述第二通孔处设置发光单元，所述发光单元通过所述第二通孔与所述第二焊盘相连。
在本申请实施例提供的阵列基板的制造方法中，所述在所述图案化的第二金属层上依次形成第二绝缘层、透明电极层、第三绝缘层和遮光层，包括：
在所述图案化的第二金属层上形成第二绝缘层；
在所述第二绝缘层上形成透明电极层；
在所述透明电极层上形成第三绝缘层；
在所述第三绝缘层上形成遮光层。
在本申请实施例提供的阵列基板的制造方法中，在所述在所述图案化的第二金属层上形成第二绝缘层之后，在所述在所述第二绝缘层上形成透明电极层之前，还包括：
在所述第二绝缘层上形成暴露所述导电金属的第三通孔。
在本申请实施例提供的阵列基板的制造方法中，在所述在所述第二绝缘层上形成透明电极层之后，在所述在所述透明电极层上形成第三绝缘层之前，还包括：
对所述透明电极层进行蚀刻，以形成图案化的透明电极层，所述图案化的透明电极层包括透明电极，所述透明电极通过所述第三通孔与所述导电金属相连。
在本申请实施例提供的阵列基板的制造方法中，所述第一金属层的材料包括铝、钼、铜或银。
在本申请实施例提供的阵列基板的制造方法中，所述第一金属层的厚度为3000Å-15000Å。
在本申请实施例提供的阵列基板的制造方法中，所述第一焊盘的厚度为3000Å-15000Å。
在本申请实施例提供的阵列基板的制造方法中，所述第二金属层的厚度为3000Å-15000Å。
在本申请实施例提供的阵列基板的制造方法中，所述第二焊盘的厚度为3000Å-15000Å。
第二方面，本申请实施例提供了一种阵列基板，包括：
基板；
第一金属层，所述金属层包括栅极、第一焊盘和导电金属；
第一绝缘层，所述第一绝缘层设置于所述第一金属层上，所述第一绝缘层上设置有暴露所述第一焊盘的第一通孔；
半导体层，所述半导体层设置于所述第一绝缘层上；
第二金属层，所述第二金属层设置于所述半导体层上，所述第二金属层包括源极、漏极和第二焊盘，所述第二焊盘通过所述第一通孔与所述第一焊盘相连；
第二绝缘层，所述第二绝缘层设置于所述第二金属层上；
透明电极层，所述透明电极层设置于所述第二绝缘层上；
第三绝缘层，所述第三绝缘层设置于所述透明电极层上；
遮光层，所述遮光层设置于所述第三绝缘层上。
在本申请实施例提供的阵列基板中，所述遮光层上设置有一贯穿所述遮光层、所述第三绝缘层和所述第二绝缘层的第二通孔，所述第二通孔与所述第二焊盘对应，所述第二通孔暴露所述第二焊盘。
在本申请实施例提供的阵列基板中，所述透明电极层包括透明电极，所述第二绝缘层上设置有暴露所述导电金属的第三通孔，所述透明电极通过所述第三通孔与所述导电金属相连。
在本申请实施例提供的阵列基板中，所述第一金属层的材料包括铝、钼、铜或银。
在本申请实施例提供的阵列基板中，所述第一金属层的厚度为3000Å-15000Å。
在本申请实施例提供的阵列基板中，所述第一焊盘的厚度为3000Å-15000Å。
在本申请实施例提供的阵列基板中，所述第二金属层的厚度为3000Å-15000Å。
在本申请实施例提供的阵列基板中，所述第二焊盘的厚度为3000Å-15000Å。
第三方面，本申请实施例还提供了一种显示装置，该显示装置包括上述的阵列基板。
 有益效果
本申请实施例提供的阵列基板的制造方法包括提供一基板；在所述基板上形成图案化的第一金属层，所述图案化的第一金属层包括栅极、第一焊盘和导电金属；在所述图案化的第一金属层上形成图案化的第一绝缘层，所述图案化的第一绝缘层具有暴露所述第一焊盘的第一通孔；在所述图案化的第一绝缘层上形成半导体层；在所述半导体层上形成图案化的第二金属层，所述图案化的第二金属层包括源极、漏极和第二焊盘，所述第二焊盘通过所述第一通孔与所述第一焊盘相连；在所述图案化的第二金属层上依次形成第二绝缘层、透明电极层、第三绝缘层和遮光层。本方案可以增加焊盘的厚度。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的阵列基板的制造方法的流程示意图。
图2是本申请实施例提供的阵列基板的第一中间产物的结构示意图。
图3是本申请实施例提供的阵列基板的第一中间产物的结构示意图。
图4是本申请实施例提供的阵列基板的第二中间产物的结构示意图。
图5是本申请实施例提供的阵列基板的第三中间产物的结构示意图。
图6是本申请实施例提供的阵列基板的第四中间产物的结构示意图。
图7是本申请实施例提供的阵列基板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供了一种阵列基板的制造方法及阵列基板，以下将分别进行详细说明。
请参阅图1，图1是本申请实施例提供的阵列基板的制造方法的流程示意图。可以理解的是，通过该阵列基板1的制造方法可以形成如图7所示的阵列基板1。该阵列基板1的制造方法的具体流程可以如下：
101、提供一基板10。
其中，该基板10的材料可以包括玻璃、石英或蓝宝石等，需要说明的是，基板10的材料包括但不限于以上材料，其还可以包括其他材料，比如聚酰亚胺等，在此不再一一列举。
102、在基板10上形成图案化的第一金属层20，图案化的第一金属层20包括栅极21、第一焊盘22和导电金属23。
具体的，可以如图2所示，通过物理气相沉积技术在基板10上沉积第一金属层20，然后再对该第一金属层20进行蚀刻，形成栅极21、第一焊盘22和导电金属23。即形成图案化的第一金属层20。
需要说明的是，该第一金属层20的材料可以包括铝（Al）、钼（Mo）、铜（Cu）或银（Ag）等金属。该第一金属层20的厚度为3000Å（埃）-15000Å（埃）。即第一焊盘22的厚度为3000Å（埃）-15000Å（埃）。
103、在图案化的第一金属层20上形成图案化的第一绝缘层30，图案化的第一绝缘层30具有暴露所述第一焊盘22的第一通孔31。
具体的，可以如图3所示，通过化学气相沉积技术在图案化的第一金属层20上沉积第一绝缘层30，然后再对该第一绝缘层30进行蚀刻，形成图案化的第一绝缘层30。即在该第一绝缘层30上形成暴露第一焊盘22的第一通孔31。
需要说明的是，该第一绝缘层30为氧化硅(SiOx)薄膜、氮化硅(SiNx)薄膜、或者氧化硅薄膜与氮化硅薄膜交替层叠设置形成的复合薄膜。
104、在图案化的第一绝缘层30上形成半导体层40。
具体的，可以如图4所示，通过物理气相沉积技术在图案化的第一绝缘层上沉积半导体层40，然后再对该半导体层40进行图案化，使得图案化后的半导体层40位于栅极21的正上方。
需要说明的是，该半导体层40的材料可以包括铟镓锌氧化物(IGZO)、铟锌锡氧化物(IZTO)、铟镓锌锡氧化物(IGZTO)中的一种或多种。
105、在半导体层40上形成图案化的第二金属层50，图案化的第二金属层50包括源极51、漏极52和第二焊盘53，第二焊盘53通过第一通孔31与第一焊盘22相连。
具体的，可以如图5所示，通过物理气相沉积技术在半导体层40上沉积第二金属层50，然后再对该第二金属层50进行蚀刻，形成源极51、漏极52和第二焊盘53。即形成图案化的第二金属层50。
可以理解的是，源极51和漏极52位于半导体层40上。第二焊盘53与第一通孔31相对应，该第二焊盘53可以通过第一通孔31与第一焊盘22相连。即该第二焊盘53设置于第一焊盘22上。
该第二金属层50的材料可以包括铝（Al）、钼（Mo）、铜（Cu）或银（Ag）等金属。该第二金属层50的厚度为3000Å（埃）-15000Å（埃）。即第二焊盘53的厚度为3000Å（埃）-15000Å（埃）。
106、在图案化的第二金属层50上依次形成第二绝缘层60、透明电极层70、第三绝缘层80和遮光层90。
具体的，可以如图6所示，在图案化的第二金属层50上形成第二绝缘层60；在第二绝缘层60上形成透明电极层70；在透明电极层70上形成第三绝缘层80；在第三绝缘层80上形成遮光层90。
需要说明的是，第二绝缘层60的材料可以为氧化硅(SiOx)薄膜、氮化硅(SiNx)薄膜、或者氧化硅薄膜与氮化硅薄膜交替层叠设置形成的复合薄膜。透明电极层70的材料可以包括氧化铟锡（ITO）。第三绝缘层80可以为氧化硅(SiOx)薄膜、氮化硅(SiNx)薄膜、或者氧化硅薄膜与氮化硅薄膜交替层叠设置形成的复合薄膜。遮光层90可以为黑色矩阵。
在一些实施例中，在形成遮光层90之后，还可以在该遮光层90上形成一贯穿遮光层90、第三绝缘层80和第二绝缘层60的第二通孔91。需要说明的是，该第二通孔91与第二焊盘53对应，该第二通孔91可以暴露第二焊盘53。
在一些实施例中，可以如图7所示，在形成第二通孔91后，还可以在该第二通孔91处设置发光单元100。可以理解的是，该发光单元100可以通过第二通孔91与第二焊盘53相连。具体的，可以通过SMT将该发光单元100焊接在第二焊盘53上。
在一些实施例中，在步骤“在图案化的第二金属层50上形成第二绝缘层60”之后，在步骤“在第二绝缘层60上形成透明电极层70”之前，还可以包括：
在第二绝缘层60上形成暴露导电金属23的第三通孔61。
具体的，可以通过蚀刻在该第二绝缘层60上形成暴露导电金属23的第三通孔61。
在一些实施例中，在步骤“在第二绝缘层60上形成透明电极层70”之后，在步骤“在透明电极层70上形成第三绝缘层80”之前，还可以包括：
对透明电极层70进行蚀刻，以形成图案化的透明电极层70。
需要说明的是，该图案化的透明电极层70可以包括透明电极71，该透明电极71可以通过第三通孔61与导电金属23相连。
由上，本申请实施例提供的阵列基板1的制造方法通过图案化的第一金属层20形成第一焊盘22，然后再在第一绝缘层30上形成暴露第一焊盘22的第一通孔31，使得图案化第二金属层50后形成的第二焊盘53可以通过该第一通孔31与第一焊盘22相连。此时，该阵列基板1的焊盘厚度为第一焊盘22的厚度与第二焊盘53的厚度之和。即，本方案可以增加该阵列基板1的焊盘厚度。因此，在通过SMT将该发光单元100焊接在第二焊盘53上时，可以避免出现由于该阵列基板1的焊盘厚度过薄，导致焊盘被锡膏腐蚀透，从而影响该阵列基板1的质量的问题。
请参阅图7，本申请实施例还提供了一种阵列基板。该阵列基板1可以包括基板10、第一金属层20、第一绝缘层30、半导体层40、第二金属层50、第二绝缘层60、透明电极层70、第三绝缘层80和遮光层90。
其中，该第一金属层20可以包括栅极21、第一焊盘22和导电金属23。
其中，该第一绝缘层30设置于第一金属层20上，该第一绝缘层30上设置有暴露第一焊盘22的第一通孔31。
其中，该半导体层40设置于第一绝缘层30上。
其中，该第二金属层50设置于半导体层40上。该第二金属层50可以包括源极51、漏极52和第二焊盘53。该第二焊盘53可以通过第一通孔31与第一焊盘22相连。
其中，该第二绝缘层60设置于第二金属层50上。
其中，该透明电极层70设置于第二绝缘层60上。
其中，该第三绝缘层80设置于透明电极层70上。
其中，该遮光层90设置于第三绝缘层80上。
在一些实施例中，该遮光层90上设置有一贯穿遮光层90、第三绝缘层80和第二绝缘层60的第二通孔91。需要说明的是，该第二通孔91与第二焊盘53对应，可以用于暴露第二焊盘53。
在一些实施例中，该阵列基板1还可以包括一发光单元100。该发光单元100可以通过第二通孔91与第二焊盘53相连。具体的，可以通过SMT将该发光单元100焊接在第二焊盘53上。
在一些实施例中，该透明电极层70可以包括透明电极71。第二绝缘层60上可以设置有暴露导电金属23的第三通孔61。该透明电极71可以通过该第三通孔61与导电金属23相连。
由上，本申请实施例提供的阵列基板1通过在基板10上设置第一焊盘22，在第一绝缘层30上设置暴露该第一焊盘22的第一通孔31，以使第二焊盘53可以通过该第一通孔31与第一焊盘22相连。即该第二焊盘53设置于第一焊盘22上。此时，该阵列基板1的焊盘厚度为第一焊盘22的厚度与第二焊盘53的厚度之和。即，本方案可以增加该阵列基板1的焊盘厚度。因此，在通过SMT将该发光单元100焊接在第二焊盘53上时，可以避免出现由于该阵列基板1的焊盘厚度过薄，导致焊盘被锡膏腐蚀透，从而影响该阵列基板1的质量的问题。
本申请实施例还提供了一种显示装置，该显示装置可以包括上述实施例中的阵列基板1。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种阵列基板的制造方法、阵列基板和显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板的制造方法，其包括：
    提供一基板；
    在所述基板上形成图案化的第一金属层，所述图案化的第一金属层包括栅极、第一焊盘和导电金属；
    在所述图案化的第一金属层上形成图案化的第一绝缘层，所述图案化的第一绝缘层具有暴露所述第一焊盘的第一通孔；
    在所述图案化的第一绝缘层上形成半导体层；
    在所述半导体层上形成图案化的第二金属层，所述图案化的第二金属层包括源极、漏极和第二焊盘，所述第二焊盘通过所述第一通孔与所述第一焊盘相连；
    在所述图案化的第二金属层上依次形成第二绝缘层、透明电极层、第三绝缘层和遮光层。
  2. 如权利要求1所述的阵列基板的制造方法，其中，在所述在所述图案化的第二金属层上依次形成第二绝缘层、透明电极层、第三绝缘层和遮光层之后，还包括：
    在所述遮光层上形成一贯穿所述遮光层、所述第三绝缘层和所述第二绝缘层的第二通孔，所述第二通孔与所述第二焊盘对应，所述第二通孔暴露所述第二焊盘。
  3. 如权利要求2所述的阵列基板的制造方法，其中，在所述遮光层上形成一贯穿所述遮光层、所述第三绝缘层和所述第二绝缘层的第二通孔之后，还包括：
    在所述第二通孔处设置发光单元，所述发光单元通过所述第二通孔与所述第二焊盘相连。
  4. 如权利要求1所述的阵列基板的制造方法，其中，所述在所述图案化的第二金属层上依次形成第二绝缘层、透明电极层、第三绝缘层和遮光层，包括：
    在所述图案化的第二金属层上形成第二绝缘层；
    在所述第二绝缘层上形成透明电极层；
    在所述透明电极层上形成第三绝缘层；
    在所述第三绝缘层上形成遮光层。
  5. 如权利要求4所述的阵列基板的制造方法，其中，在所述在所述图案化的第二金属层上形成第二绝缘层之后，在所述在所述第二绝缘层上形成透明电极层之前，还包括：
    在所述第二绝缘层上形成暴露所述导电金属的第三通孔。
  6. 如权利要求5所述的阵列基板的制造方法，其中，在所述在所述第二绝缘层上形成透明电极层之后，在所述在所述透明电极层上形成第三绝缘层之前，还包括：
    对所述透明电极层进行蚀刻，以形成图案化的透明电极层，所述图案化的透明电极层包括透明电极，所述透明电极通过所述第三通孔与所述导电金属相连。
  7. 如权利要求1所述的阵列基板的制造方法，其中，所述第一金属层的材料包括铝、钼、铜或银。
  8. 如权利要求1所述的阵列基板的制造方法，其中，所述第一金属层的厚度为3000Å-15000Å。
  9. 如权利要求8所述的阵列基板的制造方法，其中，所述第一焊盘的厚度为3000Å-15000Å。
  10. 如权利要求1所述的阵列基板的制造方法，其中，所述第二金属层的厚度为3000Å-15000Å。
  11. 如权利要求10所述的阵列基板的制造方法，其中，所述第二焊盘的厚度为3000Å-15000Å。
  12. 一种阵列基板，其包括：
    基板；
    第一金属层，所述金属层包括栅极、第一焊盘和导电金属；
    第一绝缘层，所述第一绝缘层设置于所述第一金属层上，所述第一绝缘层上设置有暴露所述第一焊盘的第一通孔；
    半导体层，所述半导体层设置于所述第一绝缘层上；
    第二金属层，所述第二金属层设置于所述半导体层上，所述第二金属层包括源极、漏极和第二焊盘，所述第二焊盘通过所述第一通孔与所述第一焊盘相连；
    第二绝缘层，所述第二绝缘层设置于所述第二金属层上；
    透明电极层，所述透明电极层设置于所述第二绝缘层上；
    第三绝缘层，所述第三绝缘层设置于所述透明电极层上；
    遮光层，所述遮光层设置于所述第三绝缘层上。
  13. 如权利要求12所述的阵列基板，其中，所述遮光层上设置有一贯穿所述遮光层、所述第三绝缘层和所述第二绝缘层的第二通孔，所述第二通孔与所述第二焊盘对应，所述第二通孔暴露所述第二焊盘。
  14. 如权利要求12所述的阵列基板，其中，所述透明电极层包括透明电极，所述第二绝缘层上设置有暴露所述导电金属的第三通孔，所述透明电极通过所述第三通孔与所述导电金属相连。
  15. 如权利要求12所述的阵列基板，其中，所述第一金属层的材料包括铝、钼、铜或银。
  16. 如权利要求12所述的阵列基板，其中，所述第一金属层的厚度为3000Å-15000Å。
  17. 如权利要求16所述的阵列基板，其中，所述第一焊盘的厚度为3000Å-15000Å。
  18. 如权利要求12所述的阵列基板，其中，所述第二金属层的厚度为3000Å-15000Å。
  19. 如权利要求18所述的阵列基板，其中，所述第二焊盘的厚度为3000Å-15000Å。
  20. 一种显示装置，其包括如权利要求12所述的阵列基板。
PCT/CN2020/088957 2020-04-08 2020-05-07 阵列基板的制造方法、阵列基板和显示装置 WO2021203501A1 (zh)

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