WO2021184522A1 - 背光模组及其制备方法和显示装置 - Google Patents

背光模组及其制备方法和显示装置 Download PDF

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Publication number
WO2021184522A1
WO2021184522A1 PCT/CN2020/090943 CN2020090943W WO2021184522A1 WO 2021184522 A1 WO2021184522 A1 WO 2021184522A1 CN 2020090943 W CN2020090943 W CN 2020090943W WO 2021184522 A1 WO2021184522 A1 WO 2021184522A1
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Prior art keywords
metal
layer
backlight module
metal layer
via hole
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PCT/CN2020/090943
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English (en)
French (fr)
Inventor
王明耀
刘俊领
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Priority to US16/962,042 priority Critical patent/US11281046B2/en
Publication of WO2021184522A1 publication Critical patent/WO2021184522A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • This application relates to the field of display technology, and in particular to a backlight module, a manufacturing method thereof, and a display device.
  • Micro-LED Micro-Light Emitting Diode (miniature light emitting diode) has developed into one of the hotspots of display technology in the future.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • LED Light Emitting Diode, light-emitting diode
  • Mini- LED Mini-Light Emitting Diode, mini light-emitting diode
  • OLED Organic Light Emitting Diode
  • the organic layer needs to use white oil, white organic photoresist, etc. as reflective materials to avoid the effect of light on the performance of the device, and the ITO overlap deep and shallow hole process is completed, but ITO is used as a metal Oxide, its conductivity is worse than that of metal, and will cause aging after a long time or high temperature, and make the via lose its overlap function.
  • the purpose of the present invention is to provide a backlight module and a preparation method thereof, and a display device using the backlight module, so as to solve the problem of poor conductivity of ITO in the prior art.
  • An embodiment of the application provides a backlight module, which includes an array substrate and a plurality of light emitting devices arranged on the array substrate, wherein the array substrate includes:
  • a metal stack disposed on the flat layer and contacting the portion of the first metal layer and the portion of the second metal layer exposed by the flat layer;
  • the metal stack includes at least one layer of first metal, at least one layer of second metal, and at least one layer of metal oxide.
  • the first metal is molybdenum.
  • the first metal is copper
  • the first metal is an alloy composed of molybdenum and copper.
  • the first metal contacts the first metal layer and the second metal layer.
  • the conductivity of the first metal is better than that of the metal oxide.
  • the light reflectivity of the second metal is greater than or equal to 80%.
  • the conductivity of the second metal is better than that of the metal oxide.
  • the second metal is one or an alloy of molybdenum, aluminum, silver, titanium, and nickel.
  • the second metal is disposed between the first metal and the metal oxide.
  • the metal oxide is a compound composed of one or more of indium tin oxide, indium zinc oxide, and indium zinc tin oxide.
  • the array substrate further includes an insulating layer disposed between the first metal layer and the second metal layer and covering the first metal layer, and the insulating layer A layer exposes a portion of the first metal layer, so that the metal stack penetrates the flat layer and the insulating layer to contact the exposed portion of the first metal layer.
  • the second metal layer includes at least one pad area, the flat layer exposes the pad area, and the metal stack exposes the pad area.
  • the pad area array is arranged or uniformly arranged on the second metal layer.
  • the plurality of light emitting devices are disposed on the array substrate through the pad area.
  • An embodiment of the application provides a display device, the backlight module of any one of claims 1-15.
  • An embodiment of the present application provides a method for manufacturing the backlight module according to claim 1, comprising the following steps:
  • a first via hole and a second via hole are formed, the first via hole penetrates the flat layer and the insulating layer to expose a portion of the first metal layer, and the second via hole penetrates the flat layer to Exposing a portion of the second metal layer;
  • a metal stack is formed on the flat layer, the metal stack contacts the exposed portion of the first metal layer through the first via hole, and the metal stack contacts the exposed portion through the second via hole. Part of the second metal layer.
  • the second metal layer includes at least one pad area, and a first opening is also formed in the step of forming the first via hole and the second via hole, so that the flat layer exposes the Pad area; and, in the step of forming a metal stack on the flat layer, the metal stack exposes the pad area.
  • the method for manufacturing the backlight module further includes: attaching a plurality of light-emitting devices, and the plurality of light-emitting devices are connected by contact with the pad area to be disposed on the array substrate. superior.
  • the diameter of the first via hole and the second via hole is between 3 ⁇ m and 30 ⁇ m.
  • the metal stack is used to overlap the first metal layer and the second metal layer, which solves the problem of poor conductivity of ITO in the prior art and long time or high temperature.
  • the metal stack contacts the flat layer through the first metal molybdenum, which not only realizes the high conductivity overlap between the first metal layer and the second metal layer , And increase the adhesion between the metal stack and the flat layer.
  • the metal laminate selects the second metal with a light reflectivity greater than or equal to 80%, so that the metal laminate can achieve high light reflection, replacing the organic light-reflecting layer in the prior art, reducing process steps and reducing manufacturing cost.
  • the technical problems of poor conductivity and easy failure of ITO in the prior art can be solved, and the prior art needs to be patterned step by step.
  • the organic reflective layer and the ITO layer are combined into one, so as to reduce the process steps and masks used in the process, and reduce the manufacturing cost.
  • FIG. 1 is a schematic diagram of the structure of the backlight module according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the structure of the array substrate of the backlight module according to an embodiment of the present application
  • FIG. 3 is a flow chart of preparing the array substrate of the backlight module according to an embodiment of the present application.
  • 4A to 4D are schematic diagrams of the structure corresponding to FIG. 3.
  • FIG. 5 is a schematic structural diagram of a display device provided by this application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • an intermediate medium it can be the internal communication of two components or the interaction of two components relation.
  • the "on" or “under” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • the "above”, “above” and “above” of the first feature on the second feature include the first feature directly above and obliquely above the second feature, or it simply means that the first feature is higher in level than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • an embodiment of the present application provides a backlight module 1, which includes an array substrate 100 and a plurality of light emitting devices 200 disposed on the array substrate 100.
  • a backlight module 1 includes an array substrate 100 and a plurality of light emitting devices 200 disposed on the array substrate 100.
  • the backlight module 1 includes a plurality of light emitting devices 200, and the light emitting devices 200 are arranged in an array or evenly distributed on the backlight. In the module.
  • the light-emitting device 200 is a Mini-LED chip with a conventional structure, and the light-emitting device 200 is mounted on the array substrate 100 in a manner known in the art.
  • the electrode 201 of the light emitting device 200 is in contact with the exposed pad area 151 on the array substrate 100 to realize the mounting of the light emitting device 200 on the array substrate 100.
  • the array substrate 100 includes: a base substrate 110, a first metal layer 120, an insulating layer 130, an active layer 140, a second metal layer 150, a flat layer 160, and a metal stack ⁇ 170.
  • the base substrate 110 is a conventional structure substrate in the field.
  • the first metal layer 120 is disposed on the base substrate 110 and includes a gate 121 and a first lap portion 122 for lapping the second metal layer 150.
  • the insulating layer 130 is disposed on the first metal layer 120 and covers the base substrate 110 and the first metal layer 120.
  • the active layer 140 is disposed on the insulating layer 130.
  • the second metal layer 150 is disposed on the active layer 140 and includes a pad area 151, a source and drain 152, and a second bonding portion 153 for bonding with the first metal layer 120.
  • the flat layer 160 is disposed on the second metal layer 150 and covers the second metal layer 150 and the insulating layer 130.
  • the thickness of the insulating layer 130 is 0.1 ⁇ m to 10 ⁇ m.
  • the thickness of the insulating layer 130 is defined as the vertical height between the side close to the upper surface of the base substrate 110 and the side away from the upper surface of the substrate 110.
  • the flat layer 160 has a first via 161, a second via 162 and a third via 163.
  • the first via hole 161 penetrates the flat layer 160 and the insulating layer 130 to expose the first overlap portion 122 of the first metal layer 120 that overlaps the second metal layer 150.
  • the second via hole 162 penetrates the flat layer 160 to expose the second overlap portion 153 of the second metal layer 150 that overlaps the first metal layer 120.
  • the third via hole 163 penetrates the planarization layer 160 to expose the pad region 151.
  • the first metal 171 covers the flat layer 160, the first via 161, and the second via 162, and exposes the third via 163.
  • the first metal 171 is in contact with the first lap portion 122 through the first via 161 and is in contact with the second lap portion 153 through the second via 162 ,
  • the second metal 172 covers the first metal 171 and exposes the third via hole 163.
  • the metal oxide 173 covers the second metal 172 and exposes the third via hole 163.
  • the metal stack 170 includes at least one layer of first metal 171, at least one layer of second metal 172, and at least one layer of metal oxide 173. As shown in FIG. 2, in this embodiment, the metal stack 170 includes a layer of first metal 171, a layer of second metal 172, and at least one layer of metal oxide 173. Those skilled in the art can understand that, The metal stack 170 may include multiple layers of first metal 171, second metal 172, or metal oxide 173 according to actual needs. For example, but not limited to: the metal stack 170 may include a layer of first metal 171, two The layer of second metal 172 and the layer of metal oxide 173 are not limited to the structure shown in FIG. 2.
  • each layer may be materials commonly used to form each layer known in the art.
  • the base substrate 110 may be a glass substrate, a polyimide substrate or a film substrate (film substrate).
  • the material of the first metal layer 120 may be one or an alloy composed of molybdenum (Mo) or copper (Cu).
  • the material of the insulating layer 130 may be one or a mixture of one or more of silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), and aluminum oxide (AlOx).
  • the material of the active layer 140 may be one or a mixture of one or more of organic semiconductor materials, metal oxides, nano materials, and graphene materials.
  • the material of the second metal layer 150 is one or an alloy composed of molybdenum (Mo) or copper (Cu).
  • the material of the flat layer 160 may be one or a mixture of more than one of silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), and aluminum oxide (AlOx).
  • the material of the first metal 171 is an alloy composed of one or two of molybdenum (Mo) or copper (Cu), and the conductivity of the first metal 171 is better than that of the metal oxide.
  • the conductivity of the material 173 to provide better conductivity.
  • the second metal 172 has high light reflectivity, the light reflectivity of the second metal 172 is greater than or equal to 80%, and the conductivity of the second metal 172 is better than that of the metal oxide 173 to replace
  • a reflective layer made of white oil, white organic photoresist, etc. is used in the organic layer, and provides better conductivity.
  • the material of the second metal 172 is, for example, but not limited to one or more of molybdenum (Mo), aluminum (Al), silver (Ag), titanium (Ti), and nickel (Ni). Alloy.
  • Mo molybdenum
  • Al aluminum
  • Ag silver
  • Ti titanium
  • Ni nickel
  • the material of the metal oxide 173 is indium tin oxide (ITO), or other metal oxides, such as but not limited to indium zinc oxide (IZO), indium zinc tin oxide (IZTO), and the like.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IZTO indium zinc tin oxide
  • the metal stack 170 is a composite of a film layer of the first metal 171, a film layer of the second metal 172, and a film layer of the metal oxide 173.
  • the manufacturing method of the backlight module 1 of the present application will be described in detail below with reference to FIGS. 3 and 4A to 4D.
  • the preparation method includes the following steps.
  • the preparation method includes step S1: providing a base substrate 110, and forming a patterned first metal layer 120 on the base substrate 110, and the first metal layer 120 Including a gate 121 and a first overlapping portion 122;
  • the preparation method includes step S2: forming an insulating layer 130 on the base substrate 110, the insulating layer 130 covering the first metal layer 120 and the base substrate 110; forming an insulating layer 130 on the base substrate 110, the insulating layer 130 covers the first metal layer 120 and the base substrate 110;
  • the preparation method includes step S3: forming a patterned active layer 140 and a second metal layer 150 on the insulating layer 130, and the second metal layer includes a pad area 151 , The source drain 152 and the second overlap portion 153;
  • the preparation method includes step S4: forming a flat layer 160 on the insulating layer 130, and the flat layer 160 covers the active layer 140, the second metal layer 150 and the
  • the insulating layer 130 is patterned to form a first via 161, a second via 162, and a third via 163.
  • the first via 161 exposes a portion of the first overlap portion 122, and the second via
  • the hole 162 exposes a portion of the second lap portion 152
  • the third via hole 163 exposes the pad region 151;
  • the preparation method includes step S5: patterning a metal stack 170 on the flat layer 160, and the metal stack 170 covers the exposed portion of the first via 161
  • the portion of the first overlap portion 122 and the portion of the second overlap portion 152 exposed by the second via 162 expose the pad region 151 exposed by the third via 163.
  • the gate 121 is prepared by depositing a first metal layer 120 on the surface of the base substrate 110, and then coating, exposing, developing, etching, peeling, etc.; the active layer 140 and the
  • the second metal layer 150 adopts the same halftone mask (Halftone Mask), and is prepared by coating, exposing, developing, etching, peeling, etc.; the first via 161, the second via 162, and The third via hole 163 is formed at a time through a mask, and the size of the first via hole 151 and the second via hole 152 can be between 3 ⁇ m and 30 ⁇ m.
  • the size of 163 only needs to correspond to the pad area 151, and no other size requirements are required.
  • the present application also provides a display device, including the backlight module 1 and the display panel 2 shown in FIG. , All kinds of wearable display devices, electronic display screens of all kinds of machinery or vehicles, etc.
  • the metal stack is used to overlap the first metal layer and the second metal layer, which solves the problem of poor conductivity of ITO in the prior art and long time or high temperature.
  • the metal stack contacts the flat layer through the first metal molybdenum, which not only realizes the high conductivity overlap between the first metal layer and the second metal layer , And increase the adhesion between the metal stack and the flat layer.
  • the metal laminate selects the second metal with a light reflectivity greater than or equal to 80%, so that the metal laminate can achieve high light reflection, replacing the organic light-reflecting layer in the prior art, reducing process steps and reducing manufacturing cost.
  • the technical problems of poor conductivity and easy failure of ITO in the prior art can be solved, and the prior art needs to be patterned step by step.
  • the organic reflective layer and the ITO layer are combined into one, so as to reduce the process steps and masks used in the process, and reduce the manufacturing cost.

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Abstract

本申请公开了一种背光模组及其制备方法、显示装置。所述背光模组包括一阵列基板以及设置于所述阵列基板上的多个发光器件，所述阵列基板包括：一衬底基板，以及设置于所述衬底基板上的第一金属层和第二金属层；一平坦层，覆盖所述第一金属层及所述第二金属层，并暴露所述第一金属层的部分和所述第二金属层的部分；以及，一金属叠层，设置于所述平坦层上并接触所述平坦层暴露的所述第一金属层的部分及所述第二金属层的部分；所述金属叠层包括至少一层的第一金属、至少一层的第二金属和至少一层的金属氧化物，并且，所述第一金属为钼。所述第二金属具有高强反光性，并且导电性优于所述金属氧化物，可有效降低光损耗，同时达到更好的导电性。

Description

背光模组及其制备方法和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种背光模组及其制备方法、显示装置。
 背景技术
随着显示技术的发展，Micro-LED（Micro-Light Emitting Diode，微型发光二极管）发展成未来显示技术的热点之一，和目前的LCD（Liquid Crystal Display,液晶显示器）、OLED（Organic Light Emitting Diode，有机发光二极管）显示器件相比，具有反应快、高色域、高PPI（Pixels Per Inch，像素密度）、低能耗等优势；但其技术难点多且技术复杂，特别是其关键技术巨量转移技术、LED（Light Emitting Diode，发光二极管）颗粒微型化成为技术瓶颈，而Mini-LED（Mini-Light Emitting Diode,迷你发光二极管）作为Micro-LED与背板结合的产物，具有高对比度、高显色性能等可与OLED相媲美的特点，成本稍高LCD，仅为OLED的六成左右，相对Micro-LED与OLED更易实施，所以Mini-LED成为各大面板厂商布局热点。
传统Mini-LED背光基板制作过程中，需要有机物层使用白油、白色有机光阻等做反光材料，以避免光线对器件性能的影响，并且ITO搭接深浅孔制程完成，但是ITO作为一种金属氧化物，其导电性能比金属差，且时间长或高温后会导致老化现象，而使过孔失去搭接功能。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明的目的在于提供一种背光模组及其制备方法,以及应用该背光模组的显示装置，以解决现有技术中ITO导电性能差且时间长或高温后会因老化现象而使过孔失去搭接功能的技术问题，同时有效减少光损失、降低能耗。
 技术解决方案
本申请实施例提供一种背光模组，包括一阵列基板以及设置于所述阵列基板上的多个发光器件，其特征在于，所述阵列基板包括：
一衬底基板，以及设置于所述衬底基板上的第一金属层和第二金属层；
一平坦层，覆盖所述第一金属层及所述第二金属层，并暴露所述第一金属层的部分和所述第二金属层的部分；以及，
一金属叠层，设置于所述平坦层上并接触所述平坦层暴露的所述第一金属层的部分及所述第二金属层的部分；
所述金属叠层包括至少一层的第一金属、至少一层的第二金属和至少一层的金属氧化物。
在一些是实施例中，所述第一金属为钼。
在一些是实施例中，所述第一金属为铜。
在一些是实施例中，所述第一金属为钼和铜组成的合金。
在一些是实施例中，所述第一金属接触所述第一金属层及所述第二金属层。
在一些是实施例中，所述第一金属的导电性优于所述金属氧化物。
在一些是实施例中，所述第二金属的光反射率大于等于80%。
在一些是实施例中，所述第二金属的导电性优于所述金属氧化物。
在一些是实施例中，所述第二金属为钼、铝、银、钛、镍中的一种或几种的合金。
在一些是实施例中，所述第二金属设置于所述第一金属与所述金属氧化物之间。
在一些是实施例中，所述金属氧化物为氧化铟锡、氧化铟锌以及氧化铟锌锡中的一种或几种组成的化合物。
在一些是实施例中，所述阵列基板还包括一绝缘层，所述绝缘层设置于所述第一金属层与第二金属层之间并覆盖所述第一金属层，并且，所述绝缘层暴露所述第一金属层的部分，以使得所述金属叠层透过所述平坦层及所述绝缘层接触暴露的所述第一金属层的部分。
在一些是实施例中，所述第二金属层包括至少一焊盘区，所述平坦层暴露所述焊盘区，并且，所述金属叠层暴露所述焊盘区。
在一些是实施例中，所述焊盘区阵列设置或均匀设置于所述第二金属层上。
在一些是实施例中，所述多个发光器件通过所述焊盘区设置于所述阵列基板上。
本申请实施例提供一种显示装置，权利要求1至15中任一项所述的背光模组。
本申请实施例提供一种如权利要求1所述的背光模组的制备方法，包括以下步骤：
提供一衬底基板，并在所述衬底基板上形成图案化的第一金属层；
在所述衬底基板上设置一绝缘层，所述绝缘层覆盖所述第一金属层及所述衬底基板；
在所述绝缘层上形成图案化的有源层及第二金属层；
在所述绝缘层上形成平坦层，所述平坦层覆盖所述有源层、第二金属层及所述绝缘层；
形成第一过孔及第二过孔，所述第一过孔贯穿所述平坦层及所述绝缘层以暴露所述第一金属层的部分，所述第二过孔贯穿所述平坦层以暴露所述第二金属层的部分；以及，
在所述平坦层上形成金属叠层，所述金属叠层通过所述第一过孔接触暴露的所述第一金属层的部分，所述金属叠层通过所述第二过孔接触暴露的所述第二金属层的部分。
在一些是实施例中，所述第二金属层包括至少一焊盘区，在所述形成第一过孔及第二过孔的步骤中还形成第一开口，使得所述平坦层暴露所述焊盘区；并且，在所述平坦层上形成金属叠层的步骤中，所述金属叠层暴露所述焊盘区。
在一些是实施例中，所述的背光模组的制备方法，还包括：贴装多个发光器件，所述多个发光器件通过与所述焊盘区接触连接，以设置于所述阵列基板上。
在一些是实施例中，所述第一过孔及所述第二过孔的直径在3μm至30μm之间。
 有益效果
在本申请的所述背光模组中，利用所述金属叠层搭接所述第一金属层与所述第二金属层，解决了现有技术中ITO导电性能差且时间长或高温后会因老化现象而使过孔失去搭接功能的技术问题。
尤其是，在本申请的所述背光模组中，所述金属叠层通过所述第一金属钼接触所述平坦层，既实现了第一金属层与第二金属层的高导电性搭接，又增加了所述金属叠层与所述平坦层之间的附着力。此外，所述金属叠层通过选择光反射率大于等于80%的所述第二金属，使得所述金属叠层可以实现高光反射，以替代现有技术中的有机物反光层，减少制程步骤，降低制造成本。
因此，在本申请的所述背光模组中，通过利用金属叠层的设置，既能够解决现有技术中ITO导电性差及易失效的技术问题，又将现有技术中需要分步图案化的有机物反光层与ITO层合二为一，以减少制程步骤及制程中使用的掩膜，降低制造成本。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为根据本申请一实施例的所述背光模组的结构示意图；
图2为根据本申请一实施例的所述背光模组的所述阵列基板的结构示意图；
图3为根据本申请一实施例的所述背光模组的所述阵列基板的制备流程图；
图4A至图4D为与所述图3相对应的结构示意图。
图5为本申请提供的一种显示装置结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
具体的，请参阅图1，本申请实施例提供一种背光模组1，包括一阵列基板100以及设置于所述阵列基板100上的多个发光器件200。本领域技术人员可以理解的是，图1中仅显示一个发光器件200，事实上所述背光模组1包含多个发光器件200，并且所述发光器件200阵列设置或均匀分布设置于所述背光模组中。
在本实施例中，所述发光器件200为一常规结构的Mini-LED芯片，并且所述发光器件200以本领域已知的方式贴装于所述阵列基板100上。例如，所述发光器件200的电极201与所述阵列基板100上暴露出来的焊盘区151接触连接，以实现将所述发光器件200贴装于所述阵列基板100上。
以下，结合图2详细描述所述阵列基板100的结构。
请参阅图2，所述阵列基板100包括：一衬底基板110、一第一金属层120、一绝缘层130、一有源层140、第二金属层150、一平坦层160，以及金属叠层170。
如图2所示，所述衬底基板110为本领域常规结构基板。所述第一金属层120设置于所述衬底基板110上，并包括栅极121以及用于与所述第二金属层150搭接的第一搭接部122。所述绝缘层130设置于所述第一金属层120上并覆盖所述衬底基板110及所述第一金属层120。所述有源层140设置于所述绝缘层130上。所述第二金属层150设置于所述有源层140上，并包括焊盘区151、源漏极152以及用于与所述第一金属层120搭接的第二搭接部153。所述平坦层160设置于所述第二金属层150上，并覆盖所述第二金属层150及所述绝缘层130。
在本实施例中，所述绝缘层130的厚度为0.1μm至10μm。定义所述绝缘层130的厚度为其靠近所述衬底基板110上表面的一侧与其远离所述基板110上表面的一侧的垂直高度。
如图2所示，所述平坦层160具有第一过孔161，第二过孔162及第三过孔163。所述第一过孔161贯穿所述平坦层160及所述绝缘层130，以暴露所述第一金属层120中与所述第二金属层150搭接的第一搭接部122。所述第二过孔162贯穿所述平坦层160，以暴露所述第二金属层150中与所述第一金属层120搭接的第二搭接部153。所述第三过孔163贯穿所述平坦层160，以暴露所述焊盘区151。
如图2所示，在本实施例中，所述第一金属171覆盖所述平坦层160、所述第一过孔161以及所述第二过孔162，并且暴露出所述第三过孔163，由此，所述第一金属171通过所述第一过孔161与所述第一搭接部122接触连接并且通过所述第二过孔162与所述第二搭接部153接触连接，以实现所述第一金属层120与所述第二金属层150的搭接连接。所述第二金属172覆盖所述第一金属171，并且暴露出所述第三过孔163。所述金属氧化物173覆盖所述第二金属172并且暴露出所述第三过孔163。
在本申请中，所述金属叠层170包括至少一层第一金属171，至少一层第二金属172和至少一层金属氧化物173。如图2所示，在本实施例中，所述金属叠层170包括一层第一金属171，一层第二金属172和至少一层金属氧化物173，本领域技术人员可以理解的是，所述金属叠层170可以根据实际需要而包括多层第一金属171、第二金属172或金属氧化物173，例如但不限于：所述金属叠层170可以包括一层第一金属171，两层第二金属172和一层金属氧化物173，并不以图2所示的结构为限。
在本申请中，如无特殊说明，所述各层的材料均可以是本领域已知的常用于形成各层的材料。
例如但不限于，所述衬底基板110可以是一玻璃基板、一聚酰亚胺基板或薄膜基板(film基板)。所述第一金属层120的材质可以为钼（Mo）或铜（Cu）中的一种或两种组成的合金。所述绝缘层130的材料可以为氮化硅（SiN）、氧化硅（SiO）、氮氧化硅（SiON）以及氧化铝（AlOx）中的一种或一种以上组成的混合物。所述有源层140的材料可以为有机半导体材料、金属氧化物、纳米材料以及石墨烯材料中的一种或一种以上组成的混合物。所述第二金属层150的材质为钼（Mo）或铜（Cu）中的一种或两种组成的合金。所述平坦层160的材料可以为氮化硅（SiN）、氧化硅（SiO）、氮氧化硅（SiON）以及氧化铝（AlOx）中的一种或一种以上组成的混合物。
在本申请中，所述第一金属171的材料为钼（Mo）或铜（Cu）中的一种或两种组成的合金，并且所述第一金属171的导电性优于所述金属氧化物173的导电性，以提供更优的导电性。
所述第二金属172具有高强反光性，所述第二金属172的光反射率大于等于80%，并且所述第二金属172的导电性优于所述金属氧化物173的导电性，以取代常规结构中在有机物层使用白油、白色有机光阻等所制备的反光层，并提供更优的导电性。在本实施例中，所述第二金属172的材料例如但不限于钼（Mo）、铝（Al）、银（Ag）、钛（Ti）、镍（Ni）中的一种或几种组成的合金。本领域技术人员可以理解的是，任意光反射率大于等于80%且适用于显示面板领域的金属均可以作为本申请的所述第二金属172。
所述金属氧化物173的材料为氧化铟锡(ITO),还可以是其他金属氧化物，例如但不限于氧化铟锌(IZO)、氧化铟锌锡(IZTO)等。
本技术领域人员可以理解的是，所述金属叠层170为所述第一金属171的膜层、所述第二金属172的膜层以及所述金属氧化物173的膜层层叠复合而成，例如但不限于：钼（Mo）/铝（Al）/氧化铟锡(ITO)、钼（Mo）/银（Ag）/氧化铟锡(ITO)、钼（Mo）/钛（Ti）镍（Ni）合金/氧化铟锡(ITO)、钼（Mo）/铝（Al）/氧化铟锌(IZO)、钼（Mo）/银（Ag）/氧化铟锌(IZO)、钼（Mo）/钛（Ti）镍（Ni）合金/氧化铟锌(IZO)、钼（Mo）/铝（Al）/氧化铟锌锡(IZTO)、钼（Mo）/银（Ag）/氧化铟锌锡(IZTO)、钼（Mo）/钛（Ti）镍（Ni）合金/氧化铟锌锡(IZTO)。
以下结合图3及图4A至图4D，详细描述本申请所述背光模组1的制备方法。所述制备方法包括以下步骤。
如图3及图4A所示，所述制备方法包括步骤S1：提供一衬底基板110，并在所述衬底基板110上形成图案化的第一金属层120，所述第一金属层120包括栅极121以及第一搭接部122；
如图3及图4B所示，所述制备方法包括步骤S2：在所述衬底基板110上形成一绝缘层130，所述绝缘层130覆盖所述第一金属层120及所述衬底基板110；在所述衬底基板110上形成一绝缘层130，所述绝缘层130覆盖所述第一金属层120及所述衬底基板110；
如图3及图4C所示，所述制备方法包括步骤S3：在所述绝缘层130上形成图案化的有源层140及第二金属层150，所述第二金属层包括焊盘区151、源漏极152以及第二搭接部153；
如图3及图4D所示，所述制备方法包括步骤S4：在所述绝缘层130上形成平坦层160，所述平坦层160覆盖所述有源层140、第二金属层150及所述绝缘层130，并且图案化形成第一过孔161、第二过孔162以及第三过孔163，所述第一过孔161暴露所述第一搭接部122的部分，所述第二过孔162暴露所述第二搭接部152的部分，所述第三过孔163暴露所述焊盘区151；
如图2及图3所示，所述制备方法包括步骤S5：在所述平坦层160上图案化形成金属叠层170，所述金属叠层170覆盖所述第一过孔161暴露的所述第一搭接部122的部分以及所述第二过孔162暴露的所述第二搭接部152的部分，暴露所述第三过孔163暴露的所述焊盘区151。
在本申请中，所述栅极121是通过在衬底基板110表面沉积第一金属层120，经涂布、曝光、显影、蚀刻、剥离等制程制备而成；所述有源层140与所述第二金属层150采用同一道半色调光罩（Halftone Mask），经过涂布、曝光、显影、蚀刻、剥离等工序完成制备；所述第一过孔161、所述第二过孔162以及所述第三过孔163经一道光罩一次形成，并且所述第一过孔151及所述第二过孔152并且所述尺寸大小在3μm至30μm之间均可，所述第三过孔163的大小与所述焊盘区151对应即可，不做其他尺寸要求。
如图5所示，本申请还提供一种显示装置，包括图1所示背光模组1以及显示面板2，该显示装置可应用于各类电子设备，例如：手机等通讯设备、各类电脑、各类穿戴显示设备、各类机械或交通工具的电子显示屏等。
在本申请的所述背光模组中，利用所述金属叠层搭接所述第一金属层与所述第二金属层，解决了现有技术中ITO导电性能差且时间长或高温后会因老化现象而使过孔失去搭接功能的技术问题。
尤其是，在本申请的所述背光模组中，所述金属叠层通过所述第一金属钼接触所述平坦层，既实现了第一金属层与第二金属层的高导电性搭接，又增加了所述金属叠层与所述平坦层之间的附着力。此外，所述金属叠层通过选择光反射率大于等于80%的所述第二金属，使得所述金属叠层可以实现高光反射，以替代现有技术中的有机物反光层，减少制程步骤，降低制造成本。
因此，在本申请的所述背光模组中，通过利用金属叠层的设置，既能够解决现有技术中ITO导电性差及易失效的技术问题，又将现有技术中需要分步图案化的有机物反光层与ITO层合二为一，以减少制程步骤及制程中使用的掩膜，降低制造成本。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种背光模组及其制备方法、显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种背光模组，包括一阵列基板以及设置于所述阵列基板上的多个发光器件，其中，所述阵列基板包括：
    一衬底基板，以及设置于所述衬底基板上的第一金属层和第二金属层；
    一平坦层，覆盖所述第一金属层及所述第二金属层，并暴露所述第一金属层的部分和所述第二金属层的部分；以及，
    一金属叠层，设置于所述平坦层上并接触所述平坦层暴露的所述第一金属层的部分及所述第二金属层的部分；
    所述金属叠层包括至少一层的第一金属、至少一层的第二金属和至少一层的金属氧化物。
  2. 如权利要求1所述的背光模组，其中，所述第一金属为钼。
  3. 如权利要求1所述的背光模组，其中，所述第一金属为铜。
  4. 如权利要求1所述的背光模组，其中，所述第一金属为钼和铜组成的合金。
  5. 如权利要求1所述的背光模组，其中，所述第一金属接触所述第一金属层及所述第二金属层。
  6. 如权利要求1所述的背光模组，其中，所述第一金属的导电性优于所述金属氧化物。
  7. 如权利要求1所述的背光模组，其中，所述第二金属的光反射率大于等于80%。
  8. 如权利要求1所述的背光模组，其中，所述第二金属的导电性优于所述金属氧化物。
  9. 如权利要求1所述的背光模组，其中，所述第二金属为钼、铝、银、钛、镍中的一种或几种的合金。
  10. 如权利要求1所述的背光模组，其中，所述第二金属设置于所述第一金属与所述金属氧化物之间。
  11. 如权利要求1所述的背光模组，其中，所述金属氧化物为氧化铟锡、氧化铟锌以及氧化铟锌锡中的一种或几种组成的化合物。
  12. 如权利要求1所述的背光模组，其中，所述阵列基板还包括一绝缘层，所述绝缘层设置于所述第一金属层与第二金属层之间并覆盖所述第一金属层，并且，所述绝缘层暴露所述第一金属层的部分，以使得所述金属叠层透过所述平坦层及所述绝缘层接触暴露的所述第一金属层的部分。
  13. 如权利要求1所述的背光模组，其中，所述第二金属层包括至少一焊盘区，所述平坦层暴露所述焊盘区，并且，所述金属叠层暴露所述焊盘区。
  14. 如权利要求13所述的背光模组，其中，所述焊盘区阵列设置或均匀设置于所述第二金属层上。
  15. 如权利要求13所述的背光模组，其中，所述多个发光器件通过所述焊盘区设置于所述阵列基板上。
  16. 一种显示装置，包括权利要求1所述的背光模组。
  17. 一种如权利要求1所述的背光模组的制备方法，包括以下步骤：
    提供一衬底基板，并在所述衬底基板上形成图案化的第一金属层；
    在所述衬底基板上设置一绝缘层，所述绝缘层覆盖所述第一金属层及所述衬底基板；
    在所述绝缘层上形成图案化的有源层及第二金属层；
    在所述绝缘层上形成平坦层，所述平坦层覆盖所述有源层、第二金属层及所述绝缘层；
    形成第一过孔及第二过孔，所述第一过孔贯穿所述平坦层及所述绝缘层以暴露所述第一金属层的部分，所述第二过孔贯穿所述平坦层以暴露所述第二金属层的部分；以及，
    在所述平坦层上形成金属叠层，所述金属叠层通过所述第一过孔接触暴露的所述第一金属层的部分，所述金属叠层通过所述第二过孔接触暴露的所述第二金属层的部分。
  18. 如权利要求17所述的制备方法，其中，所述第二金属层包括至少一焊盘区，在所述形成第一过孔及第二过孔的步骤中还形成第一开口，使得所述平坦层暴露所述焊盘区；并且，在所述平坦层上形成金属叠层的步骤中，所述金属叠层暴露所述焊盘区。
  19. 如权利要求17所述的制备方法，还包括：贴装多个发光器件，所述多个发光器件通过与所述焊盘区接触连接，以设置于所述阵列基板上。
  20. 如权利要求17所述的制备方法，其中，所述第一过孔及所述第二过孔的直径在3μm至30μm之间。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111796456A (zh) * 2020-07-09 2020-10-20 Tcl华星光电技术有限公司 背板和背板的制备方法
CN111682044B (zh) * 2020-07-10 2022-04-08 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制备方法、显示装置
CN111883551A (zh) * 2020-07-31 2020-11-03 京东方科技集团股份有限公司 基板、其制作方法、显示面板及显示装置
CN114171661A (zh) * 2020-09-10 2022-03-11 京东方科技集团股份有限公司 一种发光基板、显示装置及制作方法
CN112310141A (zh) * 2020-10-23 2021-02-02 深圳市华星光电半导体显示技术有限公司 micro LED显示面板及其制作方法
CN112750854B (zh) * 2021-02-04 2024-08-30 上海天马微电子有限公司 显示面板及显示装置
CN116417491A (zh) * 2021-12-31 2023-07-11 北京京东方技术开发有限公司 显示装置
US20240244747A1 (en) * 2021-12-31 2024-07-18 Boe Technology Group Co., Ltd. Wiring board, functional backplane and method for manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130285075A1 (en) * 2012-04-25 2013-10-31 Epistar Corporation Light-emitting device
CN109037239A (zh) * 2018-07-26 2018-12-18 上海天马微电子有限公司 一种阵列基板及其制备方法、显示面板
CN109375422A (zh) * 2018-12-24 2019-02-22 厦门天马微电子有限公司 背光模组及显示装置
CN109873007A (zh) * 2019-04-02 2019-06-11 深圳市华星光电半导体显示技术有限公司 有源矩阵微发光二极管显示面板
CN110010621A (zh) * 2017-12-27 2019-07-12 乐金显示有限公司 电致发光显示装置
CN110783362A (zh) * 2018-07-27 2020-02-11 首尔大学校产学协力团 显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW573372B (en) * 2002-11-06 2004-01-21 Super Nova Optoelectronics Cor GaN-based III-V group compound semiconductor light-emitting diode and the manufacturing method thereof
CN100498488C (zh) * 2007-07-05 2009-06-10 友达光电股份有限公司 半穿透半反射式液晶显示面板及其像素结构
CN109037262A (zh) * 2017-06-09 2018-12-18 美商晶典有限公司 微发光二极管显示模块的制造方法
CN110379322A (zh) * 2019-07-15 2019-10-25 深圳市华星光电半导体显示技术有限公司 显示面板、显示模组及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130285075A1 (en) * 2012-04-25 2013-10-31 Epistar Corporation Light-emitting device
CN110010621A (zh) * 2017-12-27 2019-07-12 乐金显示有限公司 电致发光显示装置
CN109037239A (zh) * 2018-07-26 2018-12-18 上海天马微电子有限公司 一种阵列基板及其制备方法、显示面板
CN110783362A (zh) * 2018-07-27 2020-02-11 首尔大学校产学协力团 显示装置
CN109375422A (zh) * 2018-12-24 2019-02-22 厦门天马微电子有限公司 背光模组及显示装置
CN109873007A (zh) * 2019-04-02 2019-06-11 深圳市华星光电半导体显示技术有限公司 有源矩阵微发光二极管显示面板

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