WO2023217285A1 - 显示面板的制备方法及显示面板 - Google Patents

显示面板的制备方法及显示面板 Download PDF

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Publication number
WO2023217285A1
WO2023217285A1 PCT/CN2023/094107 CN2023094107W WO2023217285A1 WO 2023217285 A1 WO2023217285 A1 WO 2023217285A1 CN 2023094107 W CN2023094107 W CN 2023094107W WO 2023217285 A1 WO2023217285 A1 WO 2023217285A1
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Prior art keywords
layer
flexible substrate
glass substrate
film transistor
thin film
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PCT/CN2023/094107
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English (en)
French (fr)
Inventor
徐苗
周雷
宁洪龙
邹建华
陶洪
王磊
彭俊彪
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华南理工大学
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Publication of WO2023217285A1 publication Critical patent/WO2023217285A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of display technology, for example, to a preparation method of a display panel and a display panel.
  • GOA array substrate gate driver
  • COF Chip On Film
  • Figure 1 is a structure of a display panel formed based on the preparation method of the display panel in the related art.
  • the preparation method of the display panel includes first forming a sacrificial layer on one side of the glass substrate, and then forming a sacrificial layer on the sacrificial layer.
  • a layer of polyimide material is coated on the flexible substrate 3 to form a flexible substrate 3; connection vias are formed on the flexible substrate 3 by laser etching; a metal layer is formed on the flexible substrate 3, and a conductive layer pattern is formed through a patterning process.
  • the conductive layer pattern has a conductive layer 2 corresponding to the connection via hole; a layer of polyimide material is coated again to form a leveling layer 5 covering the conductive layer pattern; and then a pair of the connection via hole is formed on the leveling layer 5 A corresponding thin film transistor device; a planarization layer 14 of polyimide material is formed on the side of the thin film transistor device facing away from the flexible substrate 3; and a source electrode of the thin film transistor device is formed on the side of the planarization layer 14 facing away from the flexible substrate 3.
  • the driver chip 16 is electrically connected through the pad 15; the flexible substrate 3 and the sacrificial layer are separated; and a Micro light-emitting diode (Light-Emitting Diode, LED) electrically connected to the conductive layer 2 is formed on the surface of the flexible substrate 3 away from the thin film transistor device. )17.
  • a Micro light-emitting diode Light-Emitting Diode, LED
  • the positional relationship of the source electrode 11, the drain electrode 12, the active layer 7, the gate electrode 9, the gate insulating layer 8 and the interlayer dielectric layer 4 included in the thin film transistor device can be as shown in Figure 1.
  • Light layer 1 The auxiliary wiring 13 of the thin film transistor device is connected to a conductive layer 2 .
  • Micro LED 17 needs to pass through the flexible substrate 3, leveling layer 5, buffer layer 6, gate insulating layer 8, interlayer dielectric layer 4 and drain 12 of the thin film transistor device in sequence, so the via holes that penetrate these film layers The deeper the depth, the more difficult it is to control the depth of the via hole and the easy breakage of the signal line, which reduces the production yield of the display panel.
  • the polyimide material needs to be coated multiple times during the preparation process, and there is also the problem of complex preparation processes.
  • This application provides a display panel preparation method and a display panel to simplify the display panel preparation process and improve the display panel preparation yield.
  • this application provides a method for preparing a display panel, including:
  • a thin film transistor device layer is formed on the side of the flexible substrate away from the glass substrate; the thin film transistor device layer includes a plurality of thin film transistor devices, and a front metal pad in contact with the signal input electrode in the thin film transistor device. joint layer;
  • a plurality of light-emitting structures are formed on the side of the planarization layer away from the glass substrate; each light-emitting structure is electrically connected to the source or drain of the corresponding thin film transistor device through the first opening;
  • a transparent encapsulation protective layer is formed on the side of the planarization layer away from the glass substrate, wherein the transparent encapsulation protective layer covers the plurality of light-emitting structures;
  • the overlap hole is configured as Connecting an external driver chip with the thin film transistor device; wherein the front metal overlap layer is a laminated structure; the melting point of at least the film layer close to the flexible substrate side in the laminated structure is higher than that of the thin film The melting point of the signal input electrode in a transistor device.
  • the method before forming the flexible substrate on the side of the sacrificial layer away from the glass substrate, the method further includes:
  • a backside metal wiring layer is formed on the side of the sacrificial layer away from the glass substrate.
  • the back metal wiring layer includes a dissociation layer and a conductive layer with the same pattern; relative to the conductive layer, the dissociation layer is closer to the sacrificial layer;
  • the materials of the dissociation layer include: silver (Ag) nanowires, carbon nanotubes or graphene, the thickness range of the dissociation layer includes 5nm ⁇ 50nm; the materials of the conductive layer include Ag, copper (Cu ), molybdenum (Mo), titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), palladium (Pd), platinum (Pt) or alloy materials based on the above elements, the conductive layer The thickness range includes: 50nm ⁇ 20000nm.
  • the method further includes:
  • the material of the dissociation layer includes carbon nanotubes or graphene; after forming a transparent encapsulation protective layer on the side of the planarization layer away from the glass substrate, it also includes:
  • the conductive layer and the sacrificial layer are separated by plasma bombardment of the dissociation layer.
  • forming a thin film transistor device layer on a side of the flexible substrate away from the glass substrate includes:
  • the vertical projection of the active layer on the flexible substrate at least partially coincides with the vertical projection of the gate on the flexible substrate; the source electrode and the drain electrode are located on the active layer Both sides are in contact with the active layer; the front-side metal lap layer includes a first front-side metal lap layer and a second front-side metal lap layer; the drain electrode or the source electrode is connected to the third A front metal overlap layer is in contact, and the auxiliary electrode is in contact with the second front metal overlap layer.
  • forming an overlapping hole exposing a metal overlapping layer from a side of the flexible substrate away from the thin film transistor device layer includes:
  • the flexible substrate and the gate insulating layer are sequentially etched by a laser to form an overlapping hole exposing the front metal overlapping layer.
  • the method before forming the sacrificial layer on one side of the glass substrate, the method further includes:
  • a protruding structure is formed on one side of the glass substrate where the sacrificial layer is formed; the vertical projection of the protruding structure on the glass substrate is at least partially the same as the vertical projection of the front metal overlap layer on the glass substrate. coincide;
  • the protruding structure is configured to form a second second protruding structure on the flexible substrate at a position corresponding to the protruding structure when the flexible substrate is prepared by coating a polyimide (PI) solution.
  • opening the second opening is configured to expose the gate insulating layer after separating the flexible substrate and the sacrificial layer; or, the protruding structure is configured to prepare the flexible substrate by applying a PI solution
  • a groove is formed on the position corresponding to the protruding structure in the flexible substrate, and the groove is configured to reduce the amount of the convex layer after the flexible substrate and the sacrificial layer are separated.
  • the thickness of the flexible substrate is etched when overlapping the holes.
  • Two openings are formed from the side of the flexible substrate away from the thin film transistor device layer to expose the front metal overlap layer, including:
  • the gate insulating layer exposed by the second opening is etched through a yellow light process, and a third opening is formed in the gate insulating layer to expose the front metal overlap layer; wherein, the The second opening and the third opening form an overlapping hole;
  • Lap holes for layers including:
  • etch the flexible substrate at the location of the groove to form a second opening in the flexible substrate that exposes the gate insulating layer; and continue to etch the gate insulating layer , until the front metal overlap layer is exposed; forming a third opening in the gate insulating layer that exposes the front metal overlap layer; the second opening and the third opening at the same position Form a lap hole.
  • forming a protruding structure on the side of the glass substrate on which the sacrificial layer is formed includes:
  • a photoresist layer is formed on one side of the glass substrate, and the photoresist layer is patterned to form the protruding structure; or,
  • An amorphous silicon layer is formed on one side of the glass substrate, and the amorphous silicon layer is patterned to form the protruding structure; or,
  • the present application provides a display panel formed by any of the display panel preparation methods described in the first aspect.
  • Figure 1 is a schematic structural diagram of a display panel provided in the related art
  • Figure 2 is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present application
  • Figure 3 is a structural cross-sectional view corresponding to step S110 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 4 is a structural cross-sectional view corresponding to step S120 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 5 is a structural cross-sectional view corresponding to step S130 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 6 is a structural cross-sectional view corresponding to step S140 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 7 is a structural cross-sectional view corresponding to step S160 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 8 is a structural cross-sectional view corresponding to step S170 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 9 is a structural cross-sectional view corresponding to step S170 in another display panel preparation method provided by an embodiment of the present application.
  • Figure 10 is a structural cross-sectional view corresponding to step S170 in another display panel preparation method provided by an embodiment of the present application.
  • Figure 11 is a structural cross-sectional view corresponding to step S180 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 12 is a structural cross-sectional view corresponding to step S180 in another display panel preparation method provided by an embodiment of the present application.
  • Figure 13 is a flow chart of another method of manufacturing a display panel provided by an embodiment of the present application.
  • Figure 14 is a structural cross-sectional view corresponding to step S220 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 15 is a structural cross-sectional view corresponding to step S230 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 16 is a structural cross-sectional view corresponding to step S260 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 17 is a structural cross-sectional view corresponding to step S280 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 18 is a structural cross-sectional view corresponding to step S280 in another display panel preparation method provided by an embodiment of the present application.
  • Figure 19 is a structural cross-sectional view corresponding to step S290 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 20 is a flow chart of another method of manufacturing a display panel provided by an embodiment of the present application.
  • Figure 21 is a structural cross-sectional view corresponding to step S310 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 22 is a structural cross-sectional view corresponding to step S320 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 23 is a diagram corresponding to step S330 in a method for manufacturing a display panel provided by an embodiment of the present application. Structural cross-section;
  • Figure 24 is a structural cross-sectional view corresponding to step S350 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 25 is a structural cross-sectional view corresponding to step S380 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 26 is a structural cross-sectional view corresponding to step S390 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 27 is a structural cross-sectional view corresponding to step S3100 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 28 is a structural cross-sectional view corresponding to step S3110 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • Figure 29 is a structural cross-sectional view corresponding to step S3110 in another display panel preparation method provided by an embodiment of the present application.
  • Figure 30 is a flow chart of another method of manufacturing a display panel provided by an embodiment of the present application.
  • Figure 31 is a structural cross-sectional view corresponding to step S410 in a method for manufacturing a display panel provided by an embodiment of the present application;
  • FIG. 32 is a structural cross-sectional view corresponding to step S420 in a method for manufacturing a display panel provided by an embodiment of the present application.
  • FIG. 2 is a flow chart of a method of preparing a display panel provided by the embodiment of the present application. Referring to Figure 2, the method of preparing a display panel includes:
  • S110 Provide a glass substrate, and form a sacrificial layer on one side of the glass substrate.
  • the glass substrate 10 has two opposite surfaces, and the side on which the sacrificial layer 20 is formed is set as the first surface of the glass substrate 10 .
  • a layer of amorphous silicon material may be formed on the first surface of the glass substrate 10 as the sacrificial layer 20 .
  • a flexible substrate 30 is formed on a side surface of the sacrificial layer 20 away from the glass substrate 10 .
  • the flexible substrate 30 can provide a display device for subsequent preparation. Even the entire display panel structure provides good support and protection effects, and the sacrificial layer 20 is disposed between the glass substrate 10 and the flexible substrate 30. In subsequent steps, the glass can be peeled off by separating the flexible substrate 30 and the sacrificial layer 20. Substrate 10.
  • the sacrificial layer 20 is only in contact with the flexible substrate 30, which can avoid the problem of metal breakage caused by the peeling operation in the subsequent laser peeling operation, and protects the flatness and cleanliness of the surface of the flexible substrate 30 facing the glass substrate 10 after peeling off. , no need for surface treatment, saving energy consumption.
  • the material of the flexible substrate 30 here is, for example, PI.
  • the thin film transistor device layer includes a plurality of thin film transistor devices and a front metal overlap layer in contact with the signal input electrode in the thin film transistor device.
  • a thin film transistor (TFT) device is prepared on a PI film (flexible substrate 30) and a front metal overlap layer 47 is formed to form a thin film transistor device layer.
  • the front metal overlap layer 47 has a stacked structure; at least the melting point of the film layer close to the flexible substrate 30 in the stacked structure is higher than the melting point of the signal input electrode in the thin film transistor device.
  • the material on the side of the laminated structure close to the PI film uses high melting point tungsten (W), tantalum (Ta), Mo, chromium (Cr), Ti or alloys thereof as the main material.
  • step S130 forming a thin film transistor device layer on the side of the flexible substrate away from the glass substrate includes:
  • the gate 41 in the thin film transistor device is formed on the side of the flexible substrate 30 away from the glass substrate 10; the gate 41 covers part of the flexible substrate 30; on the side of the gate 41 away from the glass substrate 10, the side of the gate 41 A gate insulating layer 42 is formed on the flexible substrate 30 that is not covered by the wall and the gate electrode 41; a front metal overlap layer 47 and a source electrode 44 in the thin film transistor device are formed on the side of the gate insulating layer 42 away from the flexible substrate 30. , drain electrode 45 (or source electrode 45, drain electrode 44), active layer 43 and auxiliary electrode 46.
  • the vertical projection of the active layer 43 on the flexible substrate 30 at least partially coincides with the vertical projection of the gate electrode 41 on the flexible substrate 30; the source electrode 44 and the drain electrode 45 are located on both sides of the active layer 43, and both are connected to the active layer 43.
  • the source layer 43 contacts; the front metal overlap layer 47 includes a first front metal overlap layer 471 and a second front metal overlap layer 472 .
  • the source electrode 44 is exemplarily shown to be in contact with the first front metal overlap layer 471
  • the auxiliary electrode 46 is in contact with the second front metal overlap layer 472 .
  • the drain electrode 45 may also be in contact with the first front-side metal overlap layer 471 .
  • the auxiliary electrode 46 may be a wiring outside the TFT in the pixel circuit, such as a ground terminal voltage (VSS), a power supply voltage (VDD), etc.
  • the signal input electrodes of the thin film transistor device are the source electrode 44, the drain electrode 45, and the auxiliary electrode 46.
  • a planarization layer 50 is formed to keep the side surface of the flexible substrate 30 away from the glass substrate 10 flat to facilitate the subsequent formation of the light-emitting structure.
  • the material of the planarization layer 50 can be polyimide or Choose other organic planarizing materials.
  • the planarization layer 50 needs to be etched to form a first opening 51; the first opening 51 exposes the source electrode 44 or The drain electrode 45 facilitates the connection between the electrode of the light-emitting structure and the thin film transistor device.
  • FIG. 6 exemplarily depicts the first opening 51 exposing the drain electrode 45 in the thin film transistor device.
  • each light-emitting structure is electrically connected to the source or drain of the corresponding thin film transistor device through the first opening.
  • the transparent packaging protective layer covers multiple light-emitting structures.
  • a transparent packaging protective layer 70 is made on the TFT and light-emitting structure 60; the material of the transparent packaging protective layer 70 can be epoxy resin, acrylic and other transparent organic materials; the transparent packaging protective layer 70 can prevent water and oxygen from damaging the display panel Damage to the internal structure can also ensure the flatness of the display panel after packaging.
  • the flexible substrate 30 can be separated from the sacrificial layer 20 using laser or mechanical force, thereby peeling off the flexible substrate 30 and the glass substrate 10, exposing the flexible substrate 30 away from the thin film transistor device layer. surface on one side.
  • the separated flexible substrate 30 is inverted, and a lap hole 81 exposing the front metal lap layer 47 is formed from the side of the flexible substrate 30 away from the thin film transistor device layer.
  • sputtering, vacuum evaporation or electroplating processes can be used to form conductive leads 822 in the overlapping hole 81 and on the flexible substrate.
  • 30 Prepare a connection pad 821 on the surface on the side facing away from the thin film transistor device layer, and bind the driver chip 90 to the connection pad 821.
  • the solution processing method can also be used to perform conductive processing on the front metal overlap layer 47 using silver paste and silver nanowires.
  • the power signal provided by the driver chip 90 is connected to the front metal overlap layer 47 via the connection pad 821 and the conductive lead 822 in the overlap hole 81 .
  • the signal input electrode in the thin film transistor device is connected to the front metal overlap layer 47, and then controls the TFT driver board to realize lighting of the light-emitting structure.
  • the PI material and the gate insulating layer 42 can be ablated using a femtosecond laser to form a bonding hole 81 exposing the front metal bonding layer 47 from the side of the flexible substrate 30 away from the thin film transistor device layer, exposing the front bonding metal.
  • the front metal overlap layer 47 has a laminated structure; the melting point of at least the film layer close to the flexible substrate 30 in the laminated structure is higher than the melting point of the signal input electrode in the thin film transistor device. The higher melting point of the front overlapping metal layer 47 is utilized to ensure that the metal material is not damaged during the laser ablation process.
  • the external driving chip is formed to connect the The overlapping hole of the thin film transistor device only penetrates the flexible substrate and the gate insulating layer, and the light-emitting structure can be connected to the thin film transistor device only through part of the planarization layer, which overall improves the difficulty of controlling the depth of the via hole and the ease of signal lines.
  • the problem of breakage improves the production yield of display panels; in addition, during the preparation process, the polyimide material only needs to be coated once when forming the flexible substrate, and there is no need to prepare a leveling layer in related technologies, simplifying The display panel preparation process is improved and the cost is reduced.
  • FIG 13 is a flow chart of another display panel preparation method provided by an embodiment of the present application.
  • the display panel preparation method includes:
  • S210 Provide a glass substrate, and form a sacrificial layer on one side of the glass substrate.
  • S220 Make a back metal wiring layer on the side of the sacrificial layer away from the glass substrate.
  • the back metal wiring layer 100 is formed on the side of the sacrificial layer 20 away from the glass substrate 10 .
  • Whether the back metal wiring layer 100 is prepared is related to the number of driver chips required to control the entire display panel. If the number of driver chips required to control the entire display panel is large, the back metal wiring layer can be prepared in the flexible substrate.
  • the display panel is an organic light-emitting diode (OLED) display panel
  • the light-emitting structure is an OLED light-emitting structure
  • Metal overlap layer can meet the settings of signal transmission lines.
  • the display panel is a Micro LED display panel
  • the light-emitting structure is an LED light-emitting structure.
  • Micro LED driving requires a relatively high number of chips.
  • Several light-emitting structures need to correspond to one driving chip.
  • the back metal wiring layer 100 needs to be prepared.
  • the backside metal wiring layer 100 includes a dissociation layer 102 and a conductive layer 101 with the same pattern; relative to the conductive layer 101, the dissociation layer 102 is closer to the sacrificial layer.
  • the dissociation layer 102 is composed of one-dimensional or two-dimensional nanomaterials such as Ag nanowires, carbon nanotubes, and graphene; or it is a sputtered carbon film.
  • the thickness of the dissociation layer 102 is 5 nm to 50 nm; the preparation method includes spin coating , spraying, inkjet printing; the conductive layer 101 is made of Ag, Cu, Mo, Ti, Al, Ni, Au, Pd, Pt or alloy materials based on the above elements, preparation method: sputtering, evaporation, chemical vapor deposition, electroplating ; The thickness of the conductive layer 101 ranges from 50nm to 20,000nm.
  • the conductive layer 101 and the dissociation layer 102 can be sequentially patterned using the same mask, so that the dissociation layer 102 and the conductive layer 101 have the same pattern.
  • step S270 after forming a transparent encapsulation protective layer on the side of the planarization layer away from the glass substrate, it also includes: etching the dissociation layer 102 with an Ag etching solution to separate the conductive layer. 101 and sacrificial layer 20. If the material of the dissociation layer 102 includes carbon nanotubes or graphene; after forming a transparent encapsulation protective layer on the side of the planarization layer away from the glass substrate, it also includes: bombarding the dissociation layer 102 with plasma to separate the conductive layer 101 and the sacrificial layer. Layer 20. By disposing the dissociation layer 102 between the conductive layer 101 and the sacrificial layer 20 , the difficulty of peeling off the backside metal wiring layer 100 from the sacrificial layer 20 can be reduced.
  • a PI solution can be applied to prepare a PI film to form a flexible substrate 30.
  • the thickness of the flexible substrate 30 ranges from 10um to 50um.
  • the thickness of the flexible substrate 30 is greater than the thickness of the back metal wiring layer 100.
  • the thin film transistor device layer includes a plurality of thin film transistor devices and a front metal overlap layer in contact with the signal input electrode in the thin film transistor device.
  • each LED light-emitting structure is electrically connected to the source or drain of the corresponding thin film transistor device through the first opening.
  • the transparent packaging protective layer covers multiple LED light-emitting structures.
  • laser or mechanical force can be used to separate the flexible substrate 30 from the sacrificial layer 20, thereby peeling off the flexible substrate 30 and the glass substrate 10, exposing the flexible substrate 30 away from the thin film transistor device layer. surface on one side.
  • the separated flexible substrate 30 is inverted, and a lap hole 81 exposing the front metal lap layer 47 is formed from the side of the flexible substrate 30 away from the thin film transistor device layer.
  • connection pad 821 is prepared on the surface of the flexible substrate 30 away from the thin film transistor device layer. , binding the driver chip 90 to the connection pad 821.
  • the overlapping hole formed to connect the external driver chip and the thin film transistor device only penetrates the flexible substrate and the gate insulating layer, and the light-emitting structure only needs to pass through part of the planarization layer.
  • the problem of easy breakage of control and signal lines improves the production yield of display panels; in addition, during the preparation process, the polyimide material only needs to be coated once when forming the flexible substrate, without the need for preparation in related technologies.
  • the leveling layer simplifies the preparation process of the display panel and reduces the cost.
  • a backside metal wiring layer is formed on the side of the sacrificial layer away from the glass substrate. It meets the requirements of Micro LED driver which requires a relatively high number of chips.
  • the back metal wiring layer includes a dissociation layer and a conductive layer with the same pattern; relative to the conductive layer, the dissociation layer is closer to the sacrificial layer.
  • FIG 20 is a flow chart of another display panel preparation method provided by an embodiment of the present application.
  • the display panel preparation method includes:
  • S310 Provide a glass substrate, and form a protruding structure on one side of the glass substrate.
  • the material of the protruding structure includes photoresist or amorphous silicon.
  • the protruding structure 11 is first formed on the side of the glass substrate 10 on which the sacrificial layer is formed.
  • Forming the protruding structure 11 may include: forming a photoresist layer on one side of the glass substrate 10 , and patterning the photoresist layer to form the protruding structure 11 .
  • an amorphous silicon layer is formed on one side of the glass substrate 10 , and the amorphous silicon layer is patterned to form the protruding structure 11 .
  • the distance range from the surface of the protruding structure 11 away from the glass substrate 10 to the glass substrate 10 includes 5um-55um, that is, the height range of the protruding structure 11 includes 5um-55um.
  • the vertical projection of the protruding structure 11 on the glass substrate 10 at least partially coincides with the vertical projection of the subsequently prepared front metal overlap layer on the glass substrate 10 .
  • the protruding structure 11 is configured to form a second opening in the flexible substrate at a position corresponding to the protruding structure 11 when the flexible substrate is prepared by coating the PI solution; the second opening is configured to form a second opening after the flexible substrate and the sacrificial layer are separated. , exposing the gate insulating layer 42 .
  • the cross-sectional shape of the protruding structure 11 may be triangular, rectangular or trapezoidal. The shape of the protruding structure 11 is not limited here. In FIG. 21 , the cross-sectional shape of the protruding structure 11 is illustrated as a triangle.
  • the height in this embodiment refers to the distance from the top of the structure to the side of the glass substrate 10 away from the structure.
  • the height of the protruding structure 11 is the distance from the triangular vertex of the protruding structure 11 facing the gate insulating layer 42 to the bottom surface of the glass substrate 10 .
  • S320 Form a sacrificial layer on one side of the glass substrate, and the sacrificial layer covers the protruding structure.
  • a sacrificial layer 20 is formed on one side of the glass substrate 10 , and the sacrificial layer 20 covers the protruding structure 11 .
  • a back metal wiring layer 100 is formed on the side of the sacrificial layer 20 away from the glass substrate 10 .
  • the composition of the back metal wiring layer 100 may refer to the above embodiment, and will not be described again here.
  • S340 Form a flexible substrate on the side of the sacrificial layer away from the glass substrate, and the flexible substrate covers the back metal wiring layer.
  • a PI solution can be applied and cured to form a flexible substrate 30.
  • the thickness of the flexible substrate 30 ranges from The range includes: 10um-50um.
  • the height of the PI solution applied may not exceed the height of the protruding structure 11.
  • the flexible substrate 30 may form a through hole, that is, a second opening. There is no need to burn the flexible substrate 30 with a laser during the process of forming the overlapping holes, which simplifies the preparation process of the display panel.
  • the sum of the heights of the protruding structure 11 and the sacrificial layer 20 at the position of the protruding structure 11 needs to be less than or equal to the height of the subsequently formed gate insulating layer 42 to prevent the formation of cracks after the flexible substrate 30 and the sacrificial layer 20 are separated.
  • the overlapping hole is too deep, affecting the front metal overlapping layer.
  • the thin film transistor device layer includes a plurality of thin film transistor devices and a front metal overlap layer in contact with the signal input electrode in the thin film transistor device.
  • each LED light-emitting structure is electrically connected to the source or drain of the corresponding thin film transistor device through the first opening.
  • S380 Form a transparent packaging protective layer on the side of the planarization layer away from the glass substrate, and the transparent packaging protective layer covers multiple LED light-emitting structures.
  • the flexible substrate 30 can be separated from the sacrificial layer 20 using laser or mechanical force, thereby peeling off the flexible substrate 30 and the glass substrate 10, exposing the side of the flexible substrate 30 away from the thin film transistor device layer. surface.
  • the flexible substrate 30 and the sacrificial layer 20 are separated, thereby exposing the second opening 31 in the flexible substrate 30 .
  • the released flexible substrate 30 is inverted, and the gate insulating layer 42 exposed by the second opening 31 is etched through a yellow light process, and a third opening 421 is formed in the gate insulating layer 42 to expose Front metal overlap layer 47; wherein, the second opening 31 and the third opening 421 at the same position form an overlap hole 81; the overlap hole 81 is configured to connect the external driver chip and the thin film transistor device.
  • connection pad 821 is prepared on the surface of the flexible substrate 30 away from the thin film transistor device layer, and the driver chip 90 is bound to the connection pad 821 .
  • the display panel preparation method provided by the embodiments of the present application is based on the above embodiments, by forming a photoresist layer or amorphous silicon layer on one side of the glass substrate, and patterning the photoresist layer or amorphous silicon layer Form a raised structure.
  • a through hole penetrating the flexible substrate can be formed during the preparation of the flexible substrate, so there is no need to etch the flexible substrate using a laser or dry etching process.
  • a third opening is formed, thereby forming an overlapping hole. It simplifies the preparation of overlapping holes in the display panel and can effectively control the depth of the overlapping holes.
  • the height of the applied PI solution may exceed the height of the protruding structure.
  • the PI solution is cured to form the flexible substrate.
  • a groove is formed in the flexible substrate at a position corresponding to the protruding structure, and the groove is configured to reduce the thickness of the flexible substrate etched when the overlapping hole is formed after the flexible substrate is separated from the sacrificial layer. It can also reduce the difficulty of etching through holes in flexible substrates.
  • the method further includes laser etching the flexible substrate at the location of the groove based on the groove to form a second opening in the flexible substrate that exposes the gate insulating layer.
  • the gate insulating layer exposed by the second opening can be etched through a yellow light process, and a third opening can be formed in the gate insulating layer to expose the front metal overlap layer; wherein, the second opening at the same position The opening and the third opening form an overlapping hole.
  • the gate insulating layer can be continuously etched with a laser until the front metal overlap layer is exposed; a third opening is formed in the gate insulating layer to expose the front metal overlap layer; thereby forming a overlap socket.
  • FIG 30 is a flow chart of another display panel preparation method provided by an embodiment of the present application.
  • the display panel preparation method includes:
  • S410 Provide a glass substrate, and pattern the surface on one side of the glass substrate to form a convex structure.
  • the surface on one side of the glass substrate 10 is etched to form a protruding structure 11 .
  • the height of the protruding structure 11 ranges from 5um to 55um, that is, the depth of the etched glass substrate 10 ranges from 5um to 55um.
  • the vertical projection of the protruding structure 11 on the glass substrate 10 at least partially coincides with the vertical projection of the subsequently prepared front metal overlap layer on the glass substrate.
  • the protruding structure 11 is configured to form a second opening in the flexible substrate at a position corresponding to the protruding structure 11 when the flexible substrate is prepared by coating the PI solution; the second opening is configured to form a second opening after the flexible substrate and the sacrificial layer are separated. , exposing the gate insulation layer.
  • S420 Form a sacrificial layer on one side of the glass substrate, and the sacrificial layer covers the protruding structure.
  • a sacrificial layer 20 is formed on one side of the glass substrate 10 , and the sacrificial layer 20 covers the protruding structure 11 .
  • the thin film transistor device layer includes a plurality of thin film transistor devices and a front metal overlap layer in contact with the signal input electrode in the thin film transistor device.
  • S460 Form a planarization layer on a side of the thin film transistor device layer away from the glass substrate, and etch the planarization layer to form a plurality of first openings; the first openings expose the source or drain electrodes in the thin film transistor device.
  • each LED light-emitting structure is electrically connected to the source or drain of the corresponding thin film transistor device through the first opening.
  • S480 Form a transparent packaging protective layer on the side of the planarization layer away from the glass substrate, and the transparent packaging protective layer covers multiple LED light-emitting structures.
  • the display panel preparation method provided by the embodiments of the present application is based on the above embodiments, and forms a PI through hole convex structure by etching a glass substrate. There is no need to form a photoresist layer or amorphous silicon layer on one side of the glass substrate, and then pattern the photoresist layer or amorphous silicon layer to form a protruding structure. Therefore, the difficulty of preparing the overlapping holes in the display panel is simplified, and the depth of the overlapping holes can be effectively controlled. At the same time, the process steps can be reduced, the preparation efficiency of the display panel can be improved, and the cost can be reduced.
  • Embodiments of the present application also provide a display panel formed by the display panel preparation method described in any of the above embodiments.
  • the display panel includes: a flexible substrate 30, a thin film transistor device layer is formed on one side of the flexible substrate 30; the thin film transistor device layer includes a plurality of thin film transistor devices, and the thin film transistor device.
  • the front metal overlap layer 47 is contacted by the signal input electrode.
  • a planarization layer 50 is formed on a side of the thin film transistor device layer away from the glass substrate.
  • the planarization layer 50 includes a first opening; the first opening exposes the source electrode 44 or the drain electrode 45 in the thin film transistor device.
  • each light-emitting structure 60 is electrically connected to the source electrode 44 or the drain electrode 45 in the corresponding thin film transistor device through the first opening.
  • a transparent packaging protective layer 70 is provided on the side of the light-emitting structure 60 away from the glass substrate.
  • a bonding hole exposing the front metal bonding layer 47 is provided on a side of the flexible substrate 30 away from the thin film transistor device layer, and a conductive lead 822 is provided in the bonding hole.
  • a connection pad 821 is prepared on the surface of the flexible substrate 30 on the side facing away from the thin film transistor device layer, and the driver chip 90 is bound to the connection pad.
  • the overlapping hole connecting the external driver chip and the thin film transistor device only penetrates the flexible substrate 30 and the gate insulating layer 42, and the light-emitting structure 60 only needs to pass through part of the planarization layer 50.
  • the problem of difficult control of via hole depth and easy breakage of signal lines is improved as a whole, and the production yield of the display panel is improved; in addition, during the preparation process, only coating is required when forming the flexible substrate 30 Only one polyimide material is needed, and there is no need to prepare a leveling layer in related technologies, which simplifies the preparation process of the display panel and reduces the cost.

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Abstract

本申请公开了显示面板的制备方法及显示面板。显示面板的制备方法包括：提供玻璃基板，并在玻璃基板的一侧依次形成牺牲层、柔性衬底、薄膜晶体管器件层、平坦化层；在平坦化层远离玻璃基板的一侧形成多个发光结构；每一发光结构通过平坦化层的第一开口与对应的薄膜晶体管器件中的源极或漏极电连接；分离柔性衬底和牺牲层，并从柔性衬底远离薄膜晶体管器件层的一侧形成暴露正面金属搭接层的搭接孔；搭接孔设置为连通外部驱动芯片与薄膜晶体管器件。

Description

显示面板的制备方法及显示面板
本申请要求在2022年05月13日提交中国专利局、申请号为202210524641.1的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如涉及显示面板的制备方法及显示面板。
背景技术
全面屏技术逐渐成为手机等手持设备的主流技术，采用阵列基板栅极驱动(Gate Driver On Array，GOA)技术实现左右边框的窄型化，采用薄膜覆晶封装(Chip On Film，COF)技术实现下边框的窄型化。但是无论是GOA还是COF，这种在显示屏边框焊接的技术依然无法实现无缝拼接。
基于上述背景，图1是基于相关技术的显示面板的制备方法形成的一种显示面板的结构，参考图1，显示面板的制备方法包括先在玻璃基板一侧表面依次形成牺牲层，在牺牲层上涂覆一层聚酰亚胺材料形成柔性衬底3；在柔性衬底3上通过激光刻蚀形成连接过孔；在柔性衬底3上形成金属层，并通过构图工艺形成导电层图案，导电层图案具有与连接过孔对应的导电层2；再次涂覆一层聚酰亚胺材料形成流平层5覆盖导电层图案；之后在流平层5上形成与所述连接过孔对一一对应的薄膜晶体管器件；在薄膜晶体管器件背离柔性衬底3一侧形成聚酰亚胺材料的平坦化层14；在平坦化层14背离柔性衬底3一侧形成与薄膜晶体管器件的源极11通过焊盘15电连接的驱动芯片16；分离柔性衬底3和牺牲层；在柔性衬底3背离薄膜晶体管器件的表面形成与导电层2电连接的Micro发光二极管(Light-Emitting Diode，LED)17。其中，薄膜晶体管器件包括的源极11、漏极12、有源层7、栅极9、栅极绝缘层8以及层间介电层4的位置关系可以如图1所示，还可以包括避光层1。薄膜晶体管器件的辅助走线13与一个导电层2连接。
Micro LED 17需依次通过柔性衬底3、流平层5、缓冲层6、栅极绝缘层8以及层间介电层4与薄膜晶体管器件的漏极12，因此贯穿这些膜层的过孔的深度较深，存在过孔深度难以控制以及信号线容易断裂的问题，降低了显示面板的制备良率。而且制备过程中需多次涂覆聚酰亚胺材料，还存在制备工艺复杂的问题。
发明内容
本申请提供了显示面板的制备方法及显示面板，以简化显示面板的制备工艺，提高显示面板的制备良率。
第一方面，本申请提供了一种显示面板的制备方法，包括：
提供玻璃基板，并在所述玻璃基板的一侧形成牺牲层；
于所述牺牲层远离所述玻璃基板的一侧形成柔性衬底；
在所述柔性衬底远离所述玻璃基板的一侧形成薄膜晶体管器件层；所述薄膜晶体管器件层包括多个薄膜晶体管器件，以及与所述薄膜晶体管器件中的信号输入电极接触的正面金属搭接层；
于所述薄膜晶体管器件层远离所述玻璃基板的一侧形成平坦化层，并刻蚀所述平坦化层形成多个第一开口；所述第一开口暴露所述薄膜晶体管器件中的源极或漏极；
在所述平坦化层远离所述玻璃基板的一侧形成多个发光结构；每一发光结构通过所述第一开口与对应的薄膜晶体管器件中的源极或漏极电连接；
在所述平坦化层远离所述玻璃基板的一侧形成透明封装保护层，其中，所述透明封装保护层覆盖所述多个发光结构；
分离所述柔性衬底和所述牺牲层，并从所述柔性衬底远离所述薄膜晶体管器件层的一侧形成暴露所述正面金属搭接层的搭接孔；所述搭接孔设置为连通外部驱动芯片与所述薄膜晶体管器件；其中，所述正面金属搭接层为叠层结构；所述叠层结构中至少靠近所述柔性衬底侧的膜层的熔点，高于所述薄膜晶体管器件中信号输入电极的熔点。
一实施例中，在所述于所述牺牲层远离所述玻璃基板的一侧形成柔性衬底之前，还包括：
在所述牺牲层远离所述玻璃基板的一侧制作背面金属走线层。
一实施例中，所述背面金属走线层包括图形相同的解离层和导电层；相对于所述导电层，所述解离层较靠近于所述牺牲层；
其中，所述解离层的材料包括：银(Ag)纳米线、碳纳米管或石墨烯，所述解离层的厚度范围包括5nm～50nm；所述导电层的材料包括Ag、铜(Cu)、钼(Mo)、钛(Ti)、铝(Al)、镍(Ni)、金(Au)、钯(Pd)、铂(Pt)或以以上元素为主体的合金材料，所述导电层的厚度范围包括：50nm～20000nm。
一实施例中，若所述解离层的材料包括Ag纳米线；在所述在所述平坦化层远离所述玻璃基板的一侧形成透明封装保护层之后，还包括：
通过Ag刻蚀液腐蚀所述解离层，分离所述导电层和所述牺牲层；
若所述解离层的材料包括碳纳米管或石墨烯；在所述在所述平坦化层远离所述玻璃基板的一侧形成透明封装保护层之后，还包括：
通过等离子体轰击所述解离层，分离所述导电层和所述牺牲层。
一实施例中，所述在所述柔性衬底远离所述玻璃基板的一侧形成薄膜晶体管器件层，包括：
于所述柔性衬底远离所述玻璃基板的一侧形成所述薄膜晶体管器件中的栅极；所述栅极覆盖部分的柔性衬底；
于所述栅极远离所述玻璃基板的一侧、所述栅极的侧壁以及所述栅极未覆盖的柔性衬底上形成栅极绝缘层；
在所述栅极绝缘层远离所述柔性衬底的一侧形成所述正面金属搭接层以及所述薄膜晶体管器件中的源极、漏极、有源层和辅助电极；
其中，所述有源层在所述柔性衬底上的垂直投影与所述栅极在所述柔性衬底上的垂直投影至少部分重合；所述源极和漏极位于所述有源层的两侧，并均与所述有源层接触；所述正面金属搭接层包括第一正面金属搭接层和第二正面金属搭接层；所述漏极或所述源极与所述第一正面金属搭接层接触，所述辅助电极与所述第二正面金属搭接层接触。
一实施例中，所述从所述柔性衬底远离所述薄膜晶体管器件层的一侧形成暴露金属搭接层的搭接孔，包括：
通过激光依次刻蚀所述柔性衬底和所述栅极绝缘层，形成暴露所述正面金属搭接层的搭接孔。
一实施例中，在所述在所述玻璃基板的一侧形成牺牲层之前，还包括：
在所述玻璃基板形成所以牺牲层的一侧形成凸起结构；所述凸起结构在所述玻璃基板上的垂直投影与所述正面金属搭接层在所述玻璃基板上的垂直投影至少部分重合；
其中，所述凸起结构设置为在通过涂敷聚酰亚胺(Polyimide，PI)溶液制备所述柔性衬底时，在所述柔性衬底中所述凸起结构对应的位置上形成第二开口；所述第二开口设置为在分离所述柔性衬底和所述牺牲层后，暴露所述栅极绝缘层；或者，所述凸起结构设置为在通过涂敷PI溶液制备所述柔性衬底时，在所述柔性衬底中所述凸起结构对应的位置上形成凹槽，所述凹槽设置为在分离所述柔性衬底和所述牺牲层后，减小在形成所述搭接孔时刻蚀所述柔性衬底的厚度。
一实施例中，若在所述柔性衬底中所述凸起结构对应的位置上形成所述第 二开口，则所述从所述柔性衬底远离所述薄膜晶体管器件层的一侧形成暴露所述正面金属搭接层的搭接孔，包括：
通过黄光制程刻蚀所述第二开口暴露出的栅极绝缘层，在所述栅极绝缘层中形成第三开口，以暴露所述正面金属搭接层；其中，同一位置上的所述第二开口与所述第三开口组成一个搭接孔；
若在所述柔性衬底中所述凸起结构对应的位置上形成所述凹槽，则所述从所述柔性衬底远离所述薄膜晶体管器件层的一侧形成暴露所述正面金属搭接层的搭接孔，包括：
基于所述凹槽，刻蚀所述凹槽所在位置的柔性衬底，在所述柔性衬底中形成暴露出所述栅极绝缘层的第二开口；并继续刻蚀所述栅极绝缘层，直至暴露出所述正面金属搭接层；在所述栅极绝缘层中形成暴露出所述正面金属搭接层的第三开口；同一位置上的所述第二开口与所述第三开口组成一个搭接孔。
一实施例中，所述在所述玻璃基板形成所述牺牲层的一侧形成凸起结构，包括：
在所述玻璃基板的一侧形成光刻胶层，图形化所述光刻胶层形成所述凸起结构；或者，
在所述玻璃基板的一侧形成非晶硅层，图形化所述非晶硅层形成所述凸起结构；或者，
图形化所述玻璃基板一侧的表面，形成所述凸起结构。第二方面，本申请提供了一种显示面板，通过第一方面任意所述的显示面板的制备方法形成。
附图说明
图1是相关技术中提供的一种显示面板的结构示意图；
图2是本申请实施例提供的一种显示面板的制备方法的流程图；
图3是本申请实施例提供的一种显示面板的制备方法中步骤S110对应的结构剖面图；
图4是本申请实施例提供的一种显示面板的制备方法中步骤S120对应的结构剖面图；
图5是本申请实施例提供的一种显示面板的制备方法中步骤S130对应的结构剖面图；
图6是本申请实施例提供的一种显示面板的制备方法中步骤S140对应的结构剖面图；
图7是本申请实施例提供的一种显示面板的制备方法中步骤S160对应的结构剖面图；
图8是本申请实施例提供的一种显示面板的制备方法中步骤S170对应的结构剖面图；
图9是本申请实施例提供的另一种显示面板的制备方法中步骤S170对应的结构剖面图；
图10是本申请实施例提供的另一种显示面板的制备方法中步骤S170对应的结构剖面图；
图11是本申请实施例提供的一种显示面板的制备方法中步骤S180对应的结构剖面图；
图12是本申请实施例提供的另一种显示面板的制备方法中步骤S180对应的结构剖面图；
图13是本申请实施例提供的另一种显示面板的制备方法的流程图；
图14是本申请实施例提供的一种显示面板的制备方法中步骤S220对应的结构剖面图；
图15是本申请实施例提供的一种显示面板的制备方法中步骤S230对应的结构剖面图；
图16是本申请实施例提供的一种显示面板的制备方法中步骤S260对应的结构剖面图；
图17是本申请实施例提供的一种显示面板的制备方法中步骤S280对应的结构剖面图；
图18是本申请实施例提供的另一种显示面板的制备方法中步骤S280对应的结构剖面图；
图19是本申请实施例提供的一种显示面板的制备方法中步骤S290对应的结构剖面图；
图20是本申请实施例提供的另一种显示面板的制备方法的流程图；
图21是本申请实施例提供的一种显示面板的制备方法中步骤S310对应的结构剖面图；
图22是本申请实施例提供的一种显示面板的制备方法中步骤S320对应的结构剖面图；
图23是本申请实施例提供的一种显示面板的制备方法中步骤S330对应的 结构剖面图；
图24是本申请实施例提供的一种显示面板的制备方法中步骤S350对应的结构剖面图；
图25是本申请实施例提供的一种显示面板的制备方法中步骤S380对应的结构剖面图；
图26是本申请实施例提供的一种显示面板的制备方法中步骤S390对应的结构剖面图；
图27是本申请实施例提供的一种显示面板的制备方法中步骤S3100对应的结构剖面图；
图28是本申请实施例提供的一种显示面板的制备方法中步骤S3110对应的结构剖面图；
图29是本申请实施例提供的另一种显示面板的制备方法中步骤S3110对应的结构剖面图；
图30是本申请实施例提供的另一种显示面板的制备方法的流程图；
图31是本申请实施例提供的一种显示面板的制备方法中步骤S410对应的结构剖面图；
图32是本申请实施例提供的一种显示面板的制备方法中步骤S420对应的结构剖面图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，所描述的实施例仅仅是本申请一部分的实施例。
本申请实施例提供了一种显示面板的制备方法，图2是本申请实施例提供的一种显示面板的制备方法的流程图，参考图2，显示面板的制备方法包括：
S110、提供玻璃基板，并在玻璃基板的一侧形成牺牲层。
参考图3，玻璃基板10具有两个相对的表面，设定形成牺牲层20的一侧为玻璃基板10的第一表面。可以在玻璃基板10的第一表面形成一层非晶硅材料作为牺牲层20。
S120、于牺牲层远离玻璃基板的一侧形成柔性衬底。
参考图4，在玻璃基板10的第一表面形成牺牲层20后，再在牺牲层20背离玻璃基板10的一侧表面形成柔性衬底30。柔性衬底30能够为后续制备的显示器件 乃至整个显示面板结构提供良好的支撑和保护效果，而牺牲层20设置于玻璃基板10与柔性衬底30之间，在后续步骤中通过将柔性衬底30与牺牲层20分离即可实现剥离玻璃基板10。并且，牺牲层20只与柔性衬底30接触，能够避免在后续激光剥离作业中剥离操作导致金属断裂的问题，保护了剥离后柔性衬底30面向玻璃基板10一侧表面的平整度和洁净度，无需进行表面处理，节省了能耗。此处的柔性衬底30的材料例如为PI。
S130、在柔性衬底远离玻璃基板的一侧形成薄膜晶体管器件层；薄膜晶体管器件层包括多个薄膜晶体管器件，以及与薄膜晶体管器件中的信号输入电极接触的正面金属搭接层。
参考图5，在PI薄膜(柔性衬底30)上制备薄膜晶体管(Thin Film Transistor，TFT)器件以及正面金属搭接层47形成薄膜晶体管器件层。其中，正面金属搭接层47为叠层结构；叠层结构中至少靠近柔性衬底30侧的膜层的熔点，高于薄膜晶体管器件中信号输入电极的熔点。例如叠层结构的靠近PI薄膜侧的材料使用高熔点的钨(W)，钽(Ta)，Mo，铬(Cr)，Ti或以其为主体材料的合金。
在步骤S130中，在柔性衬底远离玻璃基板的一侧形成薄膜晶体管器件层，包括：
于柔性衬底30远离玻璃基板10的一侧形成薄膜晶体管器件中的栅极41；栅极41覆盖部分的柔性衬底30；于栅极41远离玻璃基板10的一侧、栅极41的侧壁以及栅极41未覆盖的柔性衬底30上形成栅极绝缘层42；在栅极绝缘层42远离柔性衬底30的一侧形成正面金属搭接层47以及薄膜晶体管器件中的源极44、漏极45(或者源极45、漏极44)、有源层43和辅助电极46。
有源层43在柔性衬底30上的垂直投影与栅极41在柔性衬底30上的垂直投影至少部分重合；源极44和漏极45位于有源层43的两侧，并均与有源层43接触；正面金属搭接层47包括第一正面金属搭接层471和第二正面金属搭接层472。图5中示例性的画出源极44与第一正面金属搭接层471接触，辅助电极46与第二正面金属搭接层472接触。一实施例中，也可以为漏极45与第一正面金属搭接层471接触。辅助电极46可以是像素电路里面诸如接地端电压(VSS)、电源电压(VDD)等TFT之外的走线。薄膜晶体管器件的信号输入电极即为源极44、漏极45、辅助电极46。
S140、于薄膜晶体管器件层远离玻璃基板的一侧形成平坦化层，并刻蚀平坦化层形成多个第一开口；第一开口暴露薄膜晶体管器件中的源极或漏极。
参考图6，制作平坦化层50使得柔性衬底30背离玻璃基板10的一侧表面保持平坦，方便后续形成发光结构。平坦化层50的材料可以选择聚酰亚胺，也可以 选择其他的有机平坦化材料。于薄膜晶体管器件层远离玻璃基板10的一侧形成平坦化层50后，需对平坦化层50进行刻蚀处理，形成第一开口51；第一开口51暴露薄膜晶体管器件中的源极44或漏极45，以便于发光结构的电极与薄膜晶体管器件连接。图6示例性的画出第一开口51暴露薄膜晶体管器件中的漏极45。
S150、在平坦化层远离玻璃基板的一侧形成多个发光结构；每一发光结构通过第一开口与对应的薄膜晶体管器件中的源极或漏极电连接。
S160、在平坦化层远离玻璃基板的一侧形成透明封装保护层，透明封装保护层覆盖多个发光结构。
参考图7，在TFT和发光结构60之上制作透明封装保护层70；透明封装保护层70的材料可以是环氧树脂，亚克力等透明有机材料；透明封装保护层70可以防止水氧对显示面板内部结构的损坏，还可以保证显示面板封装后的平整性。
S170、分离柔性衬底和牺牲层，并从柔性衬底远离薄膜晶体管器件层的一侧形成暴露正面金属搭接层的搭接孔；搭接孔设置为连通外部驱动芯片与薄膜晶体管器件。
参考图8-图10，可以使用激光或是机械力的方式将柔性衬底30与牺牲层20分离，从而剥离了柔性衬底30和玻璃基板10，露出了柔性衬底30背离薄膜晶体管器件层一侧的表面。将离型后的柔性衬底30反转，从柔性衬底30远离薄膜晶体管器件层的一侧形成暴露正面金属搭接层47的搭接孔81。
S180、在搭接孔中形成导电引线，并在柔性衬底背离薄膜晶体管器件层一侧的表面制备连接焊盘，将驱动芯片与连接焊盘绑定。
参考图11-图12，形成暴露正面金属搭接层47的搭接孔81之后，可以使用溅射，真空蒸镀或者电镀工艺，在搭接孔81中形成导电引线822，并在柔性衬底30背离薄膜晶体管器件层一侧的表面制备连接焊盘821，将驱动芯片90与连接焊盘821绑定。也可以使用溶液加工法，用银浆，银纳米线对正面金属搭接层47进行导体化处理。驱动芯片90提供的电源信号经由连接焊盘821和搭接孔81中的导电引线822，与正面金属搭接层47连接。薄膜晶体管器件中的信号输入电极与正面金属搭接层47连接，进而控制TFT驱动板，实现发光结构的点亮。
可以使用飞秒激光将PI材料和栅极绝缘层42烧蚀以从柔性衬底30远离薄膜晶体管器件层的一侧形成暴露正面金属搭接层47的搭接孔81，暴露出正面搭接金属层47。正面金属搭接层47为叠层结构；叠层结构中至少靠近柔性衬底30侧的膜层的熔点，高于薄膜晶体管器件中信号输入电极的熔点。利用正面搭接金属层47较高的熔点，保证在激光烧蚀的过程中，不损伤金属材料。
本申请实施例提供的显示面板的制备方法中，形成的连通外部驱动芯片与 薄膜晶体管器件的搭接孔仅贯穿柔性衬底以及栅极绝缘层，而且发光结构只需通过部分的平坦化层即可与薄膜晶体管器件连接，整体上改善了过孔深度难以控制以及信号线容易断裂的问题，提高了显示面板的制备良率；另外，在制备过程中，只需在形成柔性衬底时涂覆一次聚酰亚胺材料即可，无需制备相关技术中的流平层，简化了显示面板的制备工艺，降低了成本。
图13是本申请实施例提供的另一种显示面板的制备方法的流程图，参考图13，显示面板的制备方法包括：
S210、提供玻璃基板，并在玻璃基板的一侧形成牺牲层。
S220、在牺牲层远离玻璃基板的一侧制作背面金属走线层。
参考图14，与上述实施例不同的是，本申请实施例中在牺牲层20远离玻璃基板10的一侧制作背面金属走线层100。背面金属走线层100是否制备与控制整个显示面板所需的驱动芯片的数量相关。若控制整个显示面板所需的驱动芯片的数量较多，则可以在柔性衬底中制备背面金属走线层。例如显示面板为有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，其中的发光结构为OLED发光结构，则可以选择不在柔性衬底中制备背面金属走线层，需要正面金属走线(正面金属搭接层)即可满足信号传输线的设置。例如显示面板为Micro LED显示面板，其中的发光结构为LED发光结构。Micro LED的驱动对芯片的数量要求比较高，几个发光结构就需要对应一个驱动芯片，此时则需制备背面金属走线层100。
背面金属走线层100包括图形相同的解离层102和导电层101；相对于导电层101，解离层102较靠近于牺牲层。解离层102为Ag纳米线、碳纳米管、石墨烯等一维或二维纳米材料构成；或是溅射的碳膜，解离层102的厚度在5nm～50nm厚；制备方法有旋涂，喷涂，喷墨打印；导电层101由Ag，Cu，Mo，Ti，Al，Ni，Au，Pd，Pt或以以上元素为主体的合金材料，制备方法溅射，蒸发，化学气相沉积，电镀；导电层101的厚度范围50nm～20 000nm。可以使用同张掩模版依次图形化导电层101和解离层102，使得解离层102和导电层101的图形相同。
若解离层102的材料包括Ag纳米线，在步骤S270即在平坦化层远离玻璃基板的一侧形成透明封装保护层之后，还包括：通过Ag刻蚀液腐蚀解离层102，分离导电层101和牺牲层20。若解离层102的材料包括碳纳米管或石墨烯；在平坦化层远离玻璃基板的一侧形成透明封装保护层之后，还包括：通过等离子体轰击解离层102，分离导电层101和牺牲层20。通过在导电层101与牺牲层20之间设置解离层102，可以降低背面金属走线层100从牺牲层20上剥离的难度。
S230、于牺牲层远离玻璃基板的一侧形成柔性衬底，柔性衬底覆盖背面金 属走线层。
参考图15，可以涂敷PI溶液，制备PI薄膜形成柔性衬底30，柔性衬底30的厚度范围包括：10um-50um。柔性衬底30的厚度大于背面金属走线层100的厚度，在后续使用激光或是机械力的方式将柔性衬底30与玻璃基板10分离时，可以保证柔性衬底30将背面金属导线固定在体内。其中，使用激光照射牺牲层20时释放氢气(H2)，可以改变牺牲层20与金属镀层的粘附力。
S240、在柔性衬底远离玻璃基板的一侧形成薄膜晶体管器件层；薄膜晶体管器件层包括多个薄膜晶体管器件，以及与薄膜晶体管器件中的信号输入电极接触的正面金属搭接层。
S250、于薄膜晶体管器件层远离玻璃基板的一侧形成平坦化层，并刻蚀平坦化层形成多个第一开口；第一开口暴露薄膜晶体管器件中的源极或漏极。
S260、在平坦化层远离玻璃基板的一侧形成多个LED发光结构；每一LED发光结构通过第一开口与对应的薄膜晶体管器件中的源极或漏极电连接。
S270、在平坦化层远离玻璃基板的一侧形成透明封装保护层，透明封装保护层覆盖多个LED发光结构。
经过步骤S240～S270后，所形成的结构剖面图如图16所示。具体步骤可参考上述实施例，这里不再赘述。
S280、分离柔性衬底和牺牲层，并从柔性衬底远离薄膜晶体管器件层的一侧形成暴露正面金属搭接层的搭接孔；搭接孔设置为于连通外部驱动芯片与薄膜晶体管器件。
参考图17和图18，可以使用激光或是机械力的方式将柔性衬底30与牺牲层20分离，从而剥离了柔性衬底30和玻璃基板10，露出了柔性衬底30背离薄膜晶体管器件层一侧的表面。将离型后的柔性衬底30反转，从柔性衬底30远离薄膜晶体管器件层的一侧形成暴露正面金属搭接层47的搭接孔81。
S290、在搭接孔中形成导电引线，并在柔性衬底背离薄膜晶体管器件层一侧的表面制备连接焊盘，将驱动芯片与连接焊盘绑定。
参考图19，形成暴露正面金属搭接层47的搭接孔81之后，在搭接孔81中形成导电引线822，并在柔性衬底30背离薄膜晶体管器件层一侧的表面制备连接焊盘821，将驱动芯片90与连接焊盘821绑定。
本申请实施例提供的显示面板的制备方法中，形成的连通外部驱动芯片与薄膜晶体管器件的搭接孔仅贯穿柔性衬底以及栅极绝缘层，而且发光结构只需通过部分的平坦化层即可与薄膜晶体管器件连接，整体上改善了过孔深度难以 控制以及信号线容易断裂的问题，提高了显示面板的制备良率；另外，在制备过程中，只需在形成柔性衬底时涂覆一次聚酰亚胺材料即可，无需制备相关技术中的流平层，简化了显示面板的制备工艺，降低了成本。在此基础上，本申请实施例中在在牺牲层远离玻璃基板的一侧制作背面金属走线层。满足Micro LED的驱动对芯片的数量要求比较高的需求。其中，背面金属走线层包括图形相同的解离层和导电层；相对于导电层，解离层较靠近于牺牲层。通过在导电层与牺牲层之间设置解离层，可以降低背面金属走线层从牺牲层上剥离的难度。
图20是本申请实施例提供的另一种显示面板的制备方法的流程图，参考图20，显示面板的制备方法包括：
S310、提供玻璃基板，在玻璃基板的一侧形成凸起结构，所述凸起结构的材料包括光刻胶或者非晶硅。
参考图21，在玻璃基板10形成牺牲层的一侧先形成凸起结构11。形成凸起结构11可以包括：在玻璃基板10的一侧形成光刻胶层，图形化光刻胶层形成凸起结构11。或者，在玻璃基板10的一侧形成非晶硅层，图形化非晶硅层形成凸起结构11。凸起结构11远离玻璃基板10一侧的表面到玻璃基板10之间的距离范围包括5um-55um，即凸起结构11的高度范围包括5um-55um。其中凸起结构11在玻璃基板10上的垂直投影与后续制备的正面金属搭接层在玻璃基板10上的垂直投影至少部分重合。凸起结构11设置为在通过涂敷PI溶液制备柔性衬底时，在柔性衬底中凸起结构11对应的位置上形成第二开口；第二开口设置为在分离柔性衬底和牺牲层后，暴露栅极绝缘层42。凸起结构11的剖面形状可以为三角形、长方形或者梯形。这里对凸起结构11的形状不进行限定，图21中示例性的画出凸起结构11的剖面形状为三角形。
本实施例中的高度是指结构的顶部至玻璃基板10的远离该结构的一侧的距离。例如凸起结构11的高度为凸起结构11朝向栅极绝缘层42的三角顶点到玻璃基板10的底面的距离。
S320、在玻璃基板的一侧形成牺牲层，牺牲层覆盖凸起结构。
参考图22，在玻璃基板10的一侧形成牺牲层20，牺牲层20覆盖凸起结构11。
S330、在牺牲层远离玻璃基板的一侧制作背面金属走线层。
参考图23，在牺牲层20远离玻璃基板10的一侧制作背面金属走线层100。背面金属走线层100的组成可参考上述实施例，这里不再赘述。
S340、于牺牲层远离玻璃基板的一侧形成柔性衬底，柔性衬底覆盖背面金属走线层。
参考图24，可以涂敷PI溶液，固化后形成柔性衬底30，柔性衬底30的厚度范 围包括：10um-50um。在凸起结构11所在的位置，涂敷PI溶液的高度可以不超过凸起结构11的高度，在固化PI溶液形成柔性衬底30后，柔性衬底30可以形成通孔，即第二开口。无需再形成搭接孔过程中通过激光灼烧柔性衬底30，简化了显示面板的制备工艺。凸起结构11和凸起结构11位置上的牺牲层20的高度值和，需小于或等于后续形成的栅极绝缘层42的高度，以防止在分离柔性衬底30和牺牲层20后形成的搭接孔过深，而影响到正面金属搭接层。
S350、在柔性衬底远离玻璃基板的一侧形成薄膜晶体管器件层；薄膜晶体管器件层包括多个薄膜晶体管器件，以及与薄膜晶体管器件中的信号输入电极接触的正面金属搭接层。
S360、于薄膜晶体管器件层远离玻璃基板的一侧形成平坦化层，并刻蚀平坦化层形成多个第一开口；第一开口暴露薄膜晶体管器件中的源极或漏极。
S370、在平坦化层远离玻璃基板的一侧形成多个LED发光结构；每一LED发光结构通过第一开口与对应的薄膜晶体管器件中的源极或漏极电连接。
S380、在平坦化层远离玻璃基板的一侧形成透明封装保护层，透明封装保护层覆盖多个LED发光结构。
经过步骤S350～S380后，所形成的结构剖面图如图25所示。步骤可参考上述实施例，这里不再赘述。
S390、分离柔性衬底和牺牲层，暴露出柔性衬底的第二开口。
参考图26，可以使用激光或是机械力的方式将柔性衬底30与牺牲层20分离，从而剥离了柔性衬底30和玻璃基板10，露出了柔性衬底30背离薄膜晶体管器件层一侧的表面。分离柔性衬底30和牺牲层20，从而暴露出柔性衬底30中的第二开口31。
S3100、通过黄光制程刻蚀第二开口暴露出的栅极绝缘层，在栅极绝缘层中形成第三开口，以暴露正面金属搭接层；其中，同一位置上的第二开口与第三开口组成一个搭接孔；搭接孔设置为连通外部驱动芯片与薄膜晶体管器件。
参考图27，将离型后的柔性衬底30反转，通过黄光制程刻蚀第二开口31暴露出的栅极绝缘层42，在栅极绝缘层42中形成第三开口421，以暴露正面金属搭接层47；其中，同一位置上的第二开口31与第三开口421组成一个搭接孔81；搭接孔81设置为连通外部驱动芯片与薄膜晶体管器件。
S3110、在搭接孔中形成导电引线，并在柔性衬底背离薄膜晶体管器件层一侧的表面制备连接焊盘，将驱动芯片与连接焊盘绑定。
参考图28-图29，形成暴露正面金属搭接层47的搭接孔81之后，在搭接孔81 中形成导电引线822，并在柔性衬底30背离薄膜晶体管器件层一侧的表面制备连接焊盘821，将驱动芯片90与连接焊盘821绑定。
本申请实施例提供的显示面板的制备方法，在上述实施例的基础上，通过在玻璃基板的一侧形成光刻胶层或非晶硅层，并图形化光刻胶层或者非晶硅层形成凸起结构。使得在制备柔性衬底过程中即可形成贯穿柔性衬底的通孔，因此不需要再用激光或者干法刻蚀工艺刻蚀柔性衬底。而仅需要采用普通黄光制程刻蚀栅极绝缘层(一般是氧化硅(SiOx)、氮化硅(SiNx)、氧化铝(AlOx)或者几者的叠层结构)形成贯通栅极绝缘层的第三开口，从而形成搭接孔。简化了显示面板中对搭接孔制备的难度，可有效的控制搭接孔的深度。
在本申请的另一个实施例中，在步骤S340于牺牲层远离玻璃基板的一侧形成柔性衬底时，涂敷PI溶液的高度可以超过凸起结构的高度，在固化PI溶液形成柔性衬底后，在柔性衬底中凸起结构对应的位置上形成凹槽，凹槽设置为在分离柔性衬底和所述牺牲层后，减小在形成搭接孔时刻蚀柔性衬底的厚度。同样可以降低刻蚀柔性衬底通孔的难度。则在步骤S390之后，还包括基于所述凹槽，通过激光刻蚀凹槽所在位置的柔性衬底，在柔性衬底中形成暴露出所述栅极绝缘层的第二开口。在S3100步骤中，可以通过黄光制程刻蚀第二开口暴露出的栅极绝缘层，在栅极绝缘层中形成第三开口，以暴露正面金属搭接层；其中，同一位置上的第二开口与第三开口组成一个搭接孔。或者，可以通过激光继续刻蚀所述栅极绝缘层，直至暴露出所述正面金属搭接层；在栅极绝缘层中形成暴露出所述正面金属搭接层的第三开口；从而形成搭接孔。
图30是本申请实施例提供的另一种显示面板的制备方法的流程图，参考图31，显示面板的制备方法包括：
S410、提供玻璃基板，图形化玻璃基板一侧的表面，形成凸起结构。
参考图31，刻蚀玻璃基板10一侧的表面，形成凸起结构11。凸起结构11的高度范围包括5um-55um，即刻蚀玻璃基板10的深度的范围包括5um-55um。
凸起结构11在玻璃基板10上的垂直投影与后续制备的正面金属搭接层在玻璃基板上的垂直投影至少部分重合。凸起结构11设置为在通过涂敷PI溶液制备柔性衬底时，在柔性衬底中凸起结构11对应的位置上形成第二开口；第二开口设置为在分离柔性衬底和牺牲层后，暴露栅极绝缘层。
S420、在玻璃基板的一侧形成牺牲层，牺牲层覆盖凸起结构。
参考图32，在玻璃基板10的一侧形成牺牲层20，牺牲层20覆盖凸起结构11。
S430、在牺牲层远离玻璃基板的一侧制作背面金属走线层。
S440、于背面金属走线层远离玻璃基板的一侧形成柔性衬底。
S450、在柔性衬底远离玻璃基板的一侧形成薄膜晶体管器件层；薄膜晶体管器件层包括多个薄膜晶体管器件，以及与薄膜晶体管器件中的信号输入电极接触的正面金属搭接层。
S460、于薄膜晶体管器件层远离玻璃基板的一侧形成平坦化层，并刻蚀平坦化层形成多个第一开口；第一开口暴露薄膜晶体管器件中的源极或漏极。
S470、在平坦化层远离玻璃基板的一侧形成多个LED发光结构；每一LED发光结构通过第一开口与对应的薄膜晶体管器件中的源极或漏极电连接。
S480、在平坦化层远离玻璃基板的一侧形成透明封装保护层，透明封装保护层覆盖多个LED发光结构。
S490、分离柔性衬底和牺牲层，暴露出柔性衬底的第二开口。
S4100、通过黄光制程刻蚀第二开口暴露出的栅极绝缘层，在栅极绝缘层中形成第三开口，以暴露正面金属搭接层；其中，同一位置上的第二开口与第三开口组成一个搭接孔；搭接孔设置为连通外部驱动芯片与薄膜晶体管器件。
S4110、在搭接孔中形成导电引线，并在柔性衬底背离薄膜晶体管器件层一侧的表面制备连接焊盘，将驱动芯片与连接焊盘绑定。
步骤S430～S4110可对应的参考S330～S3110，这里不再赘述。本申请实施例提供的显示面板的制备方法，在上述实施例的基础上，通过刻蚀玻璃基板形成PI通孔的凸起结构。无需在玻璃基板的一侧形成光刻胶层或非晶硅层，再图形化光刻胶层或者非晶硅层形成凸起结构。因此，在简化了显示面板中对搭接孔制备的难度，可有效的控制搭接孔的深度的同时，可以减少工艺步骤，提高显示面板的制备效率，降低了成本。
本申请实施例还提供了一种显示面板，通过上述任意实施例所述的显示面板的制备方法形成。
示例性的，参考图12，显示面板包括：柔性衬底30，在柔性衬底30的一侧形成有薄膜晶体管器件层；薄膜晶体管器件层包括多个薄膜晶体管器件，以及与薄膜晶体管器件中的信号输入电极接触的正面金属搭接层47。于薄膜晶体管器件层远离玻璃基板的一侧形成有平坦化层50，平坦化层50包括第一开口；第一开口暴露薄膜晶体管器件中的源极44或漏极45。在平坦化层50远离玻璃基板的一侧具有多个发光结构60；每一发光结构60通过第一开口与对应的薄膜晶体管器件中的源极44或漏极45电连接。在发光结构60远离玻璃基板的一侧设置有透明封装保护层70。从柔性衬底30远离薄膜晶体管器件层的一侧设置有暴露正面金属搭接层47的搭接孔，在搭接孔中具有导电引线822。并在柔性衬底30背离薄膜晶体管器件层一侧的表面制备连接焊盘821，将驱动芯片90与连接焊盘绑定。
本申请实施例提供的显示面板中，连通外部驱动芯片与薄膜晶体管器件的搭接孔仅贯穿柔性衬底30以及栅极绝缘层42，而且发光结构60只需通过部分的平坦化层50即可与薄膜晶体管器件连接，整体上改善了过孔深度难以控制以及信号线容易断裂的问题，提高了显示面板的制备良率；另外，在制备过程中，只需在形成柔性衬底30时涂覆一次聚酰亚胺材料即可，无需制备相关技术中的流平层，简化了显示面板的制备工艺，降低了成本。

Claims (10)

  1. 一种显示面板的制备方法，包括：
    提供玻璃基板，并在所述玻璃基板的一侧形成牺牲层；
    于所述牺牲层远离所述玻璃基板的一侧形成柔性衬底；
    在所述柔性衬底远离所述玻璃基板的一侧形成薄膜晶体管器件层；其中，所述薄膜晶体管器件层包括多个薄膜晶体管器件，以及与所述薄膜晶体管器件中的信号输入电极接触的正面金属搭接层；
    于所述薄膜晶体管器件层远离所述玻璃基板的一侧形成平坦化层，并刻蚀所述平坦化层形成多个第一开口；其中，所述第一开口暴露所述薄膜晶体管器件中的源极或漏极；
    在所述平坦化层远离所述玻璃基板的一侧形成多个发光结构；其中，每一发光结构通过所述第一开口与对应的薄膜晶体管器件中的源极或漏极电连接；
    在所述平坦化层远离所述玻璃基板的一侧形成透明封装保护层，其中，所述透明封装保护层覆盖所述多个发光结构；
    分离所述柔性衬底和所述牺牲层，并从所述柔性衬底远离所述薄膜晶体管器件层的一侧形成暴露所述正面金属搭接层的搭接孔；其中，所述搭接孔设置为连通外部驱动芯片与所述薄膜晶体管器件；所述正面金属搭接层为叠层结构；所述叠层结构中至少靠近所述柔性衬底侧的膜层的熔点，高于所述薄膜晶体管器件中信号输入电极的熔点。
  2. 根据权利要求1所述的显示面板的制备方法，在所述于所述牺牲层远离所述玻璃基板的一侧形成柔性衬底之前，还包括：
    在所述牺牲层远离所述玻璃基板的一侧制作背面金属走线层。
  3. 根据权利要求2所述的显示面板的制备方法，其中，所述背面金属走线层包括图形相同的解离层和导电层；相对于所述导电层，所述解离层较靠近于所述牺牲层；
    其中，所述解离层的材料包括：银Ag纳米线、碳纳米管或石墨烯，所述解离层的厚度范围包括5nm～50nm；所述导电层的材料包括Ag、铜Cu、钼Mo、钛Ti、铝Al、镍Ni、金Au、钯Pd、铂Pt或以以上材料为主体的合金材料，所述导电层的厚度范围包括：50nm～20000nm。
  4. 根据权利要求3所述的显示面板的制备方法，其中，在所述解离层的材料包括Ag纳米线的情况下，在所述在所述平坦化层远离所述玻璃基板的一侧形成透明封装保护层之后，还包括：
    通过Ag刻蚀液腐蚀所述解离层，分离所述导电层和所述牺牲层；
    在所述解离层的材料包括碳纳米管或石墨烯的情况下，在所述在所述平坦化层远离所述玻璃基板的一侧形成透明封装保护层之后，还包括：
    通过等离子体轰击所述解离层，分离所述导电层和所述牺牲层。
  5. 根据权利要求1所述的显示面板制备方法，其中，所述在所述柔性衬底远离所述玻璃基板的一侧形成薄膜晶体管器件层，包括：
    于所述柔性衬底远离所述玻璃基板的一侧形成所述薄膜晶体管器件中的栅极；其中，所述栅极覆盖部分的柔性衬底；
    于所述栅极远离所述玻璃基板的一侧、所述栅极的侧壁以及所述栅极未覆盖的柔性衬底上形成栅极绝缘层；
    在所述栅极绝缘层远离所述柔性衬底的一侧形成所述正面金属搭接层以及所述薄膜晶体管器件中的源极、漏极、有源层和辅助电极；
    其中，所述有源层在所述柔性衬底上的垂直投影与所述栅极在所述柔性衬底上的垂直投影至少部分重合；所述源极和漏极位于所述有源层的两侧，并均与所述有源层接触；所述正面金属搭接层包括第一正面金属搭接层和第二正面金属搭接层；所述源极或所述漏极与所述第一正面金属搭接层接触，所述辅助电极与所述第二正面金属搭接层接触。
  6. 根据权利要求5所述的显示面板的制备方法，其中，所述从所述柔性衬底远离所述薄膜晶体管器件层的一侧形成暴露金属搭接层的搭接孔，包括：
    通过激光依次刻蚀所述柔性衬底和所述栅极绝缘层，形成暴露所述正面金属搭接层的搭接孔。
  7. 根据权利要求5所述的显示面板的制备方法，在所述在所述玻璃基板的一侧形成牺牲层之前，还包括：
    在所述玻璃基板形成所述牺牲层的一侧形成凸起结构；其中，所述凸起结构在所述玻璃基板上的垂直投影与所述正面金属搭接层在所述玻璃基板上的垂直投影至少部分重合；
    其中，所述凸起结构设置为在通过涂敷聚酰亚胺PI溶液制备所述柔性衬底的情况下，在所述柔性衬底中所述凸起结构对应的位置上形成第二开口；所述第二开口设置为在分离所述柔性衬底和所述牺牲层后，暴露所述栅极绝缘层；或者，所述凸起结构设置为在通过涂敷PI溶液制备所述柔性衬底的情况下，在所述柔性衬底中所述凸起结构对应的位置上形成凹槽，所述凹槽设置为在分离所述柔性衬底和所述牺牲层后，减小在形成所述搭接孔时刻蚀所述柔性衬底的 厚度。
  8. 根据权利要求7所述的显示面板的制备方法，其中，在在所述柔性衬底中所述凸起结构对应的位置上形成所述第二开口的情况下，所述从所述柔性衬底远离所述薄膜晶体管器件层的一侧形成暴露所述正面金属搭接层的搭接孔，包括：
    通过黄光制程刻蚀所述第二开口暴露出的栅极绝缘层，在所述栅极绝缘层中形成第三开口，以暴露所述正面金属搭接层；其中，同一位置上的所述第二开口与所述第三开口组成一个搭接孔；
    在在所述柔性衬底中凸起结构对应的位置上形成所述凹槽的情况下，所述从所述柔性衬底远离所述薄膜晶体管器件层的一侧形成暴露所述正面金属搭接层的搭接孔，包括：
    基于所述凹槽，刻蚀所述凹槽所在位置的柔性衬底，在所述柔性衬底中形成暴露出所述栅极绝缘层的第二开口；并继续刻蚀所述栅极绝缘层，直至暴露出所述正面金属搭接层；在所述栅极绝缘层中形成暴露出所述正面金属搭接层的第三开口；其中，同一位置上的所述第二开口与所述第三开口组成一个搭接孔。
  9. 根据权利要求7所述的显示面板的制备方法，其中，所述在所述玻璃基板形成所述牺牲层的一侧形成凸起结构，包括：
    在所述玻璃基板的一侧形成光刻胶层，图形化所述光刻胶层形成所述凸起结构；或者，
    在所述玻璃基板的一侧形成非晶硅层，图形化所述非晶硅层形成所述凸起结构；或者，
    图形化所述玻璃基板一侧的表面，形成所述凸起结构。
  10. 一种显示面板，通过权利要求1-9任一所述的显示面板的制备方法形成。
PCT/CN2023/094107 2022-05-13 2023-05-15 显示面板的制备方法及显示面板 WO2023217285A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010244766A (ja) * 2009-04-02 2010-10-28 Toshiba Mobile Display Co Ltd 有機ｅｌ表示装置
CN206134686U (zh) * 2016-01-28 2017-04-26 信利（惠州）智能显示有限公司 一种amoled显示面板结构
CN109585462A (zh) * 2019-01-23 2019-04-05 京东方科技集团股份有限公司 一种阵列基板及其制作方法、柔性显示面板、拼接屏
CN110112171A (zh) * 2019-05-21 2019-08-09 京东方科技集团股份有限公司 一种显示面板的制作方法及显示面板
CN110998847A (zh) * 2019-05-13 2020-04-10 京东方科技集团股份有限公司 阵列基板、显示设备和制造阵列基板的方法
CN113066836A (zh) * 2021-03-19 2021-07-02 京东方科技集团股份有限公司 显示面板及显示装置
CN115036275A (zh) * 2022-05-13 2022-09-09 华南理工大学 一种显示面板的制备方法及显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010244766A (ja) * 2009-04-02 2010-10-28 Toshiba Mobile Display Co Ltd 有機ｅｌ表示装置
CN206134686U (zh) * 2016-01-28 2017-04-26 信利（惠州）智能显示有限公司 一种amoled显示面板结构
CN109585462A (zh) * 2019-01-23 2019-04-05 京东方科技集团股份有限公司 一种阵列基板及其制作方法、柔性显示面板、拼接屏
CN110998847A (zh) * 2019-05-13 2020-04-10 京东方科技集团股份有限公司 阵列基板、显示设备和制造阵列基板的方法
CN110112171A (zh) * 2019-05-21 2019-08-09 京东方科技集团股份有限公司 一种显示面板的制作方法及显示面板
CN113066836A (zh) * 2021-03-19 2021-07-02 京东方科技集团股份有限公司 显示面板及显示装置
CN115036275A (zh) * 2022-05-13 2022-09-09 华南理工大学 一种显示面板的制备方法及显示面板

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