WO2021147039A1 - 驱动背板及其制备方法、显示面板、显示装置 - Google Patents

驱动背板及其制备方法、显示面板、显示装置 Download PDF

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Publication number
WO2021147039A1
WO2021147039A1 PCT/CN2020/073910 CN2020073910W WO2021147039A1 WO 2021147039 A1 WO2021147039 A1 WO 2021147039A1 CN 2020073910 W CN2020073910 W CN 2020073910W WO 2021147039 A1 WO2021147039 A1 WO 2021147039A1
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Prior art keywords
flexible substrate
passivation layer
layer
connection terminal
via hole
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PCT/CN2020/073910
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English (en)
French (fr)
Inventor
杨维
王珂
狄沐昕
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/280,387 priority Critical patent/US20220115572A1/en
Priority to EP20864304.9A priority patent/EP4095911A4/en
Priority to PCT/CN2020/073910 priority patent/WO2021147039A1/zh
Priority to CN202080000069.8A priority patent/CN113632232A/zh
Publication of WO2021147039A1 publication Critical patent/WO2021147039A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • This application relates to the field of display technology, and in particular to a driving backplane and a manufacturing method thereof, a display panel, and a display device.
  • the application discloses a driving backplane and a preparation method thereof, a display panel, and a display device, with the purpose of improving the structure of the TPV driving backplane and increasing the yield rate of the TPV driving backplane.
  • a drive backplane includes:
  • a flexible substrate, the flexible substrate is provided with a first via
  • the first passivation layer is located on one side of the flexible substrate; the first passivation layer is provided with a second via hole, and the orthographic projection of the second via hole on the flexible substrate corresponds to the The orthographic projections of the first vias on the flexible substrate at least partially overlap;
  • a thin film transistor located on the side of the flexible substrate away from the first passivation layer;
  • the electrical connection structure includes a signal trace and a connection terminal;
  • the connection terminal is located on the side of the flexible substrate close to the first passivation layer, and includes located between the flexible substrate and the first passivation layer
  • the first part between the middle and the second part located in the second via hole, and the orthographic projection of the second via hole on the flexible substrate is located on the orthographic projection of the connection terminal on the flexible substrate
  • the signal wiring is located on the side of the flexible substrate away from the first passivation layer, is electrically connected to the thin film transistor, and is electrically connected to the connection terminal through the first via hole.
  • the orthographic projection of the first via on the flexible substrate is located within the orthographic projection of the second via on the flexible substrate.
  • the drive backplane also includes:
  • the conductive structure is located on the side of the connection terminal away from the flexible substrate and is electrically connected to the connection terminal.
  • the drive backplane also includes:
  • the integrated circuit chip is located on the side of the first passivation layer away from the flexible substrate, and is bonded and connected to the conductive structure.
  • the conductive structure is located on a side of the first passivation layer away from the flexible substrate, and the orthographic projection of the connection terminal on the flexible substrate is located on the conductive structure on the flexible substrate. In the orthographic projection on the bottom.
  • the conductive structure is a corrosion-resistant conductive material.
  • the material of the conductive structure includes ITO, IZO, Mo, MoNb, and Ti.
  • the first passivation layer has a stacked structure of SiOx and SiNx; wherein the SiNx layer is close to the flexible substrate, and the SiOx layer is far away from the flexible substrate.
  • the material of the first passivation layer includes SiN, SiON, and SiOx.
  • the edge contour of the first passivation layer is substantially aligned with the edge contour of the flexible substrate.
  • the material of the connecting terminal is Ti/Al/Ti.
  • the drive backplane further includes a second passivation layer located between the flexible substrate and the connection terminals, the second passivation layer is provided with a third via hole, and the third via hole is connected to the The first via is stacked, and the signal trace is electrically connected to the connection terminal through the first via and the third via;
  • the size of the third via hole opening toward the connecting terminal side is smaller than the size of the connecting terminal side surface facing the third via hole.
  • a method for preparing a driving backplane includes the following steps:
  • An electrical connection structure, a flexible substrate, and a thin film transistor are prepared on the first passivation layer, a first via is formed in the flexible substrate, and the orthographic projection of the first via on the flexible substrate At least partially overlap with the orthographic projection of the second via on the flexible substrate;
  • the electrical connection structure includes signal traces and connection terminals, and the connection terminals are located on the flexible substrate close to the first blunt
  • One side of the chemical layer includes a first part located between the flexible substrate and the first passivation layer and a second part located in the second via hole, and the second via hole is located in the
  • the orthographic projection on the flexible substrate is located within the orthographic projection of the connection terminal on the flexible substrate;
  • the signal trace is located on the side of the flexible substrate away from the first passivation layer, and is connected to the
  • the thin film transistor is electrically connected, and is electrically connected to the connection terminal through the first via hole.
  • the method before forming the first passivation layer, the method further includes:
  • the forming of the first passivation layer specifically includes:
  • the method further includes:
  • the sacrificial layer is sacrificed to peel off the rigid substrate.
  • the method further includes:
  • An integrated circuit chip is bound on a side of the first passivation layer away from the flexible substrate, and the integrated circuit chip is electrically connected to the connection terminal through the second via hole.
  • the preparing an electrical connection structure, a flexible substrate, and a thin film transistor on the first passivation layer specifically includes:
  • Signal traces and thin film transistors are prepared on the flexible substrate.
  • the preparing a connection terminal on the first passivation layer specifically includes:
  • a Ti/Al/Ti laminated structure is prepared on the first passivation layer, and a dry etching process is used to form the pattern of the connection terminal.
  • the method before forming the first passivation layer, the method further includes:
  • the forming of the first passivation layer specifically includes:
  • a passivation material layer is deposited, and a dry etching process is used to form the second via hole on the passivation material layer.
  • the orthographic projection of the second via hole on the flexible substrate is located in the conductive structure on the flexible substrate. Within the orthographic projection on the substrate.
  • the forming the first passivation layer specifically includes:
  • the passivation material layer including one or more of SiN, SiON, and SiOx;
  • the passivation material layer is wet-etched with an HF etching solution to form the second via hole.
  • a display device includes any of the above-mentioned driving backplanes and display elements.
  • FIG. 1 is a schematic cross-sectional structure diagram of a driving backplane provided by an embodiment of the application
  • FIG. 2 is a schematic cross-sectional structure diagram of a driving backplane provided by another embodiment of the application.
  • FIG. 3 is a schematic diagram of a cross-sectional structure of a driving backplane during a peeling process according to an embodiment of the application;
  • FIG. 4 is a schematic diagram of a partial cross-sectional structure of a driving backplane in related technical solutions
  • FIG. 5 is a schematic diagram of a partial cross-sectional structure of a driving backplane provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a partial cross-sectional structure of a driving backplane provided by another embodiment of the application.
  • FIG. 7 is a flow chart of a method for manufacturing a driving backplane according to an embodiment of the application.
  • an embodiment of the present application provides a driving backplane, including:
  • the flexible substrate 1 is provided with a first via 11;
  • the first passivation layer 21 is located on one side of the flexible substrate 1; the first passivation layer 21 is provided with a second via 211, the orthographic projection of the second via 211 on the flexible substrate 1 and the first via 11 The orthographic projections on the flexible substrate 1 at least partially overlap;
  • the thin film transistor 3 is located on the side of the flexible substrate 1 away from the first passivation layer 21;
  • the electrical connection structure includes signal traces and connection terminals 41; the connection terminal 41 is located on the side of the flexible substrate 1 close to the first passivation layer 21, and includes a first part located between the flexible substrate 1 and the first passivation layer 21 411 and the second part 412 located in the second via 211, and the orthographic projection of the second via 211 on the flexible substrate 1 is located in the orthographic projection of the connecting terminal 41 on the flexible substrate 1; signal routing (such as The signal line 51 in FIG. 1 or the signal lines 51 and 52 in FIG. 2) is located on the side of the flexible substrate 1 away from the first passivation layer 21, is electrically connected to the thin film transistor 3, and passes through the first via 11 and The connection terminal 41 is electrically connected.
  • signal routing such as The signal line 51 in FIG. 1 or the signal lines 51 and 52 in FIG. 2
  • the above-mentioned drive backplane is used to bind the connection terminal 41 of the IC 6 on one side of the flexible substrate 1 and pass through the first via 11 on the flexible substrate 1 and the pixel drive circuit on the other side of the flexible substrate 1
  • the thin film transistor 3 in the TFT is electrically connected. Therefore, the drive backplane adopts the via connection (Tough PI Via, TPV) of the substrate to realize the backplane structure in which the IC 6 is bound on the back of the substrate, which can solve the problem that the IC 6 occupies the display The problem of the area, the realization of frameless backplane production.
  • a first passivation layer 21 is provided on the back surface of the flexible substrate 1 (the side where the connection terminal 41 is provided), the first passivation layer 21 is provided with a second via 211, and the connection terminal 41 The bonding connection with the IC 6 is realized through the second via 211.
  • the connection terminal 41 includes a first part 411 and a second part 412. The first part 411 is located between the layer where the flexible substrate 1 is located and the layer where the first passivation layer 21 is located. The periphery of the second via 211 is covered by the first passivation layer 21 to avoid corrosion. Therefore, in the above-mentioned driving backplane, the connecting terminal 41 is not directly exposed to the outside, and its side surface can be effectively protected to prevent oxidation and corrosion, thereby improving the yield of the TPV driving backplane.
  • a sacrificial layer (DBL) 7 is generally formed on the rigid base 10 first, and then the metal structure layer of the connecting terminal 41, the flexible substrate 1, and the pixel driver are sequentially prepared.
  • the sacrificial layer 7 is used to peel off the rigid substrate 10, and the destruction of the sacrificial layer 7 will affect the peeling of the rigid substrate 10.
  • the connecting terminal 41 is directly prepared on the sacrificial layer 7.
  • the connecting terminal 41 preferably adopts a wet etching process instead of dry etching.
  • connection terminal 41 has great restrictions.
  • the driving backplane of the technical solution of the present application as shown in FIG. 3, is provided with a first passivation layer 21 between the connecting terminal 41 and the sacrificial layer 7, and the patterning process of the connecting terminal 41 will not affect the sacrificial layer 7. Therefore, the connection terminal 41 can be formed by any patterning process. For example, when the connection terminal 41 uses a dry etching process, since there is the first passivation layer 21 underneath, the sacrificial layer 7 can be prevented from being etched, so it will not affect Peel to the rigid substrate 10.
  • the sacrificial layer 7 is made of polyimide (PI)-like material, which can be decomposed after high-energy irradiation of the laser lift-off technology (LLO) process, so that the connecting terminal 41 and the flexible substrate 1 The structure is separated from the rigid base 10.
  • PI polyimide
  • the edge contour of the first passivation layer 21 is approximately aligned with the edge contour of the flexible substrate 1, that is, the first passivation layer is a film layer provided with via holes in a local area.
  • the connecting terminal 41 is prepared by the dry etching process, the sacrificial layer 7 under the flexible substrate 1 can be retained, and then in the subsequent peeling process, the flexible substrate 1 and the rigid substrate 10 can be separated from each other. Peel off intact and well.
  • the connecting terminal 41 adopts a metal laminated structure, such as a titanium/aluminum/titanium (Ti/Al/Ti) structure.
  • connection terminal 41 adopts the above-mentioned film material, which can reduce the power consumption of the display product and improve the display effect of the display product.
  • connection terminal 41 can also be other metal materials, such as copper (Cu), in this case, the pattern of the connection terminal 41 is formed by a wet etching process.
  • the driving backplane of the present application further includes an integrated circuit chip (IC) 6, which is located on the side of the first passivation layer 21 away from the flexible substrate 1, and is used for connecting with The terminal 41 is bonded and connected.
  • IC integrated circuit chip
  • the orthographic projection of the first via 11 of the flexible substrate 1 on the flexible substrate 1 is located on the second via 211 of the first passivation layer 21 on the flexible substrate. 1 in the orthographic projection.
  • connection terminal 41 needs to be electrically connected to the thin film transistor 3 in the pixel driving circuit on the other side of the flexible substrate 1 through the first via hole 11, and the orthographic projection of the first via hole 11 is arranged on the orthographic projection of the second via hole 211 Inside, that is, the orthographic projection of the first via hole 11 is positioned within the orthographic projection of the connection terminal 41, so that the thin film transistor 3 in the pixel circuit is overlapped with the connection terminal 41 through the signal wiring.
  • connection terminal 41 is electrically connected to the source and drain electrodes 34 of the thin film transistor (TFT) 3 in the pixel driving circuit through the first via 11, and is between the layer where the connection terminal 41 is located and the source and drain electrode layer of the thin film transistor 3, except
  • the functional structure including the flexible substrate 1 and the pixel driving circuit, such as the active layer 31, the first gate 32, and the second gate 33, may also include a barrier layer (Barrier) 81, a buffer layer (Buffer) 82, and a second gate.
  • the fourth via hole 80 is a through hole that penetrates all the above-mentioned insulating structure layers; the source and drain electrodes 34 of the thin film transistor 3 in the pixel driving circuit are connected to each other through the first via hole 11 and the fourth via hole 80 The terminal 41 is electrically connected.
  • connection terminal 41 and the signal wiring have a one-to-one correspondence relationship, and each connection terminal 41 is electrically connected to the thin film transistor of the pixel driving circuit through a corresponding signal wiring.
  • the signal wiring includes a signal line 51 prepared in the same layer as the source and drain electrodes 34 of the thin film transistor 3.
  • the first via 11 in the flexible substrate 1 and the fourth in the insulating structure layer The via 80 penetrates, and the signal line 51 is overlapped with the connection terminal 41 through the fourth via 80 and the first via 11, so as to realize the electrical connection between the pixel driving circuit and the connection terminal 41.
  • a layer of signal lines 52 can be prepared between any two layers of the flexible substrate 1 and the insulating structure layer, and one end of each signal line 52 passes through a part of the via hole and the source and drain electrodes in the insulating layer.
  • the corresponding signal line 51 in the layer is electrically connected, and the other end is electrically connected to the corresponding connection terminal 41 through a via hole in another part of the insulating layer. That is, the signal wiring includes the signal line 51 and the signal line 52, and the electrical connection between the pixel driving circuit and the connection terminal 41 is realized through the signal line 51 and the signal line 52. For example, as shown in FIG.
  • a layer of signal lines 52 may be prepared between the flexible substrate 1 and the barrier layer (Barrier) 81, each source electrode 341 in the source and drain electrode layers is connected to a corresponding signal line 51, and each Each signal line 51 is overlapped with one end of a corresponding signal line 52 through the fourth via 80. Furthermore, the other end of each signal line 52 passes through the first via 11 of the flexible substrate 1 and the corresponding connection terminal 41. By overlapping, in this way, the electrical connection between the TFT 3 of the pixel driving circuit and the corresponding connection terminal 411 can be realized.
  • a layer of signal lines can also be prepared on the layer where the first gate 32 is located or the layer where the second gate 32 is located, so as to facilitate the overlap between the source and drain electrodes 34 of the TFT 3 and the corresponding connection terminals 411.
  • the principle is the same as above, so I won't repeat it here.
  • pin terminals 42 may be provided on the side of the pixel drive circuit away from the flexible substrate 1, and these pin terminals 42 are used to bind to the cathode and anode electrode pins of the micro LED chip 9. Set connection.
  • the driving backplane of the present application may further include a conductive structure 43 located on the side of the connecting terminal 41 away from the flexible substrate 1 and electrically connected to the connecting terminal 41.
  • each conductive structure 43 is electrically connected to the corresponding connection terminal 41, and the orthographic projection pattern of the conductive structure 43 on the flexible substrate 1 and the orthographic projection pattern of the connection terminal 41 on the flexible substrate 1 may be similar.
  • 43 is used as a bonding contact layer of the connection terminal 41, that is, in the driving backplane of the embodiment of the present application, the IC is specifically bonded and contacted with the conductive structure 43.
  • the conductive structure 43 may be a corrosion-resistant conductive material to avoid corrosion.
  • the material of the conductive structure 43 may include ITO, IZO, Mo, MoNb, Ti, and the like.
  • the conductive structure 43 is located on the side of the first passivation layer 21 away from the flexible substrate 1, and the orthographic projection of the connecting terminal 41 on the flexible substrate 1 is within the orthographic projection of the conductive structure 43 on the flexible substrate 1. That is, the orthographic projection of the conductive structure 43 pattern covers the orthographic projection of the connecting terminal 41 pattern.
  • the passivation layer is generally thicker, and the sacrificial layer is generally thinner.
  • the first passivation layer 21 is about 2000 angstroms
  • the sacrificial layer 7 is about 50 angstroms to 1000 angstroms. Angstroms, when the dry etching process is used for patterning, the etching rate of the sacrificial layer 7 by the dry etching gas is greater than that of the passivation layer. Therefore, when the first passivation layer 21 is dry-etched The dry etching gas (plasma) can easily etch away the sacrificial layer 7 in the second via 211 completely. In this case, as shown in FIG. 4, the connection terminal 41 located at the second via 211 will directly contact the rigid substrate 10. During the peeling process of the rigid substrate 10, the connection terminal 41 cannot be separated from the rigid substrate 10. , Which in turn affects the bonding between the connection terminal 41 and the IC.
  • a conductive structure 43 is prepared on the side of the connecting terminal 41 away from the flexible substrate. That is, after the sacrificial layer 7 is prepared, the conductive structure is first prepared on the sacrificial layer 7 43 pattern, the conductive structure 43 is patterned by a wet etching process, the etching process will not damage the sacrificial layer 7, and then the first passivation layer 21 is deposited, and a second via 211 is formed in the first passivation layer 21, Since the second via 211 is provided at the conductive structure 43, that is, there is the conductive structure 43 under the second via 211, so when the second via 211 is formed by dry etching, etching to the sacrificial layer 7 below can be avoided. That is, the sacrificial layer 7 under the second via hole 211 can be retained, thereby ensuring that the connection terminal 41 and the rigid substrate 10 can be separated well, thereby ensuring the bonding effect of the connection
  • a plurality of connection terminals can be gathered together to form a binding structure, and each binding structure is used to correspond to and bind multiple PIN pins of an integrated circuit chip (IC). Set connection.
  • IC integrated circuit chip
  • the area where a bonding structure is located is called a bonding area (Bonding area).
  • a bonding area In the drive backplane of the present application, there may be multiple bonding areas distributed on the back of the flexible substrate.
  • the connection terminal in each binding area is electrically connected to the driving circuit (TFT) of a part of the pixel, and the IC bound to the connection terminal of the binding area is used for driving This part of the pixels; specifically, the signal trace electrically connected to the connection terminal of the binding area may diverge in a fan shape or a circle with the binding area as the center, and the other end of the signal trace is connected to the corresponding pixel drive circuit .
  • TFT driving circuit
  • the first passivation layer 21 may be a stacked structure of SiOx and SiNx; for example, at this time, a dry etching process may be used to pattern the first passivation layer 21 to form the second via 211 .
  • SiOx Due to the characteristics of the material itself, SiOx is easier to separate from the sacrificial layer 7 than SiNx, and SiNx has better insulation performance than SiOx. Therefore, in the first passivation layer 21, the SiOx layer is far away from the flexible substrate 1 and close to the sacrificial layer. 7. The SiNx layer is close to the flexible substrate 1 and away from the sacrificial layer 7.
  • the material of the first passivation layer 21 may include SiN, SiON, and SiOx.
  • a wet etching process may be used to pattern the first passivation layer 21 to form the second via hole 211.
  • a certain concentration of hydrogen fluoride (HF) etching solution may be used, and a wet etching process may be used.
  • the etching process forms the second via hole 211.
  • the HF etching solution will not damage the sacrificial layer 7. Therefore, even if the conductive structure is not provided, the sacrificial layer 7 under the second via 211 will not be corroded, which can ensure that the connection terminal 41 can It is separated from the rigid substrate 10.
  • the driving backplane of the present application may further include a second passivation layer 22 located between the flexible substrate 1 and the connection terminal 41, and the second passivation layer 22 is provided with a third via 221, the third via 221 is laminated with the first via 11, and the signal wiring is electrically connected to the connection terminal 41 through the first via 11 and the third via 221.
  • the size of the third via hole 221 opening toward the connecting terminal 41 is smaller than the size of the surface of the connecting terminal 41 facing the third via hole 221; in this way, the side surface of the connecting terminal 41 and the connecting terminal 41
  • the edge area of the surface on the side of the third via hole 221 will be covered by the second passivation layer 22, that is, the second passivation layer 22 covers the side surface and the surface edge of the second part 412 of the connecting terminal 41, which can avoid
  • the moisture in the material of the flexible substrate 1 and the high temperature heating (OVEN) process cause the connection terminal 41 to be oxidized and corroded.
  • the size of the opening of the third via on the side of the connecting terminal depends on the shape of the opening.
  • the size of the opening is the diameter of the circle
  • the shape of the opening is polygonal
  • the The size of the opening is the diagonal of the polygon.
  • the size of the surface of the connecting terminal facing the third via hole is determined according to the surface shape. For example, when the surface shape is a circle, the size of the surface is the diameter of the circle; when the surface shape is a polygon, the size of the surface is the diameter of the circle. The size of the surface is the diagonal of the polygon.
  • the second passivation layer 22 may be an entire layer structure aligned with the edge of the flexible substrate 1, or as shown in FIG. 1 to FIG. It depends on actual needs.
  • the embodiments of the present application also provide a method for manufacturing the driving backplane. As shown in FIG. 7, the method includes the following steps:
  • Step 101 forming a first passivation layer, and forming a second via hole in the first passivation layer;
  • Step 102 preparing an electrical connection structure, a flexible substrate and a thin film transistor on the first passivation layer, forming a first via in the flexible substrate, the orthographic projection of the first via on the flexible substrate and the second via
  • the orthographic projections on the flexible substrate are at least partially overlapped;
  • the electrical connection structure includes signal traces and connection terminals.
  • the connection terminals are located on the side of the flexible substrate close to the first passivation layer, and include the flexible substrate and the first passivation layer.
  • the first part between and the second part located in the second via hole, and the orthographic projection of the second via hole on the flexible substrate is in the orthographic projection of the connecting terminal on the flexible substrate; the signal traces are located on the flexible substrate
  • the side away from the first passivation layer is electrically connected to the thin film transistor and electrically connected to the connection terminal through the first via hole.
  • the method before step 101, that is, before forming the first passivation layer, the method further includes:
  • a rigid substrate 10 is provided, and a sacrificial layer 7 is formed on the rigid substrate 10.
  • the material of the rigid substrate 10 may be glass, quartz, plastic, polymethyl methacrylate, and other materials.
  • Step 101 forming a first passivation layer, specifically includes: forming a first passivation layer 21 on the sacrificial layer 7.
  • step 102 that is, after preparing the electrical connection structure, the flexible substrate 1 and the thin film transistor 3 on the first passivation layer 21, the method further includes:
  • the sacrificial layer 7 is sacrificed to peel off the rigid substrate 10.
  • a laser lift-off process may be used to decompose the sacrificial layer 7 to separate the rigid substrate 10 and the first passivation layer 21.
  • the following steps may be further included:
  • an integrated circuit chip (IC) 6 is bound on the side of the first passivation layer 21 away from the flexible substrate 1, and the integrated circuit chip 6 is electrically connected to the connection terminal 41 through the second via 211 .
  • preparing an electrical connection structure, a flexible substrate, and a thin film transistor on the first passivation layer may specifically include:
  • a connecting terminal 41 is prepared on the first passivation layer 21; a flexible substrate 1 is prepared on the connecting terminal 41; signal traces are prepared on the flexible substrate 1 (such as the signal in Figure 1).
  • preparing the connection terminal 41 on the first passivation layer 21 may specifically include:
  • a Ti/Al/Ti laminated structure is prepared on the first passivation layer 21, and a dry etching process is used to form a pattern of the connection terminal 41.
  • the resistance of the Ti/Al/Ti metal laminate material is very small, and the connection terminal adopts the above-mentioned film material, which can reduce the power consumption of the display product and improve the display effect of the display product.
  • connection terminal is not limited to Ti/Al/Ti, and can also be other metal materials, such as copper (Cu).
  • the pattern of the connection terminal is formed by a wet etching process.
  • the first passivation layer 21 before forming the first passivation layer 21, it may further include:
  • a conductive material layer is prepared on the sacrificial layer 7, and a pattern of the conductive structure 43 is formed through a patterning process.
  • the conductive structure 43 is a patterned structure and corresponds to the connection terminal 41 one-to-one. Each conductive structure 43 is used as a bonding contact layer corresponding to the connection terminal 41.
  • the orthographic projection pattern on the flexible substrate 1 and the corresponding connection terminal 41 are in contact with each other.
  • the orthographic projection pattern on the flexible substrate 1 can be similar.
  • the conductive structure 43 may be a corrosion-resistant conductive material to avoid corrosion.
  • the material of the conductive structure 43 may specifically include ITO, IZO, Mo, MoNb, Ti, and the like.
  • forming the first passivation layer 21 may specifically include:
  • a passivation material layer is deposited, and a second via 211 is formed on the passivation material layer by a dry etching process.
  • the orthographic projection of the second via 211 on the flexible substrate 1 is located on the conductive structure 43 on the flexible substrate 1 Within the orthographic projection.
  • the passivation material layer may be a stacked structure of SiOx and SiNx; wherein, the SiOx layer is close to the sacrificial layer 7 and the SiNx layer is far away from the sacrificial layer 7.
  • the connecting terminal 41 prepared on the first passivation layer 21 is electrically connected to the conductive structure 43 through the second via 211.
  • the second via 211 is provided at the conductive structure 43, that is, there is the conductive structure 43 under the second via 211, so when the second via 211 is formed by dry etching, etching to the sacrificial layer 7 below can be avoided. That is, the sacrificial layer 7 under the second via hole 211 can be retained, thereby ensuring that the connection terminal 41 can be well separated from the glass substrate 10, thereby ensuring the bonding effect between the connection terminal 41 and the IC.
  • forming the first passivation layer may specifically include:
  • a passivation material layer is deposited, the passivation material layer includes one or more of SiN, SiON, and SiOx; the passivation material layer is wet-etched with an HF etching solution to form the second via hole.
  • the second via hole 211 is formed by etching with an HF etching solution.
  • the HF etching solution will not damage the sacrificial layer 7. Therefore, even if the conductive structure 43 is not provided, the second via The sacrificial layer 7 under 211 will not be corroded either, which can ensure that the connection terminal 41 can be well separated from the glass substrate, thereby ensuring the bonding effect between the connection terminal 41 and the IC.
  • the manufacturing method of the driving backplane may specifically include the following processes:
  • step 201 a sacrificial layer 7 is deposited on the rigid substrate 10.
  • a first passivation layer (PVX1) 21, a connection terminal 41, a second passivation layer (PVX2) 22, a flexible substrate (PI) 1, a barrier layer (Barrier) 81, a buffer layer are sequentially fabricated on the sacrificial layer 7.
  • the material of PVX1 can be SiOx/SiNx
  • the material of PVX2 can be SiNx
  • the barrier material can be SiOx
  • the buffer material can be SiNx/SiOx
  • Active is a patterned structure.
  • GI1 and GI2 materials can be SiNx/SiOx, and Gate1 and Gate2 are patterned structures.
  • Step 204 forming sequentially through the interlayer insulating layer (ILD) 85, the second gate insulating layer (GI2) 84, the first gate insulating layer (GI1) 83, and the buffer layer (Buffer) 82 through 1 to 3 etchings. , The barrier layer (Barrier) 81, the flexible substrate (PI) 1 and the deep holes of the second passivation layer (PVX2) 22 to expose the connection terminals 41.
  • Step 205 forming via holes that sequentially penetrate the interlayer insulating layer (ILD) 85, the second gate insulating layer (GI2) 84 and the first gate insulating layer (GI1) 83 by etching to expose part of the active layer 31 .
  • ILD interlayer insulating layer
  • GI2 second gate insulating layer
  • GI1 first gate insulating layer
  • step 206 source and drain electrodes (SD) 34 are fabricated, and the source and drain electrodes (SD) 34 are respectively overlapped with the active layer 31 and the connection terminal 41.
  • a planarization layer (PLN) 86 is formed on the source and drain electrodes (SD) 34.
  • Step 208 forming pin terminals 42 on the planarization layer (PLN) 86 for bonding with the micro LED chip 9.
  • a passivation layer (PVX) 87 is formed on the pin terminal 42 to prevent the side surface of the pin terminal 42 from being oxidized.
  • a light-shielding layer (BM) 88 is made, which is used to prevent the light emitted by the micro LED chip 9 from reaching the driving circuit array (array) and then being reflected out, which affects the display effect.
  • the light shielding layer 88 has an opening to expose the pin terminals 42 to facilitate the binding and connection of the pin terminals 42 and the micro LED chip 9. The edge of the opening of the light shielding layer 88 can extend to the edge of the pin terminals as much as possible. The area outside the pin terminal 42 is shielded to prevent reflected light from exiting.
  • step 211 the micro LED chip 9 is transferred to the driving backplane, and the micro LED chip 9 is bonded and packaged.
  • step 212 after the above-mentioned driving backplane is manufactured, the rigid base 10 is separated from the upper backplane by using LLO.
  • Step 213 Bonding IC 6 on the back of the drive backplane.
  • an embodiment of the present application also provides a display device, which includes any one of the above-mentioned drive backplanes and display elements.
  • the above-mentioned display device is a TPV display device in which ICs are bound on the back of a flexible substrate, which can solve the problem that the IC occupies the display area and realize the manufacture of a frameless backplane.
  • the connection terminal on the back of the flexible substrate is not exposed, and the side surface of the connection terminal is effectively protected to prevent oxidation and corrosion, thereby improving the yield of the TPV display device.
  • the connection terminals can be either wet etching process or dry etching process. There are many material choices. Specifically, materials with good conductivity can be selected to reduce the performance of the display product. Consumption, improve the display effect of display products.
  • the display element may be a micro LED chip.

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Abstract

一种驱动背板及其制备方法、显示面板、显示装置，目的是改善TPV驱动背板结构，提高TPV驱动背板良率。驱动背板包括：柔性衬底(1)，设有第一过孔(11)；第一钝化层(21)，位于柔性衬底(1)一侧，设有第二过孔(211)，第二过孔(211)的正投影与第一过孔(11)的正投影至少部分重叠；薄膜晶体管(3)，位于柔性衬底(1)背离第一钝化层(21)的一侧；电连接结构，包括信号走线和连接端子(41)；连接端子(41)位于柔性衬底(1)靠近第一钝化层(21)的一侧，包括位于柔性衬底(1)和第一钝化层(21)之间的第一部分(411)以及位于第二过孔(211)内的第二部分(412)，且第二过孔(211)的正投影位于连接端子(41)的正投影内；信号走线位于柔性衬底(1)背离第一钝化层(21)的一侧，与薄膜晶体管(3)电连接、且通过第一过孔(11)与连接端子(41)电连接。

Description

驱动背板及其制备方法、显示面板、显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种驱动背板及其制备方法、显示面板、显示装置。
背景技术
近些年，随着显示产品的快速发展，Micro-LED显示产品已成为技术开发的热点。现有Micro-LED产品的集成电路芯片(IC)绑定(Bonding)在屏幕的正面，IC会在显示区域占据一定的面积，导致Micro-LED产品的拼接缝隙较大。针对这一问题，有人提出了一种Trough PI Via(TPV)制作工艺，即直接在柔性衬底(PI)上面制作薄膜晶体管(TFT)，通过柔性衬底(PI)上的通孔连接导线，实现在柔性衬底(PI)的背面Bonding IC，解决IC占据显示区域的问题，同时可以实现无边框的背板制作。但是，这种方法存在一个问题，即用于绑定IC的连接端子(Bonding Pad)金属结构制作在柔性衬底的下面，完全暴露在空气环境下，导致容易被氧化和腐蚀，影响驱动电路良率。
发明内容
本申请公开了一种驱动背板及其制备方法、显示面板、显示装置，目的是改善TPV驱动背板结构，提高TPV驱动背板良率。
为达到上述目的，本申请提供以下技术方案：
一种驱动背板，包括：
柔性衬底，所述柔性衬底上设有第一过孔；
第一钝化层，位于所述柔性衬底的一侧；所述第一钝化层上设有第二过孔，所述第二过孔在所述柔性衬底上的正投影与所述第一过孔在所述柔性衬底上的正投影至少部分重叠；
薄膜晶体管，位于所述柔性衬底背离所述第一钝化层的一侧；
电连接结构，包括信号走线和连接端子；所述连接端子位于所述柔性衬底靠近所述第一钝化层的一侧，包括位于所述柔性衬底和所述第一钝化层之间的第一部分以及位于所述第二过孔内的第二部分，且所述第二过孔在所述柔性衬底上的正投影位于所述连接端子在所述柔性衬底上的正投影内；所述信号走线位于所述柔性衬底背离所述第一钝化层的一侧，与所述薄膜晶体管电连接、且通过所述第一过孔与所述连接端子电连接。
可选的，所述第一过孔在所述柔性衬底上的正投影位于所述第二过孔在所述柔性衬底上的正投影内。
可选的，驱动背板还包括：
导电结构，位于所述连接端子背离所述柔性衬底的一侧，且与所述连接端子电连接。
可选的，驱动背板还包括：
集成电路芯片，位于所述第一钝化层背离所述柔性衬底的一侧，与所述导电结构绑定连接。
可选的，所述导电结构位于所述第一钝化层背离所述柔性衬底的一侧，所述连接端子在所述柔性衬底上的正投影位于所述导电结构在所述柔性衬底上的正投影内。
可选的，所述导电结构为抗腐蚀性导电材料。
可选的，所述导电结构的材料包括ITO、IZO、Mo、MoNb、Ti。
可选的，所述第一钝化层为SiOx和SiNx叠层结构；其中，SiNx层靠近所述柔性衬底，SiOx层远离所述柔性衬底。
可选的，所述第一钝化层的材料包括SiN、SiON、SiOx。
可选的，所述第一钝化层的边缘轮廓与所述柔性衬底的边缘轮廓大致对齐。
可选的，所述连接端子的材料为Ti/Al/Ti。
可选的，驱动背板还包括位于所述柔性衬底和所述连接端子之间的第二钝化层，所述第二钝化层设有第三过孔，所述第三过孔与所述第一过孔层叠， 所述信号走线通过所述第一过孔和第三过孔与所述连接端子电连接；
所述第三过孔朝向所述连接端子一侧开口的尺寸小于所述连接端子朝向所述第三过孔一侧表面的尺寸。
一种驱动背板的制备方法，包括以下步骤：
形成第一钝化层，在所述第一钝化层中形成第二过孔；
在所述第一钝化层上制备电连接结构、柔性衬底和薄膜晶体管，在所述柔性衬底中形成第一过孔，所述第一过孔在所述柔性衬底上的正投影与所述第二过孔在所述柔性衬底上的正投影至少部分重叠；所述电连接结构包括信号走线和连接端子，所述连接端子位于所述柔性衬底靠近所述第一钝化层的一侧，包括位于所述柔性衬底和所述第一钝化层之间的第一部分以及位于所述第二过孔内的第二部分，且所述第二过孔在所述柔性衬底上的正投影位于所述连接端子在所述柔性衬底上的正投影内；所述信号走线位于所述柔性衬底背离所述第一钝化层的一侧，与所述薄膜晶体管电连接、且通过所述第一过孔与所述连接端子电连接。
可选的，所述形成第一钝化层之前，还包括：
提供刚性基底；
在所述刚性基底上形成牺牲层；
所述形成第一钝化层，具体包括：
在所述牺牲层上形成第一钝化层；
所述在所述第一钝化层上制备电连接结构、柔性衬底和薄膜晶体管之后，还包括：
牺牲所述牺牲层，以将所述刚性基底剥离。
可选的，所述将所述刚性基底剥离之后，还包括：
在所述第一钝化层背离所述柔性衬底的一侧绑定集成电路芯片，所述集成电路芯片通过所述第二过孔与所述连接端子电连接。
可选的，所述在所述第一钝化层上制备电连接结构、柔性衬底和薄膜晶体管，具体包括：
在所述第一钝化层上制备连接端子；
在所述连接端子上制备柔性衬底；
在所述柔性衬底上制备信号走线和薄膜晶体管。
可选的，所述在所述第一钝化层上制备连接端子，具体包括：
在所述第一钝化层上制备Ti/Al/Ti层叠结构，并采用干法刻蚀工艺形成所述连接端子的图形。
可选的，所述形成第一钝化层之前，还包括：
在所述牺牲层上制备导电材料层，并通过构图工艺形成导电结构的图形；
所述形成第一钝化层，具体包括：
沉积钝化材料层，并采用干法刻蚀工艺在所述钝化材料层上形成所述第二过孔，所述第二过孔在柔性衬底上的正投影位于所述导电结构在柔性衬底上的正投影内。
可选的，所述形成第一钝化层，具体包括：
沉积钝化材料层，所述钝化材料层包括SiN、SiON、SiOx中的一种或几种材料；
采用HF刻蚀液对所述钝化材料层进行湿法刻蚀、以形成所述第二过孔。
一种显示装置，包括上述任一项所述的驱动背板和显示元件。
附图说明
图1为本申请一实施例提供的一种驱动背板的截面结构示意图；
图2为本申请另一实施例提供的一种驱动背板的截面结构示意图；
图3为本申请实施例提供的一种驱动背板在剥离工艺过程中的截面结构示意图；
图4为相关技术方案中一种驱动背板的部分截面结构示意图；
图5为本申请一实施例提供的一种驱动背板的部分截面结构示意图；
图6为本申请另一实施例提供的一种驱动背板的部分截面结构示意图；
图7为本申请一实施例提供的一种驱动背板的制备方法流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1和图2所示，本申请实施例提供了一种驱动背板，包括：
柔性衬底1，柔性衬底1上设有第一过孔11；
第一钝化层21，位于柔性衬底1的一侧；第一钝化层21上设有第二过孔211，第二过孔211在柔性衬底1上的正投影与第一过孔11在柔性衬底1上的正投影至少部分重叠；
薄膜晶体管3，位于柔性衬底1背离第一钝化层21的一侧；
电连接结构，包括信号走线和连接端子41；连接端子41位于柔性衬底1靠近第一钝化层21的一侧，包括位于柔性衬底1和第一钝化层21之间的第一部分411以及位于第二过孔211内的第二部分412，且第二过孔211在柔性衬底1上的正投影位于连接端子41在柔性衬底1上的正投影内；信号走线(如图1中的信号线51或者如图2中的信号线51、52)位于柔性衬底1背离第一钝化层21的一侧，与薄膜晶体管3电连接、且通过第一过孔11与连接端子41电连接。
上述驱动背板，用于绑定IC 6的连接端子41位于柔性衬底1的一侧、并通过柔性衬底1上的第一过孔11与位于柔性衬底1另一侧的像素驱动电路中的薄膜晶体管3电连接，因此，该驱动背板为采用衬底的过孔连接(Trough PI Via，TPV)实现在衬底背面绑定IC 6的背板结构，从而可以解决IC 6占据显示区域的问题，实现无边框的背板制作。
并且，上述驱动背板，在柔性衬底1的背面(设置连接端子41的一侧)设有第一钝化层21，该第一钝化层21设有第二过孔211，连接端子41通过该第二过孔211实现与IC 6的绑定连接。连接端子41包括第一部分411和第二部分412，第一部分411位于柔性衬底1所在层和第一钝化层21所在层之 间，未暴露在外，不会被腐蚀；第二部分412位于第二过孔211内，其四周被第一钝化层21包覆，可以避免被腐蚀。因此，上述驱动背板中，连接端子41未直接暴露在外，其侧面可以得到有效的保护，防止被氧化和腐蚀，进而可以提高TPV驱动背板的良率。
另外，如图3所示，TPV驱动背板在制作过程中，一般先在刚性基底10上形成牺牲层(DBL)7，然后再依次制备连接端子41金属结构层、柔性衬底1、像素驱动电路(包括TFT 3)，牺牲层7用于将刚性基底10剥离，牺牲层7被破坏则会影响刚性基底10的剥离。相关技术方案中，直接在牺牲层7上制备连接端子41，为了避免制备连接端子41时破坏牺牲层7的表面，连接端子41优先采用湿法刻蚀工艺，而要避免采用干法刻蚀，因此连接端子41的材料选择具有很大的限制。然而，本申请技术方案的驱动背板，如图3所示，在连接端子41与牺牲层7之间设有第一钝化层21，连接端子41的构图过程不会影响到牺牲层7，因此，可以通过任意一种构图工艺形成连接端子41，例如在连接端子41使用干法刻蚀工艺时，由于下方有第一钝化层21，可以避免刻蚀到牺牲层7，因此不会影响到刚性基底10的剥离。
具体的，如图3所示，牺牲层7为类聚酰亚胺(PI)材料，经过激光剥离技术(LLO)过程的高能量照射，可以发生分解，从而使得连接端子41及柔性衬底1结构与刚性基底10之间分离。
一些实施例中，如图3所示，第一钝化层21的边缘轮廓与柔性衬底1的边缘轮廓大致对齐，即第一钝化层为局部区域设置有过孔的膜层。这样，可以在采用干法刻蚀工艺制备连接端子41时，使得柔性衬底1下方的牺牲层7都能够得以保留，进而在后续的剥离工序中，柔性衬底1和刚性基底10之间能够完整良好地剥离。
一些实施例中，连接端子41采用金属叠层的结构，如钛/铝/钛(Ti/Al/Ti)结构。
Ti/Al/Ti金属层叠材料的电阻很小，连接端子41采用上述膜层材料，可以降低显示产品的功耗，改善显示产品的显示效果。
当然，连接端子41的材料也可以是其它金属材料，如铜(Cu)，在这种情况下，连接端子41的图形采用湿法刻蚀工艺形成。
进一步的，如图1和图2所示，本申请的驱动背板还包括集成电路芯片(IC)6，IC 6位于第一钝化层21背离柔性衬底1的一侧，用于与连接端子41绑定连接。
一些实施例中，如图1和图2所示，柔性衬底1的第一过孔11在柔性衬底1上的正投影位于第一钝化层21的第二过孔211在柔性衬底1上的正投影内。
连接端子41需要通过第一过孔11实现与柔性衬底1另一侧的像素驱动电路中的薄膜晶体管3电连接，将第一过孔11的正投影设置于第二过孔211的正投影内，即使得第一过孔11的正投影位于连接端子41的正投影内，从而使像素电路中的薄膜晶体管3通过信号走线与连接端子41之间实现搭接。
具体的，连接端子41通过第一过孔11与像素驱动电路中薄膜晶体管(TFT)3的源漏电极34电连接，在连接端子41所在层与薄膜晶体管3的源漏电极层之间，除了包括柔性衬底1和像素驱动电路的功能结构，例如有源层31、第一栅极32、第二栅极33外，还可以包括阻挡层(Barrier)81，缓冲层(Buffer)82，第一栅极绝缘层(GI1)83，第二栅极绝缘层(GI2)84，层间绝缘层(ILD)85等绝缘结构层，上述所有绝缘结构层中设有一过孔，可以称之为第四过孔80，该第四过孔80为贯穿上述所有绝缘结构层的通孔；则像素驱动电路中薄膜晶体管3的源漏电极34通过第一过孔11和第四过孔80实现与连接端子41电连接。
具体的，连接端子41和信号走线为一一对应的关系，每个连接端子41通过对应的信号走线与像素驱动电路的薄膜晶体管电连接。
示例性的，如图1所示，信号走线包括与薄膜晶体管3的源漏电极34同层制备的信号线51，柔性衬底1中的第一过孔11与绝缘结构层中的第四过孔80贯通，信号线51通过第四过孔80和第一过孔11实现与连接端子41搭接，从而实现像素驱动电路与连接端子41之间的电连接。
或者，示例性的，还可以在柔性衬底1和绝缘结构层中的任意两层之间制备一层信号线52，每条信号线52的一端通过一部分绝缘层中的过孔与源漏电极层中对应的信号线51电连接，另一端通过另一部分绝缘层中的过孔与对应的连接端子41电连接。即信号走线包括信号线51以及信号线52，通过信号线51以及信号线52实现像素驱动电路与连接端子41之间的电连接。例如，如图2所示，可以在柔性衬底1和阻挡层(Barrier)81之间制备一层信号线52，源漏电极层中每个源电极341与对应的信号线51相连，而每个信号线51通过第四过孔80与对应的一条信号线52的一端搭接，进一步地，每个信号线52另一端又通过柔性衬底1的第一过孔11与对应的连接端子41搭接，这样即可以实现像素驱动电路的TFT 3与对应的连接端子411之间的电连接。当然，也可以在第一栅极32所在层或者第二栅极32所在层制备一层信号线，以便于TFT 3的源漏电极34与对应的连接端子411之间的搭接，其搭接原理同上，此处不再赘述。
具体的，如图1和图2所示，在像素驱动电路背离柔性衬底1的一侧可以设有引脚端子42，这些引脚端子42用于与微型LED芯片9的阴阳电极引脚绑定连接。
一些实施例中，如图6所示，本申请的驱动背板还可以包括导电结构43，该导电结构43位于连接端子41背离柔性衬底1的一侧，且与连接端子41电连接。
具体的，每个导电结构43与对应的连接端子41电连接，且导电结构43在柔性衬底1上的正投影图形与连接端子41在柔性衬底1上的正投影图形可以相似，导电结构43用作连接端子41的绑定接触层，即，本申请实施例的驱动背板中，IC具体与导电结构43绑定接触。
具体的，作为连接端子41的绑定接触层，导电结构43可以为抗腐蚀性导电材料，避免被腐蚀。
具体的，导电结构43的材料可以包括ITO、IZO、Mo、MoNb、Ti等。
具体的，导电结构43位于第一钝化层21背离柔性衬底1的一侧，且连 接端子41在柔性衬底1上的正投影位于导电结构43在柔性衬底1上的正投影内，即导电结构43图形的正投影将连接端子41图形的正投影覆盖。
在实际工艺过程中，钝化层一般较厚，而牺牲层一般较薄，例如，具体的，如图4所示，第一钝化层21约为2000埃，牺牲层7为50埃～1000埃，采用干法刻蚀工艺构图时，干刻气体对牺牲层7的刻蚀速率要大于其对钝化层的刻蚀速率，因此，在对第一钝化层21进行干法刻蚀时，干刻气体(plasma)很容易将第二过孔211内的牺牲层7完全刻蚀掉。这种情况下，如图4所示，位于第二过孔211处的连接端子41会直接与刚性基底10接触，在进行刚性基底10剥离工艺时，连接端子41就不能够与刚性基底10分离，进而影响到连接端子41与IC的bonding。
本申请技术方案中，如图5和图6所示，在连接端子41背离柔性衬底的一侧制备有导电结构43，即在制备完成牺牲层7后，先在牺牲层7上制备导电结构43图形，导电结构43采用湿法刻蚀工艺构图，刻蚀过程不会破坏牺牲层7，然后再沉积第一钝化层21，并在第一钝化层21中形成第二过孔211，由于第二过孔211设置在导电结构43处，即第二过孔211下方有导电结构43，因此在采用干法刻蚀形成第二过孔211时，可以避免刻蚀到下方的牺牲层7，即第二过孔211下方的牺牲层7能够得以保留，进而可以保证连接端子41与刚性基底10能够良好分离，从而保证连接端子41与IC的bonding效果。
一些实施例中，本申请的驱动背板中，多个连接端子聚集在一起可以形成一个绑定结构，每个绑定结构用于与一个集成电路芯片(IC)的多个PIN脚对应且绑定连接。
一些实施例中，一个绑定结构所在区域称为一个绑定区(Bonding区)，本申请的驱动背板中，柔性衬底的背面可以分布有多个绑定区，这些绑定区既可以位于显示区内，也可以位于非显示区内；每个绑定区内的连接端子与一部分像素的驱动电路(TFT)对应电连接，与该绑定区的连接端子绑定的IC用于驱动该部分像素；具体的，与该绑定区的连接端子电连接的信号走线可以以该绑定区为中心呈扇形或圆形发散，而信号走线的另一端连接至对应的 像素驱动电路。
一些实施例中，第一钝化层21可以为SiOx和SiNx叠层结构；示例性的，此时可以采用干法刻蚀工艺对第一钝化层21进行构图，以形成第二过孔211。
由于材料本身特性，SiOx相比SiNx，更容易与牺牲层7分离，而SiNx相比SiOx，绝缘性能更好，因此，第一钝化层21中，SiOx层远离柔性衬底1，靠近牺牲层7，SiNx层靠近柔性衬底1，远离牺牲层7。
另一些实施例中，第一钝化层21的材料可以包括SiN、SiON、SiOx。示例性的，此时可以采用湿法刻蚀工艺对第一钝化层21进行构图，以形成第二过孔211，具体可以使用一定浓度的氟化氢(HF)刻蚀药液，通过湿法刻蚀工艺形成第二过孔211。如图3所示，HF刻蚀药液不会对牺牲层7造成损伤，因此，即使不设置导电结构，第二过孔211下方的牺牲层7也不会被腐蚀，可以确保连接端子41能够与刚性基底10分离。
一些实施例中，如图1至图3、图6所示，本申请的驱动背板还可以包括位于柔性衬底1和连接端子41之间的第二钝化层22，第二钝化层22设有第三过孔221，第三过孔221与第一过孔11层叠，信号走线通过第一过孔11和第三过孔221与连接端子41电连接。
具体的，如图6所示，第三过孔221朝向连接端子41一侧开口的尺寸小于连接端子41朝向第三过孔221一侧表面的尺寸；这样，连接端子41的侧面以及连接端子41朝向第三过孔221一侧的表面的边缘区域会被第二钝化层22所覆盖，即第二钝化层22将连接端子41第二部分412的侧面和表面边缘包覆，可以避免在后续工艺中，柔性衬底1材料中的水气和高温加热(OVEN)工艺导致连接端子41发生氧化和腐蚀。具体的，第三过孔朝向连接端子一侧开口的尺寸，根据开口的形状而定，例如，开口形状为圆形时，该开口的尺寸即为圆形的直径，开口形状为多边形时，该开口的尺寸即为多边形的对角线。同理，连接端子朝向第三过孔一侧表面的尺寸则根据表面形状而定，例如当表面形状为圆形时，该表面的尺寸即为圆形的直径；当表面形状为多边形时，该表面的尺寸即为多边形的对角线。
具体的，第二钝化层22可以是与柔性衬底1边缘对齐的整层结构，或者如图1至图3所示，也可以仅覆盖绑定区或仅覆盖连接端子41，具体可以根据实际需求而定。
基于与本申请实施例提供的驱动背板相同的发明构思，本申请实施例还提供了一种驱动背板的制备方法，如图7所示，该方法包括以下步骤：
步骤101，形成第一钝化层，在第一钝化层中形成第二过孔；
步骤102，在第一钝化层上制备电连接结构、柔性衬底和薄膜晶体管，在柔性衬底中形成第一过孔，第一过孔在柔性衬底上的正投影与第二过孔在柔性衬底上的正投影至少部分重叠；电连接结构包括信号走线和连接端子，连接端子位于柔性衬底靠近第一钝化层的一侧，包括位于柔性衬底和第一钝化层之间的第一部分以及位于第二过孔内的第二部分，且第二过孔在柔性衬底上的正投影位于连接端子在柔性衬底上的正投影内；信号走线位于柔性衬底背离第一钝化层的一侧，与薄膜晶体管电连接、且通过第一过孔与连接端子电连接。
一些实施例中，如图3所示，在步骤101之前，即形成第一钝化层之前，还包括：
提供刚性基底10，并在刚性基底10上形成牺牲层7。
具体的，刚性基底10的材质可以为玻璃，石英，塑料，聚甲基丙烯酸甲酯等材质。
步骤101，形成第一钝化层，具体包括：在牺牲层7上形成第一钝化层21。
在步骤102之后，即在第一钝化层21上制备电连接结构、柔性衬底1和薄膜晶体管3之后，还包括：
牺牲牺牲层7，以将刚性基底10剥离。
具体可以采用激光剥离工艺(LLO)将牺牲层7分解，从而将刚性基底10与第一钝化层21之间分离。
一些实施例中，将刚性基底剥离之后，还可以包括以下步骤：
如图1和图2所示，在第一钝化层21背离柔性衬底1的一侧绑定集成电路芯片(IC)6，集成电路芯片6通过第二过孔211与连接端子41电连接。
一些实施例中，在第一钝化层上制备电连接结构、柔性衬底和薄膜晶体管，具体可以包括：
如图1和图2所示，在第一钝化层21上制备连接端子41；在连接端子41上制备柔性衬底1；在柔性衬底1上制备信号走线(如图1中的信号线51或者如图2中的信号线51、52)和薄膜晶体管3。
示例性的，如图1和图2所示，在第一钝化层21上制备连接端子41，具体可以包括：
在第一钝化层21上制备Ti/Al/Ti层叠结构，并采用干法刻蚀工艺形成连接端子41的图形。
Ti/Al/Ti金属层叠材料的电阻很小，连接端子采用上述膜层材料，可以降低显示产品的功耗，改善显示产品的显示效果。
当然，连接端子的材料并不限于Ti/Al/Ti，也可以是其它金属材料，如铜(Cu)，此时，连接端子的图形采用湿法刻蚀工艺形成。
一些实施例中，如图5和图6所示，在形成第一钝化层21之前，还可以包括：
在牺牲层7上制备导电材料层，并通过构图工艺形成导电结构43的图形。
导电结构43为图形化结构，与连接端子41一一对应，每个导电结构43用作于对应连接端子41的绑定接触层，在柔性衬底1上的正投影图形与对应连接端子41在柔性衬底1上的正投影图形可以相似。
具体的，作为连接端子41的绑定接触层，导电结构43可以为抗腐蚀性导电材料，避免被腐蚀。导电结构43的材料具体可以包括ITO、IZO、Mo、MoNb、Ti等。
进一步的，如图5和图6所示，形成第一钝化层21，具体可以包括：
沉积钝化材料层，并采用干法刻蚀工艺在钝化材料层上形成第二过孔211，第二过孔211在柔性衬底1上的正投影位于导电结构43在柔性衬底1上的正 投影内。
具体的，钝化材料层可以为SiOx和SiNx叠层结构；其中，SiOx层靠近牺牲层7，SiNx层远离牺牲层7。
具体的，如图5和图6所示，后续在第一钝化层21上制备的连接端子41通过第二过孔211与导电结构43电连接。
由于第二过孔211设置在导电结构43处，即第二过孔211下方有导电结构43，因此在采用干法刻蚀形成第二过孔211时，可以避免刻蚀到下方的牺牲层7，即第二过孔211下方的牺牲层7能够得以保留，进而可以保证连接端子41处与玻璃基底10能够良好分离，从而保证连接端子41与IC的bonding效果。
另一些实施例中，形成第一钝化层，具体可以包括：
沉积钝化材料层，钝化材料层包括SiN、SiON、SiOx中的一种或几种材料；采用HF刻蚀液对钝化材料层进行湿法刻蚀、以形成第二过孔。
如图5和图6所示，采用HF刻蚀液刻蚀形成第二过孔211，HF刻蚀药液不会对牺牲层7造成损伤，因此，即使不设置导电结构43，第二过孔211下方的牺牲层7也不会被腐蚀，可以确保连接端子41能够与玻璃基板良好分离，从而保证连接端子41与IC的bonding效果。
一些实施例中，如图1至图3所示，驱动背板的制备方法，具体可以包括以下流程：
步骤201，在刚性基底10上沉积牺牲层7。
步骤202，在牺牲层7上依次制作第一钝化层(PVX1)21、连接端子41、第二钝化层(PVX2)22、柔性衬底(PI)1、阻挡层(Barrier)81、缓冲层(Buffer)82、有源层(Active)31。其中，PVX1的材料可以选择SiOx/SiNx，PVX2的材料选择SiNx，Barrier材料选择SiOx，Buffer材料选择SiNx/SiOx，Active为图案化结构。
步骤203，依次制作第一栅极绝缘层(GI1)83、第一栅极(Gate1)32、第二栅极绝缘层(GI2)84、第二栅极(Gate2)33和层间绝缘层(ILD)85。 其中，GI1和GI2材料可以为SiNx/SiOx，Gate1和Gate2为图案化结构。
步骤204，通过1～3次刻蚀形成依次贯穿层间绝缘层(ILD)85、第二栅极绝缘层(GI2)84、第一栅极绝缘层(GI1)83、缓冲层(Buffer)82、阻挡层(Barrier)81、柔性衬底(PI)1和第二钝化层(PVX2)22的深孔，以露出连接端子41。
步骤205，通过刻蚀形成依次贯穿层间绝缘层(ILD)85、第二栅极绝缘层(GI2)84和第一栅极绝缘层(GI1)83的过孔、以露出部分有源层31。
步骤206，制作源漏电极(SD)34，源漏电极(SD)34分别与有源层31和连接端子41搭接。
步骤207，在源漏电极(SD)34上制作平坦化层(PLN)86。
步骤208，在平坦化层(PLN)86上制作引脚端子42，用于与微型LED芯片9做Bonding。
步骤209，在引脚端子42上制作一层钝化层(PVX)87，以防止引脚端子42的侧面被氧化。
步骤210，制作遮光层(BM)88，作用是防止微型LED芯片9发出的光照到驱动电路阵列(array)再被反射出去，影响显示效果。具体的，遮光层88具有开口，以暴露出引脚端子42，便于引脚端子42与微型LED芯片9的绑定连接，遮光层88的开口边沿可以延伸至引脚端子的边缘，以尽可能将引脚端子42以外的区域遮挡，避免有反射光出射。
步骤211，将微型LED芯片9转移至驱动背板上，并将微型LED芯片9绑定(Bonding)和封装(Packaging)。
步骤212，制作完上述驱动背板后，采用LLO将刚性基底10与上面的背板分离。
步骤213，在驱动背板的背面Bonding IC 6。
另外，本申请实施例还提供一种显示装置，该显示装置包括上述任一项的驱动背板和显示元件。
上述显示装置为在柔性衬底背面绑定IC的TPV显示装置，可以解决IC 占据显示区域的问题，实现无边框的背板制作。并且，上述显示装置中，在柔性衬底背面的连接端子并未裸露在外，连接端子的侧面得到了有效的保护，可以防止被氧化和腐蚀，进而可以提高TPV显示装置的良率。另外，本申请技术方案的显示装置，连接端子既可以使用湿法刻蚀工艺，也可以使用干法刻蚀工艺，材料选择性很多，具体可以选择导电性好的材料，以降低显示产品的功耗，改善显示产品的显示效果。
具体的，本申请的显示装置中，显示元件可以为微型LED芯片。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (17)

  1. 一种驱动背板，包括：
    柔性衬底，所述柔性衬底上设有第一过孔；
    第一钝化层，位于所述柔性衬底的一侧；所述第一钝化层上设有第二过孔，所述第二过孔在所述柔性衬底上的正投影与所述第一过孔在所述柔性衬底上的正投影至少部分重叠；
    薄膜晶体管，位于所述柔性衬底背离所述第一钝化层的一侧；
    电连接结构，包括信号走线和连接端子；所述连接端子位于所述柔性衬底靠近所述第一钝化层的一侧，包括位于所述柔性衬底和所述第一钝化层之间的第一部分以及位于所述第二过孔内的第二部分，且所述第二过孔在所述柔性衬底上的正投影位于所述连接端子在所述柔性衬底上的正投影内；所述信号走线位于所述柔性衬底背离所述第一钝化层的一侧，与所述薄膜晶体管电连接、且通过所述第一过孔与所述连接端子电连接。
  2. 如权利要求1所述的驱动背板，其中，所述第一过孔在所述柔性衬底上的正投影位于所述第二过孔在所述柔性衬底上的正投影内。
  3. 如权利要求1所述的驱动背板，其中，还包括：
    导电结构，位于所述连接端子背离所述柔性衬底的一侧，且与所述连接端子电连接。
  4. 如权利要求3所述的驱动背板，其中，还包括：
    集成电路芯片，位于所述第一钝化层背离所述柔性衬底的一侧，与所述导电结构绑定连接。
  5. 如权利要求3所述的驱动背板，其中，所述导电结构位于所述第一钝化层背离所述柔性衬底的一侧，所述连接端子在所述柔性衬底上的正投影位于所述导电结构在所述柔性衬底上的正投影内。
  6. 如权利要求3-5任一项所述的驱动背板，其中，所述导电结构为抗腐蚀性导电材料。
  7. 如权利要求6所述的驱动背板，其中，所述导电结构的材料包括ITO、IZO、Mo、MoNb、Ti。
  8. 如权利要求1-5任一项所述的驱动背板，其中，所述第一钝化层为SiOx和SiNx叠层结构；其中，SiNx层靠近所述柔性衬底，SiOx层远离所述柔性衬底。
  9. 如权利要求1-5任一项所述的驱动背板，其中，还包括位于所述柔性衬底和所述连接端子之间的第二钝化层，所述第二钝化层设有第三过孔，所述第三过孔与所述第一过孔层叠，所述信号走线通过所述第一过孔和第三过孔与所述连接端子电连接；
    所述第三过孔朝向所述连接端子一侧开口的尺寸小于所述连接端子朝向所述第三过孔一侧表面的尺寸。
  10. 一种驱动背板的制备方法，包括以下步骤：
    形成第一钝化层，在所述第一钝化层中形成第二过孔；
    在所述第一钝化层上制备电连接结构、柔性衬底和薄膜晶体管，在所述柔性衬底中形成第一过孔，所述第一过孔在所述柔性衬底上的正投影与所述第二过孔在所述柔性衬底上的正投影至少部分重叠；所述电连接结构包括信号走线和连接端子，所述连接端子位于所述柔性衬底靠近所述第一钝化层的一侧，包括位于所述柔性衬底和所述第一钝化层之间的第一部分以及位于所述第二过孔内的第二部分，且所述第二过孔在所述柔性衬底上的正投影位于所述连接端子在所述柔性衬底上的正投影内；所述信号走线位于所述柔性衬底背离所述第一钝化层的一侧，与所述薄膜晶体管电连接、且通过所述第一过孔与所述连接端子电连接。
  11. 如权利要求10所述的制备方法，其中，
    所述形成第一钝化层之前，还包括：
    提供刚性基底；
    在所述刚性基底上形成牺牲层；
    所述形成第一钝化层，具体包括：
    在所述牺牲层上形成第一钝化层；
    所述在所述第一钝化层上制备电连接结构、柔性衬底和薄膜晶体管之后，还包括：
    牺牲所述牺牲层，以将所述刚性基底剥离。
  12. 如权利要求11所述的制备方法，其中，所述将所述刚性基底剥离之后，还包括：
    在所述第一钝化层背离所述柔性衬底的一侧绑定集成电路芯片，所述集成电路芯片通过所述第二过孔与所述连接端子电连接。
  13. 如权利要求11所述的制备方法，其中，所述在所述第一钝化层上制备电连接结构、柔性衬底和薄膜晶体管，具体包括：
    在所述第一钝化层上制备连接端子；
    在所述连接端子上制备柔性衬底；
    在所述柔性衬底上制备信号走线和薄膜晶体管。
  14. 如权利要求13所述的制备方法，其中，所述在所述第一钝化层上制备连接端子，具体包括：
    在所述第一钝化层上制备Ti/Al/Ti层叠结构，并采用干法刻蚀工艺形成所述连接端子的图形。
  15. 如权利要求11-14任一项所述的制备方法，其中，
    所述形成第一钝化层之前，还包括：
    在所述牺牲层上制备导电材料层，并通过构图工艺形成导电结构的图形；
    所述形成第一钝化层，具体包括：
    沉积钝化材料层，并采用干法刻蚀工艺在所述钝化材料层上形成所述第二过孔，所述第二过孔在柔性衬底上的正投影位于所述导电结构在柔性衬底上的正投影内。
  16. 如权利要求11-14任一项所述的制备方法，其中，所述形成第一钝化层，具体包括：
    沉积钝化材料层，所述钝化材料层包括SiN、SiON、SiOx中的一种或 几种材料；
    采用HF刻蚀液对所述钝化材料层进行湿法刻蚀、以形成所述第二过孔。
  17. 一种显示装置，包括如权利要求1-9任一项所述的驱动背板和显示元件。
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