WO2021056549A1 - 阵列基板及其制作方法、母板以及显示装置 - Google Patents

阵列基板及其制作方法、母板以及显示装置 Download PDF

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Publication number
WO2021056549A1
WO2021056549A1 PCT/CN2019/109103 CN2019109103W WO2021056549A1 WO 2021056549 A1 WO2021056549 A1 WO 2021056549A1 CN 2019109103 W CN2019109103 W CN 2019109103W WO 2021056549 A1 WO2021056549 A1 WO 2021056549A1
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Prior art keywords
wiring
sub
display area
array substrate
electrode
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PCT/CN2019/109103
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English (en)
French (fr)
Inventor
缪应蒙
张银淑
孙志华
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/109103 priority Critical patent/WO2021056549A1/zh
Priority to US16/965,739 priority patent/US11955491B2/en
Priority to CN201980001855.7A priority patent/CN112888997A/zh
Publication of WO2021056549A1 publication Critical patent/WO2021056549A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133351—Manufacturing of individual cells out of a plurality of cells, e.g. by dicing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels

Definitions

  • the embodiments of the present disclosure relate to an array substrate, a manufacturing method thereof, a motherboard, and a display device.
  • the signal lines in the array substrate are generally configured to provide electrical signals to a plurality of pixel units in the display area.
  • the gate line is configured to provide scan signals to a plurality of pixel units in the display area.
  • a large amount of electric charge may be accumulated on the gate line.
  • an arc arching
  • Defects such as thread breakage.
  • an array substrate has a display area and a non-display area, and includes: a base substrate, a plurality of signal lines arranged on the base substrate, and at least one switch Connecting electrodes, wherein the plurality of signal lines extend from the display area to the non-display area along a first direction, and at least one of the plurality of signal lines includes a first wiring located in the display area And a second trace located in the non-display area, the second trace includes at least two sub traces that are disconnected from each other, wherein the at least two sub traces of the second trace are close to the display
  • the sub-wiring of the area is directly connected to the first wiring, and every two adjacent sub-wirings in the second wiring are electrically connected to each other through the transfer electrode.
  • the first wiring and the second wiring are provided in the same layer relative to the base substrate.
  • the plurality of signal lines are arranged in parallel along a second direction, and the first direction and the second direction intersect;
  • the first sub-wiring includes
  • the extension direction of the part as the fan-out-shaped wiring is a third direction, and the third direction intersects both the first direction and the second direction.
  • the first sub-wiring is connected to the transfer electrode through at least one first via
  • the second sub-wiring is connected through at least one second via. Connected to the transfer electrode.
  • the projection position of the first via on the surface of the base substrate is located at an end of the first sub-wiring away from the display area;
  • the projection position of the second via hole on the board surface of the base substrate is located at an end of the second sub-wiring close to the display area.
  • the multiple signal lines are multiple gate lines
  • the array substrate includes a gate metal layer, at least one insulating layer, and a gate metal layer sequentially disposed on the base substrate.
  • a conductive layer, the gate metal layer includes the plurality of gate lines, the conductive layer includes the at least one via electrode, and both the first via hole and the second via hole penetrate the at least one insulating layer.
  • the array substrate further includes a thin film transistor on the base substrate, wherein the thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain,
  • the gate insulating layer is located between the gate and the active layer
  • the gate metal layer further includes the gate
  • the conductive layer further includes the source and the drain
  • the At least one insulating layer includes the gate insulating layer.
  • the array substrate further includes a thin film transistor, a passivation layer, and a pixel electrode on the base substrate, wherein the thin film transistor includes a gate, a gate insulating layer, and an active layer.
  • the thin film transistor includes a gate, a gate insulating layer, and an active layer.
  • Source and drain the gate insulating layer is located between the gate and the active layer
  • the passivation layer is disposed on the side of the thin film transistor away from the base substrate and includes exposing the A via hole of one of the source electrode and the drain electrode
  • the pixel electrode is disposed on the side of the passivation layer away from the base substrate and passes through the via hole and the source electrode and the drain electrode.
  • the gate metal layer further includes the gate
  • the conductive layer further includes the pixel electrode
  • the pixel electrode is located in the display area
  • the at least one insulating layer includes the gate insulating layer and The stack of passivation layers.
  • a display device comprising: an array substrate, a counter substrate, and a flexible circuit board according to any one of the above embodiments, the counter substrate is boxed with the array substrate, The flexible circuit board is bonded to the array substrate for electrical connection.
  • a motherboard including at least one array substrate unit, the array substrate unit has a display area and a non-display area, and includes: a base substrate, arranged on the base substrate The plurality of signal lines, at least one switching electrode, and the detection line, wherein the plurality of signal lines extend from the display area to the non-display area along the first direction, and at least one of the plurality of signal lines It includes a first wire located in the display area and a second wire located in the non-display area, the second wire includes at least two sub-wires that are disconnected from each other, wherein the second wire Among the at least two sub-wiring lines of the line, the sub-wiring close to the display area is directly connected to the first wiring, and each two adjacent sub-wiring lines in the second wiring are electrically connected to each other through the transfer electrode.
  • the detection line is arranged in the non-display area along a second direction, the detection line is connected to a sub-wiring far away from the display area among at least two sub-wiring lines of the second wiring, the The first direction and the second direction intersect.
  • the second trace includes a first sub trace and a second sub trace that are disconnected from each other, and the first sub trace and the first trace The line is directly connected, and the second sub-line is directly connected to the detection line.
  • the distance between the end of the first sub-wiring away from the display area and the end of the second sub-wiring near the display area is the first The distance, the first distance is greater than or equal to 5 microns and less than or equal to 12 microns.
  • the distance of the transfer electrode in a direction perpendicular to the extending direction of the first sub-line is a second distance, and the second distance is greater than or equal to 35. Micron and less than or equal to 45 microns.
  • the first sub-wiring is connected to the transfer electrode through at least one first via
  • the second sub-wiring is connected through at least one second via. Connected to the transfer electrode.
  • the projection position of the first via on the surface of the base substrate is located at an end of the first sub-wiring away from the display area;
  • the projection position of the second via hole on the board surface of the base substrate is located at an end of the second sub-wiring close to the display area.
  • the plurality of signal lines are a plurality of gate lines
  • the array substrate unit includes a gate metal layer and at least one insulating layer sequentially arranged on the base substrate.
  • a conductive layer the gate metal layer includes the plurality of gate lines
  • the conductive layer includes the at least one via electrode
  • the first via and the second via both penetrate the at least one insulation
  • the projections of the transfer electrode and the at least one first via on the board surface of the base substrate at least partially overlap, and the transfer electrode and the at least one second via are in the The projections on the plate surface of the base substrate at least partially overlap.
  • a method for manufacturing an array substrate includes: providing a base substrate, and forming a multi-layer substrate on the base substrate.
  • Signal lines and at least one switching electrode wherein the plurality of signal lines extend from the display area to the non-display area along the first direction, and at least one of the plurality of signal lines includes The first wiring in the area and the second wiring located in the non-display area, the second wiring includes at least two sub-wiring disconnected from each other, wherein at least two sub-wiring of the second wiring The sub-wiring in the wiring close to the display area is directly connected to the first wiring, and every two adjacent sub-wirings in the second wiring are electrically connected to each other through the switching electrode.
  • forming a plurality of signal lines and at least one transfer electrode on the base substrate includes: sequentially forming a gate metal layer and at least one insulating layer on the base substrate A conductive layer, wherein the plurality of signal lines are a plurality of gate lines, the gate metal layer includes the plurality of gate lines, the conductive layer includes the at least one via electrode, and the at least one insulating layer It includes at least one first via hole and at least one second via hole, the first sub-wiring is connected to the transfer electrode through at least one first via, and the second sub-wiring is connected through at least one second via. The hole is connected to the transfer electrode.
  • the manufacturing method further includes: forming a detection line arranged in a second direction in the non-display area, wherein the detection line and at least two sub-tracks of the second wiring line The sub-wiring at one end of the line away from the display area is connected, and the first direction and the second direction intersect.
  • the manufacturing method according to at least one embodiment of the present disclosure further includes: cutting off the part where the detection line is located from the base substrate.
  • FIG. 1A is a schematic diagram of a process flow of manufacturing an array substrate
  • FIG. 1B is a schematic cross-sectional view of an array substrate manufactured by using the process flow shown in FIG. 1A;
  • FIG. 1C is a top view of an array substrate manufactured by using the process flow shown in FIG. 1A;
  • FIG. 1D is a schematic diagram of an array substrate
  • FIG. 2 is a schematic diagram of an array substrate provided by at least one embodiment of the present disclosure
  • 3A is a schematic diagram of a second wiring provided by at least one embodiment of the present disclosure.
  • 3B is a schematic diagram of another second wiring provided by at least one embodiment of the present disclosure.
  • FIG. 4A is an enlarged schematic diagram corresponding to the part inside the dashed ellipse in FIG. 3A;
  • FIG. 4B is an enlarged schematic diagram corresponding to the part in the dashed ellipse in FIG. 3B;
  • FIG. 5 is a schematic diagram of a motherboard for an array substrate provided by at least one embodiment of the present disclosure
  • FIG. 6A is a schematic diagram of a first sub-wiring line and a second sub-wiring line provided by at least one embodiment of the present disclosure
  • 6B is a schematic diagram of another first sub-wiring and second sub-wiring provided by at least one embodiment of the present disclosure
  • 6C is a schematic diagram of still another first sub-wiring and second sub-wiring provided by at least one embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a via hole and a second via hole provided by at least one embodiment of the present disclosure.
  • FIG. 8A is a schematic cross-sectional view of a display area of an array substrate according to at least one embodiment of the present disclosure
  • FIG. 8B is an example of a cross-sectional view along the dashed line AA′ in FIG. 7;
  • FIG. 8C is an example of a cross-sectional view along the dashed line AA′ in FIG. 7;
  • FIG. 9 is a schematic diagram of a process flow of manufacturing an array substrate according to at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 1A shows a process flow of manufacturing an array substrate
  • FIG. 1B is a schematic cross-sectional view of an array substrate manufactured using the process flow of FIG. 1A.
  • the array substrate can be used in combination with a counter substrate to form a thin film transistor Liquid crystal display (TFT-LCD).
  • TFT-LCD thin film transistor Liquid crystal display
  • FIG. 1A The six process steps shown in FIG. 1A will be described below with reference to the schematic cross-sectional view of the array substrate shown in FIG. 1B.
  • ITO indium tin oxide
  • the base substrate 801 for example, a glass substrate
  • glue, expose, develop and etch for example, wet etching
  • the ITO film that is not protected by the photoresist is etched away, and finally the remaining photoresist on the base substrate 801 is stripped and cleaned to form an ITO film.
  • the ITO film can be It is called the first ITO (1ITO) film layer.
  • a common electrode (VCOM) 802 may be formed in the 1ITO film layer.
  • the gate metal layer includes a gate electrode 803 for the thin film transistor TFT and a gate line (GL) connected to the gate electrode 803, and a common electrode line electrically connected to the common electrode 802 may also be formed.
  • a gate insulating layer (GI) 804 is formed by a deposition process.
  • the material of the gate insulating layer 804 can be silicon nitride, and the active layer 805 is formed by a deposition process.
  • a plasma-enhanced chemical vapor deposition (PECVD) process is used to deposit SiNx, a-Si and n+a-Si three-layer thin films on the base substrate 801 respectively; then, the coating, exposure, development and etching (for example, , Dry etching), the three-layer film that is not protected by the photoresist is etched away, and finally the remaining photoresist on the base substrate 801 is stripped and cleaned, thereby forming the gate insulating layer 804 and the active layer of the thin film transistor TFT 805.
  • PECVD plasma-enhanced chemical vapor deposition
  • the source-drain metal layer includes a source electrode 806 and a drain electrode 807 for the thin film transistor TFT, and a data line (DL) connected to the thin film transistor TFT.
  • a PECVD process is used to form a uniform insulating layer on the base substrate 801; then coating, exposure, development, and etching (for example, dry etching) are carried out in sequence to remove the insulating layer that is not protected by photoresist It is etched away, and finally the remaining photoresist on the base substrate 801 is stripped and cleaned, thereby forming a passivation layer (PVX) 808.
  • the passivation layer 808 is patterned to form a via 811 exposing the drain 807, and the passivation layer 808 also provides a flat surface on the side away from the base substrate, which serves as a flattening layer.
  • the ITO film layer may be called the second ITO (2ITO) film layer.
  • the pixel electrode 809 may be formed in the 2ITO film layer. The pixel electrode 809 is electrically connected to the drain electrode 807 through the via hole 811.
  • the pixel electrode 809 may be a slit electrode, and the common electrode 802 is a plate electrode.
  • the pixel electrode 809 includes a plurality of parts 81 arranged at intervals, and a slit is formed between two adjacent parts of the plurality of parts 81.
  • the electric field generated at the edge of the slit electrode and the electric field generated between the slit electrode and the plate electrode can form a multi-dimensional electric field.
  • FIG. 1C is a top view of an array substrate manufactured by using the process flow shown in FIG. 1A.
  • the array substrate includes a plurality of pixel units PU arranged in an array, and each pixel unit PU includes a thin film transistor TFT.
  • the gate electrode 803 of the thin film transistor TFT and the gate line GL are electrically connected to receive scan signals
  • the source electrode 806 of the thin film transistor TFT is connected to the data line DL to receive data signals
  • the drain electrode 807 is electrically connected to the pixel electrode 809.
  • FIG. 1D is a schematic diagram of a motherboard of an array substrate manufactured by using the above-mentioned process flow.
  • the mother board includes one or more array substrate units. These array substrate units are cut and separated to obtain an array substrate for the subsequent box forming process. Therefore, after the preparation process is completed but before the cutting process, the array substrate unit is not removed. Except for some parts, it has the same structure as the array substrate.
  • the array substrate unit 60 includes a display area 610 (also referred to as an effective display area AA) and a non-display area 620 (also referred to as a peripheral area) surrounding the display area 610.
  • a plurality of gate lines GL are provided in the display area 610 of the array substrate unit 60.
  • the plurality of gate lines GL are configured to provide scanning signals to the gates of the thin film transistors in the plurality of pixel units. .
  • an array test (Array Test) process is required.
  • the purpose is to detect possible defects of the array substrate, such as broken grid lines, All grid shorts can be detected.
  • it is necessary to lead all the gate lines GL in the display area 610 to the non-display area 620, and use a detection line 630 (also referred to as a shorting bar) for short-circuiting.
  • a detection line 630 also referred to as a shorting bar
  • the gate line GL connected to the detection line 630 is also cut accordingly, so that the gate line GL is connected to the end face of the array substrate in the non-display area ( The edges are flush due to cutting.
  • the material of the gate insulating layer is silicon nitride, for example, it can be formed from NH3, SiH4, and N2 through a chemical reaction in a plasma environment.
  • the plasma environment contains a lot of electrons, and the plasma The source is located above the array substrate. Since the gate metal layer is directly exposed to the plasma environment, a large amount of electric charge is easily accumulated on the gate line GL of the display area 610.
  • This charge is conducted along the gate line GL, and when it is conducted to the connection between the gate line GL and the detection line 630 (for example, the line at the connection is at a right angle), the tip discharges easily, causing arching to easily occur at the bend. Phenomenon, the gate line GL may be burnt and breakage and other defects may occur.
  • At least one embodiment of the present disclosure provides an array substrate.
  • the array substrate has a display area and a non-display area, and includes a base substrate, a plurality of signal lines disposed on the base substrate, and at least one transfer electrode.
  • the multiple signal lines extend from the display area to the non-display area along the first direction, at least one of the multiple signal lines includes a first wiring located in the display area and a second wiring located in the non-display area, and the second wiring It includes at least two sub-wires that are disconnected from each other.
  • the sub-wire close to the display area is directly connected to the first wire, and every two adjacent sub-wires in the second wire are directly connected to each other.
  • the individual traces are electrically connected to each other through the transfer electrode.
  • At least one embodiment of the present disclosure also provides a display panel including the above-mentioned array substrate.
  • At least one embodiment of the present disclosure also provides a manufacturing method corresponding to the above-mentioned array substrate.
  • the signal line since the signal line adopts a disconnected design, the charge that may be accumulated on the signal line in the display area when the array substrate is manufactured will not be conducted to other traces, such as It will not be conducted to the detection line, thereby avoiding arcing at the connection between the signal line and other traces in the array substrate, and thereby avoiding defects such as breakage of the signal line.
  • the array substrate 100 has a display area DR and a non-display area PR, and includes a base substrate and a plurality of signal lines arranged on the base substrate 400.
  • the display area DR includes a plurality of pixel units arranged in an array, and each pixel unit includes a thin film transistor TFT, a pixel electrode, a common electrode, and other structures.
  • the signal line 400 in the embodiment of the present disclosure may be a gate line, for example, the gate line is configured to provide a scan signal to the gate of the thin film transistor in the display region DR.
  • the embodiments of the present disclosure include but are not limited thereto.
  • the signal lines 400 in the array substrate 100 provided by the embodiments of the present disclosure may also be signal lines that provide other electrical signals.
  • the plurality of signal lines 400 extend from the display area DR to the non-display area PR along the first direction D1, and at least one of the plurality of signal lines 400 includes a first wiring WL1 located in the display area DR and The second trace WL2 of the non-display area PR.
  • the gate driving circuit or the driving chip provides scanning signals to the gate of the thin film transistor in the display area DR through the gate line; in order not to occupy the space of the display area DR, the gate The driving circuit or the driving chip generally needs to be arranged in the non-display area PR, so the gate line needs to extend from the display area DR to the non-display area PR.
  • the gate line after the gate line extends to the non-display area PR, it needs to be electrically connected to the above-mentioned gate drive circuit or drive chip.
  • the gate drive circuit or drive chip needs to provide a connection port or connection pin for each gate line. Therefore, in order to reduce To reduce the area occupied by the gate drive circuit or drive chip, part of the gate line needs to be set as a fan-out trace, so that multiple gate lines can be gathered together, and then connected to the gate drive circuit or drive chip. connection.
  • the multiple signal lines 400 (for example, gate lines) in the array substrate 100 shown in FIG. 2 are divided into two groups during fan-out wiring.
  • the embodiments of the present disclosure include but are not limited to this.
  • the plurality of signal lines 400 may also not be grouped or divided into more groups during fan-out routing.
  • the signal line 400 needs to be provided with fan-out traces.
  • the three regions through which the signal line 400 extends are called the first region R1 ( That is, the display area DR), the second area R2 (the area where the fan-out wiring is provided), and the third area R3 (the area connected to other signal wiring).
  • the portion of the signal line 400 located in the first region R1 ie, the display region DR
  • the portion of the signal line 400 located in the second region R2 and the third region R3 is called a second wiring WL2.
  • the array substrate is obtained by cutting the mother board (refer to FIG. 5), so that the end surface of the signal line 400 in the third region R3 is flush with the edge of the array substrate (obtained by the cutting).
  • the second wire WL2 includes at least two sub wires SL that are disconnected from each other, and the sub wire SL close to the display area DR among the at least two sub wires SL of the second wire WL2 is directly connected to the first wire WL1 .
  • the base substrate at least two sub-wirings SL that are disconnected from each other included in the second wiring WL2 are located on the same layer, that is, arranged in the same layer.
  • “same-layer arrangement” means that two structural layers are formed in the same layer and the same material in the hierarchical structure. Therefore, in the manufacturing process, the two structural layers can be formed from the same material layer, and The required patterns and structures can be formed through the same patterning process.
  • the second wire WL2 includes two sub wires SL that are disconnected from each other, and the sub wire SL of the two sub wires SL that is close to the display area DR It is directly connected to the first trace WL1; for another example, in other embodiments of the present disclosure, as shown in FIG. 3B, the second trace WL2 includes three sub-traces SL that are disconnected from each other. The sub-line SL close to the display area DR in the SL is directly connected to the first line WL1.
  • FIGS. 3A and 3B schematically show a situation where the second trace WL2 includes two and three disconnected sub traces SL.
  • the embodiments of the present disclosure include but are not limited to this, for example
  • the second wiring WL2 may also include four or more sub-wiring SLs that are disconnected from each other.
  • the embodiment of the present disclosure does not limit the number of the sub-wiring SL included in the second wiring WL2.
  • the array substrate 100 further includes at least one transfer electrode disposed on the base substrate, and every two adjacent sub-wiring lines SL in the second wiring WL2 are electrically connected to each other through the transfer electrode.
  • the adapter electrode is not shown in FIGS. 2, 3A, and 3B.
  • the part in the dashed ellipse in Figure 3A is enlarged and shown in Figure 4A
  • the part in the dashed ellipse in Figure 3B is enlarged and shown in Figure 4B
  • the lines SL are electrically connected to each other through the transfer electrode TE
  • every two adjacent sub-lines SL are electrically connected to each other through the transfer electrode TE, and the three disconnected sub-lines SL need to be provided with two correspondingly Transfer electrode TE.
  • the signal line 400 since the signal line 400 adopts a disconnected design, the charge that may be accumulated on the signal line 400 in the display area DR when the array substrate 100 is manufactured will not be conducted to other circuits.
  • the wire for example, will not be conducted to the detection wire described below, so that an arc can be avoided at the connection between the signal wire 400 and other wires in the array substrate 100, and the signal wire 400 can be prevented from breaking and other defects.
  • some embodiments of the present disclosure provide a motherboard 10 for the above-mentioned array substrate 100, which includes at least one array substrate unit, and each array substrate unit is used to form the above-mentioned array substrate 100 after being cut.
  • the motherboard includes a plurality of array substrate units, these array substrate units are, for example, arranged in an array with multiple rows and multiple columns.
  • FIG. 5 only shows one array substrate unit, the embodiment of the present disclosure is not limited to this. Therefore, after the preparation process is completed but before the cutting process, the array substrate unit has the same structure as the array substrate except for the cut portion, so the following description of the same structure of the array substrate and the array substrate unit may refer to each other.
  • each array substrate unit further includes a detection line TL arranged in the non-display area PR along the second direction D2.
  • the detection line TL is connected to the sub-wiring SL at one end of the plurality of signal lines 400 away from the display area DR, and the first direction D1 and the second direction D2 intersect.
  • the second direction D2 is perpendicular to the first direction D1.
  • the detection line TL may be a detection line TL used to detect the gate line in the aforementioned array test (Array Test) process.
  • Array Test array test
  • the part where the inspection line TL is located needs to be cut off from the array substrate unit corresponding to the array substrate 100, for example, the inspection line TL is cut along the cutting line CL shown in FIG. 5 .
  • the detection line TL used for detection is cut off, so as not to affect the normal operation of the finally manufactured display panel.
  • the end surface of the signal line 400 in the third region R3 is flush with the edge of the array substrate (due to the cutting).
  • the disconnection of the two disconnected sub-wirings included in the second wiring WL2 is located at the junction of the second region R2 and the third region R3.
  • the embodiment of the present disclosure Including but not limited to this situation, the position of the disconnection of the second wiring WL2 may also be located in the second region R2 or in the third region R3.
  • FIGS. 6A, 6B, and 6C Several implementations of the second wiring WL2 will be described below with reference to FIGS. 6A, 6B, and 6C. It should be noted that only a part of the first wiring WL1 and a part of the first wiring WL1 are shown in FIGS. 6A, 6B, and 6C. A part of the detection line TL; in addition, the transfer electrode TE is not shown in FIGS. 5 to 6C.
  • the second trace WL2 includes a first sub trace SL1 and a second sub trace SL2 that are disconnected from each other.
  • the trace SL1 is directly connected to the first trace WL1
  • the second sub trace SL2 is directly connected to the detection line TL.
  • the dotted circles in FIGS. 6A, 6B, and 6C indicate the disconnection between the first sub-line SL1 and the second sub-line SL2 included in the second line WL2.
  • the first sub-line SL1 is a fan-out line
  • the extension direction of the first sub-line SL1 is the third direction D3
  • the third direction D3 is connected to the first The direction D1 and the second direction D2 both intersect, and the extending direction of the second sub-line SL2 is parallel to the first direction D1.
  • the fan-out wiring is to make multiple signal lines 400 gather together, so the direction of the fan-out wiring intersects the first direction D1.
  • the disconnection between the first sub-line SL1 and the second sub-line SL2 included in the second trace WL2 is located at the junction of the second region R2 and the third region R3.
  • the first sub-line SL1 is a fan-out line
  • the extension direction of the first sub-line SL1 is the third direction D3
  • the third direction D3 is the same as the first direction. Both D1 and the second direction D2 intersect.
  • the second sub-line SL2 includes a first portion SL21 extending along the third direction D3 and a second portion SL22 extending along the first direction D1, and the first portion SL21 and the second portion SL22 are directly connected.
  • the disconnection between the first sub-wiring SL1 and the second sub-wiring SL2 included in the second wiring WL2 is located in the second region R2.
  • the first sub-line SL1 includes a first portion SL11 extending along the third direction D3 and a second portion SL12 extending along the first direction D1.
  • the one direction D1 and the second direction D2 both intersect, and the first portion SL11 is a fan-out trace, and the extension direction of the second sub-line SL2 is parallel to the first direction D1.
  • the disconnection between the first sub-wiring SL1 and the second sub-wiring SL2 included in the second wiring WL2 is located in the third region R3.
  • Figure 6A (or 6B or 6C) and the transition electrode TE shown in Figure 7 are enlarged and the part within the circle of the dotted line is shown in Figure 7.
  • the following describes two disconnected sub-wiring (for example, the first sub-wiring with reference to Figure 7).
  • SL1 and the second sub-line SL2) are electrically connected through the transfer electrode TE.
  • the first sub-line SL1 is connected to the transfer electrode TE through at least one first via V1
  • the second sub-line SL2 is connected through at least one second via.
  • the hole V2 is connected to the transition electrode TE.
  • the projection position of the first via hole V1 on the board surface of the base substrate 101 is located at the end of the first sub-line SL1 away from the display area DR; the projection position of the second via hole V2 on the board surface of the base substrate 101 Located at the end of the second sub-line SL2 close to the display area DR.
  • Figure 7 shows four first vias V1 and four first vias V1 are distributed in a square shape.
  • Figure 7 shows four second vias V2 and four second vias V2 are in a square shape. distributed.
  • the embodiments of the present disclosure do not limit the number and distribution positions of the first via holes V1, as long as the first sub-line SL1 and the transition electrode TE can be electrically connected; in addition, the embodiments of the present disclosure The number and distribution positions of the second via holes V2 are not limited, as long as the second sub-wiring SL2 and the transition electrode TE can be electrically connected. The following embodiments are the same as this, and will not be repeated here.
  • the distance between the end of the first sub-line SL1 away from the display area DR and the end of the second sub-line SL2 close to the display area DR is referred to as the first distance DT1.
  • the first distance DT1 in order to reduce the risk that the etching cannot be formed, the first distance DT1 needs to be greater than a certain value; in addition, in order to minimize the increase in resistance caused by the transfer electrode TE to the signal line 400, the first distance DT1 needs to be less than a certain value value.
  • the first distance DT1 is greater than or equal to 5 micrometers ( ⁇ m) and less than or equal to 12 micrometers ( ⁇ m).
  • the first distance DT1 is greater than or equal to 7 microns and less than or equal to 10 microns.
  • the distance of the transfer electrode TE in the direction perpendicular to the extension direction of the first sub-line SL1 is the second distance DT2; since the resistivity of the transfer electrode TE may be relatively large, in order to try To reduce the increase in resistance of the transfer electrode TE to the signal line 400, for example, the second distance DT2 can be greater than or equal to 35 microns and less than or equal to 45 microns; for example, the second distance DT2 is approximately equal to 40 microns. For example, when the second distance DT2 is 40 microns, the on-resistance of the transfer electrode TE is less than 20 ohms ( ⁇ ).
  • FIG. 8A is a schematic cross-sectional view of the display area of the array substrate of at least one embodiment of the present disclosure
  • FIG. 8B is an example of a cross-sectional view along the dashed line AA' in FIG. 7
  • FIG. 8C is a cross-sectional view along the dashed line AA' in FIG. 7
  • the schematic cross-sectional view shown in FIG. 8A corresponds to, for example, the array substrate of FIG. 2 or the array substrate mother board shown in FIG. 5.
  • the signal line 400 is used as a gate line as an example for description.
  • the array substrate includes a plurality of pixel units arranged in an array, and the pixel units include thin film transistors TFT.
  • the thin film transistor TFT includes a gate 103 located on a base substrate 101, a gate insulating layer 121, an active layer 105, a source 106 and a drain 107, and the gate insulating layer 121 is located on the gate 103. And the active layer 105.
  • the pixel unit further includes a common electrode 102, a pixel electrode 109, and a passivation layer 122.
  • the common electrode 102 is disposed on the base substrate and is covered by the gate insulating layer 121.
  • the passivation layer 122 is disposed on the side of the thin film transistor TFT away from the base substrate 101 and includes a via hole 111 exposing one of the source electrode 106 and the drain electrode 107. In the example in the figure, the drain electrode 107 is exposed by the via hole 111.
  • the pixel electrode 109 is arranged on the side of the passivation layer 122 away from the base substrate and is electrically connected to the remaining drain electrode 107 through a via hole.
  • the gate 103 of the thin film transistor TFT is electrically connected to the gate line to receive a scan signal, and the source 106 of the thin film transistor TFT is connected to the data line to receive a data signal.
  • the pixel electrode 109 is a slit electrode, and the common electrode 102 is a plate electrode.
  • the pixel electrode 109 includes a plurality of parts 11, the plurality of parts 11 are arranged at intervals, and a slit is formed between two adjacent parts of the plurality of parts 11.
  • the electric field generated at the edge of the slit electrode and the electric field generated between the slit electrode and the plate electrode can form a multi-dimensional electric field.
  • the material of the active layer may include polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the material of the gate and the gate line may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer (such as titanium, aluminum, and titanium). Three-layer metal stack (Al/Ti/Al)).
  • the material of the source electrode, the drain electrode, and the data line may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer (such as titanium).
  • the embodiments of the present disclosure do not specifically limit the material of each functional layer.
  • the material of the pixel electrode and the common electrode may include a transparent conductive material, such as indium tin oxide (ITO).
  • the array substrate 100 includes a gate metal layer 110, at least one insulating layer 120, and a conductive layer 130 arranged in sequence.
  • the gate metal layer 110 includes a plurality of gate lines and gates, and the conductive layer 130 includes at least one The transfer electrode TE, the first via hole V1 and the second via hole V2 all penetrate through at least one insulating layer 120.
  • the at least one insulating layer 120 is a gate insulating layer 121
  • the conductive layer 130 is a source and drain electrode layer, that is, the transfer electrode TE is in the same layer as the source 106 and drain 107 of the thin film transistor.
  • the transition electrode TE is made of, for example, a metal material.
  • the at least one insulating layer 120 is a gate insulating layer, and the at least one insulating layer 120 is a gate insulating layer 121 and a passivation layer 122.
  • the stacked conductive layer 130 may be a pixel electrode layer, that is, ,
  • the transfer electrode TE and the pixel electrode in the display area are arranged in the same layer.
  • the transfer electrode TE is made of, for example, an ITO material (for example, the 2TIO film layer shown in FIG. 1).
  • the electrode pattern of the transfer electrode TE can be formed by a photolithography process when the conductive layer 130 is formed.
  • the transfer electrode TE does not need to be too large, and the transfer electrode TE is on the surface of the base substrate 101.
  • the embodiment of the present disclosure also provides a method for manufacturing an array substrate, which has a display area and a non-display area.
  • the method includes: providing a base substrate, and forming a plurality of signal lines and at least one transfer electrode on the base substrate.
  • the multiple signal lines extend from the display area to the non-display area along the first direction, at least one of the multiple signal lines includes a first wiring located in the display area and a second wiring located in the non-display area, and the second wiring It includes at least two sub-wires that are disconnected from each other.
  • the sub-wire close to the display area is directly connected to the first wire, and every two adjacent sub-wires in the second wire are directly connected to each other.
  • the individual traces are electrically connected to each other through the transfer electrode.
  • FIG. 9 is a schematic diagram of a process flow of manufacturing an array substrate according to at least one embodiment of the present disclosure.
  • This embodiment corresponds to the embodiment shown in FIG. 8C, for example.
  • the array substrate is formed by a mother board, the mother board includes a plurality of array substrate units, and each array substrate unit is used for cutting to form a separate array substrate.
  • a magnetron sputtering (sputter) process to form a uniform transparent conductive material (such as an indium tin oxide (ITO) film) on the surface of the base substrate 101 (for example, a glass substrate); Exposure, development and etching (for example, wet etching), etch away the ITO film that is not protected by the photoresist, and finally strip and clean the remaining photoresist on the base substrate 101 to form an ITO film, for example
  • This ITO film layer can be referred to as the first ITO (1ITO) film layer.
  • a common electrode (VCOM) 102 may be formed in the 1ITO film layer.
  • the gate metal layer includes a gate 103 for the thin film transistor TFT and a gate line connected to the gate 103, and a common electrode line electrically connected to the common electrode 102 may also be formed.
  • the gate line includes a first wiring WL1 located in the display area and a second wiring WL2 located in the non-display area, and the second wiring WL2 includes at least two sub-wiring SLs that are disconnected from each other.
  • the gate metal layer further includes a detection line TL located in the non-display area, and the detection line TL is electrically connected to one of the at least two sub-wirings SL included in the second wiring WL2 that is far from the display region.
  • the gate insulating layer 121 is formed by a deposition process.
  • the material of the gate insulating layer 121 can be silicon nitride, silicon oxide, silicon oxynitride, etc., and the active layer 105 is formed by a deposition process.
  • a plasma-enhanced chemical vapor deposition (PECVD) process is used to deposit SiNx, a-Si, and n+a-Si three-layer thin films on the base substrate 101 respectively; then, coating, exposure, development, and etching (such as , Dry etching), the three-layer film that is not protected by the photoresist is etched away, and finally the remaining photoresist on the base substrate 101 is stripped and cleaned, thereby forming the gate insulating layer 121 and the active layer of the thin film transistor TFT 105.
  • PECVD plasma-enhanced chemical vapor deposition
  • the source-drain metal layer includes a source 106 and a drain 107 for the thin film transistor TFT, and a data line connected to the thin film transistor TFT.
  • a PECVD process is used to form a uniform insulating layer on the base substrate 101; then, coating, exposure, development, and etching (for example, dry etching) are carried out in sequence to remove the insulating layer that is not protected by photoresist. It is etched away, and finally the remaining photoresist on the base substrate 101 is stripped and cleaned, thereby forming a passivation layer (PVX) 122.
  • the passivation layer 101 is patterned to form the via 111 exposing the drain 107 and the first via V1 and the second via V2 respectively exposing the two sub-wiring SLs of the second wiring.
  • the via 111 passes through the passivation layer 122, and the first via V1 and the second via V2 pass through the stack 120 of the passivation layer 122 and the gate insulating layer 121.
  • the passivation layer 122 also provides a flat surface on the side away from the base substrate and functions as a flattening layer.
  • the ITO film can be called the second ITO (2ITO) film Floor.
  • the pixel electrode 109 and the conversion electrode TE may be formed in the 2ITO film layer.
  • the pixel electrode 109 is electrically connected to the drain electrode 107 through the via hole 111.
  • the conversion electrode TE electrically connects the disconnected sub-wiring SL of the second wiring WL2 through the first via V1 and the second via V2.
  • the above-mentioned process flow of manufacturing the array substrate is not limited to the above-mentioned steps, and can be modified accordingly.
  • the step of forming the common electrode can be performed after the gate metal layer is formed and before the gate insulating layer is formed, or the step of forming the common electrode can be It is performed after the source and drain metal layers are formed and before the passivation layer is formed,..., the embodiment of the present disclosure does not limit this.
  • an example of at least one embodiment of the present disclosure provides a manufacturing method of the array substrate 100.
  • the manufacturing method includes: providing a base substrate 101 and sequentially forming on the base substrate 101 The gate metal layer 110, at least one insulating layer 120, and a conductive layer 130.
  • the array substrate is formed by a mother board including a plurality of array substrate units, and each array substrate unit for forming the array substrate 100 has a display area DR and a non-display area PR.
  • the gate metal layer 110 includes a plurality of gate lines, and further includes a gate of a thin film transistor, a common electrode line, a detection line TL, and the like.
  • the plurality of gate lines extend from the display area DR to the non-display area PR along the first direction D1; at least one of the plurality of gate lines includes a first wiring WL1 located in the display area DR and a second wiring located in the non-display area PR. Line WL2.
  • the conductive layer 130 includes at least one transfer electrode TE.
  • the conductive layer 130 further includes the source and drain of a thin film transistor and a data line, or in another example, the conductive layer 130 further includes a pixel electrode.
  • the second wiring WL2 includes at least two sub-wiring SLs that are disconnected from each other.
  • the sub-wiring SL close to the display area DR in the second wiring WL2 is directly connected to the first wiring WL1, and each phase in the second wiring WL2
  • Two adjacent sub-wires SL are electrically connected to each other through the transfer electrode TE.
  • the gate metal layer 110 further includes a detection line TL arranged in the non-display area PR along the second direction D2, and the detection line TL and the plurality of gate lines
  • the sub-wiring SL at one end far away from the display area DR is connected, and the first direction D1 and the second direction D2 intersect.
  • the second trace WL2 includes a first sub trace SL1 and a second sub trace SL2 that are disconnected from each other, and the first sub trace SL1 and the first trace WL1 is directly contacted and connected, and the second sub-line SL2 and the detection line TL are directly contacted and connected.
  • the first sub-line SL1 is connected to the transfer electrode TE through at least one first via V1
  • the second sub-line SL2 is through at least one second via V2.
  • the first via hole V1 and the second via hole V2 both penetrate through at least one insulating layer 120, and the projection of the transfer electrode TE and the at least one first via hole V1 on the surface of the base substrate 101 is at least Partially overlaps, and the projections of the transfer electrode TE and the at least one second via V2 on the plate surface of the base substrate 101 at least partly overlap.
  • the manufacturing method provided by some embodiments of the present disclosure further includes: cutting the part where the detection line TL is located from the base substrate 101 along a predetermined cutting line CL, thereby obtaining a separate array substrate from the array substrate unit.
  • the detection line TL used for detection is cut off, so as not to affect the normal operation of the finally manufactured display panel.
  • the end surface of the gate line GL in the non-display area is flush with the edge (obtained by cutting) of the array substrate.
  • array substrate 100 for example, it is necessary to fabricate multiple array substrates on a large motherboard first, and then perform a cutting process to form a single array substrate, and then perform a boxing process with the counter substrate, for example.
  • a boxing process with the counter substrate, for example.
  • the cutting process structures that are not needed for subsequent display can be cut off, for example, the inspection line TL used for inspection can be cut off.
  • At least one embodiment of the present disclosure further provides a display device 1.
  • the display device 1 includes any array substrate 100 provided in the embodiments of the present disclosure.
  • the display device 1 is a liquid crystal display device, and includes an array substrate 100 and a counter substrate 200.
  • the array substrate 100 and the counter substrate 200 are opposed to each other to form a liquid crystal cell (double cell), and the liquid crystal cell is filled with a liquid crystal material 300.
  • the counter substrate 200 is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate 100 is used to apply an electric field to control the degree of rotation of the liquid crystal material 300 to perform a display operation.
  • the liquid crystal display device further includes a backlight source 600 that provides a backlight for the array substrate 100.
  • the display device 1 further includes a flexible circuit board 150 and an integrated circuit chip 151 provided on the flexible circuit board 150.
  • the integrated circuit chip 151 may be a control chip or a driver chip or the like.
  • the flexible circuit board including the chips mounted on it can be called COF (Chip On Film) mode.
  • the flexible circuit board is electrically connected to the contact pads provided on the array substrate 100 through a bonding mode, thereby being connected to the contact pads on the array substrate.
  • the signal line is electrically connected.
  • contact pads electrically connected to the gate lines may be provided on the array substrate, thereby electrically connecting with the flexible circuit board provided with the gate driving circuit (gate driving chip), so that the gate driving
  • the circuit can apply scanning signals to the gate lines; for example, contact pads electrically connected to the data lines can also be provided on the array substrate, thereby electrically connecting with the flexible circuit board provided with the data driving circuit (data driving chip) to The data driving circuit can apply the data signal to the data line.
  • the display device 1 in this embodiment can be: liquid crystal panel, liquid crystal TV, display, OLED panel, OLED TV, electronic paper, mobile phone, tablet computer, notebook computer, digital photo frame, navigator, etc. Functional products or components.
  • the display device 1 may also include other conventional components such as a display panel, which is not limited in the embodiment of the present disclosure.

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Abstract

一种阵列基板（100）及其制作方法、母板以及显示装置。阵列基板（100）具有显示区域（DR）和非显示区域（PR），且包括衬底基板、设置在衬底基板上的多条信号线（400）和至少一个转接电极。多条信号线（400）沿第一方向从显示区域（DR）延伸至非显示区域（PR），多条信号线（400）中的至少一条包括位于显示区域（DR）内的第一走线（WL1）和位于非显示区域（PR）的第二走线（WL2），第二走线（WL2）包括至少两个彼此断开的子走线，其中，第二走线（WL2）的至少两个子走线中靠近显示区域（DR）的子走线和第一走线（WL1）直接连接，第二走线（WL2）中每相邻的两个子走线通过转接电极彼此电连接。阵列基板（100）可以改善或避免由于信号线（400）上的电荷累积而造成的断裂等不良。

Description

阵列基板及其制作方法、母板以及显示装置 技术领域
本公开的实施例涉及一种阵列基板及其制作方法、母板以及显示装置。
背景技术
阵列基板中的信号线通常被配置为向显示区域中的多个像素单元提供电信号。例如，栅线被配置为向显示区域中的多个像素单元提供扫描信号。在制作该阵列基板的过程中，该栅线上可能会累积大量电荷，当栅线在延伸时遇到弯折较大的走线时，可能会发生电弧(arching)现象，从而有可能烧毁栅线而发生断裂等不良。
发明内容
根据本公开的至少一实施例提供了一种阵列基板，该阵列基板具有显示区域和非显示区域，且包括：衬底基板、设置在所述衬底基板上的多条信号线和至少一个转接电极，其中，所述多条信号线沿第一方向从所述显示区域延伸至所述非显示区域，所述多条信号线中的至少一条包括位于所述显示区域内的第一走线和位于所述非显示区域的第二走线，所述第二走线包括至少两个彼此断开的子走线，其中，所述第二走线的至少两个子走线中靠近所述显示区域的子走线和所述第一走线直接连接，所述第二走线中每相邻的两个子走线通过所述转接电极彼此电连接。
例如，根据本公开至少一实施例的阵列基板中，所述第一走线和所述第二走线相对于所述衬底基板同层设置。
例如，根据本公开至少一实施例的阵列基板中，所述多条信号线沿第二方向平行设置，所述第一方向和所述第二方向相交；所述第一子走线包括作为扇出形走线的部分，作为扇出形走线的所述部分的延伸方向为第三方向，所述第三方向与所述第一方向以及所述第二方向均相交。
例如，根据本公开至少一实施例的阵列基板中，所述第一子走线通过至少一个第一过孔和所述转接电极连接，所述第二子走线通过至少一个第二过孔和所述转接电极连接。
例如，根据本公开至少一实施例的阵列基板中，所述第一过孔在所述衬底基板的板面上的投影位置位于所述第一子走线远离所述显示区域的一端；所述第二过孔在所述衬底基板的板面上的投影位置位于所述第二子走线靠近所述显示区域的一端。
例如，根据本公开至少一实施例的阵列基板中，所述多条信号线为多条栅线，所述阵列基板包括在所述衬底基板上依次设置的栅金属层、至少一个绝缘层以及导电层，所述栅金属层包括所述多条栅线，所述导电层包括所述至少一个转接电极，所述第一过孔与所述第二过孔均贯穿所述至少一个绝缘层；所述转接电极和所述至少一个第一过孔在所述衬底基板的板面上的投影至少部分重叠，且所述转接电极和所述至少一个第二过孔在所述阵列基板的板面上的投影至少部分重叠。
例如，根据本公开至少一实施例的阵列基板还包括在所述衬底基板上的薄膜晶体管，其中，所述薄膜晶体管包括栅极、栅极绝缘层、有源层、源极和漏极，所述栅极绝缘层位于所述栅极和所述有源层之间，所述栅金属层还包括所述栅极，所述导电层还包括所述源极和所述漏极，所述至少一个绝缘层包括所述栅绝缘层。
例如，根据本公开至少一实施例的阵列基板还包括在所述衬底基板上的薄膜晶体管、钝化层和像素电极，其中，所述薄膜晶体管包括栅极、栅极绝缘层、有源层、源极和漏极，所述栅极绝缘层位于所述栅极和所述有源层之间，所述钝化层设置在所述薄膜晶体管远离所述衬底基板一侧且包括暴露所述源极和所述漏极之一的过孔，所述像素电极设置在所述钝化层远离所述衬底基板一侧且通过所述过孔与所述源极和所述漏极之一电连接，所述栅金属层还包括所述栅极，所述导电层还包括所述像素电极，所述像素电极位于所述显示区，所述至少一个绝缘层包括所述栅绝缘层和所述钝化层的叠层。
根据本公开至少一实施例还提供了一种显示装置，该显示装置包括：根据上述任一实施例的阵列基板、对置基板和柔性电路板，该对置基板与所述阵列基板对盒，该柔性电路板与所述阵列基板邦定以电连接。
根据本公开至少一实施例还提供了一种母板，包括至少一个阵列基板单元，所述阵列基板单元具有显示区域和非显示区域，且包括：衬底基板、设置在所述衬底基板上的多条信号线、至少一个转接电极和检测线，其中，所述多条信号线沿第一方向从所述显示区域延伸至所述非显示区域，所述多条信号 线中的至少一条包括位于所述显示区域内的第一走线和位于所述非显示区域的第二走线，所述第二走线包括至少两个彼此断开的子走线，其中，所述第二走线的至少两个子走线中靠近所述显示区域的子走线和所述第一走线直接连接，所述第二走线中每相邻的两个子走线通过所述转接电极彼此电连接，所述检测线设置在所述非显示区域中沿第二方向，所述检测线和所述第二走线的至少两个子走线中远离所述显示区域的子走线连接，所述第一方向和所述第二方向相交。
例如，根据本公开至少一实施例的母板中，所述第二走线包括彼此断开的第一子走线和第二子走线，所述第一子走线和所述第一走线直接连接，所述第二子走线和所述检测线直接连接。
例如，根据本公开至少一实施例的母板中，所述第一子走线远离所述显示区域的一端和所述第二子走线靠近所述显示区域的一端之间的距离为第一距离，所述第一距离大于等于5微米且小于等于12微米。
例如，根据本公开至少一实施例的母板中，所述转接电极在垂直于所述第一子走线的延伸方向的方向上的距离为第二距离，所述第二距离大于等于35微米且小于等于45微米。
例如，根据本公开至少一实施例的母板中，所述第一子走线通过至少一个第一过孔和所述转接电极连接，所述第二子走线通过至少一个第二过孔和所述转接电极连接。
例如，根据本公开至少一实施例的母板中，所述第一过孔在所述衬底基板的板面上的投影位置位于所述第一子走线远离所述显示区域的一端；所述第二过孔在所述衬底基板的板面上的投影位置位于所述第二子走线靠近所述显示区域的一端。
例如，根据本公开至少一实施例的母板中，所述多条信号线为多条栅线，所述阵列基板单元包括在所述衬底基板上依次设置的栅金属层、至少一个绝缘层以及导电层，所述栅金属层包括所述多条栅线，所述导电层包括所述至少一个转接电极，所述第一过孔与所述第二过孔均贯穿所述至少一个绝缘层；所述转接电极和所述至少一个第一过孔在所述衬底基板的板面上的投影至少部分重叠，且所述转接电极和所述至少一个第二过孔在所述衬底基板的板面上的投影至少部分重叠。
根据本公开至少一实施例还提供了一种阵列基板的制作方法，所述阵列 基板具有显示区域和非显示区域，所述方法包括：提供一衬底基板，以及在所述衬底基板形成多条信号线和至少一个转接电极，其中，所述多条信号线沿第一方向从所述显示区域延伸至所述非显示区域，所述多条信号线中的至少一条包括位于所述显示区域内的第一走线和位于所述非显示区域的第二走线，所述第二走线包括至少两个彼此断开的子走线，其中，所述第二走线的至少两个子走线中靠近所述显示区域的子走线和所述第一走线直接连接，所述第二走线中每相邻的两个子走线通过所述转接电极彼此电连接。
例如，根据本公开至少一实施例的制作方法中，在所述衬底基板形成多条信号线和至少一个转接电极包括：在所述衬底基板上依次形成栅金属层、至少一个绝缘层、导电层，其中，所述多条信号线为多条栅线，所述栅金属层包括所述多条栅线，所述导电层包括所述至少一个转接电极，所述至少一个绝缘层包括至少一个第一过孔和至少一个第二过孔，所述第一子走线通过至少一个第一过孔和所述转接电极连接，所述第二子走线通过至少一个第二过孔和所述转接电极连接。
例如，根据本公开至少一实施例的制作方法还包括：在所述非显示区域中形成沿第二方向设置的检测线，其中，所述检测线和所述第二走线的至少两个子走线中远离所述显示区域的一端的子走线连接，所述第一方向和所述第二方向相交。
例如，根据本公开至少一实施例的制作方法还包括：将所述检测线所在的部分从所述衬底基板上切割掉。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种制作阵列基板的工艺流程示意图；
图1B为采用图1A所示的工艺流程制作的一种阵列基板的截面示意图；
图1C为采用图1A所示的工艺流程制作的一种阵列基板的俯视图；
图1D为一种阵列基板的示意图；
图2为本公开至少一实施例提供的一种阵列基板的示意图；
图3A为本公开至少一实施例提供的一种第二走线的示意图；
图3B为本公开至少一实施例提供的另一种第二走线的示意图；
图4A为对应于图3A中虚线椭圆内的部分放大后的示意图；
图4B为对应于图3B中虚线椭圆内的部分放大后的示意图；
图5为本公开至少一实施例提供的一种用于阵列基板的母板的示意图；
图6A为本公开至少一实施例提供的一种第一子走线和第二子走线的示意图；
图6B为本公开至少一实施例提供的另一种第一子走线和第二子走线的示意图；
图6C为本公开至少一实施例提供的又一种第一子走线和第二子走线的示意图；
图7为本公开至少一实施例提供的一种一过孔和第二过孔的示意图；
图8A为本公开至少一实施例的阵列基板的显示区的截面示意图；
图8B为沿图7中虚线AA'的截面图的一种示例；
图8C为沿图7中虚线AA'的截面图的一种示例；
图9为本公开至少一实施例的制作阵列基板的工艺流程示意图；以及
图10为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接 的。
图1A示出了一种制作阵列基板的工艺流程，图1B为采用图1A的工艺流程制作的一种阵列基板的截面示意图，例如，该阵列基板可以用于与对置基板组合以形成薄膜晶体管液晶显示器(TFT-LCD)。
下面结合图1B所示的阵列基板的截面示意图对图1A所示出的六个工艺步骤进行描述。
首先，例如利用磁控溅射(sputter)工艺在衬底基板801(例如，玻璃衬底)表面形成一层均匀的氧化铟锡(ITO)薄膜；然后依次进行涂胶﹑曝光、显影和刻蚀(例如，湿刻)，将没有受到光刻胶保护的ITO薄膜刻蚀掉，最后将衬底基板801上剩余的光刻胶剥离和清洗，从而形成ITO膜层，例如可以将该ITO膜层称为第一ITO(1ITO)膜层。例如，在1ITO膜层中可以形成公共电极(VCOM)802。
然后，例如利用磁控溅射(sputter)工艺在衬底上形成一层均匀的金属膜层；然后依次进行涂胶﹑曝光、显影和刻蚀(例如，湿刻)，将没有受到光刻胶保护的金属膜层刻蚀掉，最后将衬底上剩余的光刻胶剥离和清洗，从而形成栅金属层。例如，栅金属层包括用于薄膜晶体管TFT的栅极803以及和栅极803连接的栅线(GL)，并且还可以形成与公共电极802电连接的公共电极线。
然后，例如通过沉积工艺形成栅绝缘层(GI)804，例如，栅绝缘层804的材料可以采用氮化硅，以及通过沉积工艺形成有源层805。其中，利用等离子体增强化学气相沉积(PECVD)工艺在衬底基板801上分别沉积SiNx、a-Si以及n+a-Si三层薄膜；然后依次进行涂胶﹑曝光、显影和刻蚀(例如，干刻)，将没有受到光刻胶保护的三层薄膜刻蚀掉，最后将衬底基板801上剩余的光刻胶剥离和清洗，从而形成薄膜晶体管TFT的栅绝缘层804和有源层805。
然后，例如利用磁控溅射工艺在衬底基板801上形成一层均匀的金属膜层；然后依次进行涂胶﹑曝光、显影和刻蚀(例如，湿刻)，将没有受到光刻胶保护的金属膜层刻蚀掉，最后将衬底基板801上剩余的光刻胶剥离和清洗，从而形成源漏金属层(S/D)。例如，源漏金属层包括用于薄膜晶体管TFT的源极806和漏极807，以及连接到薄膜晶体管TFT的数据线(DL)。
然后，例如利用PECVD工艺在在衬底基板801上形成一层均匀的绝缘层；然后依次进行涂胶﹑曝光、显影和刻蚀(例如，干刻)，将没有受到光刻 胶保护的绝缘层刻蚀掉，最后将衬底基板801上剩余的光刻胶剥离和清洗，从而形成钝化层(PVX)808。例如，对钝化层808进行构图以形成暴露漏极807的过孔811，而且钝化层808还在远离衬底基板一侧提供了平坦表面，起到了平坦化层的作用。
然后，例如利用磁控溅射(sputter)工艺在衬底基板801表面形成一层均匀的ITO薄膜；然后依次进行涂胶﹑曝光、显影和刻蚀(例如，湿刻)，将没有受到光刻胶保护的ITO膜刻蚀掉，最后将衬底基板801上剩余的光刻胶剥离和清洗，从而形成ITO膜层，例如可以将该ITO膜层称为第二ITO(2ITO)膜层。例如，在2ITO膜层中可以形成像素电极809。该像素电极809通过过孔811和漏极807电连接。
例如，像素电极809可以是狭缝电极，公共电极802是板状电极。像素电极809包括多个部分81，多个部分81间隔排布，多个部分81中相邻的两个部分之间形成狭缝。狭缝电极边缘所产生的电场以及狭缝电极与板状电极间产生的电场能够形成多维电场。当利用该阵列基板制作得到液晶面板时，使位于狭缝电极间、电极正上方所有取向的液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率。
图1C为采用图1A所示的工艺流程制作的一种阵列基板的俯视图。如图1C所示，该阵列基板包括多个呈阵列排布的像素单元PU，每个像素单元PU包括薄膜晶体管TFT。例如，该薄膜晶体管TFT的栅极803和栅线GL电连接以接收扫描信号，该薄膜晶体管TFT的源极806和数据线DL连接以接收数据信号，漏极807与像素电极809电连接。
例如，图1D为采用上述工艺流程制作的一种阵列基板的母板的示意图。该母板包括一个或多个阵列基板单元，这些阵列基板单元在切割、分离之后得到用于后续成盒工艺的阵列基板，因此，制备工艺完成之后但在切割工艺之前，阵列基板单元除被切除部分之外与阵列基板具有相同结构。如图1D所示，该阵列基板单元60包括显示区域610(又称为有效显示区域AA)和围绕显示区域610的非显示区域620(又可以称为周边区域)。
如图1D所示，在阵列基板单元60的显示区域610中设置有多条栅线GL，例如，该多条栅线GL被配置为向多个像素单元中的薄膜晶体管的栅极提供扫描信号。
在上述制作阵列基板的工艺流程中，为了实现质量监控，在阵列基板制作 完成后，需要进行阵列检测(Array Test)工序，目的是为了检查出可能存在的阵列基板不良，例如，栅线断裂、栅线短路都可以被检测出来。为了进行上述阵列检测工序，需要将显示区域610中的全部栅线GL引出到非显示区域620中，并采用一根检测线630(又可以称为shorting bar)进行短接。在进行阵列检测工序时，只需要在检测线630上施加一个电压(例如，正电压)即可。完成上述阵列检测工序后，例如，在后续的成盒(Cell)阶段之前的切割(Cutting)工序中，沿着预定的切割线CL进行切割，上述用于检测的检测线630被切除，从而不影响最终制作的显示面板正常工作。
如果图1D所示，在进行上述切割工序之后所得到的阵列基板中，与检测线630相连的栅线GL也相应地被切断，由此栅线GL在非显示区的端面与阵列基板的(由于切割所得到的)边缘平齐。
但是，发明人发现在制作上述阵列基板的工艺流程中，可能会存在以下问题。例如，由上述可知，栅绝缘层(GI)的材料为氮化硅，例如，可以由NH3、SiH4、N2在等离子体(Plasma)环境下通过化学反应形成，等离子体环境含有大量电子，且等离子源位于阵列基板上方，由于栅金属层直接暴露在等离子体环境中，大量电荷容易累积到显示区域610的栅线GL上。该电荷沿着栅线GL传导，当传导至栅线GL与检测线630的连接处(例如，连接处的走线呈直角)时，由于尖端放电，导致在弯折处容易发生电弧(arching)现象，从而可能会烧毁栅线GL而发生断裂等不良。
本公开的至少一实施例提供一种阵列基板，该阵列基板具有显示区域和非显示区域，且包括：衬底基板、设置在衬底基板上的多条信号线和至少一个转接电极。多条信号线沿第一方向从显示区域延伸至非显示区域，多条信号线中的至少一条包括位于显示区域内的第一走线和位于非显示区域的第二走线，第二走线包括至少两个彼此断开的子走线，其中，第二走线的至少两个子走线中靠近显示区域的子走线和第一走线直接连接，第二走线中每相邻的两个子走线通过转接电极彼此电连接。
本公开的至少一实施例还提供包括上述阵列基板的显示面板。
本公开的至少一实施例还提供一种对应于上述阵列基板的制作方法。
在本公开的实施例提供的阵列基板中，由于信号线采用断开的设计，所以在制作该阵列基板时位于显示区域中的信号线上可能累积的电荷不会传导至其它走线上，例如不会传导到检测线上，从而可以避免该阵列基板中的信号线 和其它走线的连接处发生电弧，进而可以避免信号线发生断裂等不良。
下面将对一些具体的实施例进行描述，本公开不限于这些实施例，这些实施例中包括的特征在不矛盾的情况下可以相互组合。
本公开至少一实施例提供一种阵列基板100，如图2所示，该阵列基板100具有显示区域DR和非显示区域PR，且包括衬底基板和设置在衬底基板上的多条信号线400。显示区域DR包括多个呈阵列排布的像素单元，每个像素单元包括薄膜晶体管TFT、像素电极、公共电极等结构。需要说明的是，本公开的实施例中的信号线400可以为栅线，例如，该栅线被配置为向显示区域DR中的薄膜晶体管的栅极提供扫描信号。本公开的实施例包括但不限于此，本公开的实施例提供的阵列基板100中的信号线400还可以是提供其它电信号的信号线。
如图2所示，多条信号线400沿第一方向D1从显示区域DR延伸至非显示区域PR，多条信号线400中的至少一条包括位于显示区域DR内的第一走线WL1和位于非显示区域PR的第二走线WL2。
例如，以信号线400为栅线为例进行说明，栅极驱动电路或者驱动芯片通过栅线向显示区域DR中的薄膜晶体管的栅极提供扫描信号；为了不占用显示区域DR的空间，栅极驱动电路或者驱动芯片一般需要设置在非显示区域PR中，所以，栅线需要从显示区域DR延伸至非显示区域PR。另外，栅线延伸至非显示区域PR后需要和上述栅极驱动电路或驱动芯片电连接，栅极驱动电路或驱动芯片需要为每一条栅线设置一个连接端口或连接引脚，所以，为了减小该栅极驱动电路或驱动芯片所占用的面积，栅线的一部分需要被设置为扇出形走线，从而使得多条栅线可以聚拢在一起，然后再和栅极驱动电路或驱动芯片电连接。
需要说明的是，图2所示的阵列基板100中的多条信号线400(例如，栅线)在进行扇出形走线时分成了两组，本公开的实施例包括但不限于此，多条信号线400在进行扇出形走线时也可以不分组或者分成更多个组。
如上所述，信号线400需要设置扇出形走线，如图2所示，在本公开的实施例中，将信号线400在延伸时所经过的三个区域分别称为第一区域R1(即显示区域DR)、第二区域R2(设置扇出形走线的区域)以及第三区域R3(和其它信号走线连接的区域)。另外，将信号线400位于第一区域R1(即显示区域DR)中的部分称为第一走线WL1，将信号线400位于第二区域R2以及第 三区域R3的部分称为第二走线WL2。
该阵列基板为通过对母板进行切割所得到(参考图5)，由此信号线400在第三区域R3的端面与阵列基板的(由于切割所得到的)边缘平齐。
例如，第二走线WL2包括至少两个彼此断开的子走线SL，第二走线WL2的至少两个子走线SL中靠近显示区域DR的子走线SL和第一走线WL1直接连接。
例如，在衬底基板上，第二走线WL2包括的至少两个彼此断开的子走线SL位于同一层，即同层设置。在本公开的实施例中，“同层设置”为两个结构层在层级结构中同层且同材料形成，由此在制备工艺中，该两个结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。
例如，在本公开的一些实施例中，如图3A所示，第二走线WL2包括两个彼此断开的子走线SL，该两个子走线SL中靠近显示区域DR的子走线SL和第一走线WL1直接连接；又例如，在本公开的另一些实施例中，如图3B所示，第二走线WL2包括三个彼此断开的子走线SL，该三个子走线SL中靠近显示区域DR的子走线SL和第一走线WL1直接连接。
需要说明的是，图3A和3B分别示意性地示出了第二走线WL2包括两个和三个彼此断开的子走线SL的情形，本公开的实施例包括但不限于此，例如，第二走线WL2还可以包括四个或更多个彼此断开的子走线SL，本公开的实施例对第二走线WL2包括的子走线SL的个数不作限定。
例如，阵列基板100还包括设置在衬底基板上的至少一个转接电极，第二走线WL2中每相邻的两个子走线SL通过转接电极彼此电连接。需要说明的是，图2、图3A、图3B中并没有示出该转接电极。为了清楚地示意出转接电极，将图3A中虚线椭圆内的部分放大后示于图4A，将图3B中虚线椭圆内的部分放大后示于图4B；如图4A所示，两个子走线SL通过转接电极TE彼此电连接；如图4B所示，每相邻的两个子走线SL通过转接电极TE彼此电连接，三个彼此断开的子走线SL需要对应设置两个转接电极TE。
在本公开的实施例提供的阵列基板100，由于信号线400采用断开的设计，所以在制作该阵列基板100时位于显示区域DR中的信号线400上可能累积的电荷不会传导至其它走线上，例如不会传导到下文中描述的检测线上，从而可以避免该阵列基板100中的信号线400和其它走线的连接处发生电弧，进而可以避免信号线400发生断裂等不良。
如图5所示，本公开的一些实施例提供了用于上述阵列基板100的母板10，包括至少一个阵列基板单元，每个阵列基板单元在切割之后用于形成上述阵列基板100。当该母板包括多个阵列基板单元的情形，这些阵列基板单元例如排列为多行多列的阵列。虽然图5仅示出了一个阵列基板单元，但是本公开的实施例不以此为限。因此，制备工艺完成之后但在切割工艺之前，阵列基板单元除被切除部分之外与阵列基板具有相同结构，因此下面对于阵列基板和阵列基板单元的相同结构的描述可以相互参考。
每个阵列基板单元相比于切割后得到的阵列基板100还包括设置在非显示区域PR中沿第二方向D2设置的检测线TL。例如，检测线TL和多条信号线400中的远离显示区域DR的一端的子走线SL连接，第一方向D1和第二方向D2相交。例如，在本公开的一些实施例中，第二方向D2与第一方向D1垂直。例如，当信号线400为栅线时，检测线TL可以是用于在上述阵列检测(Array Test)工序中对栅线进行检测的检测线TL。例如，在进行阵列检测工序时，只需要在检测线TL上施加一个电压(例如，正电压)即可。
需要说明是，在上述阵列检测工序完成后，需要将检测线TL所在的部分从阵列基板100对应的阵列基板单元上切割掉，例如，沿图5中所示的切割线CL将检测线TL切除。例如，在成盒(Cell)阶段的切割(Cutting)工序中，用于检测的检测线TL被切除，从而不影响最终制作的显示面板正常工作。
由于该切割工序，信号线400在第三区域R3的端面与阵列基板的(由于切割所得到的)边缘平齐。
需要说明的是，如图5所示，第二走线WL2包括的两个彼此断开的子走线的断开处位于第二区域R2和第三区域R3的交界处，本公开的实施例包括但不限于此情形，第二走线WL2的断开处的位置还可以位于第二区域R2中或者位于第三区域R3中。
下面结合图6A、图6B、图6C对第二走线WL2的几个实施方式进行描述，需要说明的是，图6A、图6B、图6C中仅示出了第一走线WL1的一部分和检测线TL的一部分；另外，图5-图6C均为没有示出转接电极TE。
例如，在本公开的一些实施例中，如图6A、图6B、图6C所示，第二走线WL2包括彼此断开的第一子走线SL1和第二子走线SL2，第一子走线SL1和第一走线WL1直接连接，第二子走线SL2和检测线TL直接连接。需要说明的是，图6A、图6B、图6C中虚线圆形标识的即为第二走线WL2包括的 第一子走线SL1与第二子走线SL2的断开处。
例如，如图6A所示，在一些实施例中，第一子走线SL1为扇出形走线，该第一子走线SL1的延伸方向为第三方向D3，第三方向D3与第一方向D1以及第二方向D2均相交，第二子走线SL2的延伸方向与第一方向D1平行。如上所述，扇出形走线是为了使得多条信号线400聚拢在一起，所以扇出形走线的方向和第一方向D1相交。在图6A所示的实施例中，第二走线WL2包括的第一子走线SL1与第二子走线SL2的断开处位于第二区域R2和第三区域R3的交界处。
例如，如图6B所示，在一些实施例中，第一子走线SL1为扇出形走线，第一子走线SL1的延伸方向为第三方向D3，第三方向D3与第一方向D1以及第二方向D2均相交。第二子走线SL2包括沿第三方向D3延伸的第一部分SL21和沿第一方向D1延伸的第二部分SL22，第一部分SL21和第二部分SL22直接连接。在图6B所示的实施例中，第二走线WL2包括的第一子走线SL1与第二子走线SL2的断开处位于第二区域R2中。
例如，如图6C所示，在一些实施例中，第一子走线SL1包括沿第三方向D3延伸的第一部分SL11和沿第一方向D1延伸的第二部分SL12，第三方向D3与第一方向D1以及第二方向D2均相交，且第一部分SL11为扇出形走线，第二子走线SL2的延伸方向与第一方向D1平行。在图6C所示的实施例中，第二走线WL2包括的第一子走线SL1与第二子走线SL2的断开处位于第三区域R3中。
将图6A(或6B或6C)中虚线圆形内的部分放大后以及转接电极TE示于图7，下面结合图7描述两个彼此断开的子走线(例如，第一子走线SL1以及第二子走线SL2)通过转接电极TE实现电连接的实施方式。
例如，如图7所示，在本公开的一些实施例中，第一子走线SL1通过至少一个第一过孔V1和转接电极TE连接，第二子走线SL2通过至少一个第二过孔V2和转接电极TE连接。
例如，第一过孔V1在衬底基板101的板面上的投影位置位于第一子走线SL1远离显示区域DR的一端；第二过孔V2在衬底基板101的板面上的投影位置位于第二子走线SL2靠近显示区域DR的一端。
图7示出了四个第一过孔V1且四个第一过孔V1呈田字形分布，另外，图7示出了四个第二过孔V2且四个第二过孔V2呈田字形分布。
需要说明的是，本公开的实施例对第一过孔V1的数量以及分布位置不作限定，只要可以实现第一子走线SL1和转接电极TE电连接即可；另外，本公开的实施例对第二过孔V2的数量以及分布位置不作限定，只要可以实现第二子走线SL2和转接电极TE电连接即可。以下各实施例与此相同，不再赘述。
例如，如图7所示，将第一子走线SL1远离显示区域DR的一端和第二子走线SL2靠近显示区域DR的一端之间的距离称为第一距离DT1。
考虑到工艺问题，为了降低刻蚀不能形成的风险，第一距离DT1需要大于一定的值；另外，为了尽量降低转接电极TE对信号线400造成的电阻增加，第一距离DT1需要小于一定的值。例如，在本公开的一些实施例中，第一距离DT1大于等于5微米(μm)且小于等于12微米(μm)。
又例如，在本公开的其它一些实施例中，第一距离DT1大于等于7微米且小于等于10微米。
例如，如图7所示，将转接电极TE在垂直于第一子走线SL1的延伸方向的方向上的距离为第二距离DT2；由于转接电极TE的电阻率可能较大，为了尽量降低转接电极TE对信号线400造成的电阻增加，例如，可以使得第二距离DT2大于等于35微米且小于等于45微米；例如，第二距离DT2约等于40微米。例如，当第二距离DT2为40微米时，转接电极TE的导通电阻小于20欧姆(Ω)。
图8A为本公开至少一实施例的阵列基板的显示区的截面示意图；图8B为沿图7中虚线AA'的截面图的一种示例；图8C为沿图7中虚线AA'的截面图的一种示例。图8A所示出的截面示意图例如对应于图2的阵列基板或图5所示的阵列基板母板。
下面结合图7和图8A描述上述阵列基板100中各个膜层之间的关系。需要说明的是，以下实施例以信号线400为栅线为例进行描述。
该阵列基板包括多个呈阵列排布的像素单元，像素单元包括薄膜晶体管TFT。如图8A所示，该薄膜晶体管TFT包括位于衬底基板101之上的栅极103、栅绝缘层121、有源层105、源极106和漏极107，栅极绝缘层121位于栅极103和有源层105之间。像素单元还包括公共电极102、像素电极109、钝化层122。公共电极102设置在衬底基板，且由栅极绝缘层121覆盖。钝化层122设置在薄膜晶体管TFT远离衬底基板101一侧，且包括暴露源极106和漏极107之一的过孔111，在图中的示例中，漏极107被过孔111暴露。像 素电极109设置在钝化层122远离衬底基板一侧且通过过孔与111余漏极107电连接。
该薄膜晶体管TFT的栅极103和栅线电连接以接收扫描信号，该薄膜晶体管TFT的源极106和数据线连接以接收数据信号。
像素电极109为狭缝电极，公共电极102为板状电极。像素电极109包括多个部分11，多个部分11间隔排布，多个部分11中相邻的两个部分之间形成狭缝。狭缝电极边缘所产生的电场以及狭缝电极与板状电极间产生的电场能够形成多维电场。
有源层的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)。栅极以及栅线的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Al/Ti/Al))。源极、漏极以及数据线的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Al/Ti/Al))。本公开的实施例对各功能层的材料不做具体限定。像素电极和公共电极的材料可以包括透明导电材料，例如氧化铟锡(ITO)。
在本公开的一些实施例中，阵列基板100包括依次设置的栅金属层110、至少一个绝缘层120以及导电层130，栅金属层110包括多条栅线和栅极，导电层130包括至少一个转接电极TE，第一过孔V1与第二过孔V2均贯穿至少一个绝缘层120。
在图8B所示的示例中，该至少一个绝缘层120为栅绝缘层121，导电层130为源漏电极层，也即，转接电极TE与薄膜晶体管的源极106和漏极107同层设置。该示例中，转接电极TE例如由金属材料制备。
在图8B所示的示例中，该至少一个绝缘层120为栅绝缘层，该至少一个绝缘层120为栅绝缘层121和钝化层122的叠层导电层130可以为像素电极层，也即，转接电极TE与显示区中的像素电极同层设置。该示例中，转接电极TE例如由ITO材料制备(例如图1所示的2TIO膜层)。
转接电极TE和至少一个第一过孔V1在衬底基板101的板面上的投影至少部分重叠，且转接电极TE和至少一个第二过孔V2在衬底基板101的板面上的投影至少部分重叠。需要说明的是，转接电极TE的电极图案可以在形成导电层130时利用光刻工艺形成，例如，转接电极TE不需要设置太大，转接 电极TE在衬底基板101的板面上的投影只要覆盖第一过孔V1以及第二过孔V2即可。
本公开的实施例还提供一种阵列基板的制作方法，阵列基板具有显示区域和非显示区域。该方法包括：提供一衬底基板，以及，在衬底基板形成多条信号线和至少一个转接电极。多条信号线沿第一方向从显示区域延伸至非显示区域，多条信号线中的至少一条包括位于显示区域内的第一走线和位于非显示区域的第二走线，第二走线包括至少两个彼此断开的子走线，其中，第二走线的至少两个子走线中靠近显示区域的子走线和第一走线直接连接，第二走线中每相邻的两个子走线通过转接电极彼此电连接。
图9为本公开至少一实施例的制作阵列基板的工艺流程示意图，该实施例例如对应于图8C所示的实施例。例如，通过母板来形成该阵列基板，该母板包括多个阵列基板单元，每个阵列基板单元用于切割形成单独的阵列基板。
首先，例如利用磁控溅射(sputter)工艺在衬底基板101(例如，玻璃衬底)表面形成一层均匀的透明导电材料(例如氧化铟锡(ITO)薄膜)；然后依次进行涂胶﹑曝光、显影和刻蚀(例如，湿刻)，将没有受到光刻胶保护的ITO薄膜刻蚀掉，最后将衬底基板101上剩余的光刻胶剥离和清洗，从而形成ITO膜层，例如可以将该ITO膜层称为第一ITO(1ITO)膜层。例如，在1ITO膜层中可以形成公共电极(VCOM)102。
然后，例如利用磁控溅射(sputter)工艺在衬底上形成一层均匀的金属膜层；然后依次进行涂胶﹑曝光、显影和刻蚀(例如，湿刻)，将没有受到光刻胶保护的金属膜层刻蚀掉，最后将衬底上剩余的光刻胶剥离和清洗，从而形成栅金属层。例如，栅金属层包括用于薄膜晶体管TFT的栅极103以及和栅极103连接的栅线，并且还可以形成与公共电极102电连接的公共电极线。该栅线包括位于显示区域内的第一走线WL1和位于非显示区域的第二走线WL2，第二走线WL2包括至少两个彼此断开的子走线SL。同时，栅金属层还包括位于非显示区中的检测线TL，该检测线TL与第二走线WL2包括的至少两个子走线SL中远离显示区的一个电连接。
然后，例如通过沉积工艺形成栅绝缘层121，例如，栅绝缘层121的材料可以采用氮化硅、氧化硅、氧氮化硅等，以及通过沉积工艺形成有源层105。例如，利用等离子体增强化学气相沉积(PECVD)工艺在衬底基板101上分别沉积SiNx、a-Si以及n+a-Si三层薄膜；然后依次进行涂胶﹑曝光、显影和 刻蚀(例如，干刻)，将没有受到光刻胶保护的三层薄膜刻蚀掉，最后将衬底基板101上剩余的光刻胶剥离和清洗，从而形成薄膜晶体管TFT的栅绝缘层121和有源层105。
然后，例如利用磁控溅射工艺在衬底基板101上形成一层均匀的金属膜层；然后依次进行涂胶﹑曝光、显影和刻蚀(例如，湿刻)，将没有受到光刻胶保护的金属膜层刻蚀掉，最后将衬底基板101上剩余的光刻胶剥离和清洗，从而形成源漏金属层(S/D)。例如，源漏金属层包括用于薄膜晶体管TFT的源极106和漏极107，以及连接到薄膜晶体管TFT的数据线。
然后，例如利用PECVD工艺在在衬底基板101上形成一层均匀的绝缘层；然后依次进行涂胶﹑曝光、显影和刻蚀(例如，干刻)，将没有受到光刻胶保护的绝缘层刻蚀掉，最后将衬底基板101上剩余的光刻胶剥离和清洗，从而形成钝化层(PVX)122。例如，对钝化层101进行构图以形成暴露漏极107的过孔111以及分别暴露第二走线的两个子走线SL的第一过孔V1、第二过孔V2。过孔111穿过钝化层122，而第一过孔V1和第二过孔V2穿过了钝化层122和栅绝缘层121的叠层120。钝化层122还在远离衬底基板一侧提供了平坦表面，起到了平坦化层的作用。
然后，例如利用磁控溅射工艺在衬底基板101表面形成一层均匀的透明导电材料(例如ITO薄膜)；然后依次进行涂胶﹑曝光、显影和刻蚀(例如，湿刻)，将没有受到光刻胶保护的ITO膜刻蚀掉，最后将衬底基板101上剩余的光刻胶剥离和清洗，从而形成ITO膜层，例如可以将该ITO膜层称为第二ITO(2ITO)膜层。例如，在2ITO膜层中可以形成像素电极109和转换电极TE。该像素电极109通过过孔111和漏极107电连接。转换电极TE通过第一过孔V1和第二过孔V2将第二走线WL2的彼此断开的子走线SL电连接。
上述制作阵列基板的工艺流程并不限于上述步骤，可以进行相应的修改，例如，形成公共电极的步骤可以在形成了栅金属层之后且在形成栅绝缘层之前进行，或者形成公共电极的步骤可以在形成了源漏金属层之后且在形成钝化层之前进行，….，本公开的实施例对此不作限制。
又例如，本公开的至少一实施例的示例提供一种阵列基板100的制作方法，参考图8B和图8C，该制作方法包括：提供一衬底基板101，以及在衬底基板101上依次形成栅金属层110、至少一个绝缘层120、导电层130。
例如，通过母板来形成该阵列基板，该母板包括多个阵列基板单元，每个 用于形成该阵列基板100的阵列基板单元具有显示区域DR和非显示区域PR。栅金属层110包括多条栅线，还进一步包括薄膜晶体管的栅极、公共电极线、检测线TL等。多条栅线沿第一方向D1从显示区域DR延伸至非显示区域PR；多条栅线中的至少一条包括位于显示区域DR内的第一走线WL1和位于非显示区域PR的第二走线WL2。导电层130包括至少一个转接电极TE，在一个示例中导电层130还包括薄膜晶体管的源极和漏极、数据线，或者在另一个示例中导电层130还包括像素电极。第二走线WL2包括至少两个彼此断开的子走线SL，第二走线WL2中靠近显示区域DR的子走线SL和第一走线WL1直接连接，第二走线WL2中每相邻的两个子走线SL通过转接电极TE彼此电连接。
例如，在本公开的一些实施例提供的制作方法中，栅金属层110还包括设置在非显示区域PR中沿第二方向D2设置的检测线TL，该检测线TL和多条栅线中的远离显示区域DR的一端的子走线SL连接，第一方向D1和第二方向D2相交。
例如，在本公开的一些实施例提供的制作方法中，第二走线WL2包括彼此断开的第一子走线SL1和第二子走线SL2，第一子走线SL1和第一走线WL1直接接触连接，第二子走线SL2和检测线TL直接接触连接。
例如，在本公开的一些实施例提供的制作方法中，第一子走线SL1通过至少一个第一过孔V1和转接电极TE连接，第二子走线SL2通过至少一个第二过孔V2和转接电极TE连接，第一过孔V1与第二过孔V2均贯穿至少一个绝缘层120，转接电极TE和至少一个第一过孔V1在衬底基板101的板面上的投影至少部分重叠，且转接电极TE和至少一个第二过孔V2在衬底基板101的板面上的投影至少部分重叠。
例如，本公开的一些实施例提供的制作方法还包括：将检测线TL所在的部分从衬底基板101上沿预定的切割线CL切割掉，由此由阵列基板单元得到单独的阵列基板。例如，在成盒(Cell)阶段之前的切割(Cutting)工序中，用于检测的检测线TL被切除，从而不影响最终制作的显示面板正常工作。由此，栅线GL在非显示区的端面与阵列基板的(由于切割所得到的)边缘平齐。
需要说明的是，为了制作上述阵列基板100，例如，首先需要在一个大母板上制作多个阵列基板，之后再进行切割工序，形成单独的阵列基板，然后例如和对置基板进行对盒工艺以形成显示面板。例如，在切割工序中可以将进行 后续显示不需要的结构切除，例如将用于检测的检测线TL切除。
需要说明的是，关于本公开的实施例提供的制作方法的详细描述以及技术效果可以参考上述实施例中关于阵列基板100中的相应描述，这里不再赘述。
本公开的至少一实施例还提供一种显示装置1，如图10所示，该显示装置1包括本公开的实施例提供的任一阵列基板100。
例如，该显示装置1为液晶显示装置，包括阵列基板100和对置基板200。该阵列基板100与对置基板200彼此对置以形成液晶盒(对盒)，在液晶盒中填充有液晶材料300。该对置基板200例如为彩膜基板。阵列基板100的每个像素单元的像素电极用于施加电场对液晶材料300的旋转的程度进行控制从而进行显示操作。在一些示例中，该液晶显示装置还包括为阵列基板100提供背光的背光源600。
显示装置1还包括柔性电路板150以及设置在柔性电路板150上的集成电路芯片151。该集成电路芯片151可以为控制芯片或驱动芯片等。该包括安装在其上的芯片的柔性电路板可以称为COF(Chip On Film)方式，该柔性电路板通过绑定方式与阵列基板100上设置的接触垫电连接，由此与阵列基板上的信号线电连接。
在不同的实施例中，例如，阵列基板上可以设置与栅线电连接的接触垫，由此与设置有栅极驱动电路(栅极驱动芯片)的柔性电路板电连接，以使得栅极驱动电路可以将扫描信号施加到栅线上；又例如，阵列基板上还可以设置与数据线电连接的接触垫，由此与设置有数据驱动电路(数据驱动芯片)的柔性电路板电连接，以使得数据驱动电路可以将数据信号施加到数据线上。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限制。
本公开的实施例提供的显示装置1的技术效果，可以参考上述实施例中关于阵列基板100中的相应描述，这里不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板，具有显示区域和非显示区域，且包括：衬底基板、设置在所述衬底基板上的多条信号线和至少一个转接电极，其中，
    所述多条信号线沿第一方向从所述显示区域延伸至所述非显示区域，
    所述多条信号线中的至少一条包括位于所述显示区域内的第一走线和位于所述非显示区域的第二走线，
    所述第二走线包括至少两个彼此断开的子走线，其中，所述第二走线的至少两个子走线中靠近所述显示区域的子走线和所述第一走线直接连接，
    所述第二走线中每相邻的两个子走线通过所述转接电极彼此电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第一走线和所述第二走线相对于所述衬底基板同层设置。
  3. 根据权利要求1或2所述的阵列基板，其中，
    所述多条信号线沿第二方向平行设置，所述第一方向和所述第二方向相交；
    所述第一子走线包括作为扇出形走线的部分，作为扇出形走线的所述部分的延伸方向为第三方向，所述第三方向与所述第一方向以及所述第二方向均相交。
  4. 根据权利要求1-3任一所述的阵列基板，其中，
    所述第一子走线通过至少一个第一过孔和所述转接电极连接，所述第二子走线通过至少一个第二过孔和所述转接电极连接。
  5. 根据权利要求4所述的阵列基板，其中，
    所述第一过孔在所述衬底基板的板面上的投影位置位于所述第一子走线远离所述显示区域的一端；
    所述第二过孔在所述衬底基板的板面上的投影位置位于所述第二子走线靠近所述显示区域的一端。
  6. 根据权利要求4或5所述的阵列基板，其中，
    所述多条信号线为多条栅线，
    所述阵列基板包括在所述衬底基板上依次设置的栅金属层、至少一个绝缘层以及导电层，所述栅金属层包括所述多条栅线，所述导电层包括所述至少 一个转接电极，所述第一过孔与所述第二过孔均贯穿所述至少一个绝缘层；
    所述转接电极和所述至少一个第一过孔在所述衬底基板的板面上的投影至少部分重叠，且所述转接电极和所述至少一个第二过孔在所述阵列基板的板面上的投影至少部分重叠。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括在所述衬底基板上的薄膜晶体管，
    其中，所述薄膜晶体管包括栅极、栅极绝缘层、有源层、源极和漏极，所述栅极绝缘层位于所述栅极和所述有源层之间，
    所述栅金属层还包括所述栅极，所述导电层还包括所述源极和所述漏极，所述至少一个绝缘层包括所述栅绝缘层。
  8. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括在所述衬底基板上的薄膜晶体管、钝化层和像素电极，
    其中，所述薄膜晶体管包括栅极、栅极绝缘层、有源层、源极和漏极，所述栅极绝缘层位于所述栅极和所述有源层之间，
    所述钝化层设置在所述薄膜晶体管远离所述衬底基板一侧且包括暴露所述源极和所述漏极之一的过孔，
    所述像素电极设置在所述钝化层远离所述衬底基板一侧且通过所述过孔与所述源极和所述漏极之一电连接，
    所述栅金属层还包括所述栅极，所述导电层还包括所述像素电极，所述像素电极位于所述显示区，所述至少一个绝缘层包括所述栅绝缘层和所述钝化层的叠层。
  9. 一种显示装置，包括：
    根据权利要求1-8任一所述的阵列基板，
    对置基板，与所述阵列基板对盒，
    柔性电路板，与所述阵列基板邦定以电连接。
  10. 一种母板，包括至少一个阵列基板单元，所述阵列基板单元具有显示区域和非显示区域，且包括：衬底基板、设置在所述衬底基板上的多条信号线、至少一个转接电极和检测线，其中，
    所述多条信号线沿第一方向从所述显示区域延伸至所述非显示区域，
    所述多条信号线中的至少一条包括位于所述显示区域内的第一走线和位 于所述非显示区域的第二走线，
    所述第二走线包括至少两个彼此断开的子走线，其中，所述第二走线的至少两个子走线中靠近所述显示区域的子走线和所述第一走线直接连接，
    所述第二走线中每相邻的两个子走线通过所述转接电极彼此电连接，
    所述检测线设置在所述非显示区域中沿第二方向，
    所述检测线和所述第二走线的至少两个子走线中远离所述显示区域的子走线连接，所述第一方向和所述第二方向相交。
  11. 根据权利要求10所述的母板，其中，所述第二走线包括彼此断开的第一子走线和第二子走线，所述第一子走线和所述第一走线直接连接，所述第二子走线和所述检测线直接连接。
  12. 根据权利要求11所述的母板，其中，
    所述第一子走线远离所述显示区域的一端和所述第二子走线靠近所述显示区域的一端之间的距离为第一距离，所述第一距离大于等于5微米且小于等于12微米。
  13. 根据权利要求12所述的母板，其中，
    所述转接电极在垂直于所述第一子走线的延伸方向的方向上的距离为第二距离，所述第二距离大于等于35微米且小于等于45微米。
  14. 根据权利要求10-13任一所述的母板，其中，
    所述第一子走线通过至少一个第一过孔和所述转接电极连接，所述第二子走线通过至少一个第二过孔和所述转接电极连接。
  15. 根据权利要求14所述的母板，其中，
    所述第一过孔在所述衬底基板的板面上的投影位置位于所述第一子走线远离所述显示区域的一端；
    所述第二过孔在所述衬底基板的板面上的投影位置位于所述第二子走线靠近所述显示区域的一端。
  16. 根据权利要求14或15所述的母板，其中，
    所述多条信号线为多条栅线，
    所述阵列基板单元包括在所述衬底基板上依次设置的栅金属层、至少一个绝缘层以及导电层，所述栅金属层包括所述多条栅线，所述导电层包括所述至少一个转接电极，所述第一过孔与所述第二过孔均贯穿所述至少一个绝缘 层；
    所述转接电极和所述至少一个第一过孔在所述衬底基板的板面上的投影至少部分重叠，且所述转接电极和所述至少一个第二过孔在所述衬底基板的板面上的投影至少部分重叠。
  17. 一种阵列基板的制作方法，所述阵列基板具有显示区域和非显示区域，所述方法包括：
    提供一衬底基板，以及
    在所述衬底基板形成多条信号线和至少一个转接电极，
    其中，所述多条信号线沿第一方向从所述显示区域延伸至所述非显示区域，
    所述多条信号线中的至少一条包括位于所述显示区域内的第一走线和位于所述非显示区域的第二走线，
    所述第二走线包括至少两个彼此断开的子走线，其中，所述第二走线的至少两个子走线中靠近所述显示区域的子走线和所述第一走线直接连接，
    所述第二走线中每相邻的两个子走线通过所述转接电极彼此电连接。
  18. 根据权利要求17所述的制作方法，其中，在所述衬底基板形成多条信号线和至少一个转接电极包括：
    在所述衬底基板上依次形成栅金属层、至少一个绝缘层、导电层，其中，
    所述多条信号线为多条栅线，所述栅金属层包括所述多条栅线，
    所述导电层包括所述至少一个转接电极，
    所述至少一个绝缘层包括至少一个第一过孔和至少一个第二过孔，所述第一子走线通过至少一个第一过孔和所述转接电极连接，所述第二子走线通过至少一个第二过孔和所述转接电极连接。
  19. 根据权利要求17或18所述的制作方法，还包括：
    在所述非显示区域中形成沿第二方向设置的检测线，
    其中，所述检测线和所述第二走线的至少两个子走线中远离所述显示区域的一端的子走线连接，所述第一方向和所述第二方向相交。
  20. 根据权利要求19所述的制作方法，还包括：
    将所述检测线所在的部分从所述衬底基板上切割掉。
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