WO2014183420A1 - 一种阵列基板及其制作方法和显示面板 - Google Patents

一种阵列基板及其制作方法和显示面板 Download PDF

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Publication number
WO2014183420A1
WO2014183420A1 PCT/CN2013/088457 CN2013088457W WO2014183420A1 WO 2014183420 A1 WO2014183420 A1 WO 2014183420A1 CN 2013088457 W CN2013088457 W CN 2013088457W WO 2014183420 A1 WO2014183420 A1 WO 2014183420A1
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Prior art keywords
line
array substrate
data line
layer
passivation layer
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PCT/CN2013/088457
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English (en)
French (fr)
Inventor
陈曦
冯玉春
袁剑峰
王琳琳
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/354,186 priority Critical patent/US9638972B2/en
Publication of WO2014183420A1 publication Critical patent/WO2014183420A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133351—Manufacturing of individual cells out of a plurality of cells, e.g. by dicing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects

Definitions

  • Embodiments of the present invention relate to the field of liquid crystal display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display panel. Background technique
  • liquid crystal display technology has replaced cathode ray tube display technology as the mainstream technology in the field of daily display. Due to the reduced production cost of the liquid crystal display device, the improvement of the manufacturing process and its own advantages, it has become an ideal display device in the market and consumers.
  • stereoscopic display technology is on the rise in the market, so the technical shortcomings of the stereoscopic display technology are solved, and the image quality is improved (such as reducing color shift, reducing bright spots, bright lines, reducing stereo crosstalk, flickering the screen, increasing the viewing angle, etc.) It has become increasingly important.
  • a Thin Film Transistor Liquid Crystal Display includes an array substrate, an opposite substrate, and a liquid crystal layer between the array substrate and the opposite substrate.
  • the array substrate is provided with mutually intersecting gate scan lines and data lines, and the gate scan lines and the data lines are respectively used as transmission scan driving signals and image data signals to realize control of deflection of liquid crystal molecules, thereby further controlling the intensity of light rays. And, under the joint action of the opposite substrates, the display of the image is realized.
  • the LCD In the manufacturing process of the LCD, it is required to include a specified position on the entire larger panel of the array substrate 1 and the opposite substrate 2, thereby forming a separate liquid crystal cell to expose the solder on the array substrate 1.
  • the disk (PAD) region 101 it is necessary to cut the region of the opposite substrate 2 corresponding thereto. As shown in FIG. 1 and FIG. 2, the array substrate 1 and the opposite substrate 2 are cut along the cutting line A to form a separate liquid crystal cell, and the opposite substrate 2 is cut along the opposite substrate cutting line B to expose the PAD region 101 of the array substrate 1. .
  • an insulating layer 5 is generally designed on the data line 4 on the array substrate 1.
  • the opposing substrate material under cutting may directly damage the data line 4 of the PAD region 101 near the substrate cutting line B, or may cause damage to the insulating layer 5 during the production process. This can cause subsequent data lines 4 to corrode or oxidize.
  • absolutely The hardness and adhesion of the material of the edge layer 5 are relatively low, and it is easy to fall off due to the external force, thereby causing the conductive layer to be exposed, and it is easy to be damaged or even fall off under the action of external force, and the protection effect on the data line 4 is relatively poor.
  • the scratching, detachment and destruction of the insulating layer 5 are also potential factors affecting the quality of the product.
  • the insulating layer 5 which is damaged and detached easily causes defects such as corrosion of the conductive layer, thereby affecting the quality of the product.
  • the PAD region may include an LED region that is far from the substrate cutting line B, is less prone to data line breakage, and a break-prone region 102 that is located near the opposite substrate cutting line B, in order to solve the data line break.
  • a protective layer 103 is generally disposed over the leads on both sides of the opposite substrate cutting line B to reduce the relative substrate material pair during the cutting process. Insulation and data lines cause damage, which protects the leads and reduces potential for product scrap.
  • this solution can only prevent the occurrence of data line disconnection. In the event of data line disconnection, this solution cannot solve the problem of poor display caused by data line disconnection. Summary of the invention
  • the embodiment of the invention provides an array substrate, a manufacturing method thereof and a display panel, which are used to solve the problem of poor display caused by data line breakage and improve the picture quality of the liquid crystal panel.
  • An embodiment of the present invention provides an array substrate.
  • the array substrate includes: a substrate substrate, a gate scan line above the substrate substrate, a gate insulating layer above the gate scan line, and an active layer above the gate insulating layer. a data line above the active layer, a passivation layer above the data line, and a pixel electrode above the passivation layer, the array substrate further including a connection line and a bridge structure corresponding to each data line;
  • the bridging structure is disposed above the passivation layer and disposed in the same layer as the pixel electrode; each connecting line is located above the substrate and is connected to the data line through a bridging structure of the LED region and a lower region of the opposite substrate cutting line.
  • connection lines are disposed in the same layer as the gate scan lines but do not intersect.
  • connection line and the gate scan line are perpendicular to each other.
  • connection line is made of the same material as the gate scan line.
  • the coverage area of the connection line and the coverage area of the data line do not overlap.
  • the bridging structure passes through a first type of via that penetrates the passivation layer and is above the data line. Data line connection.
  • the bridge structure is connected to the connection line by a second type of via extending through the passivation layer, the active layer, and the gate insulating layer and over the connection.
  • Embodiments of the present invention provide a display panel, which includes the above array substrate.
  • Embodiments of the present invention provide a method for fabricating the above array substrate, the method comprising: forming a gate scan line on a base substrate, forming a gate insulating layer over the gate scan line, and forming an active layer above the gate insulating layer, A data line is formed over the active layer, a passivation layer is formed over the data line, and a pixel electrode is formed over the passivation layer.
  • the method further includes:
  • connection line corresponding to each data line above the base substrate, the connection line being connected to the data line through a bridge structure of the LED area and a lower area of the opposite substrate cutting line; forming a bridge structure above the passivation layer
  • the bridge structure is disposed in the same layer as the pixel electrode.
  • the array substrate provided by the embodiment of the present invention includes a data line, a connection line corresponding to each data line, and a bridge structure, wherein the bridge structure is located above the passivation layer, is disposed in the same layer as the pixel electrode, and is disposed in the LED area.
  • each connecting line is located above the base substrate, and the bridging structure and data passing through the LED area and the lower area of the opposite substrate cutting line
  • the line connection is such that when the data line between the LED area and the opposite substrate cutting line is broken, the image data signal can be continuously transmitted through the connecting line, which can effectively solve the problem of poor display caused by the disconnection of the data line, thereby
  • the picture display quality is improved, the display effect of the liquid crystal display is enhanced, and the user experience is improved.
  • FIG. 1 is a plan view of a display panel in the prior art
  • FIG. 2 is a PAD area diagram of the array substrate of the display panel shown in FIG. 1;
  • FIG. 3 is a schematic view showing a planar structure of an array substrate for preventing data line breakage in the prior art
  • FIG. 4 is a schematic plan view showing a planar structure of an array substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic cross-sectional view of the array substrate along the line C-C' of FIG. 4;
  • FIG. 6 is a schematic plan view of another array substrate according to an embodiment of the present invention. Plane structure diagram;
  • FIG. 8 is a plan view showing the structure of an array substrate on which data lines are formed
  • FIG. 9 is a plan view showing the structure of an array substrate in which the first type of via holes and the second type of via holes are formed;
  • FIG. 10 is a schematic plan view showing the planar structure of the array substrate fabricated by the bridge structure. detailed description
  • the embodiment of the invention provides an array substrate, a manufacturing method thereof and a display panel, which are used to solve the problem of poor display caused by data line breakage and improve the display effect of the liquid crystal display device.
  • An embodiment of the present invention provides an array substrate.
  • the array substrate includes: a substrate substrate, a gate scan line above the substrate substrate, a gate insulating layer above the gate scan line, and an active layer above the gate insulating layer. a data line above the active layer, a passivation layer above the data line, and a pixel electrode above the passivation layer, the array substrate further including a connection line and a bridge structure corresponding to each data line;
  • the bridge structure is located above the passivation layer and disposed in the same layer as the pixel electrode;
  • Each of the connecting lines is located above the substrate and is connected to the data line through a bridging structure of the LED area and the lower area of the opposing substrate cutting line.
  • the bridge structure is connected to the data line through a first type of via hole penetrating the passivation layer and located above the data line; the bridge structure is located through the passivation layer, the active layer, and the gate insulating layer A second type of via above the connection line is connected to the connection line.
  • the bridging structure is disposed in the same layer as the pixel electrode, for example, is a tube forming process, and the material of the bridging structure is made of the same material as the pixel electrode, generally indium tin oxide (ITO);
  • ITO indium tin oxide
  • the structure can also be made of other conductive materials.
  • connection line is located above the substrate substrate, disposed in the same layer as the gate scan line, and perpendicular to the gate scan line but not intersecting; in addition, the connection line may also be disposed in other layers, for example, the connection The line can also be placed in the same layer as the data line.
  • the position of the connecting line is relatively close to the surface, and it may break during the transfer and splitting process, and the poor display problem caused by the disconnection of the data line cannot be well solved.
  • the connecting wire is made of a conductive metal material, which may be the same as the material of the gate scan line; the resistance of the connecting wire can be effectively reduced by using a metal material.
  • the connecting wire may also use other conductive materials such as indium tin oxide (ITO), etc., but the ITO has a large electrical resistance, which is disadvantageous for the transmission of electrical signals.
  • ITO indium tin oxide
  • FIG. 4 is a plan view of the array substrate provided by the implementation of the present invention
  • FIG. 5 is a cross-sectional view taken along line C-C' of FIG. FIG. 4 and FIG. 5, the array substrate includes: a substrate 401, a gate scan line 402, a connection line 403, a gate insulating layer 404, an active layer 405, and a data line 406.
  • the array substrate further includes a pixel electrode (not shown), and the film connected to the pixel electrode The drain of the transistor and its gate and source.
  • the gate (not shown) of the thin film transistor, the gate scan line 402, and the connection line 403 are disposed in the same layer, and are located above the base substrate 401; and the gate and gate scan lines of the thin film transistor 402 and the connecting wire 403 are made of the same material and are a metal such as molybdenum Mo, aluminum Al, chromium Cr or copper Cu.
  • the electrical resistance of the connecting wire 403 can be effectively reduced by using a metal material; in addition, the connecting wire 403 can also use other conductive materials, such as indium tin oxide (ITO), etc., but the ITO has a large electrical resistance, which is disadvantageous for The transmission of electrical signals will also increase the manufacturing process.
  • ITO indium tin oxide
  • the connecting line 403 In the array substrate, a plurality of structures are covered above the connecting line 403.
  • the multi-layer structure located above the connecting line 403 can protect the connecting line 403, so that the connecting line 403 will not break during the process of moving and splitting.
  • connection line 403 is disposed such that its wiring direction is perpendicular to the wiring direction of the gate scanning line 402, and the connection line 403 does not intersect the gate scanning line 402.
  • the gate insulating layer 404 is located at a gate of the thin film transistor, a gate scan line 402, and a connection line.
  • the gate, the gate scan line and the connection line 403 of the thin film transistor are insulated from other layers, and the material is made of silicon nitride SiN x or silicon oxide SiO x .
  • the active layer 405 is located above the gate insulating layer 404.
  • a source (not shown) of the thin film transistor is disposed in the same layer as a drain (not shown) of the thin film transistor, and is located above the active layer 405; a source and a drain of the thin film transistor
  • the material is made of a conductive metal, for example, a single molybdenum (Mo), chromium (Gr) or a double-layered aluminum-milled alloy molybdenum (AlNb/Mo).
  • the data line 406 is located above the active layer 405 and below the passivation layer 407, and its wiring direction is consistent with the wiring direction of the connection line 403; to prevent a height difference, the coverage area of the data line 406 and the The coverage areas of the connection lines 403 do not overlap, and the data lines 406 and connection lines The distance between 403 remains the same, and at the same time, to reduce the resistance between the connection line 403 and the data line 406, the connection line 403 and the data line 406 should be as close as possible.
  • the passivation layer 407 is located above the source and the drain of the thin film transistor, and is made of the same material as the gate insulating layer 404, and is silicon nitride 81 or silicon oxide SiO x .
  • the pixel electrode (not shown) is disposed above the passivation layer 407 and directly connected to the drain of the array substrate through a third type of via (not shown) in the passivation layer 407;
  • the material is a transparent conductive material such as indium tin oxide (ITO) or the like.
  • the bridging structure 408 is disposed above the passivation layer 407 and disposed in the same layer as the pixel electrode. Moreover, the bridging structure 408 and the pixel electrode are made of the same material and manufacturing process.
  • the pixel electrode and the bridge structure 408 are different in a distribution area, and the pixel electrode is located in the display area for driving liquid crystal molecules to deflect and realize image display; the bridge structure 408 is located in the non-display area and is on the connection line 403 and Above the data line 406, the data line 406 and the connection line 403 are connected through the first type of via 409 and the second type of via 410, respectively.
  • the first type of via 409 is located above the data line 406 and extends through the passivation layer 407 such that the bridge structure 408 is connected to the data line 406 through the first type of via 409; and, the LED area and the opposite substrate are cut.
  • Each of the lower regions of the line B is provided with at least one of the first type of vias 409;
  • the second type of via 410 is located above the connection line 403, and sequentially penetrates the gate insulating layer 404, the active layer 405 and the passivation layer 407, so that the bridge structure 408 is connected to the connection line 403 through the second type of via 410. Further, at least one of the second type of via holes 410 is disposed in the lower region of the LED region and the cut-off substrate B.
  • FIG. 6 Another array substrate provided by the embodiment of the present invention has a planar structure as shown in FIG. 6.
  • the array substrate and the array substrate shown in FIG. 4 have substantially the same structure;
  • a plurality of second type vias 410 having a smaller aperture are disposed above the connection line 403, and the connection lines pass through the plurality of apertures in the area.
  • a small second type of via 410 and a first type of via 409, and a bridging structure 408 overlying the connection of the data line 406 and the connection line 403; and in the array substrate shown in FIG.
  • a second type of via hole 410 having a larger aperture is disposed above the connecting line, and the connecting line 403 passes through the second type of via hole 410 and the first type of via hole 409 having a larger aperture, and is covered in the area.
  • the connection of the data line 406 to the connecting line 403 is achieved.
  • a method for preparing an array substrate includes: manufacturing on a substrate As a gate scan line, a gate insulating layer is formed over the gate scan line, an active layer is formed over the gate insulating layer, a data line is formed over the active layer, a passivation layer is formed over the data line, and a passivation layer is formed over the passivation layer a pixel electrode; the method further includes:
  • connection line corresponding to each data line above the substrate of the village, the connection line being connected to the data line through a bridge structure of the LED area and a lower area of the opposite substrate cutting line;
  • a bridge structure is formed over the passivation layer, and the bridge structure is disposed in the same layer as the pixel electrode.
  • the method further includes: forming a first type of via hole penetrating the passivation layer over the data line, such that the bridge structure is connected to the data line through the first type of via hole; forming a through hole above the connection line
  • a second type of via of the passivation layer, the active layer and the gate insulating layer is such that the bridge structure is connected to the connection line through the second type of via.
  • the method for fabricating the array substrate provided by the embodiment of the present invention is described in detail below with reference to the accompanying drawings.
  • the structure of the array substrate shown in FIG. 2 is taken as an example, and the manufacturing steps may include:
  • a metal layer such as molybdenum Mo, aluminum A1 or cadmium Cr is deposited on the glass substrate, and then a gate electrode (not shown) of the array substrate, the gate scan line, and the upper and lower sides are formed by a patterning process.
  • a silicon nitride SiN x or silicon oxide SiO x layer is deposited over the gate of the array substrate, the gate scan line and the connection line, and then the gate insulating layer is formed by a patterning process.
  • a semiconductor film, a doped semiconductor film, and a source/drain metal film are deposited on the gate insulating layer, and an active layer and a source of the array substrate are formed on the gate insulating layer by using a half mask technique ( Not shown), the drain (not shown) of the array substrate and the data line 406.
  • a silicon nitride film is deposited over the active layer, the source and the drain to form a passivation layer; and after being coated with a photoresist, exposed and developed, etching and stripping are performed. And a process, forming a first type of via 409 penetrating the passivation layer, and a second type of via 410 extending through the passivation layer, the active layer, and the gate insulating layer.
  • a transparent conductive film of indium tin oxide (ITO) is deposited on the passivation layer 36 by magnetron sputtering, and after being coated with a photoresist and exposed to light, wet etching and stripping are performed.
  • ITO indium tin oxide
  • the bridge structure is connected to the data line 406 through the first type of via 409, and is connected to the connection line 403 through the second type of via 410; the pixel electrode passes
  • a third type of via (not shown) in the passivation layer is directly connected to the drain of the array substrate.
  • the array substrate formed by the above method is provided with a connection line connected to the data line through the bridge structure of the LED area and the lower area of the opposite substrate cutting line, so that the data line between the LED area and the opposite substrate cutting line
  • the data image signal of the signal on the data line can be transmitted from one end of the breakpoint to the other end of the breakpoint through the connecting line, thereby ensuring the normal transmission of the image data signal, effectively solving the problem caused by the disconnection of the data line.
  • the display problem is poor, which improves the display effect of the liquid crystal display and improves the user experience.
  • Embodiments of the present invention provide a display panel, which includes the above array substrate.
  • an embodiment of the present invention provides an array substrate, a method for fabricating the same, and a display panel.
  • the array substrate is provided with a connection line and a bridge structure corresponding to each data line, and the connection line bridges the data line located in the area below the LED area and the opposite substrate cutting line, so that the LED line and the opposite substrate cutting line are located
  • the signal on the data line can still be transmitted normally; meanwhile, since the connection line is located between the base substrate and the gate insulating layer, the upper layer is covered with a multi-layer structure,
  • the layer structure can protect the connecting line during the subsequent cutting process, so that the connecting line does not break during the process of moving and splitting.
  • the array substrate effectively solves the problem of poor display caused by disconnection of the data line, thereby improving the display effect of the liquid crystal display and improving the user experience.

Abstract

一种阵列基板及其制作方法和显示面板，该阵列基板包括衬底基板（401）、栅扫描线（402）、栅绝缘层（404）、有源层（405）、数据线（406）、钝化层（407）和像素电极，还包括每一数据线（406）对应的连接线（403）和桥接结构（408）；该桥接结构（408）位于钝化层（407）的上方，与像素电极同层设置；每一连接线（403），位于衬底基板（401）的上方，并通过LED区域以及相对基板切割线的下方区域的桥接结构（408）与数据线（406）连接。从而解决了因数据线（406）断线而导致的显示不良问题，提高液晶显示装置的显示效果。

Description

一种阵列基板及其制作方法和显示面板 技术领域
本发明的实施例涉及液晶显示技术领域， 尤其涉及一种阵列基板及其制 作方法和显示面板。 背景技术
随着薄膜晶体管液晶显示技术的发展和工业技术的进步， 液晶显示技术 已经取代了阴极射线管显示技术成为日常显示领域的主流技术。 由于液晶显 示器件生产成本降低、 制造工艺的日益完善以及其本身所具有的优点， 在市 场和消费者心中成为理想的显示器件。 目前市场上立体显示技术日益兴起， 故而解决立体显示技术上的技术缺点， 改善成像质量（如减小色偏， 减少亮 点、 亮线， 降低立体串扰， 画面闪烁， 增大可视角度等）也变得日益重要。
薄膜晶体管液晶显示器（ Thin Film Transistor Liquid Crystal Display , 缩 写为 TFT-LCD )包括阵列基板、相对基板以及位于阵列基板和相对基板之间 的液晶层。 阵列基板中设置有相互交叉的栅扫描线和数据线， 栅扫描线和数 据线分别被用作传输扫描驱动信号和图像数据信号， 来实现对液晶分子偏转 的控制， 从而进一步控制光线的强弱， 并且在相对基板的共同作用下， 实现 图像的显示。
在 LCD的制造工艺中， 需要包含阵列基板 1与相对基板 2的一整块较 大的面板上的指定位置进行切剖， 进而形成一个个独立的液晶盒， 为显露出 阵列基板 1上的焊盘（PAD ) 区域 101 , 需要将相对基板 2的与其对应的区 域切割掉。 如图 1和图 2所示， 沿切割线 A切割阵列基板 1及相对基板 2, 形成独立的液晶盒， 再沿相对基板切割线 B切割相对基板 2, 以显露出阵列 基板 1的 PAD区域 101。
目前， 如图 2所示， 阵列基板 1上的数据线 4上通常设计有一层绝缘层 5。在切割工艺的搬送和裂片过程中，切割下的相对基板材料可能会对相对基 板切割线 B附近的 PAD区域 101的数据线 4造成直接损伤， 或者在生产过 程中可能造成绝缘层 5损伤， 也会导致后续数据线 4腐蚀或氧化。 此外， 绝 缘层 5可用材料的硬度、 附着力相对较低， 受外力作用易脱落， 从而造成导 电层棵露在外， 容易在外力作用下损伤甚至脱落， 对数据线 4的保护效果相 对较差。 同时绝缘层 5的划伤、脱落及破坏， 也是影响产品品质的潜在因素， 随着时间的推移， 损伤脱落的绝缘层 5容易造成导电层的腐蚀等缺陷， 从而 影响产品的品质。 在生产实际中， 己经有由于绝缘层损伤导致产品 废的先 例。
如图 3所示， 所述 PAD区域可以包括距离相对基板切割线 B较远、 不 易发生数据线断裂的 LED区域和位于相对基板切割线 B附近的断裂易发区 域 102, 为解决该数据线断线问题， 现有技术中一般是通过在相对基板切割 线 B的两侧区域的引线上方设置一个保护层 103, 以减少在切割工艺的般送 和裂片过程中， 由于切割下的相对基板材料对绝缘层和数据线造成损伤， 起 到保护引线的作用， 减少了产品报废的潜在因素。 但是， 该方案只能起到预 防数据线断线的发生， 一旦发生数据线断线， 该方案则无法解决因数据线断 线而导致的不良显示问题。 发明内容
本发明实施例提供了一种阵列基板及其制作方法和显示面板， 用以解决 因数据线断裂导致的不良显示问题， 提高液晶面板的画面质量。
本发明实施例提供了一种阵列基板， 所述阵列基板包括： 衬底基板， 位 于衬底基板上方的栅扫描线， 位于栅扫描线上方的栅绝缘层， 位于栅绝缘层 上方的有源层， 位于有源层上方的数据线， 位于数据线上方的钝化层， 以及 位于钝化层上方的像素电极， 所述阵列基板还包括与每一数据线对应的连接 线和桥接结构； 其中， 所述桥接结构位于钝化层的上方， 与像素电极同层设 置； 每一连接线，位于衬底基板的上方， 并通过 LED区域以及相对基板切割 线的下方区域的桥接结构与数据线连接。
例如， 所述连接线与栅扫描线同层设置但不相交。
例如， 所述连接线与栅扫描线相互垂直。
例如， 所述连接线与栅扫描线的制作材料相同。
例如， 所述连接线的覆盖区域和数据线的覆盖区域不重叠。
例如， 所述桥接结构通过贯穿钝化层且位于数据线上方的第一类过孔与 数据线连接。
例如， 所述桥接结构通过贯穿钝化层、 有源层和栅绝缘层且位于所述连 接线上方的第二类过孔与连接线连接。
本发明实施例提供了一种显示面板，所述显示面板包括上述的阵列基板。 本发明实施例提供了一种上述阵列基板的制作方法， 所述方法包括： 在 衬底基板上制作栅扫描线， 在栅扫描线上方制作栅绝缘层， 在栅绝缘层上方 制作有源层， 在有源层上方制作数据线， 在数据线上方制作钝化层， 以及在 所述钝化层上方制作像素电极， 所述方法还包括：
在衬底基板上方制作与每一数据线对应的连接线，所述连接线通过 LED 区域以及相对基板切割线的下方区域的桥接结构与数据线连接； 在钝化层的 上方制作桥接结构， 所述桥接结构与像素电极同层设置。
本发明实施例提供的阵列基板包括位于数据线、 与每一数据线对应的连 接线和桥接结构， 其中， 所述桥接结构位于钝化层的上方， 与像素电极同层 设置，并且在 LED区域以及相对基板切割线的下方区域均同时连接数据线和 与之对应的连接线； 每一连接线， 位于衬底基板的上方， 并通过 LED区域以 及相对基板切割线的下方区域的桥接结构与数据线连接，使得当位于 LED区 域与相对基板切割线之间的数据线发生断裂时， 图像数据信号可以通过所述 连接线继续传输， 能够有效解决因数据线断线而导致的不良显示问题， 从而 提高了画面显示质量， 增强了液晶显示器的显示效果， 提高了用户感受。 附图说明
图 1为现有技术中显示面板的平面图；
图 2为图 1所示显示面板的阵列基板的 PAD区域图；
图 3为现有技术中防止数据线断线的阵列基板平面结构示意图； 图 4为本发明实施例提供的一种阵列基板的平面结构示意图；
图 5为沿图 4中虚线 C一 C'方向的阵列基板的剖面结构示意图； 图 6为本发明实施例提供的另一种阵列基板的平面结构示意图； 图 7为完成连接线制作的阵列基板的平面结构图；
图 8为完成数据线制作的阵列基板的平面结构图；
图 9为完成第一类过孔和第二类过孔的制作的阵列基板的平面结构图； 图 10为完成桥接结构制作的阵列基板的平面结构示意图。 具体实施方式
本发明实施例提供了一种阵列基板及其制作方法和显示面板， 用以解决 因数据线断裂导致的不良显示问题， 提高液晶显示装置的显示效果。
本发明实施例提供了一种阵列基板， 所述阵列基板包括： 衬底基板， 位 于衬底基板上方的栅扫描线， 位于栅扫描线上方的栅绝缘层， 位于栅绝缘层 上方的有源层， 位于有源层上方的数据线， 位于数据线上方的钝化层， 以及 位于钝化层上方的像素电极， 所述阵列基板还包括与每一数据线对应的连接 线和桥接结构； 其中，
所述桥接结构位于钝化层的上方， 与像素电极同层设置；
每一连接线，位于衬底基板的上方，并通过 LED区域以及相对基板切割 线的下方区域的桥接结构与数据线连接。
例如， 所述桥接结构通过贯穿钝化层、 且位于所述数据线上方的第一类 过孔与数据线连接； 所述桥接结构通过贯穿钝化层、 有源层和栅绝缘层的且 位于所述连接线上方的第二类过孔与连接线连接。
所述桥接结构与像素电极同层设置， 例如， 为筒化制作工艺， 所述桥接 结构的制作材料导电材料与像素电极的制作材料相同， 一般为氧化铟锡 ( ITO ) ； 此外， 所述桥接结构还可以用其它的导电材料制作。
例如， 所述连接线位于衬底基板的上方， 与栅扫描线同层设置， 并且与 栅扫描线相互垂直但不相交； 此外， 所述连接线还可以设置在其它层， 例如， 所述连接线还可以与数据线同层设置， 但是这种结构中连接线位置比较靠近 表面， 也可能会在搬送和裂片过程中发生断裂， 不能很好地解决由数据线断 线导致的不良显示问题。
例如， 所述连接线的制作材料为导电金属材料， 可以与所述栅扫描线的 制作材料相同； 使用金属材料可以有效减小所述连接线的电阻。 同时， 所述 连接线还可以使用其它的导电材料， 如氧化铟锡（ITO )等， 但是 ITO具有 较大的电阻， 不利于电信号的传输。
例如， 所述连接线的覆盖区域和数据线的覆盖区域不重叠， 所述连接线 的覆盖区域和数据线的覆盖区域之间具有一定的距离， 且距离保持不变。 下面结合附图， 详细介绍本发明实施例提供的阵列基板， 参见图 4和图 5, 图 4为本发明实施提供的阵列基板的平面图， 图 5为沿图 4中虚线 C—C' 方向的阵列基板的剖面结构示意图； 结合图 4和图 5, 可以看出所述阵列基 板包括： 衬底基板 401、 栅扫描线 402、 连接线 403、 栅绝缘层 404、 有源层 405、 数据线 406、 钝化层 407、 桥接结构 408、 第一类过孔 409、 以及第二类 过孔 410; 此外， 所述阵列基板中还包括未图示的像素电极， 以及所述与像 素电极连接的薄膜晶体管的漏极和其栅极、 源极。
例如， 所述薄膜晶体管的栅极 (未图示） 、 栅扫描线 402和连接线 403 同层设置， 均位于所述衬底基板 401上方； 并且， 所述薄膜晶体管的栅极、 栅扫描线 402和连接线 403的制作材料相同， 为钼 Mo、 铝 Al、 铬 Cr或铜 Cu等金属。
使用金属材料可以有效地减小所述连接线 403的电阻； 此外， 所述连接 线 403还可以使用其它的导电材料， 如氧化铟锡（ITO )等， 但是 ITO具有 较大的电阻， 不利于电信号的传输， 同时还会增加制作工艺程序。
所述阵列基板中， 连接线 403上方有多层结构覆盖， 在进行后续切割工 艺时， 位于所述连接线 403上方的所述多层结构对该连接线 403能够起到保 护作用， 使得连接线 403不会在搬动和裂片的过程中断裂。
所述连接线 403设置为其布线方向与栅扫描线 402的布线方向相互垂直， 且所述连接线 403与栅扫描线 402不相交。
所述栅绝缘层 404位于所述薄膜晶体管的栅极、 栅扫描线 402和连接线
403上方， 用于将所述薄膜晶体管的栅极、 栅扫描线和连接线 403与其它层 绝缘， 其制作材料为氮化硅 SiNx或氧化硅 SiOx。
所述有源层 405位于所述栅绝缘层 404上方。
所述薄膜晶体管的源极（未图示）与所述薄膜晶体管的漏极（未图示） 同层设置， 均位于所述有源层 405的上方； 所述薄膜晶体管的源极和漏极的 制作材料为导电金属， 例如， 单一的钼（Mo )、 铬（Gr )或者双层的铝铣合 金钼 （AlNb/Mo )等金属。
所述数据线 406, 位于有源层 405的上方、 钝化层 407的下方， 其布线 方向与连接线 403的布线方向一致； 为防止产生高度差， 所述数据线 406的 覆盖区域和所述连接线 403的覆盖区域不重叠， 且所述数据线 406和连接线 403之间的距离保持不变， 同时， 为减小连接线 403与数据线 406之间的电 阻， 连接线 403与数据线 406应尽量靠近。
所述钝化层 407, 位于所述薄膜晶体管的源极和漏极的上方， 其制作材 料与栅绝缘层 404的制作材料相同， 为氮化硅 81^或氧化硅 SiOx。
所述像素电极（未图示） ， 位于钝化层 407上方， 并通过钝化层 407中 的第三类过孔（未图示）与阵列基板的漏极直接连接； 所述像素电极的制作 材料为透明导电材料， 如氧化铟锡（ITO )等。
所述桥接结构 408, 位于钝化层 407上方， 与所述像素电极同层设置； 并且， 所述桥接结构 408和像素电极的制作材料和制作工艺均相同。
所述像素电极和桥接结构 408的分布区域不同， 所述像素电极位于显示 区域， 用于驱动液晶分子发生偏转， 实现图像显示； 所述桥接结构 408位于 非显示区域且在所述连接线 403和数据线 406上方，用于通过第一类过孔 409 和第二类过孔 410分别连接数据线 406和连接线 403。
所述第一类过孔 409,位于数据线 406上方， 贯穿钝化层 407,使得桥接 结构 408通过该第一类过孔 409与数据线 406连接； 并且，在所述 LED区域 和相对基板切割线 B的下方区域内均设置有至少一个所述第一类过孔 409;
所述第二类过孔 410,位于连接线 403上方，依次贯穿栅绝缘层 404、有 源层 405和钝化层 407, 使得桥接结构 408通过该第二类过孔 410与连接线 403连接； 并且，在所述 LED区域和对盒基板切割线 B的下方区域内均设置 有至少一个所述第二类过孔 410。
本发明实施例还提供的另一种阵列基板， 其平面结构如图 6所示， 从图 6中可以看出， 该阵列基板和图 4所示的阵列基板的结构基本相同； 两者的 区别之处在于， 图 4所示的阵列基板中， 在 LED区域内， 在连接线 403上方 设置多个孔径较小的第二类过孔 410, 在该区域内连接线通过所述多个孔径 较小的第二类过孔 410和第一类过孔 409, 以及覆盖在上方的桥接结构 408, 实现数据线 406与连接线 403的连接； 而在图 6所示的阵列基板中， 在 LED 区域内， 在连接线上方设置一个孔径较大的第二类过孔 410, 在该区域内连 接线 403通过所述一个孔径较大的第二类过孔 410和第一类过孔 409, 以及 覆盖在上方的桥接结构 408, 实现数据线 406与连接线 403的连接。
本发明实施例提供的一种阵列基板的制备方法， 包括： 在衬底基板上制 作栅扫描线， 在栅扫描线上方制作栅绝缘层， 在栅绝缘层上方制作有源层， 在有源层上方制作数据线， 在数据线上方制作钝化层， 以及在钝化层上制作 像素电极； 所述方法还包括：
在村底基板上方制作与每一数据线对应的连接线，所述连接线通过 LED 区域以及相对基板切割线的下方区域的桥接结构与数据线连接；
在钝化层的上方制作桥接结构， 所述桥接结构与像素电极同层设置。 例如， 所述方法还包括： 在所述数据线上方形成贯穿钝化层的第一类过 孔， 使得桥接结构通过该第一类过孔与数据线连接； 在所述连接线的上方形 成贯穿钝化层、 有源层和栅绝缘层的第二类过孔， 使得桥接结构通过该第二 类过孔与连接线连接。
下面结合附图， 详细介绍本发明实施例提供的阵列基板的制作方法， 以 图 2所示的阵列基板的结构为例， 其制作步骤可以包括：
第一步， 参见图 7, 在玻璃基板上沉积钼 Mo、 铝 A1或镉 Cr等金属层， 然后利用构图工艺， 形成阵列基板的栅极（未图示） 、 栅扫描线和呈上窄下 宽状的连接线 403; 所述连接线 403的覆盖范围和栅扫描线的覆盖范围不重 叠， 并且， 其布线方向和栅扫描线的布线方向相互垂直。
第二步， 在阵列基板的栅极、 栅扫描线和连接线上方沉积氮化硅 SiNx 或氧化硅 SiOx层， 然后利用构图工艺形成栅绝缘层。
第三步， 参见图 8, 在栅绝缘层上沉积半导体薄膜、 掺杂半导体薄膜和 源漏金属薄膜， 采用半掩膜技术， 在栅极绝缘层上形成有源层、 阵列基板的 源极（未图示） 、 阵列基板的漏极（未图示）和数据线 406。
第四步， 参见图 9, 在所述有源层、 源极和漏极上方沉积氮化硅薄膜， 形成钝化层； 并且， 经涂覆光刻胶、 曝光显影后， 进行刻蚀、 剥离等工艺， 形成贯穿所述钝化层的第一类过孔 409, 和贯穿所述钝化层、 有源层、 栅绝 缘层的第二类过孔 410。
第五步， 参见图 10, 使用磁控溅射法在钝化层 36上沉积一层氧化铟锡 ( ITO )透明导电薄膜， 经涂覆光刻胶并曝光显影后， 再进行湿刻、 剥离， 形成像素电极（未图示）和桥接结构 408; 所述桥接结构通过第一类过孔 409 与数据线 406连接， 同时通过第二类过孔 410与连接线 403连接； 所述像素 电极通过位于钝化层中的第三类过孔（未图示）直接与阵列基板的漏极连接。 经过上述步骤， 即可制得本发明实施例提供的其结构如图 2所示的阵列 基板。 利用上述方法形成的阵列基板中设置有连接线， 所述连接线通过 LED 区域以及相对基板切割线的下方区域的桥接结构与数据线连接， 使得位于 LED区域与相对基板切割线之间的数据线发生断线时，数据线上的信号的数 据图像信号可以通过连接线从断点的一端传输到断点的另一端， 保证了图像 数据信号的正常传输， 有效解决了因数据线断线产生的不良显示问题， 从而 改善了液晶显示器的显示效果， 提高了用户感受。
本发明实施例提供了一种显示面板，所示显示面板包括上述的阵列基板。 综上所述， 本发明实施例一种阵列基板及其制作方法和显示面板。 所述 阵列基板中设置有与每一数据线对应的连接线和桥接结构， 所述连接线跨接 位于 LED区域和相对基板切割线下方区域的数据线， 使得在位于 LED区域 和相对基板切割线之间的数据线的发生断线时， 该数据线上的信号依然能够 正常传输； 同时， 由于所述连接线位于衬底基板和栅绝缘层之间， 上方覆盖 有多层结构， 所述多层结构在进行后续切割工艺时， 对连接线能够起到保护 作用， 使得连接线在搬动和裂片的过程中不会断裂。 所述阵列基板有效解决 了因数据线断线产生的不良显示问题， 从而改善了液晶显示器的显示效果， 提高了用户感受。 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权利要求书
1、 一种阵列基板， 所述阵列基板包括： 衬底基板， 位于衬底基板上方的 栅扫描线， 位于栅扫描线上方的栅绝缘层， 位于栅绝缘层上方的有源层、 位 于有源层上方的数据线， 位于数据线上方的钝化层， 位于钝化层上方的像素 电极， 其中， 所述阵列基板还包括与每一数据线对应的连接线和桥接结构； 其中， 所述桥接结构位于钝化层的上方， 与像素电极同层设置； 每一连接线，位于衬底基板的上方，并通过 LED区域以及相对基板切割 线的下方区域的桥接结构与数据线连接。
2、如权利要求 1所述阵列基板， 其中， 所述连接线与栅扫描线同层设置 但不相交。
3、如权利要求 1所述阵列基板，其中，所述连接线与栅扫描线相互垂直。
4、如权利要求 1所述阵列基板， 其中， 所述连接线与栅扫描线的制作材 料相同。
5、如权利要求 1所述阵列基板， 其中， 所述连接线的覆盖区域和数据线 的覆盖区域不重叠。
6、如权利要求 1所述阵列基板， 其中， 所述桥接结构通过贯穿钝化层且 位于数据线上方的第一类过孔与数据线连接。
7、 如权利要求 1所述阵列基板， 其中， 所述桥接结构通过贯穿钝化层、 有源层和栅绝缘层且位于所述连接线上方的第二类过孔与连接线连接。
8、 一种显示面板， 其中， 所述显示面板包括权利要求 1~7任一所述的 阵列基板。
9、一种阵列基板的制作方法， 所述方法包括： 在衬底基板上制作栅扫描 线， 在栅扫描线上方制作栅绝缘层， 在栅绝缘层上方制作有源层， 在有源层 上方制作数据线，在数据线上方制作钝化层，以及在钝化层上制作像素电极； 其中， 所述方法还包括：
在衬底基板上方制作与每一数据线对应的连接线，所述连接线通过 LED 区域以及相对基板切割线的下方区域的桥接结构与数据线连接；
在钝化层的上方制作桥接结构， 所述桥接结构与像素电极同层设置。
PCT/CN2013/088457 2013-05-17 2013-12-03 一种阵列基板及其制作方法和显示面板 WO2014183420A1 (zh)

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