WO2019184327A1 - 基板及其制作方法、电子装置 - Google Patents

基板及其制作方法、电子装置 Download PDF

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Publication number
WO2019184327A1
WO2019184327A1 PCT/CN2018/112199 CN2018112199W WO2019184327A1 WO 2019184327 A1 WO2019184327 A1 WO 2019184327A1 CN 2018112199 W CN2018112199 W CN 2018112199W WO 2019184327 A1 WO2019184327 A1 WO 2019184327A1
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Prior art keywords
common electrode
substrate
electrode lead
layer
working area
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PCT/CN2018/112199
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English (en)
French (fr)
Inventor
高玟虎
董婉俐
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/471,336 priority Critical patent/US11482592B2/en
Priority to JP2019547303A priority patent/JP7368233B2/ja
Priority to EP18887217.0A priority patent/EP3779585A4/en
Publication of WO2019184327A1 publication Critical patent/WO2019184327A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • Embodiments of the present disclosure relate to a substrate, a method of fabricating the same, and an electronic device.
  • the resistance deviation of the connection line in the circuit causes the signal transmission speed in the circuit to slow down, thereby causing uneven brightness of the display screen and affecting the display quality.
  • the connection line in the circuit for example, the driving circuit
  • At least one embodiment of the present disclosure provides a substrate including: a working area, a non-working area located around the working area; a substrate; a peripheral circuit located on the substrate and located in the non-working area And a common electrode lead; wherein the common electrode lead is located on a side of the peripheral circuit adjacent to the working area.
  • the substrate provided by at least one embodiment of the present disclosure further includes a common electrode, wherein the common electrode extends from the working region to the non-working region; and the common electrode is in direct contact with at least a portion of the common electrode lead.
  • the peripheral circuit is a gate driving circuit
  • the common electrode is a cathode
  • the common electrode lead is a cathode lead
  • the substrate provided by at least one embodiment of the present disclosure further includes a flat layer covering the peripheral circuit and the common electrode lead, wherein the common electrode is located on a side of the flat layer away from the base substrate;
  • the planarization layer includes a via that exposes at least a portion of the common electrode lead, the common electrode being in direct contact with the common electrode lead at the via.
  • the substrate provided in at least one embodiment of the present disclosure further includes an electrostatic protection layer, wherein the electrostatic protection layer is disposed on a side of the planarization layer away from the substrate substrate and covers at least a portion of the peripheral circuit, and The electrostatic protection layer is electrically connected to the common electrode lead at the via.
  • the substrate provided by at least one embodiment of the present disclosure further includes a flat layer, wherein the common electrode and the common electrode lead are located on a side of the flat layer away from the base substrate, and the common electrode is At least a portion of the common electrode leads are in direct contact.
  • the common electrode directly overlaps at least a portion of the common electrode lead to directly contact the common electrode lead.
  • the common electrode lead directly overlaps at least a portion of the common electrode to be in direct contact with the common electrode.
  • one end of the common electrode is butted to one end of the common electrode lead to directly contact the common electrode with the common electrode lead.
  • the working area includes a plurality of working units distributed in an array, each of the working units including: a first electrode disposed on the base substrate; a layer disposed on a side of the first electrode away from the substrate; a second electrode disposed on a side of the functional layer away from the substrate; wherein the second electrode is Said common electrode.
  • the common electrode lead is disposed in the same layer as the first electrode.
  • the substrate provided by at least one embodiment of the present disclosure further includes an electrostatic protection layer disposed on a side of the planar layer away from the substrate substrate and covering at least a portion of the peripheral circuit and The common electrode leads are electrically connected.
  • the electrostatic protection layer directly overlaps at least a portion of the common electrode lead to be electrically connected to the common electrode lead.
  • the common electrode lead directly overlaps at least a part of the electrostatic protection layer to be electrically connected to the electrostatic protection layer.
  • the other end of the common electrode lead is butted to one end of the electrostatic protection layer to electrically connect the common electrode lead to the electrostatic protection layer.
  • At least one embodiment of the present disclosure also provides an electronic device comprising the substrate provided by any of the above embodiments.
  • At least one embodiment of the present disclosure further provides a method of fabricating a substrate including a working area and a non-working area around the working area, the manufacturing method comprising: providing a substrate; on the substrate A peripheral circuit and a common electrode lead are formed in the non-working area; wherein the common electrode lead is located on a side of the peripheral circuit close to the working area.
  • the substrate fabrication method provided by at least one embodiment of the present disclosure further includes forming a common electrode extending from the working region to the non-working region, and the common electrode is in direct contact with at least a portion of the common electrode lead .
  • the substrate fabrication method provided by at least one embodiment of the present disclosure further includes forming a planar layer covering the peripheral circuit and the common electrode lead; the common electrode is located away from the substrate of the planar layer One side of the substrate; the forming the planar layer includes forming a via in the planar layer exposing at least a portion of the common electrode lead, the common electrode being in direct contact with the common electrode lead at the via.
  • the substrate fabrication method provided by at least one embodiment of the present disclosure further includes forming a planar layer, the common electrode and the common electrode lead being formed on a side of the flat layer away from the substrate, and the common The electrode is in direct contact with at least a portion of the common electrode lead.
  • the substrate manufacturing method provided by at least one embodiment of the present disclosure further includes forming an electrostatic protection layer, wherein the electrostatic protection layer is formed on a side of the flat layer away from the substrate substrate and covers at least part of the periphery And electrically connected to the common electrode lead.
  • 1 is a schematic cross-sectional view of a substrate
  • FIG. 2A is a schematic plan view showing a planar structure of a substrate according to an embodiment of the present disclosure
  • 2B is a schematic plan view showing another substrate according to an embodiment of the present disclosure.
  • 2C is a schematic plan view showing another substrate according to an embodiment of the present disclosure.
  • Figure 3A is a cross-sectional structural view taken along line G-G' in Figure 2A or line I-I' in Figure 2B;
  • Figure 3B is a schematic cross-sectional view showing another structure along the line G-G' in Figure 2A or the line I-I' in Figure 2B;
  • Fig. 3B' is a schematic cross-sectional structural view taken along the line G-G' in Fig. 2A or the line I-I' in Fig. 2B;
  • Figure 3B is a schematic cross-sectional view of another cross-sectional view taken along the line G-G' in Figure 2A or the line I-I' in Figure 2B;
  • Figure 3C is a schematic cross-sectional structural view taken along the line G-G' in Figure 2A or the line I-I' in Figure 2B;
  • Figure 3C' is a schematic cross-sectional structural view taken along the line G-G' in Figure 2A or the line I-I' in Figure 2B;
  • Figure 3C is a schematic cross-sectional structural view taken along line G-G' in Figure 2A or line I-I' in Figure 2B;
  • Figure 3C"' is a schematic cross-sectional view along the line G-G' in Figure 2A or the line I-I' in Figure 2B;
  • 4A-4O are schematic diagrams of processes of a method for fabricating a substrate according to an embodiment of the present disclosure
  • 5A-5F are schematic diagrams of processes of a method for fabricating another substrate according to an embodiment of the present disclosure.
  • 6A-6B are schematic diagrams showing processes of a method for fabricating a substrate according to an embodiment of the present disclosure
  • FIG. 7 is a block diagram of an electronic device according to an embodiment of the present disclosure.
  • the substrate is a display substrate, for example, for forming an organic display device.
  • the display substrate includes a base substrate 201, a driving circuit 202, and a common electrode lead 103.
  • the display substrate includes a display area 1001 and a non-working area 1002 located around the display area 1001.
  • a driving circuit 202 is provided in the non-working area 1002 of the display substrate, and the driving circuit 202 is, for example, a gate driving circuit, for example, a gate driving circuit (GOA) integrated on the array substrate.
  • the common electrode lead 103 is disposed on the non-working area 1002 on the base substrate 201 and is located on a side of the driving circuit 202 remote from the display area 1001 and extends along an outer contour edge of the base substrate 201.
  • the display substrate further includes a planarization layer 1004 covering the driver circuit 202 and a portion of the common electrode lead 103. A portion of the planarization layer 1004 is also located between the driver circuit 202 and the common electrode lead 103 to insulate the driver circuit 202 from the common electrode lead 103.
  • the display substrate further includes a jumper electrode 109 and a common electrode 105.
  • the common electrode 105 is electrically connected to the common electrode lead 103 through the jumper electrode 109, that is, the jumper electrode 109 serves as a bridge for electrically connecting the common electrode 105 and the common electrode lead 103.
  • the common electrode 105 extends from the display region 1001 to the non-working region 1002 and is in contact with one end of the jumper electrode 109 near the display region 1001 to electrically connect the common electrode 105 and the jumper electrode 109; the jumper electrode 109 is away from the display region 1001 One end is in contact with the common electrode lead 103 to electrically connect the jumper electrode 109 with the common electrode lead 103, thereby electrically connecting the common electrode 105 and the common electrode lead 103.
  • the common electrode is electrically connected to the common electrode lead through the jumper electrode, the distance between the common electrode lead and the common electrode is large, the length of the jumper electrode is large, and the common electrode lead and the common The resistance between the electrodes is large.
  • this situation is not conducive to the reduction of the local and the overall voltage drop of the circuit, thereby affecting the transmission speed of the signal, and ultimately causing the brightness of the display screen to be uneven; on the other hand, the large resistance will cause the Joule heat to increase, The life of the display device to which the display substrate is applied is shortened.
  • the position error of the mask during the vapor deposition process causes the contact area of the common electrode and the jumper electrode, and the contact area between the jumper electrode and the common electrode lead is not fixed.
  • the contact area of the common electrode and the jumper electrode, the contact area of the jumper electrode and the common electrode lead are directly affected by the position of the vapor deposition mask, and the contact area size is not fixed, which may eventually cause the size error of the substrate to be excessively large. .
  • the mask position error during the evaporation process also causes the distance of the common electrode lead to the outer contour edge of the substrate to be not fixed. It is generally desirable to provide a dam on the substrate on one side of the common electrode lead 103 near the outer contour edge of the substrate for, for example, mating with an encapsulation layer or package substrate to effect encapsulation, the dam to the common electrode lead A certain distance is usually required to be reserved, and the distance is also affected by the position error of the vapor deposition mask. If the evaporation mask is too shifted toward the dam glue direction, the dam glue needs to be transferred between the vapor deposition masks. A larger margin is not conducive to the realization of a narrow bezel display device.
  • At least one embodiment of the present disclosure provides a substrate including a working area, a non-working area located around the working area, a base substrate, a peripheral circuit, and a common electrode lead; the peripheral circuit and the common electrode lead are disposed on the base substrate and Located in the non-working area; the common electrode lead is located on the side of the peripheral circuit near the working area.
  • FIG. 2A is a schematic diagram of a planar structure of a substrate according to an embodiment of the present disclosure
  • FIG. 2B is a schematic plan view of another substrate according to an embodiment of the present disclosure
  • FIG. 2C is a schematic diagram of an embodiment of the present disclosure.
  • a schematic diagram of a planar structure of another substrate, and FIG. 3A is a schematic cross-sectional structural view taken along line GG' of FIG. 2A or line I-I' of FIG. 2B.
  • the substrate 10 includes a working area 101, a non-working area 102 located around the working area 101, a base substrate 1, a peripheral circuit 2, a common electrode lead 3, and a common electrode 5, and a peripheral circuit 2 and a common
  • the electrode lead 3 is disposed on the base substrate 1 and located in the non-working area 102, the common electrode 5 extends from the working area 101 to the non-working area 102, and the common electrode lead 3 is located on the side of the peripheral circuit 2 near the working area 101; the common electrode 5 is in direct contact with at least a portion of the common electrode lead 3.
  • the base substrate 1 includes an outer contour edge 104.
  • the work area 101 may be a display area or a light-emitting area or the like
  • the non-work area 102 may be a non-display area or a non-light-emitting area or the like.
  • the non-work area 102 is, for example, not used for display, light emission, or the like, but may be provided with circuits, pads, interconnection structures, and the like for supporting and realizing functions such as display, light emission, and the like.
  • the peripheral circuit 2 (not shown in detail in the drawing) is disposed on the base substrate 1 and located in the non-working area 102.
  • the peripheral circuit 2 can be used, for example, to control the operating state of the working unit 14 in the working area 101.
  • the peripheral circuit 2 can be used to control the light emitting unit to emit light and not to emit light and to emit light.
  • the peripheral circuit 2 may be, for example, a drive circuit such as a gate drive circuit or a data drive circuit.
  • the type and specific structure of the peripheral circuit 2 are not limited in this embodiment.
  • the gate driving circuit may be a gate driving circuit (GOA) integrated on the array substrate.
  • the common electrode lead 3 is located on the base substrate 1 and disposed along a portion of the outer contour edge of the base substrate 1, that is, the common electrode lead 3 extends along a portion of the outer contour edge of the base substrate 1.
  • the common electrode lead 3 is located on the side of the peripheral circuit 2 close to the working area 101, which enables the common electrode lead 3 to be brought closer to the subsequently formed common electrode, thereby enabling the common electrode lead 3 to be in direct contact with the subsequently formed common electrode to achieve common
  • the electrode lead 3 is electrically connected to the common electrode to reduce the resistance of the signal from the common electrode lead 3 to the common electrode.
  • the common electrode lead 3 is a cathode lead.
  • the common electrode 5 extends from the work area 101 to the non-working area 102.
  • the common electrode 5 is in direct contact with a portion of the common electrode lead 3 to electrically connect the common electrode 5 with the common electrode lead 3.
  • the common electrode 5 is a cathode.
  • the common electrode lead 3 is in direct contact with the common electrode to achieve electrical connection, which can reduce the signal conduction from the common electrode lead to the common
  • the resistance of the circuit of the electrode is beneficial to increase the conduction speed of the signal between the common electrode lead and the common electrode.
  • the substrate is a display substrate
  • the brightness of the display screen can be made uniform, thereby obtaining a better display.
  • the reduction in the resistance of the circuit that conducts the signal from the common electrode lead to the common electrode is advantageous for reducing power consumption and Joule heat during operation, and reducing the temperature rise caused by Joule heat, thereby facilitating the extension of the device using the substrate For example, the life of the display device.
  • the common electrode 5 in the substrate 10 provided by the embodiment of the present disclosure, in the process of forming the common electrode 5 and the common electrode lead 3 by the vapor deposition method, even if there is a positional error of the vapor deposition mask, the common electrode 5 can be ensured.
  • the common electrode lead maintains a certain contact area, and therefore, it is not necessary to reserve an excessive margin between the common electrode lead 3 and the dam glue near the outer contour edge 104 of the base substrate 1, thereby facilitating the realization of a narrow bezel, and It is possible to avoid problems such as inconsistent dimensional errors of the substrate products or inconsistent uniformity of display brightness due to different positional errors of the vapor deposition mask in a plurality of productions.
  • the direct contact of the common electrode lead with the common electrode means that at least a portion of the common electrode lead is in contact with at least a portion of the common electrode, and the common electrode lead is not in contact with the common electrode.
  • the electrical resistance involved in conducting electrical signals from the common electrode lead to the common electrode is: resistance of the common electrode lead, contact resistance of the common electrode lead and the jumper electrode, resistance across the electrode, jumper The sum of the contact resistance of the electrode and the common electrode and the resistance of the common electrode.
  • the resistance involved in conducting signals from the common electrode lead to the common electrode is: the resistance of the common electrode lead, the contact resistance of the common electrode lead and the common electrode, and the sum of the resistances of the common electrode. Therefore, in the substrate provided by the embodiment of the present disclosure, the resistance of the circuit from which the signal is conducted from the common electrode lead to the common electrode is reduced as compared with the case where the common electrode lead is electrically connected to the common electrode by the jumper electrode.
  • the substrate 10 further includes a flat layer 4 covering the peripheral circuit 2 and the common electrode lead 3, while a portion of the flat layer 4 is located between the peripheral circuit 2 and the common electrode lead 3 to realize the peripheral circuit 2 It is insulated from the common electrode lead 3.
  • the common electrode 5 is located on a side of the flat layer 4 remote from the base substrate 1, and the flat layer 4 includes a via 401 exposing a portion of the common electrode lead 3, and the common electrode 5 is in direct contact with the common electrode lead 3 at the via 401 to realize The common electrode 5 is electrically connected to the common electrode lead 3.
  • the planar shape of the via 401 may be a dot shape, and may be, for example, a circle, an ellipse, a polygon (for example, a triangle, a rectangle, or the like).
  • the flat layer 4 may further include a via hole exposing a portion of the common electrode lead 3, the plane shape of the via hole being a strip shape, such as a rectangle, a wave, in a plane parallel to the board surface of the base substrate 1. Linear and so on.
  • the common electrode 5 is electrically connected to the common electrode lead 3 through the via.
  • the embodiment of the present disclosure does not limit the shape of the via hole.
  • the above-mentioned via holes may also expose the entire common electrode lead, which is not limited by the embodiment of the present disclosure.
  • the common electrode lead 3 and the peripheral circuit 2 are used to control the operating state of the work area 101.
  • the common electrode lead 3 and the peripheral circuit 2 may be located at a position on the left side of the substrate 10 near the outer contour edge thereof, and a control signal is input from the left side to the work area 101.
  • the common electrode lead 3 and the peripheral circuit 2 may be disposed at a position on the upper side of the substrate 10 near the outer contour edge thereof, and a control signal is input from the upper side to the work area 101.
  • the common electrode lead 3 and the peripheral circuit 2 may be disposed on opposite sides of the substrate 10, such as the positions of the left and right sides near the outer contour edge thereof.
  • the control signals can be simultaneously input to the working area 101 on both sides, and the technical effect of reducing the signal delay can be achieved, so that the substrate 10 can achieve a better working effect.
  • This technical effect is more prominent in the case where the planar area of the substrate 10 is large.
  • the material of the common electrode lead 3 and the common electrode 5 may be a transparent conductive material or an opaque conductive material.
  • the transparent conductive material may be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO) or the like;
  • the opaque conductive material may be, for example, a metal material such as copper, aluminum, a copper alloy, an aluminum alloy or the like having a high electrical conductivity.
  • the common electrode lead 3 and the common electrode 5 employ the above-described or other kinds of materials having a higher conductivity, which is advantageous for increasing the speed of common signal conduction.
  • the common electrode 5 is a transparent material.
  • work area 101 includes a plurality of work units 14 distributed in an array.
  • the plurality of work cells include array elements, for example, the array elements include a first electrode 7, a functional layer 8, and a second electrode 5.
  • the first electrode 7 is provided on the base substrate 1, for example, on the side of the flat layer 4 remote from the base substrate 1.
  • the functional layer 8 is disposed on a side of the first electrode 7 remote from the substrate 1 .
  • the second electrode is a common electrode disposed on a side of the functional layer 8 remote from the substrate 1 .
  • the functional layer 8 is an electroluminescent layer, such as an organic electroluminescent layer.
  • the array element may be an organic light emitting diode device, and the organic light emitting diode device may be a structure such as a top emission, a bottom emission, or the like.
  • an organic light emitting diode device includes an oppositely disposed anode and cathode and an organic light emitting layer between the anode and the cathode.
  • the first electrode 7 is an anode.
  • the common electrode lead 3 is a common cathode lead, and a low level signal is input to the common electrode 5 during operation.
  • the anode may be a reflective electrode or the anode includes a reflective layer (not shown).
  • the cathode may be a reflective electrode or the cathode includes a reflective layer.
  • the locations of the anode and cathode may be interchanged.
  • the anode may also be a common electrode 5, and the first electrode 7 is a cathode.
  • the common electrode lead 3 is a common anode lead, and a high level signal is input to the common electrode 5 during operation.
  • the substrate 10 further includes a pixel defining layer 6 to define a plurality of light emitting units or pixel units to prevent crosstalk between adjacent light emitting units or adjacent pixel units.
  • the pixel defining layer 6 includes an opening corresponding to the working cell 14, and the functional layer 8 is disposed at least in the opening, for example, the common electrode 5 covers the pixel defining layer 6.
  • the peripheral circuit 2 may be a gate drive circuit or a data drive circuit or the like.
  • the gate driving circuit or the data driving circuit may include a thin film transistor, a capacitor, a gate line lead, or a data line lead or the like according to different examples.
  • the substrate 10 can be a flexible substrate.
  • the substrate 10 further includes a flexible encapsulation layer including a first organic encapsulation layer 9, an inorganic encapsulation layer 11, and a second organic encapsulation layer 12.
  • the first organic encapsulation layer 9 covers the work area 101 and a portion of the non-working area 102.
  • the inorganic encapsulation layer 11 is disposed on the first organic encapsulation layer 9 and covers the work area 101 and a portion of the non-working area 102.
  • the second organic encapsulation layer 12 is disposed on the inorganic encapsulation layer 11 to cover the working area 101 and a portion of the non-working area 102 and cover a portion of the substrate substrate 1.
  • the first organic encapsulating layer 9 has a weak ability to block water and oxygen, and the inorganic encapsulating layer 11 has a good ability to block water and oxygen. Therefore, the inorganic encapsulating layer 11 can provide a flexible substrate with better water and oxygen resistance. The ability to protect the functional layer 8 disposed on the flexible substrate.
  • the material of the first organic encapsulating layer 9 and the second organic encapsulating layer 12 may be a combination of one or more of polyimide, polyester, and polyfluoride.
  • Polyimide has the characteristics of good light transmittance, high temperature resistance and bending resistance.
  • the materials of the first organic encapsulating layer 9 and the second organic encapsulating layer 12 are not limited to the types listed above.
  • the material of the inorganic encapsulation layer 11 may include silicon oxide or silicon nitride.
  • the material of the inorganic encapsulating layer 11 is not limited to the ones listed above. Any inorganic layer having a good ability to block water and oxygen can be applied.
  • the material of the base substrate 1 may be a combination of one or more of polyimide, polyester, and polyfluoride.
  • the material of the base substrate may be a combination of one or more of polyimide, polyester, and polyfluoride.
  • embodiments of the present disclosure do not limit the material of the base substrate.
  • FIG. 3B is another cross-sectional structural view taken along line G-G' in FIG. 2A or line I-I' in FIG. 2B, and FIG. 3B shows another substrate provided by an embodiment of the present disclosure.
  • the common electrode 5 and the common electrode lead 3 are located on the flat layer 4, and the common electrode 5 is directly overlapped on the partial common electrode lead 3 to be in direct contact with the common electrode lead 3.
  • the common electrode 5 may also be directly overlapped over the entire common electrode lead 3 to be in direct contact with the common electrode lead 3. Therefore, the technical effects similar to those of the substrate shown in FIG. 3A can be achieved. Please refer to the above description, and details are not described herein again.
  • the direct bonding of the common electrode and the common electrode lead means that a part of the common electrode overlaps with at least part of the common electrode lead in a direction perpendicular to the base substrate and a part of the common electrode Contact is made with at least a portion of the common electrode lead for electrical connection, and there are no other layers between the common electrode and the common electrode lead, both of which need not be connected through, for example, vias.
  • the flat layer 4 of the substrate 10 covers the peripheral circuit 2 and a portion of the base substrate 1, and a portion of the flat layer 4 is located between the common electrode lead 3 and the peripheral circuit 2 to insulate the common electrode lead 3 from the peripheral circuit 2.
  • the common electrode lead 3 may be disposed in the same layer as the first electrode 7. This can make the common electrode lead 3 and the first electrode 7 can be simultaneously formed by the same material through the same process, which is advantageous for simplifying the manufacturing process of the substrate 10 and improving the production efficiency.
  • a portion of the orthographic projection of the common electrode lead 3 on the base substrate 1 may coincide with a portion of the orthographic projection of the peripheral circuit 2 on the base substrate 1, which is advantageous for further reducing the border of the substrate.
  • FIG. 3B′ is another cross-sectional structural diagram along line GG′ in FIG. 2A or line I′′ in FIG. 2B
  • FIG. 3B′ illustrates another example provided by an embodiment of the present disclosure.
  • the common electrode 5 and the common electrode lead 3 are located on the flat layer 4, and one end of the common electrode 5 is butted to one end of the partial common electrode lead 3 to directly contact the common electrode with the common electrode lead. Therefore, the technical effects similar to those of the substrate shown in FIG. 3A can be achieved. Please refer to the above description, and details are not described herein again.
  • the one end of the common electrode and the one end of the partial common electrode lead mean that the common electrode and the partial common electrode lead are in direct contact only at the end, and the common electrode and the common electrode lead are lined.
  • the orthographic projections on the base substrate do not overlap.
  • FIG. 3B′′ is another cross-sectional structural diagram along the line GG′ in FIG. 2A or the line I′′ in FIG. 2B
  • FIG. 3B′′ shows another example provided by the embodiment of the present disclosure.
  • the common electrode 5 and the common electrode lead 3 are located on the flat layer 4, and the common electrode lead 3 is directly overlapped on the partial common electrode 5 to be in direct contact with the common electrode 5.
  • the common electrode lead 3 can also be directly overlapped on the entire common electrode 5 to directly contact the common electrode 5. This can also achieve similar technical effects as the substrate shown in FIG. 3A, please refer to the above description, here No longer.
  • FIG. 3C is a schematic cross-sectional structural view taken along the line G-G' in FIG. 2A or the line I-I' in FIG. 2B, and FIG. 3C shows still another substrate provided by an embodiment of the present disclosure.
  • the substrate shown in FIG. 3C is different from the substrate shown in FIG. 3A in that the substrate 10 further includes an electrostatic protection layer 13 disposed on a side of the planar layer 4 remote from the substrate 1 and covering the peripheral circuit 2 and Electrically connected to the common electrode lead 3, for example, the common electrode 5 is disposed on the electrostatic protection layer 13, and the common electrode 5 is directly overlapped on the electrostatic protection layer 13, and the end of the electrostatic protection layer 13 near the common electrode lead 3 passes through the via hole.
  • the 401 is in direct contact with the common electrode lead 3 to electrically connect the electrostatic protection layer 13 with the common electrode lead 3.
  • other via holes may be formed on the flat layer such that one end of the electrostatic protection layer 13 close to the common electrode lead 3 is in direct contact with the common electrode lead 3 through the other via holes, instead of using one via hole with the common electrode.
  • the electrostatic protection layer 13 can conduct static electricity outside the peripheral circuit 2 through the common electrode lead to prevent electrostatic charges from entering the peripheral circuit 2 and causing interference with the operating state of the peripheral circuit 2.
  • the electrostatic protection layer 13 and the common electrode lead 3 can be used as a part of the static electricity prevention circuit, and when it is necessary to provide the static electricity prevention circuit on the substrate 10, the components of the substrate 10 can be simplified.
  • Fig. 3C' is a schematic cross-sectional structural view taken along the line G-G' in Fig. 2A or the line I-I' in Fig. 2B, and Fig. 3C' shows still another substrate provided by the embodiment of the present disclosure.
  • the substrate shown in FIG. 3C′ is different from the substrate shown in FIG. 3B in that the substrate 10 further includes an electrostatic protection layer 13 disposed on a side of the planar layer 4 remote from the substrate 1 and covering the peripheral circuit 2 .
  • the electrostatic protection layer 13 is directly overlapped on at least part of the common electrode lead 3, so that the electrostatic protection layer 13 is electrically connected to the common electrode lead 3.
  • the electrostatic protection layer 13 can conduct static electricity outside the peripheral circuit 2 through the common electrode lead to prevent electrostatic charges from entering the peripheral circuit 2 and causing interference with the operating state of the peripheral circuit 2.
  • the electrostatic protection layer 13 and the common electrode lead 3 can be used as a part of the static electricity prevention circuit, and when it is necessary to provide the static electricity prevention circuit on the substrate 10, the components of the substrate 10 can be simplified.
  • FIG. 3C" is a schematic cross-sectional structural view taken along line G-G' in FIG. 2A or line I-I' in FIG. 2B, and FIG. 3C" shows still another substrate provided by an embodiment of the present disclosure.
  • the substrate shown in FIG. 3C” is different from the substrate shown in FIG. 3B in that the substrate 10 further includes an electrostatic protection layer 13 disposed on a side of the flat layer 4 remote from the substrate 1 and covering the peripheral circuit 2 And electrically connected to the common electrode lead 3, for example, the common electrode lead 3 directly overlaps at least part of the electrostatic protection layer 13 to electrically connect the electrostatic protection layer 13 with the common electrode lead 3.
  • the electrostatic protection layer 13 can be used to surround the peripheral circuit 2
  • the external static electricity is conducted through the common electrode lead to prevent electrostatic charges from entering the peripheral circuit 2 to interfere with the operating state of the peripheral circuit 2.
  • the electrostatic protection layer 13 and the common electrode lead 3 can be used as part of the static electricity prevention circuit when needed When the static electricity prevention circuit is provided on the substrate 10, the components of the substrate 10 can be simplified.
  • FIG. 3C′′ is another cross-sectional structural view along line GG′ in FIG. 2A or line I′′ in FIG. 2B
  • FIG. 3C′′ shows another substrate provided by an embodiment of the present disclosure.
  • the substrate shown in FIG. 3C′ is different from the substrate shown in FIG. 3B in that the substrate 10 further includes an electrostatic protection layer 13 disposed on a side of the flat layer 4 remote from the substrate 1 and covering the peripheral circuit 2 And electrically connected to the common electrode lead 3, for example, the other end of the common electrode lead 3 is butted to one end of the electrostatic protection layer 13 to electrically connect the electrostatic protection layer 13 with the common electrode lead 3.
  • the electrostatic protection layer 13 can be used to the peripheral circuit 2
  • the external static electricity is conducted through the common electrode lead to prevent electrostatic charges from entering the peripheral circuit 2 to interfere with the operating state of the peripheral circuit 2.
  • the electrostatic protection layer 13 and the common electrode lead 3 can be used as part of the static electricity prevention circuit when needed
  • the static electricity prevention circuit is provided on the substrate 10, the components of the substrate 10 can be simplified.
  • the other end of the common electrode lead and the one end of the electrostatic protection layer mean that the common electrode lead and the electrostatic protection layer are in direct contact only at the end, and the common electrode lead and the electrostatic protection layer The orthographic projections on the base substrate do not overlap.
  • the substrate provided by the embodiment of the present disclosure may be used for an electronic device such as a display device, a lighting device, or the like.
  • the substrate provided by the embodiments of the present disclosure may be a flexible substrate for a flexible display panel, a light emitting panel, or the like.
  • FIG. 7 is a block diagram of an electronic device according to an embodiment of the present disclosure.
  • the electronic device includes any one of the substrates provided by the embodiments of the present disclosure.
  • the electronic device can be a display device, for example, the display device can be an organic light emitting diode display device.
  • the display device can be a flexible display device.
  • the display device can be implemented as a product, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, an electronic advertisement screen, or the like.
  • the electronic device can also be a lighting device, for example, the lighting device can be a decorative light fixture or the like.
  • FIG. 7 is a block diagram of a display device including any of the substrates provided by the embodiments of the present disclosure. Other structures of the display device are not shown. Those skilled in the art may refer to the conventional technology, which is not limited by the embodiments of the present disclosure.
  • the electronic device provided by the embodiments of the present disclosure can reduce the resistance of the common electrode lead and the common electrode to achieve electrical connection, which is advantageous for improving the conduction speed of the signal between the common electrode lead and the common electrode, for example, when the substrate is a light-emitting substrate, for example When the substrate is displayed, the uniformity of brightness of the display screen can be made higher, and a better display effect can be obtained; and the reduction of the electrical connection between the common electrode lead and the common electrode for electrical connection is advantageous for reducing power consumption during operation of the electronic device. And Joule heat, which reduces the temperature rise caused by Joule heat, thereby contributing to the improvement of the life of the electronic device.
  • the electronic device provided by the embodiment of the present disclosure can also implement a narrow frame.
  • At least one embodiment of the present disclosure further provides a substrate manufacturing method, the substrate includes a working area and a non-working area located around the working area, the manufacturing method includes: providing a substrate; on the substrate and in the non-working area Forming a peripheral circuit and a common electrode lead; forming a common electrode in the working area and the non-working area; wherein the common electrode lead is located on a side of the peripheral circuit adjacent to the working area; and the common electrode is in direct contact with at least a portion of the common electrode lead.
  • FIGS. 4A-4O are schematic diagrams of processes of a method of fabricating a substrate according to an embodiment of the present disclosure.
  • the following is an exemplary introduction of a substrate forming a working region including an organic light emitting diode device.
  • a base substrate 1 is provided.
  • the base substrate 1 may be, for example, a glass substrate, a quartz substrate, a resin (for example, polyethylene) substrate, or the like, or may be a flexible substrate made of, for example, polyimide.
  • the base substrate 1 includes an outer contour edge, and a working area 101 included in the substrate to be formed and a non-working area 102 located around the working area 101 correspond to an area on the base substrate 1 as shown in FIG. 4A.
  • a peripheral circuit 2 is provided in the non-working area 102 of the substrate, which may be, for example, a driving circuit such as a gate driving circuit or a data driving circuit.
  • a driving circuit such as a gate driving circuit or a data driving circuit.
  • the specific manufacturing method of the peripheral circuit 2 can refer to the conventional technology by those skilled in the art.
  • the common electrode lead 3 is located on the side of the peripheral circuit 2 close to the working area 101 so as to be in direct contact with the subsequently formed common electrode extending from the working area 101 to the non-working area 102. Also, a certain distance is left between the common electrode lead 3 and the peripheral circuit 2 for insulating the common electrode lead 3 from the peripheral circuit 2.
  • the material of the common electrode lead 3 may be, for example, a transparent conductive material or an opaque conductive material, and the transparent conductive material may be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), etc., and the opaque conductive material may be, for example, a metal material. For example, copper, aluminum, copper alloy, etc. having a high electrical conductivity.
  • the common electrode lead 3 can be formed by a method such as chemical vapor deposition, magnetron sputtering, or vapor deposition in conjunction with a mask.
  • the method further includes forming a planar layer 4.
  • the flat layer 4 covers the peripheral circuit 2 and the common electrode lead 3.
  • a portion of the flat layer 4 is located between the common electrode lead 3 and the peripheral circuit 2 to insulate the common electrode lead 3 from the peripheral circuit 2.
  • the material of the flat layer 4 may be an insulating material while serving as an insulating layer.
  • the insulating material may be, for example, an inorganic material or an organic material, for example, a resin material such as a polyethylene resin, a polyacryl resin, a polyester resin, a polyamide resin, or the like.
  • the material of the flat layer 4 is not limited in the embodiment of the present disclosure.
  • a planarization process is performed on the flat layer 4, and a via hole 401 exposing a portion of the common electrode lead is formed in the flat layer 4.
  • the patterning process can be photolithography.
  • the recess of the common electrode lead may be formed by patterning the flat layer 4, which is a special form of via.
  • a pre-pixel defining layer 601 is formed over the planar layer 4, and the pre-pixel defining layer 601 can be formed, for example, by coating.
  • the material of the pre-pixel defining layer 601 may be a photosensitive material to facilitate subsequent photolithography processes.
  • the photosensitive material may include a photoresist material and a metal halide such as a silver halide (for example, AgCl or AgBr).
  • the material of the pre-pixel defining layer 601 may also be a dark material, such as black resin, metallic chromium or chromium oxide, etc., and the desired pattern can be obtained by a patterning method such as printing, photolithography or the like.
  • the material of the pre-pixel defining layer 601 may also be other materials, and those skilled in the art may also select as needed.
  • the pixel defining layer 6 is formed by patterning the pre-pixel defining layer 601.
  • the pixel defining layer 6 has an opening.
  • the pixel defining layer 6 defines a plurality of working units distributed in an array in the working area 101, that is, a plurality of working units distributed in an array are formed in the working area 101.
  • the patterning process can be a photolithography process.
  • the pixel defining layer 6 may be formed by an exposure-developing process.
  • the metal halide is a low optical density material when not exposed, and after exposure Decomposition forms metal particles which, due to small particles, appear black and have a high optical density value.
  • the photoresist material is a negative photoresist material which becomes insoluble in the developer after exposure and remains, so that the pixel defining layer 6 can be formed.
  • the first electrode 7 may be formed on the flat layer 4 by, for example, a method of vapor deposition or deposition in conjunction with a mask, and the first electrode 7 is, for example, an anode.
  • the pre-first electrode layer 701 is first formed by evaporation, magnetron sputtering deposition, or chemical vapor deposition, and then the first electrode 7 as shown in FIG. 4I is formed by a photolithography process.
  • the first electrode 7 is located in the opening of the pixel defining layer 6 in each working cell.
  • the functional layer 8 on the side of the first electrode 7 remote from the substrate 1 is formed by a deposition method or the like in cooperation with the mask.
  • the functional layer 8 is an organic light-emitting layer.
  • the pre-functional layer 801 is formed by a coating method, and then the functional layer 8 as shown in FIG. 4K is formed by photolithography, for example, the functional layer 8 is located in the pixel defining layer 6 in each working cell. In the opening.
  • the common electrode 5 is formed.
  • the common electrode 5 is a cathode.
  • the common electrode 5 may be an anode and the first electrode 7 may be a cathode.
  • the common electrode 5 covers the pixel defining layer 6 and extends from the working area 101 to the non-working area 102. In the non-working area 102, the common electrode 5 can be in direct contact with the common electrode lead 3 through the via 401 to electrically connect the common electrode 5 with the common electrode lead 3.
  • the direct contact between the common electrode 5 and the common electrode lead 3 please refer to the description in the previous embodiment, and details are not described herein again.
  • the substrate fabrication method further includes forming a flexible encapsulation layer.
  • Forming the flexible encapsulation layer includes forming a first organic encapsulation layer, an inorganic encapsulation layer, and a second organic encapsulation layer.
  • a first organic encapsulation layer 9 covering the working area 101 and a portion of the non-working area 102 is formed.
  • the material of the first organic encapsulating layer 9 may be a combination of one or more of polyimide, polyester, and polyfluoride. Polyimide has the characteristics of good light transmittance, high temperature resistance and bending resistance.
  • the material of the first organic encapsulating layer 9 is not limited to the above-listed types.
  • the first organic encapsulating layer 9 can be formed by a coating method.
  • an inorganic encapsulation layer 11 disposed on the first organic encapsulation layer 9 is formed.
  • the material of the inorganic encapsulation layer 11 may include silicon oxide or silicon nitride.
  • the material of the inorganic encapsulating layer 11 is not limited to the above-listed types. Any inorganic layer having a good ability to block water and oxygen can be used.
  • the inorganic encapsulating layer 11 can be formed by a method such as evaporation, chemical vapor deposition, or magnetron sputtering deposition.
  • a second organic encapsulation layer 12 disposed on the inorganic encapsulation layer 11 and covering a portion of the substrate 1 is formed.
  • the material and formation method of the second organic encapsulation layer 12 are the same as those of the first organic encapsulation layer 9.
  • the substrate as shown in Fig. 4O can be formed by the above method.
  • the substrate can also be a non-flexible substrate.
  • FIGS. 5A-5F are schematic diagrams of processes of a method for fabricating another substrate according to an embodiment of the present disclosure. After forming the structure as shown in FIG. 4B, a flat layer 4 as shown in FIG. 5A is formed, and the flat layer 4 covers the peripheral circuit 2. Please refer to the above description for the material and formation method of the flat layer.
  • the pixel defining layer 6 is formed in the same manner as shown in FIGS. 4F-4G.
  • the common electrode lead 3 and the first electrode 7 may be simultaneously formed on the side of the flat layer 4 remote from the base substrate 1, that is, the common electrode lead 3 and the first electrode 7 may be simultaneously formed by the same process, Simplify the fabrication process of the substrate.
  • the functional layer 8 is formed in the same manner as shown in Fig. 4K.
  • the common electrode 5 is formed on the side of the flat layer 4 remote from the base substrate 1.
  • the common electrode 5 covers the pixel defining layer 6 and extends from the working area 101 to the non-working area 102.
  • the common electrode 5 and the partial common electrode lead 3 are directly overlapped to directly contact each other to electrically connect the common electrode 5 with the common electrode lead 3.
  • the common electrode 5 may be in direct contact with at least a portion of the common electrode lead 3 on a plane parallel to the surface of the substrate 1 to achieve the common electrode 5. It is electrically connected to the common electrode lead 3, that is, the portion where the common electrode 5 and the partial common electrode lead 3 are directly overlapped is removed. The subsequent process is based on the structure shown in Figure 5E.
  • the first organic encapsulating layer 9, the inorganic encapsulating layer 11, and the second organic encapsulating layer 12 are sequentially formed by the same method as that shown in FIGS. 4M to 4O, and a substrate as shown in FIG. 5F can be formed.
  • the manufacturing method shown in 5A-5F can achieve the same or similar technical effects as the manufacturing method shown in FIGS. 4A-4O, and other technical features of the method are the same as those shown in FIGS. 4M-4O, please refer to the above description.
  • FIGS. 6A-6B are schematic diagrams showing processes of a method of fabricating a substrate provided by an embodiment of the present disclosure.
  • the method also includes forming an electrostatic protection layer.
  • the electrostatic protection layer 13 and the first electrode 7 are simultaneously formed by the same process.
  • the electrostatic protection layer 13 covers the peripheral circuit 2 and is electrically connected to the common electrode lead 3.
  • One end of the electrostatic protection layer 13 close to the common electrode lead 3 is directly overlapped with the common electrode lead 3 through the via 401 to directly contact, so that the electrostatic protection layer 13 is electrically connected to the common electrode lead 3.
  • the electrostatic protection layer 13 can conduct static electricity outside the peripheral circuit 2 through the common electrode lead to prevent electrostatic charges from entering the peripheral circuit 2 and causing interference with the operating state of the peripheral circuit 2.
  • the electrostatic protection layer 13 and the common electrode lead 3 can be used as a part of the static electricity prevention circuit, and when it is necessary to provide the static electricity prevention circuit on the substrate 10, the components of the substrate 10 can be simplified.
  • the electrostatic protection layer 13 and the first electrode 7 are simultaneously formed by the same process to facilitate the fabrication process of the substrate.
  • the first organic encapsulating layer 9, the inorganic encapsulating layer 11, and the second organic encapsulating layer 12 are sequentially formed by the same method as that shown in FIGS. 4M to 4O, and a substrate as shown in FIG. 6B can be formed.
  • Embodiments of the present disclosure provide a substrate, a method of fabricating the same, and an electronic device.
  • a common electrode lead is located on a side of the peripheral circuit adjacent to the working area, which enables the common electrode lead to be closer to the common
  • the electrodes are such that the common electrode lead can be in direct contact with at least the common electrode to effect electrical connection of the common electrode lead to the common electrode.
  • the common electrode lead is in direct contact with the common electrode to achieve electrical connection, which can reduce the resistance of the circuit in which the signal is conducted from the common electrode lead to the common electrode.
  • the substrate is a light-emitting substrate such as a display substrate
  • brightness uniformity of the display screen can be made higher, and a better display effect can be obtained
  • the reduction of the resistance is advantageous for reducing power consumption and Joule heat during operation, and reducing temperature rise caused by Joule heat, thereby contributing to improving the life of a device to which the substrate is applied, such as a display device.
  • the common electrode for the substrate provided in the embodiment of the present disclosure, for example, in the process of forming the common electrode and the common electrode lead by the vapor deposition method, even if there is a position error of the vapor deposition mask, it can be ensured.
  • the common electrode maintains a certain contact area with the common electrode lead, and therefore, it is not necessary to reserve an excessive margin between the common electrode lead and the dam glue near the outer contour edge of the substrate substrate, thereby facilitating the realization of the narrow frame, and It is possible to avoid problems such as inconsistent dimensional errors of the substrate products or inconsistent uniformity of display brightness due to different positional errors of the vapor deposition mask in a plurality of productions.

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Abstract

一种基板及其制作方法、电子装置。该基板（10）包括工作区域（101）、位于工作区域（101）周边的非工作区（102）；衬底基板（1）；位于衬底基板（1）上且位于非工作区（102）的周边电路（2）和公共电极引线（3）；其中，公共电极引线（3）位于周边电路（2）的靠近工作区域（101）的一侧。在该基板（10）中，公共电极引线（3）能够与公共电极直接接触以实现公共电极引线（3）与公共电极电连接，从而能够减小信号由公共电极引线（3）传导至公共电极的电路的电阻，并且应用该基板（10）的电子装置能够具有较窄的边框。

Description

基板及其制作方法、电子装置
本申请要求于2018年3月30日递交的中国专利申请第201810293281.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种基板及其制作方法、电子装置。
背景技术
在显示基板中，电路(例如驱动电路)中的连接线的电阻偏大会造成电路中信号传输速度减慢，从而造成显示画面亮度不均等问题，影响显示质量。另外，随着显示技术的发展，人们对窄边框的要求也越来越高。
发明内容
本公开至少一实施例提供一种基板，该基板包括：工作区域、位于所述工作区域周边的非工作区；衬底基板；位于所述衬底基板上且位于所述非工作区的周边电路和公共电极引线；其中，所述公共电极引线位于所述周边电路的靠近所述工作区域的一侧。
例如，本公开至少一实施例提供的基板还包括公共电极，其中，所述公共电极由所述工作区域延伸至所述非工作区；所述公共电极与至少部分所述公共电极引线直接接触。
例如，在本公开至少一实施例提供的基板中，所述周边电路为栅极驱动电路，所述公共电极为阴极，所述公共电极引线为阴极引线。
例如，本公开至少一实施例提供的基板还包括覆盖所述周边电路和所述公共电极引线的平坦层，其中，所述公共电极位于所述平坦层的远离所述衬底基板的一侧；所述平坦层包括暴露至少部分所述公共电极引线的过孔，所述公共电极在所述过孔处与所述公共电极引线直接接触。
例如，本公开至少一实施例提供的基板还包括静电保护层，其中，所述静电保护层设置在所述平坦层的远离所述衬底基板的一侧且覆盖至少部 分所述周边电路，且所述静电保护层在所述过孔处与所述公共电极引线电连接。
例如，本公开至少一实施例提供的基板还包括平坦层，其中，所述公共电极和所述公共电极引线位于所述平坦层的远离所述衬底基板的一侧，且所述公共电极与至少部分所述公共电极引线直接接触。
例如，在本公开至少一实施例提供的基板中，所述公共电极直接搭接于至少部分所述公共电极引线上以和所述公共电极引线直接接触。
例如，在本公开至少一实施例提供的基板中，所述公共电极引线直接搭接于至少部分所述公共电极上以和所述公共电极直接接触。
例如，在本公开至少一实施例提供的基板中，所述公共电极的一端与所述公共电极引线的一端对接以使所述公共电极与所述公共电极引线直接接触。
例如，在本公开至少一实施例提供的基板中，所述工作区域包括多个呈阵列分布的工作单元，每个所述工作单元包括：第一电极，设置于所述衬底基板上；功能层，设置于所述第一电极的远离所述衬底基板的一侧；第二电极，设置于所述功能层的远离所述衬底基板的一侧；其中，所述第二电极为所述公共电极。
例如，在本公开至少一实施例提供的基板中，所述公共电极引线与所述第一电极同层设置。
例如，本公开至少一实施例提供的基板还包括静电保护层，所述静电保护层设置在所述平坦层的远离所述衬底基板的一侧且覆盖至少部分所述周边电路且与所述公共电极引线电连接。
例如，在本公开至少一实施例提供的基板中，所述静电保护层直接搭接于至少部分所述公共电极引线上以和所述公共电极引线电连接。
例如，在本公开至少一实施例提供的基板中，所述公共电极引线直接搭接于至少部分所述静电保护层上以和所述静电保护层电连接。
例如，在本公开至少一实施例提供的基板中，所述公共电极引线的另一端与所述静电保护层的一端对接以使所述公共电极引线与所述静电保护层电连接。
本公开至少一实施例还提供一种电子装置，包括上述任一实施例提供 的基板。
本公开至少一实施例还提供一种基板的制作方法，该基板包括工作区域和位于所述工作区域周边的非工作区，该制作方法包括：提供衬底基板；在所述衬底基板上且在所述非工作区中形成周边电路和公共电极引线；其中，所述公共电极引线位于所述周边电路的靠近所述工作区域的一侧。
例如，本公开至少一实施例提供的基板制作方法还包括形成公共电极，所述公共电极由所述工作区域延伸至所述非工作区，所述公共电极与至少部分所述公共电极引线直接接触。
例如，本公开至少一实施例提供的基板制作方法还包括形成平坦层，所述平坦层覆盖所述周边电路和所述公共电极引线；所述公共电极位于所述平坦层的远离所述衬底基板的一侧；所述形成平坦层包括在所述平坦层中形成暴露至少部分所述公共电极引线的过孔，所述公共电极在所述过孔处与所述公共电极引线直接接触。
例如，本公开至少一实施例提供的基板制作方法还包括形成平坦层，所述公共电极和所述公共电极引线形成于所述平坦层的远离所述衬底基板的一侧，且所述公共电极与至少部分所述公共电极引线直接接触。
例如，本公开至少一实施例提供的基板制作方法还包括形成静电保护层，其中，所述静电保护层形成在所述平坦层的远离所述衬底基板的一侧且覆盖至少部分所述周边电路且与所述公共电极引线电连接。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种基板的截面结构示意图；
图2A为本公开一实施例提供的一种基板的平面结构示意图；
图2B为本公开一实施例提供的另一种基板的平面结构示意图；
图2C为本公开一实施例提供的又一种基板的平面结构示意图；
图3A为沿图2A中的G-G’线或图2B中的I-I’线的一种剖面结构示意图；
图3B为沿图2A中的G-G’线或图2B中的I-I’线的另一种剖面结构 示意图；
图3B’为沿图2A中的G-G’线或图2B中的I-I’线的另一种剖面结构示意图；
图3B”为沿图2A中的G-G’线或图2B中的I-I’线的另一种剖面结构示意图；
图3C为沿图2A中的G-G’线或图2B中的I-I’线的又一种剖面结构示意图；
图3C’为沿图2A中的G-G’线或图2B中的I-I’线的又一种剖面结构示意图；
图3C”为沿图2A中的G-G’线或图2B中的I-I’线的又一种剖面结构示意图；
图3C”’为沿图2A中的G-G’线或图2B中的I-I’线的又一种剖面结构示意图；
图4A-4O为本公开一实施例提供的一种基板的制作方法的过程示意图；
图5A-5F为本公开一实施例提供的另一种基板的制作方法的过程示意图；
图6A-6B本公开一实施例提供的又一种基板的制作方法的过程示意图；以及
图7为本公开一实施例提供的一种电子装置的框图。
具体实施方式
为使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包 含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的附图的尺寸并不是严格按实际比例绘制，基板中阵列单元的个数也不是限定为图中所示的数量。本公开的附图中各个结构的具体地尺寸和数量可根据实际需要进行确定。本公开中所描述的附图仅是结构示意图。
图1为一种基板的截面结构示意图，例如，该基板为一种显示基板，该显示基板例如用于形成有机显示装置。如图1所示，该显示基板包括衬底基板201、驱动电路202和公共电极引线103。该显示基板包括显示区域1001和位于显示区域1001周边的非工作区1002。在该显示基板的非工作区1002设置有驱动电路202，驱动电路202例如为栅驱动电路，例如为集成在阵列基板上的栅驱动电路(GOA)。公共电极引线103设置于衬底基板201上的非工作区1002，并位于驱动电路202的远离显示区域1001的一侧且沿衬底基板201的外轮廓边缘延伸。
该显示基板还包括覆盖驱动电路202和部分公共电极引线103的平坦层1004，平坦层1004的一部分还位于驱动电路202和公共电极引线103之间，以使驱动电路202与公共电极引线103绝缘。该显示基板还包括跨接电极109和公共电极105，公共电极105通过跨接电极109与公共电极引线103电连接，即跨接电极109作为实现公共电极105与公共电极引线103电连接的桥梁。公共电极105从显示区域1001延伸至非工作区1002并且与跨接电极109的靠近显示区域1001的一端接触，以实现公共电极105和跨接电极109电连接；跨接电极109的远离显示区域1001的一端与公共电极引线103接触，以实现跨接电极109与公共电极引线103电连接，从而实现公共电极105与公共电极引线103电连接。
在图1所示的显示基板中，公共电极通过跨接电极与公共电极引线实现电连接，公共电极引线与公共电极之间的距离较大，跨接电极的长度较大，公共电极引线与公共电极之间的电阻较大。一方面，这种情况不利于局部及电路整体压降的减小，从而影响信号的传输速度，最终造成显示屏幕亮度不均一的现象；另一方面，该电阻较大会导致焦耳热增大，会缩短 应用该显示基板的显示装置的寿命。此外，在蒸镀形成公共电极和跨接电极时，蒸镀过程中的掩模位置误差会造成公共电极和跨接电极的接触面积、跨接电极与公共电极引线的接触面积大小不固定，因此公共电极和跨接电极的接触面积、跨接电极与公共电极引线的接触面积大小直接受蒸镀掩模的位置的影响，该接触面积大小不固定最终可能导致基板的尺寸误差过大的问题出现。
另外，蒸镀过程中的掩模位置误差还会造成公共电极引线到基板的外轮廓边缘的距离不固定。通常需要在基板上设置位于公共电极引线103的靠近基板的外轮廓边缘的一侧的坝胶(Dam)，以用于例如与封装层或封装基板配合以实现封装，该坝胶到公共电极引线之间通常需要预留一定的距离，该距离也会受到蒸镀掩模的位置误差的影响，若蒸镀掩模过于往坝胶方向偏移，则需要坝胶到蒸镀掩模之间的预留余量更大，则不利于实现窄边框的显示装置。
本公开至少一实施例提供一种基板，该基板包括工作区域、位于工作区域周边的非工作区、衬底基板、周边电路和公共电极引线；周边电路和公共电极引线设置于衬底基板上且位于非工作区；公共电极引线位于周边电路的靠近工作区域的一侧。
示范性地，图2A为本公开一实施例提供的一种基板的平面结构示意图，图2B为本公开一实施例提供的另一种基板的平面结构示意图，图2C为本公开一实施例提供的又一种基板的平面结构示意图，图3A为沿图2A中的G-G’线或图2B中的I-I’线的一种剖面结构示意图。
如图2A和图3A所示，基板10包括工作区域101、位于工作区域101周边的非工作区102、衬底基板1、周边电路2、公共电极引线3和公共电极5，周边电路2和公共电极引线3设置于衬底基板1上且位于非工作区102，公共电极5由工作区域101延伸至非工作区102，公共电极引线3位于周边电路2的靠近工作区域101的一侧；公共电极5与至少部分公共电极引线3直接接触。
例如，衬底基板1包括外轮廓边缘104。例如，对于显示装置或照明装置而言，工作区域101可以为显示区域或发光区域等，相应地，非工作区102可以为非显示区或非发光区等。非工作区102例如虽然非用于显示、发光等，但是其中可以设置有用于支持和实现显示、发光等功能的电路、 焊盘、互联结构等。周边电路2(图中未具体示出周边电路结构)设置于衬底基板1上且位于非工作区102，周边电路2例如可以用于控制工作区域101内的工作单元14的工作状态。例如，当工作单元14为发光单元时，周边电路2可以用于控制发光单元发光与不发光以及发光强度。周边电路2例如可以是驱动电路，例如栅驱动电路或数据驱动电路等。对于周边电路2的类型和具体结构本实施不作限定，例如栅极驱动电路可以为集成于阵列基板上的栅极驱动电路(GOA)。
公共电极引线3位于衬底基板1上且沿衬底基板1的部分外轮廓边缘设置，即公共电极引线3沿衬底基板1的部分外轮廓边缘延伸。公共电极引线3位于周边电路2的靠近工作区域101的一侧，这能够使得公共电极引线3更加靠近后续形成的公共电极，从而使公共电极引线3能够与后续形成的公共电极直接接触以实现公共电极引线3与公共电极电连接，以减小信号从公共电极引线3传导至公共电极的电阻。例如，该公共电极引线3为阴极引线。
例如，公共电极5由工作区域101延伸至非工作区102。公共电极5与部分公共电极引线3直接接触，以实现公共电极5与公共电极引线3电连接。例如，该公共电极5为阴极。与通过跨接电极实现公共电极引线3与公共电极5电连接的情况相比，一方面，公共电极引线3与公共电极直接接触而实现电连接，这能够减小信号由公共电极引线传导至公共电极的电路的电阻，有利于提高信号在公共电极引线和公共电极之间的传导速度，例如，当该基板为显示基板时，可以使显示画面的亮度均一性更高，从而获得更好的显示效果；并且，信号由公共电极引线传导至公共电极的电路的电阻减小有利于减小工作过程中的功耗和焦耳热，降低焦耳热导致的温升，从而有利于延长应用该基板的装置例如显示装置的寿命。
另一方面，对于本公开的实施例提供的基板10，在用蒸镀法形成公共电极5和公共电极引线3的过程中，即使存在蒸镀掩模的位置误差，也可以保证公共电极5与公共电极引线保持一定的接触面积，因此，不需要在公共电极引线3和靠近衬底基板1的外轮廓边缘104的坝胶之间预留过大的余量，从而有利于实现窄边框，而且能够避免因为在多次生产中由于蒸镀掩模的位置误差不同而导致的基板产品的尺寸误差不一致或者显示亮度的均匀性不一致等问题。
需要说明的是，在本公开的实施例中，公共电极引线与公共电极直接接触是指：公共电极引线的至少部分与公共电极的至少部分之间接触，公共电极引线与公共电极在接触处不存在其他的用于连接这两者的部件(例如跨接电极、导线等)。
在图1所示的基板中，电信号从公共电极引线传导至公共电极所涉及的电阻为：公共电极引线的电阻、公共电极引线与跨接电极的接触电阻、跨接电极的电阻、跨接电极与公共电极的接触电阻以及公共电极的电阻之和。在本公开的实施例提供的基板中，信号从公共电极引线传导至公共电极所涉及的电阻为：公共电极引线的电阻、公共电极引线与公共电极的接触电阻以及公共电极的电阻之和。因此，与通过跨接电极实现公共电极引线与公共电极电连接的情况相比，在本公开的实施例提供的基板中，信号从公共电极引线传导至公共电极的电路的电阻减小。
例如，如图3A所示，基板10还包括覆盖周边电路2和公共电极引线3的平坦层4，同时，部分平坦层4位于周边电路2和公共电极引线3之间，以实现将周边电路2和公共电极引线3绝缘。公共电极5位于平坦层4的远离衬底基板1的一侧，平坦层4包括暴露部分公共电极引线3的过孔401，公共电极5在过孔401处与公共电极引线3直接接触，以实现公共电极5与公共电极引线3电连接。例如，在平行于衬底基板1板面的平面上，过孔401的平面形状可以为点状，例如可以为圆形、椭圆形、多边形(例如三角形、矩形等)等。
当然，在其他示例中，平坦层4还可以包括暴露部分公共电极引线3的过孔，在平行于衬底基板1板面的平面上，该过孔的平面形状为条形，例如矩形、波浪线形等。公共电极5通过该过孔与公共电极引线3电连接。本公开的实施例对该过孔的形状不作限定。当然，在本公开的其他实施例中，上述过孔也可以暴露整个公共电极引线，本公开的实施例对此不作限定。
公共电极引线3和周边电路2用于控制工作区域101的工作状态。例如，如图2A所示，公共电极引线3和周边电路2可以位于基板10的左侧的靠近其外轮廓边缘的位置，从左侧向工作区域101输入控制信号。例如，如图2B所示，公共电极引线3和周边电路2也可以设置于基板10的上侧的靠近其外轮廓边缘的位置，从上侧向工作区域101输入控制信号。又例 如，如图2C所示，公共电极引线3和周边电路2还可以设置于基板10上的相对的两侧，如左侧和右侧的靠近其外轮廓边缘的位置。这样可以在两侧同时向工作区域101输入控制信号，能够达到减小信号延迟的技术效果，从而使基板10达到更好的工作效果。对于基板10的平面面积较大的情况，这种技术效果更加突出。需要说明的是，本公开的实施例中的“左”“右”“上”是指在相应附图中所示的相对位置。
例如，公共电极引线3和公共电极5的材料可以为透明导电材料或不透明导电材料。透明导电材料例如可以为铟锡氧化物(ITO)或铟锌氧化物(IZO)等；不透明导电材料例如可以是金属材料，例如电导率较高的铜、铝、铜合金、铝合金等。公共电极引线3和公共电极5采用上述或其他种类的电导率较高的材料，有利于提高公共信号传导的速度。例如，当工作区域101为发光区域，且需要使光从图3A中的公共电极5一侧出射时，则公共电极5为透明材料。
上述列举的材料种类仅为示范性示例，本公开的实施例对公共电极引线和公共电极的材料不作限定，本领域技术人员可以根据具体需要进行选择。
例如，工作区域101包括多个呈阵列分布的工作单元14。多个工作单元包括阵列元件，例如，阵列元件包括第一电极7、功能层8和第二电极5。第一电极7设置于衬底基板1上，例如，设置于平坦层4的远离衬底基板1的一侧。功能层8设置于第一电极7的远离衬底基板1的一侧。在本公开一实施例中，第二电极为公共电极，其设置于功能层8的远离衬底基板1的一侧。例如，功能层8为电致发光层，例如有机电致发光层。例如，阵列元件可以为有机发光二极管器件，该有机发光二极管器件可以为顶发射、底发射等结构。示范性地，有机发光二极管器件包括相对设置的阳极和阴极以及位于阳极和阴极之间的有机发光层。
例如，在图3A所示的示例中，第一电极7为阳极。此时，公共电极引线3为公共阴极引线，工作过程中向公共电极5输入低电平信号。例如，阳极可以为反射电极或者阳极包括反射层(图未示出)，工作过程中，光从阴极侧出射；或者阴极可以为反射电极或者阴极包括反射层，工作过程中，光从阳极侧出射。在本公开的实施例的其他示例中，阳极和阴极的位置可以互换。例如，阳极也可以为公共电极5，第一电极7为阴极，此时，公 共电极引线3为公共阳极引线，工作过程中向公共电极5输入高电平信号。
例如，基板10还包括像素界定层6，以限定出多个发光单元或像素单元，防止相邻发光单元或相邻像素单元之间的光互相串扰。像素界定层6包括对应于工作单元14的开口，功能层8至少设置于开口中，例如，公共电极5覆盖像素界定层6。
例如，周边电路2可以为栅极驱动电路或数据驱动电路等。例如，该栅极驱动电路或数据驱动电路根据不同的示例可以包括薄膜晶体管、电容器、栅线引线或数据线引线等。
例如，基板10可以是柔性基板。此时，该基板10还包括柔性封装层，柔性封装层包括第一有机封装层9、无机封装层11和第二有机封装层12。第一有机封装层9覆盖工作区域101和部分非工作区102。无机封装层11设置于第一有机封装层9上，且覆盖工作区域101和部分非工作区102。第二有机封装层12设置于无机封装层11上，覆盖工作区域101和部分非工作区102，且覆盖部分衬底基板1。第一有机封装层9的隔绝水、氧气的能力较弱，而无机封装层11具有较好的隔绝水、氧气的能力，因此设置无机封装层11能够使柔性基板具有更好的隔绝水、氧气的能力，以保护设置于柔性基板上的功能层8。
例如，第一有机封装层9和第二有机封装层12的材料可以为聚酰亚胺、聚酯类、聚氟类中一种或多种的组合。聚酰亚胺具有透光性好、耐高温性、抗弯折性能均比较优异的特点。当然，第一有机封装层9和第二有机封装层12的材料不仅限于是上述列举的种类。
例如，无机封装层11的材料可以包括氧化硅或氮化硅。当然，无机封装层11的材料不仅限于是上述列举的种类。只要是具有较好的隔绝水、氧气的能力的无机层均可以适用。
例如，当基板10为柔性基板时，衬底基板1的材料也可以为聚酰亚胺、聚酯类、聚氟类中的一种或多种的组合。当然，本公开的实施例对衬底基板的材料不作限定。
图3B为沿图2A中的G-G’线或图2B中的I-I’线的另一种剖面结构示意图，图3B示出了本公开的实施例提供的另一种基板。如图3B所示，公共电极5和公共电极引线3位于平坦层4上，且公共电极5直接搭接于部分公共电极引线3上以和公共电极引线3直接接触。当然，在本公开的其 他实施例中，公共电极5也可以直接搭接于整个公共电极引线3上以和公共电极引线3直接接触。这样也能够达到与图3A所示的基板相似的技术效果，请参考上述描述，在此不再赘述。
需要说明的是，在本公开的实施例中，公共电极与公共电极引线直接搭接是指：公共电极的一部分与至少部分公共电极引线在垂直于衬底基板的方向上重叠且公共电极的一部分与至少部分公共电极引线接触以实现电连接，公共电极与公共电极引线之间没有其他的层，这两者不需要经过例如过孔进行连接。
在图3B中，基板10的平坦层4覆盖周边电路2和部分衬底基板1，部分平坦层4位于公共电极引线3与周边电路2之间，以将公共电极引线3与周边电路2绝缘。
例如，如图3B所示，公共电极引线3可以与第一电极7同层设置。这样可以使得公共电极引线3可以与第一电极7可以由同一材料经由同一工艺同时形成，有利于简化基板10的制作工艺，提高生产效率。
例如，如图3B所示，公共电极引线3在衬底基板1上的正投影的一部分可以与周边电路2在衬底基板1上的正投影的一部分重合，这样有利于进一步减小基板的边框，从而有利于减小应用该基板的装置例如显示装置的边框。
图3B所示的基板的其他特征及其效果与图3A所示的相同，请参考上述描述。
例如，图3B’为沿图2A中的G-G’线或图2B中的I-I’线的另一种剖面结构示意图，图3B’示出了本公开的实施例提供的另一种基板。如图3B’所示，公共电极5和公共电极引线3位于平坦层4上，且公共电极5的一端与部分公共电极引线3的一端对接以使公共电极与公共电极引线直接接触。这样也能够达到与图3A所示的基板相似的技术效果，请参考上述描述，在此不再赘述。
需要说明的是，在本公开的实施例中，公共电极的一端与部分公共电极引线的一端对接是指：公共电极与部分公共电极引线仅在端部直接接触，公共电极与公共电极引线在衬底基板上的正投影不重叠。
例如，图3B”为沿图2A中的G-G’线或图2B中的I-I’线的另一种剖面结构示意图，图3B”示出了本公开的实施例提供的另一种基板。如 图3B”所示，公共电极5和公共电极引线3位于平坦层4上，且公共电极引线3直接搭接于部分公共电极5上以和公共电极5直接接触。当然，在本公开的其他实施例中，公共电极引线3也可以直接搭接于整个公共电极5上以和公共电极5直接接触。这样也能够达到与图3A所示的基板相似的技术效果，请参考上述描述，在此不再赘述。
图3C为沿图2A中的G-G’线或图2B中的I-I’线的又一种剖面结构示意图，图3C示出了本公开的实施例提供的又一种基板。图3C所示的基板与图3A所示的基板的区别在于，基板10还包括静电保护层13，静电保护层13设置在平坦层4的远离衬底基板1的一侧且覆盖周边电路2且与公共电极引线3电连接，例如，公共电极5设置在静电保护层13上，且公共电极5直接搭接在静电保护层13上，静电保护层13的靠近公共电极引线3的一端通过过孔401与公共电极引线3直接接触，以实现静电保护层13与公共电极引线3电连接。例如，也可以在平坦层上形成其他过孔，以使得静电保护层13的靠近公共电极引线3的一端通过其他过孔与公共电极引线3直接接触，而不是与公共电极采用一个过孔。静电保护层13能够将周边电路2外部的静电通过公共电极引线传导，以防止静电电荷进入周边电路2内而对周边电路2的工作状态造成干扰。如此，静电保护层13与公共电极引线3能够作为静电防止电路的一部分，当需要在基板10上设置静电防止电路时，可以简化基板10的部件。
图3C’为沿图2A中的G-G’线或图2B中的I-I’线的又一种剖面结构示意图，图3C’示出了本公开的实施例提供的又一种基板。图3C’所示的基板与图3B所示的基板的区别在于，基板10还包括静电保护层13，静电保护层13设置在平坦层4的远离衬底基板1的一侧且覆盖周边电路2且与公共电极引线3电连接，例如，静电保护层13直接搭接于至少部分公共电极引线3上，以实现静电保护层13与公共电极引线3电连接。静电保护层13能够将周边电路2外部的静电通过公共电极引线传导，以防止静电电荷进入周边电路2内而对周边电路2的工作状态造成干扰。如此，静电保护层13与公共电极引线3能够作为静电防止电路的一部分，当需要在基板10上设置静电防止电路时，可以简化基板10的部件。
图3C”为沿图2A中的G-G’线或图2B中的I-I’线的又一种剖面结构示意图，图3C”示出了本公开的实施例提供的又一种基板。图3C” 所示的基板与图3B所示的基板的区别在于，基板10还包括静电保护层13，静电保护层13设置在平坦层4的远离衬底基板1的一侧且覆盖周边电路2且与公共电极引线3电连接，例如，公共电极引线3直接搭接于至少部分静电保护层13上，以实现静电保护层13与公共电极引线3电连接。静电保护层13能够将周边电路2外部的静电通过公共电极引线传导，以防止静电电荷进入周边电路2内而对周边电路2的工作状态造成干扰。如此，静电保护层13与公共电极引线3能够作为静电防止电路的一部分，当需要在基板10上设置静电防止电路时，可以简化基板10的部件。
图3C”’为沿图2A中的G-G’线或图2B中的I-I’线的又一种剖面结构示意图，图3C”示出了本公开的实施例提供的又一种基板。图3C”所示的基板与图3B所示的基板的区别在于，基板10还包括静电保护层13，静电保护层13设置在平坦层4的远离衬底基板1的一侧且覆盖周边电路2且与公共电极引线3电连接，例如，公共电极引线3的另一端与静电保护层13的一端对接，以实现静电保护层13与公共电极引线3电连接。静电保护层13能够将周边电路2外部的静电通过公共电极引线传导，以防止静电电荷进入周边电路2内而对周边电路2的工作状态造成干扰。如此，静电保护层13与公共电极引线3能够作为静电防止电路的一部分，当需要在基板10上设置静电防止电路时，可以简化基板10的部件。
需要说明的是，在本公开的实施例中，公共电极引线的另一端与静电保护层的一端对接是指：公共电极引线与静电保护层仅在端部直接接触，公共电极引线与静电保护层在衬底基板上的正投影不重叠。
本公开的实施例提供的基板可以用于显示装置、照明装置等电子装置。本公开的实施例提供的基板可以为柔性基板，用于柔性显示面板、发光面板等。
本公开一实施例还提供一种电子装置，包括本公开的上述实施例提供的任意一种基板。示范性地，图7为本公开一实施例提供的一种电子装置的框图。如图7所示，该电子装置包括本公开实施例提供的任意一种基板。例如，该电子装置可以是显示装置，例如，该显示装置可以为有机发光二极管显示装置。例如该显示装置可以为柔性显示装置。例如，该显示装置可以实现为如下的产品：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子广告屏等任何具有显示功能的产品或部件。例如， 该电子装置也可以是照明装置，例如该照明装置可以是装饰性灯具等。
图7只是一个包括本公开实施例提供的任意一种基板的显示装置的框图，未示出显示装置的其他结构，本领域技术人员可参考常规技术，本公开的实施例对此不作限定。
本公开的实施例提供的电子装置可以减小公共电极引线和公共电极实现电连接的电阻，这有利于提高信号在公共电极引线和公共电极之间的传导速度，例如当该基板为发光基板例如显示基板时，可以使显示画面的亮度均一性更高，能够得到更好的显示效果；并且，公共电极引线和公共电极实现电连接的电阻减小有利于减小电子装置工作过程中的功耗和焦耳热，降低焦耳热导致的温升，从而有利于提高电子装置的寿命。此外，本公开实施例提供的电子装置还能够实现较窄的边框。
本公开至少一实施例还提供一种基板制作方法，该基板包括工作区域和位于工作区域周边的非工作区，该制作方法包括：提供衬底基板；在衬底基板上且在非工作区中形成周边电路和公共电极引线；在工作区域和非工作区形成公共电极；其中，公共电极引线位于周边电路的靠近工作区域的一侧；公共电极与至少部分公共电极引线直接接触。
示范性地，图4A-4O为本公开实施例提供的一种基板的制作方法的过程示意图。下面以形成工作区域包括有机发光二极管器件的基板为例进行示范性介绍。
如图4A所示，提供衬底基板1。衬底基板1例如可以为玻璃基板、石英基板、树脂(例如聚乙烯)基板等，也可以为柔性基板，例如由聚酰亚胺等制成。衬底基板1包括外轮廓边缘，将要形成的基板所包括的工作区域101和位于工作区域101周边的非工作区102对应于衬底基板1上的区域如图4A所示。
如图4B所示，在基板的非工作区102中提供周边电路2，该周边电路2例如可以为驱动电路，例如栅极驱动电路或数据驱动电路。该周边电路2的具体制作方法本领域技术人员可参考常规技术。
如图4C所示，公共电极引3位于周边电路2的靠近工作区域101的一侧，以便于其与后续形成的从工作区域101延伸至非工作区102的公共电极直接接触。并且，公共电极引线3与周边电路2之间留有一定的距离，以用于使公共电极引线3与周边电路2绝缘。例如，公共电极引线3的材 料例如可以为透明导电材料或不透明导电材料，透明导电材料例如可以为铟锡氧化物(ITO)或铟锌氧化物(IZO)等，不透明导电材料例如可以是金属材料，例如，电导率较高的铜、铝、铜合金等。公共电极引线3可以配合掩模采用化学气相沉积法或磁控溅射法、蒸镀等方法形成。
如图4D所示，该方法还包括形成平坦层4。平坦层4覆盖周边电路2和公共电极引线3。部分平坦层4位于公共电极引线3与周边电路2之间，以将公共电极引线3与周边电路2绝缘。例如，平坦层4的材料可以为绝缘材料，同时充当绝缘层。该绝缘材料例如可以为无机材料或有机材料，该有机材料例如为树脂材料，例如聚乙烯树脂、聚丙烯酸树脂、聚酯树脂、聚酰胺树脂等。本公开实施例对平坦层4的材料不作限定。
如图4E所示，对平坦层4进行构图工艺，在平坦层4中形成暴露部分公共电极引线的过孔401。例如，该构图工艺可以为光刻。当然，在其他实施例中，也可以通过对平坦层4进行构图工艺形成暴露部分共电极引线的凹槽，凹槽是过孔的一种特殊形式。
如图4F所示，在平坦层4的上方形成预像素界定层601，例如可以采用涂覆方式形成预像素界定层601。例如，预像素界定层601的材料可以为感光材料，以便于后续进行光刻工艺。例如，该感光材料可以包括光刻胶材料和金属卤化物，金属卤化物例如为卤化银(例如AgCl或AgBr)。预像素界定层601的材料还可以为深色材料，例如黑色树脂、金属铬或铬氧化物等，可以通过印刷、光刻等构图方法得到需要的图案。当然，预像素界定层601的材料也可以是其他材料，本领域技术人员也可以根据需要进行选择。
如图4G所示，通过对预像素界定层601进行构图工艺形成像素界定层6。像素界定层6具有开口。像素界定层6在工作区域101中限定出多个呈阵列分布的工作单元，即在工作区域101形成了多个呈阵列分布的工作单元。例如，该构图工艺可以为光刻工艺。例如，像素界定层6可以经过曝光-显影工艺形成，当预像素界定层601的材料包括光刻胶材料和金属卤化物时，金属卤化物在未曝光时为低光密度的材料，曝光后会分解形成金属微粒，该金属微粒由于颗粒小会呈现为黑色，具有高光密度值。同时，例如光刻胶材料为负性光刻胶材料，其在曝光后变得不溶于显影液而保留下来，从而可以形成像素界定层6。
如图4I所示，例如可以配合掩模通过蒸镀或沉积的方法等在平坦层4上形成第一电极7，第一电极7例如为阳极。或者，如图4H所示，先通过蒸镀、磁控溅射沉积或化学气相沉积等方法形成预第一电极层701，然后再通过光刻工艺形成如图4I所示的第一电极7。第一电极7位于每个工作单元中的像素界定层6的开口中。
如图4K所示，配合掩模通过沉积的方法等形成位于第一电极7的远离衬底基板1的一侧的功能层8。例如，功能层8为有机发光层。或者，如图4J所示，通过涂布的方法形成预功能层801，再通过光刻形成如图4K所示的功能层8，例如，功能层8位于每个工作单元中的像素界定层6的开口中。
如图4L所示，形成公共电极5。例如，公共电极5为阴极。当然，在其他实施例中，也可以是公共电极5为阳极，第一电极7为阴极。公共电极5覆盖像素界定层6，并由工作区域101延伸至非工作区102。在非工作区102，公共电极5通过过孔401与公共电极引线3能够直接接触，以实现公共电极5与公共电极引线3电连接。公共电极5与公共电极引线3直接接触的技术效果请参考之前的实施例中的描述，在此不再赘述。
例如，当该基板为柔性基板时，该基板制作方法还包括形成柔性封装层。形成柔性封装层包括形成第一有机封装层、无机封装层和第二有机封装层。如图4M所示，形成覆盖工作区域101和部分非工作区102的第一有机封装层9。例如，例如，第一有机封装层9的材料可以为聚酰亚胺、聚酯类、聚氟类中一种或多种的组合。聚酰亚胺具有透光性好、耐高温性、抗弯折性能均比较优异的特点。当然，第一有机封装层9的材料不仅限于是上述列举种类。例如，第一有机封装层9可以采用涂布方法形成。
如图4N所示，形成设置于第一有机封装层9上的无机封装层11。例如，无机封装层11的材料可以包括氧化硅或氮化硅。当然，无机封装层11的材料不仅限于是上述列举种类。只要是具有较好的隔绝水、氧气的能力的无机层均可以。例如，无机封装层11可以采用蒸镀、化学气相沉积或磁控溅射沉积等方法形成。
如图4O所示，形成设置于无机封装层11上且覆盖部分衬底基板1的第二有机封装层12。第二有机封装层12的材料和形成方法与第一有机封装层9的相同。通过上述方法可以形成如图4O所示的基板。
需要说明的是，本公开实施例以形成柔性基板为例进行说明。在一些实施例中，基板也可以为非柔性基板。
图5A-5F为本公开实施例提供的另一种基板的制作方法的过程示意图。在形成如图4B所示的结构之后，形成如图5A所示的平坦层4，平坦层4覆盖周边电路2。平坦层的材料和形成方法请参考上述描述。
如图5B所示，采用和图4F-4G所示的相同的方法形成像素界定层6。如图5C所示，可以在平坦层4的远离衬底基板1的一侧同时形成公共电极引线3和第一电极7，即公共电极引线3和第一电极7可以通过同一工艺同时形成，以简化基板的制作工艺。
如图5D所示，采用和图4K所示的相同的方法形成功能层8。
如图5E所示，在平坦层4的远离衬底基板1的一侧形成公共电极5。公共电极5覆盖像素界定层6，并由工作区域101延伸至非工作区102。在非工作区102，公共电极5与部分公共电极引线3直接搭接以直接接触，以实现公共电极5与公共电极引线3电连接。
例如，在图5E的一种变形中，如图5E’所示，公共电极5可以与至少部分公共电极引线3在平行于衬底基板1板面的平面上直接接触，以实现实现公共电极5与公共电极引线3电连接，即去掉了公共电极5与部分公共电极引线3直接搭接的部分。后续过程以图5E所示的结构为基础。
通过与图4M-4O所示的方法相同的方法依次形成第一有机封装层9、无机封装层11和第二有机封装层12，可以形成如图5F所示的基板。
5A-5F所示的制作方法能够达到与图4A-4O所示的制作方法相同或相似的技术效果，该方法的其他技术特征均与图4M-4O所示的方法相同，请参考上述描述。
图6A-6B本公开实施例提供的又一种基板的制作方法的过程示意图。该方法还包括在形成静电保护层。如图4G所示的结构之后，利用同一工艺同时形成静电保护层13和第一电极7。静电保护层13覆盖周边电路2且与公共电极引线3电连接。静电保护层13的靠近公共电极引线3的一端通过过孔401与公共电极引线3直接搭接以直接接触，以实现静电保护层13与公共电极引线电3电连接。静电保护层13能够将周边电路2外部的静电通过公共电极引线传导，以防止静电电荷进入周边电路2内而对周边电路2的工作状态造成干扰。如此，静电保护层13与公共电极引线3能够 作为静电防止电路的一部分，当需要在基板10上设置静电防止电路时，可以简化基板10的部件。在本公开一实施例中，静电保护层13和第一电极7通过同一工艺同时形成有利于简化基板的制作工艺。
通过与图4M-4O所示的方法相同的方法依次形成第一有机封装层9、无机封装层11和第二有机封装层12，可以形成如图6B所示的基板。
本公开的实施例提供一种基板及其制作方法、电子装置，在本公开的至少一实施例中，公共电极引线位于周边电路的靠近工作区域的一侧，这能够使得公共电极引线更加靠近公共电极，从而使公共电极引线能够与至少公共电极直接接触以实现公共电极引线与公共电极电连接。与通过跨接电极实现公共电极引线与公共电极电连接的情况相比，一方面，公共电极引线与公共电极直接接触而实现电连接能够减小信号由公共电极引线传导至公共电极的电路的电阻，这有利于提高信号在公共电极引线和公共电极之间的传导速度，例如当该基板为发光基板例如显示基板时，可以使显示画面的亮度均一性更高，获得更好的显示效果；并且，该电阻的减小有利于减小工作过程中的功耗和焦耳热，降低焦耳热导致的温升，从而有利于提高应用该基板的装置例如显示装置的寿命。另一方面，对于本公开实施例提供的基板，制作公共电极的过程中，例如在用蒸镀法形成公共电极和公共电极引线的过程中，即使存在蒸镀掩模的位置误差，也可以保证公共电极与公共电极引线保持一定的接触面积，因此，不需要在公共电极引线和靠近衬底基板的外轮廓边缘的坝胶之间预留过大的余量，从而有利于实现窄边框，而且能够避免因为在多次生产中由于蒸镀掩模的位置误差不同而导致的基板产品的尺寸误差不一致或者显示亮度的均匀性不一致等问题。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (21)

  1. 一种基板，包括：
    工作区域、位于所述工作区域周边的非工作区；
    衬底基板；
    位于所述衬底基板上且位于所述非工作区的周边电路和公共电极引线；
    其中，所述公共电极引线位于所述周边电路的靠近所述工作区域的一侧。
  2. 根据权利要求1所述的基板，还包括公共电极，其中，
    所述公共电极由所述工作区域延伸至所述非工作区；
    所述公共电极与至少部分所述公共电极引线直接接触。
  3. 根据权利要求2所述的基板，其中，所述周边电路为栅极驱动电路，所述公共电极为阴极，所述公共电极引线为阴极引线。
  4. 根据权利要求2或3所述的基板，还包括覆盖所述周边电路和所述公共电极引线的平坦层，
    其中，所述公共电极位于所述平坦层的远离所述衬底基板的一侧；所述平坦层包括暴露至少部分所述公共电极引线的过孔，所述公共电极在所述过孔处与所述公共电极引线直接接触。
  5. 根据权利要求4所述的基板，还包括静电保护层，其中，所述静电保护层设置在所述平坦层的远离所述衬底基板的一侧且覆盖至少部分所述周边电路，且所述静电保护层在所述过孔处与所述公共电极引线电连接。
  6. 根据权利要求2或3所述的基板，还包括平坦层，其中，所述公共电极和所述公共电极引线位于所述平坦层的远离所述衬底基板的一侧，且所述公共电极与至少部分所述公共电极引线直接接触。
  7. 根据权利要求6所述的基板，其中，所述公共电极直接搭接于至少部分所述公共电极引线上以和所述公共电极引线直接接触。
  8. 根据权利要求6所述的基板，其中，所述公共电极引线直接搭接于至少部分所述公共电极上以和所述公共电极直接接触。
  9. 根据权利要求6所述的基板，其中，所述公共电极的一端与所述 公共电极引线的一端对接以使所述公共电极与所述公共电极引线直接接触。
  10. 根据权利要求7或9所述的基板，其中，所述工作区域包括多个呈阵列分布的工作单元，每个所述工作单元包括：
    第一电极，设置于所述衬底基板上；
    功能层，设置于所述第一电极的远离所述衬底基板的一侧；
    第二电极，设置于所述功能层的远离所述衬底基板的一侧；
    其中，所述第二电极为所述公共电极。
  11. 根据权利要求10所述的基板，其中，所述公共电极引线与所述第一电极同层设置。
  12. 根据权利要求6-11中任一项所述的基板，还包括静电保护层，其中，所述静电保护层设置在所述平坦层的远离所述衬底基板的一侧且覆盖至少部分所述周边电路且与所述公共电极引线电连接。
  13. 根据权利要求12所述的基板，其中，所述静电保护层直接搭接于至少部分所述公共电极引线上以和所述公共电极引线电连接。
  14. 根据权利要求12所述的基板，其中，所述公共电极引线直接搭接于至少部分所述静电保护层上以和所述静电保护层电连接。
  15. 根据权利要求12所述的基板，其中，所述公共电极引线的另一端与所述静电保护层的一端对接以使所述公共电极引线与所述静电保护层电连接。
  16. 一种电子装置，包括权利要求1-15中任一项所述的基板。
  17. 一种基板制作方法，所述基板包括工作区域和位于所述工作区域周边的非工作区，所述制作方法包括：
    提供衬底基板；
    在所述衬底基板上且在所述非工作区中形成周边电路和公共电极引线；
    其中，所述公共电极引线位于所述周边电路的靠近所述工作区域的一侧。
  18. 根据权利要求17所述的基板制作方法，还包括形成公共电极，
    其中，所述公共电极由所述工作区域延伸至所述非工作区，所述公共 电极与至少部分所述公共电极引线直接接触。
  19. 根据权利要求18所述的基板制作方法，还包括形成平坦层，其中，
    所述平坦层覆盖所述周边电路和所述公共电极引线；
    所述公共电极位于所述平坦层的远离所述衬底基板的一侧；
    所述形成平坦层包括在所述平坦层中形成暴露至少部分所述公共电极引线的过孔，所述公共电极在所述过孔处与所述公共电极引线直接接触。
  20. 根据权利要求18所述的基板制作方法，还包括形成平坦层，其中，
    所述公共电极和所述公共电极引线形成于所述平坦层的远离所述衬底基板的一侧，且所述公共电极与至少部分所述公共电极引线直接接触。
  21. 根据权利要求17-20中任一项所述的基板制作方法，还包括形成静电保护层，
    其中，所述静电保护层形成在所述平坦层的远离所述衬底基板的一侧且覆盖至少部分所述周边电路且与所述公共电极引线电连接。
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