WO2021254150A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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WO2021254150A1
WO2021254150A1 PCT/CN2021/097936 CN2021097936W WO2021254150A1 WO 2021254150 A1 WO2021254150 A1 WO 2021254150A1 CN 2021097936 W CN2021097936 W CN 2021097936W WO 2021254150 A1 WO2021254150 A1 WO 2021254150A1
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layer
electrode
auxiliary
display substrate
forming
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PCT/CN2021/097936
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English (en)
French (fr)
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曹席磊
徐映嵩
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/770,614 priority Critical patent/US20220293704A1/en
Publication of WO2021254150A1 publication Critical patent/WO2021254150A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80516—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, display technology, in particular to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • the embodiments of the present disclosure provide a display substrate, a preparation method thereof, and a display device.
  • embodiments of the present disclosure provide a method for manufacturing a display substrate, including:
  • a flat layer is formed on the side of the drive structure layer away from the substrate, and after curing and polishing the flat layer, a first pass is formed that penetrates the flat layer and exposes the first electrode of the thin film transistor. hole;
  • a light emitting structure layer is formed on the side of the flat layer away from the substrate.
  • the method before forming the light-emitting structure layer on the side of the flat layer away from the substrate, the method further includes:
  • An auxiliary layer is formed between the flat layer and the light emitting structure layer.
  • the forming the first via hole penetrating the planarization layer and exposing the first electrode of the thin film transistor includes: etching the first via hole using the auxiliary layer as a mask. hole.
  • the material of the auxiliary layer includes metal.
  • the forming an auxiliary layer between the flat layer and the light-emitting structure layer includes:
  • auxiliary layer including a first auxiliary electrode and a second auxiliary electrode that are independent of each other between the flat layer and the light-emitting structure layer;
  • Forming a light emitting structure layer on the side of the flat layer away from the substrate includes:
  • first electrode Forming a first electrode on the side of the auxiliary layer away from the substrate, and the first electrode is electrically connected to the first auxiliary electrode and the first electrode of the thin film transistor;
  • the pixel defining layer is provided with a second via hole exposing the second auxiliary electrode;
  • An organic light-emitting layer and a second electrode are sequentially formed on the side of the pixel defining layer away from the substrate, and the second electrode is electrically connected to the second auxiliary electrode through the second via hole.
  • the material of the flat layer includes a black material.
  • an embodiment of the present disclosure provides a display substrate, the display substrate comprising: a base, a driving structure layer, a flat layer, and a light emitting structure layer sequentially disposed on the base;
  • the driving structure layer includes a thin film transistor,
  • the thin film transistor includes a first electrode, the flat layer is provided with a first via hole exposing the first electrode of the thin film transistor, and the first via hole is formed after curing and polishing the flat layer .
  • the display substrate further includes: an auxiliary layer provided between the flat layer and the light emitting structure layer.
  • the material of the auxiliary layer includes metal.
  • the auxiliary layer includes a first auxiliary electrode
  • the light-emitting structure layer includes a first electrode, a pixel defining layer, an organic light-emitting layer, and a second electrode that are sequentially arranged from a side close to the auxiliary layer to a side away from the auxiliary layer, and the first electrode passes through the first electrode.
  • a via hole is electrically connected to the first electrode of the thin film transistor, and the first electrode is electrically connected to the first auxiliary electrode.
  • the auxiliary layer includes a first auxiliary electrode and a second auxiliary electrode that are independent of each other;
  • the light-emitting structure layer includes a first electrode, a pixel defining layer, an organic light-emitting layer, and a second electrode that are sequentially arranged from a side close to the auxiliary layer to a side away from the auxiliary layer, and the first electrode passes through the first electrode.
  • a via hole is electrically connected to the first electrode of the thin film transistor, and the first electrode is electrically connected to the first auxiliary electrode;
  • the pixel defining layer is provided with a second via hole exposing the second auxiliary electrode;
  • the second electrode is electrically connected to the second auxiliary electrode through the second via hole.
  • the first electrode is disposed on the surface of the first auxiliary electrode.
  • the material of the flat layer includes a black material.
  • the material of the flat layer includes a non-photosensitive material.
  • an embodiment of the present disclosure provides a display device, including the display substrate described in the foregoing embodiment.
  • Figure 1 is a schematic diagram of a display substrate provided by a technical solution
  • FIG. 2 is a flow chart of a method for manufacturing a display substrate provided by an embodiment
  • FIG. 3 is a schematic diagram after forming a base pattern according to an embodiment
  • FIG. 4 is a schematic diagram after forming a driving structure layer according to an embodiment
  • FIG. 5 is a schematic diagram after forming a flat layer according to an embodiment
  • FIG. 6 is a schematic diagram after depositing an auxiliary layer according to an embodiment
  • FIG. 7 is a schematic diagram after forming an auxiliary layer pattern according to an embodiment
  • FIG. 8 is a schematic diagram after forming a first via hole according to an embodiment
  • FIG. 9 is a schematic diagram after forming an anode according to an embodiment
  • FIG. 10 is a schematic diagram after forming a light-emitting structure layer according to an embodiment
  • FIG. 11 is a schematic diagram after forming an encapsulation layer according to an embodiment
  • FIG. 12 is a schematic diagram of a display substrate provided by an embodiment
  • FIG. 13 is a schematic diagram of a display substrate provided by another embodiment
  • FIG. 14 is a schematic diagram of a display substrate provided by another embodiment.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to a region through which current mainly flows.
  • it may be the drain electrode of the first electrode and the source electrode of the second electrode, or it may be the source electrode of the first electrode and the drain electrode of the second electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged.
  • the first electrode may be an anode and the second electrode may be a cathode; or, the first electrode may be a cathode, and the second electrode may be an anode, depending on the light-emitting structure of the display substrate.
  • RGB Color filters red, green, and blue color filters
  • POL polarizers
  • FIG. 1 is a schematic diagram of a display substrate provided in a technical solution.
  • the display substrate includes a base 1, a driving structure layer 2, and a flat layer 3.
  • the driving structure layer 2 includes a thin film transistor (TFT).
  • TFT thin film transistor
  • the layer 3 area has been designed for leveling, the height here is 0.2 micrometers ( ⁇ m) to 1.2 micrometers higher than other areas due to the influence of process deviation (floating), resulting in unevenness of the flat layer 3, thus Causes color separation, making the display uneven.
  • the flat layer 3 after the flat layer 3 is punched, it will be cured by thermal baking, which will cause the aperture ratio to change.
  • the range of change is approximately 1% to 10%.
  • the aperture ratio changes greatly, resulting in the anode and the film.
  • the contact resistance of the transistor changes, which affects the display effect.
  • the embodiments of the present disclosure provide a display substrate, a preparation method thereof, and a display device to meet the requirement of flat anode and prevent color separation caused by uneven anode during the design of color filter structure (Color Filter on Encapsulation, COE) Phenomenon, and can ensure the aperture ratio.
  • COE Color Filter on Encapsulation
  • FIG. 2 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the disclosure. As shown in Figure 2, the method for preparing the display substrate provided by the embodiment of the present disclosure may include:
  • Step 201 forming a substrate, and forming a driving structure layer on the substrate, the driving structure layer including a thin film transistor, and the thin film transistor including a first electrode;
  • a flat layer is formed on the side of the drive structure layer away from the substrate, and after curing and polishing the flat layer, a first electrode penetrating through the flat layer and exposing the first electrode of the thin film transistor is formed.
  • Step 203 forming a light-emitting structure layer on the side of the flat layer away from the substrate.
  • the flat layer is cured and polished and flattened, which improves the flatness of the flat layer, avoids the uneven display caused by color separation, and improves the display effect.
  • punching after curing, polishing and flattening on the one hand, avoids the residue of polishing agent (or acid or alkali will cause certain corrosion and affect TFT characteristics), on the other hand, compared with punching before curing, it can reduce the change of pore diameter. , To avoid affecting the contact resistance and improve the display effect.
  • the first electrode is, for example, a drain electrode, but the embodiment of the present disclosure is not limited thereto.
  • the first electrode may be a source electrode.
  • the method may further include: forming an auxiliary layer between the flat layer and the light emitting structure layer.
  • the auxiliary layer may be insulating, or may be conductive, or may be partially insulated and partially conductive, and so on. In other embodiments, there may be no auxiliary layer.
  • the auxiliary layer can be used as an auxiliary electrode, or can be used as a mask in the subsequent process.
  • the forming the first via hole penetrating the planarization layer and exposing the first electrode of the thin film transistor may include: forming the first via etching using the auxiliary layer as a mask. Via.
  • the auxiliary layer is formed before forming the first via hole.
  • the auxiliary layer is used as a mask, which can simplify the preparation process and reduce the cost.
  • the auxiliary layer may not be used as a mask.
  • the material of the auxiliary layer may include metal.
  • the auxiliary layer is made of metal, it can be used as an auxiliary electrode.
  • the auxiliary electrode is used to reduce IR drop.
  • non-metals may be used for the auxiliary layer.
  • the auxiliary layer may include a first auxiliary electrode and a second auxiliary electrode that are independent of each other;
  • the forming a light-emitting structure layer on a side of the flat layer away from the substrate may include:
  • first electrode Forming a first electrode on the side of the auxiliary layer away from the substrate, and the first electrode may be electrically connected to the first auxiliary electrode and the first electrode of the thin film transistor;
  • the pixel defining layer is provided with a second via hole exposing the second auxiliary electrode;
  • An organic light-emitting layer and a second electrode are sequentially formed on the side of the pixel defining layer away from the substrate, and the second electrode is electrically connected to the second auxiliary electrode through the second via hole.
  • the auxiliary layer serves as the auxiliary electrode of the first electrode and the auxiliary electrode of the second electrode, which reduces IR Drop.
  • the preparation process of the display substrate through an example.
  • the "patterning process” in this embodiment includes the processes of depositing a film layer, coating photoresist, mask exposure, developing, etching, and stripping the photoresist.
  • the "photolithography process” "Process” includes treatments such as film coating, mask exposure, development, etc.
  • the evaporation, deposition, coating, coating, etc. mentioned in this embodiment are all mature preparation processes in related technologies.
  • the preparation process of the display substrate includes:
  • Forming the base pattern includes: coating a layer of flexible material on the glass carrier 9 and curing it into a film to form the first base 10.
  • a layer of buffer film is deposited on the first substrate 10 to form a pattern of the buffer layer 11 covering the entire first substrate 10.
  • the flexible material can be made of materials such as Pressure Sensitive Adhesive (PSA), polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film, etc.
  • PSA Pressure Sensitive Adhesive
  • PI polyimide
  • PET polyethylene terephthalate
  • Flexible substrate as shown in Figure 3.
  • the buffer film may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., may be a single layer, or may be a silicon nitride/silicon oxide multilayer structure.
  • An active layer, a gate electrode, a source electrode and a drain electrode pattern are formed on the substrate.
  • forming the active layer, the gate electrode, the source electrode and the drain electrode pattern on the substrate includes:
  • the first insulating film and the first metal film are sequentially deposited, and the first metal film is patterned through a patterning process to form a first insulating layer 13 covering the active layer 12 and a first gate electrode 14 disposed on the first insulating layer 13 , The second gate electrode (not shown) and the gate line (not shown) pattern.
  • a second insulating film and a second metal film are sequentially deposited, and the second metal film is patterned through a patterning process to form a second insulating layer 16 covering the first gate electrode 14 and the second gate electrode and to be disposed on the second insulating layer 16
  • the pattern of the capacitor electrode (not shown), the position of the capacitor electrode corresponds to the position of the second gate electrode, and the capacitor electrode and the second gate electrode form a capacitor.
  • a third insulating film is deposited, and the third insulating film is patterned through a patterning process to form a pattern of the third insulating layer 18 with via holes in the display area, and the third insulating layer 18 in the via holes ,
  • the second insulating layer 16 and the first insulating layer 13 are etched away, exposing the active layer 12;
  • a third metal film is deposited, and the third metal film is patterned through a patterning process to form source electrode 19, drain electrode 20, and data line (not shown) patterns in the display area.
  • the source electrode 19 and the drain electrode 20 are connected to each other through via holes.
  • the active layer 12 is connected.
  • the driving structure layer includes an active layer 12, a first gate electrode 14, a second gate electrode, a capacitor electrode, a source electrode 19, a drain electrode 20, a gate line and a data line.
  • the gate line and the data line perpendicularly intersect to define a sub-pixel
  • a thin film transistor composed of the active layer 12, the first gate electrode 14, the source electrode 19 and the drain electrode 20 is arranged in the sub-pixel.
  • the first insulating layer 13 and the second insulating layer 16 may be referred to as a gate insulating layer (GI)
  • the third insulating layer 18 may be referred to as an interlayer insulating layer (ILD).
  • Forming a flat layer pattern includes: on the basis of forming the above-mentioned structure, coating a fourth insulating film, baking and curing forming, polishing and flattening to form a flat layer 21 pattern covering the source electrode 19 and the drain electrode 20, as shown in FIG. 5 .
  • the flatness can be improved by polishing and flattening, so that the flatness of the subsequent anode is correspondingly improved.
  • polishing and flattening may be performed chemically (using a polishing agent) or mechanically.
  • the fourth insulating film may use a black material to prevent light from affecting the gate wiring and reduce the reflectivity of the wiring.
  • the black material here includes black and materials close to black.
  • the black material includes, for example, black PI, silicone-based adhesives, or black pigments, dyes, and the like.
  • non-black materials may be used, such as transparent materials, non-black anti-reflection materials, and so on.
  • the fourth insulating film may use a non-photosensitive material. Since the cost of the photosensitive material is relatively high, the use of the non-photosensitive material can reduce the cost. Conventional flat layer materials contain photosensitive materials, and therefore, materials that do not contain photosensitive materials can be used to make the flat layer.
  • the fourth insulating film may be a black non-photosensitive material, or a non-black non-photosensitive material.
  • the formation of the auxiliary layer pattern includes:
  • the auxiliary layer film is, for example, a conductive material or an insulating material
  • the conductive material includes, for example, a metal or a conductive film (such as indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), etc.).
  • the metal includes, for example, one of metal materials such as magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), lithium (Li), or an alloy of the foregoing metals.
  • the insulating material includes, for example, an inorganic insulating material, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride, and the like.
  • the auxiliary layer film is patterned through a patterning process to generate an auxiliary layer including a first auxiliary electrode 221 and a second auxiliary electrode 222, as shown in FIG. 7.
  • the first auxiliary electrode 221 may be electrically connected to the anode
  • the second auxiliary electrode 222 may be electrically connected to the cathode, thereby reducing the IR voltage drop.
  • the embodiments of the present disclosure are not limited thereto, and only the first auxiliary electrode 221 may be electrically connected to the anode, or only the second auxiliary electrode 222 may be electrically connected to the cathode. When only the first auxiliary electrode 221 is electrically connected to the anode, there is no second via hole.
  • the auxiliary layer may partly use insulating materials (the part corresponding to the first auxiliary electrode 221), partly use metal (the part corresponding to the second auxiliary electrode 222), and so on.
  • etch such as dry etching
  • the auxiliary layer is used as the mask, which avoids the additional use of the mask, simplifies the process, and reduces the cost.
  • the via hole is formed after the flat layer is polished and flattened. Compared with the polishing and flattening after the first via hole is formed, the solution provided in this embodiment does not have polishing agent residue (the polishing agent or acid or alkali will Causes certain corrosion and affects TFT characteristics), and will not cause damage to the source and drain electrodes.
  • perforating after baking and curing will affect the change in aperture ratio within 2%, which greatly reduces the change in aperture ratio, avoids changes in the contact resistance between the anode and the drain electrode, and improves the display effect.
  • a transparent conductive film is deposited, and the transparent conductive film is patterned through a patterning process to form a pattern of the anode 31 in the display area, and the anode 31 is connected to the drain electrode 20 through the first via 23, as shown in FIG. 9.
  • the transparent conductive film can be ITO or IZO or ITO/Al (aluminum)/ITO multilayer composite material.
  • the second auxiliary electrode 222 and the anode 31 may be provided in the same layer.
  • the formation of the pixel defining layer, the organic light emitting layer and the cathode pattern includes: coating a pixel defining film on the substrate forming the aforementioned pattern, and forming a pixel defining layer (PDL) 32 pattern in the display area through a photolithography process.
  • the pixel defining The layer 32 defines a pixel opening area exposing the anode 31 and a second via hole in each sub-pixel, and the second via hole exposes the second auxiliary electrode 222.
  • the material of the pixel defining layer 32 can be polyimide, Acrylic or polyethylene terephthalate, etc.
  • the organic light-emitting material and cathode metal are deposited sequentially to form the pattern of the organic light-emitting layer 33 and the cathode 34.
  • the organic light-emitting layer 33 is connected to the anode 31 in the pixel opening area defined by the pixel defining layer 32, and the cathode 34 is disposed on the organic light-emitting layer 33 ,
  • the cathode 34 is electrically connected to the second auxiliary electrode 222, as shown in FIG. 10.
  • the organic light-emitting layer 33 includes a light-emitting layer (EML).
  • the organic light-emitting layer 33 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer sequentially arranged to improve the efficiency of electron and hole injection into the light-emitting layer.
  • the cathode 34 may be magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), lithium (Li) and other metal materials, or an alloy of the foregoing metals.
  • Forming the encapsulation layer pattern includes: first depositing a first inorganic film on the substrate on which the aforementioned pattern is formed to form the first inorganic layer pattern, and forming an organic layer in the display area by inkjet printing. The organic layer is only formed on the first part of the display area. On the inorganic layer. A second inorganic thin film is deposited, and the second inorganic thin film covers the display area and the non-display area to form a second inorganic layer pattern, as shown in FIG. 11.
  • the encapsulation layer 35 including an inorganic/organic/inorganic three-layer structure is completed, the organic layer in the middle is only formed in the display area, and the upper and lower inorganic layers cover the display area and the non-display area.
  • the first inorganic film is, for example, silicon oxynitride (SiON)
  • the second inorganic film is, for example, silicon nitride (SiNx).
  • the display substrate can be not only a top emission structure, but also a bottom emission structure.
  • the thin film transistor may be a top gate structure, or may be a bottom gate structure, or may be a double gate structure, or may be a single gate structure.
  • the thin film transistor can be an amorphous silicon (a-Si) thin film transistor, a low temperature polysilicon (LTPS) thin film transistor or an oxide (Oxide) thin film transistor, and other electrodes, leads and structures can be provided in the driving structure layer and the light emitting structure layer.
  • a-Si amorphous silicon
  • LTPS low temperature polysilicon
  • Oxide oxide
  • other electrodes, leads and structures can be provided in the driving structure layer and the light emitting structure layer.
  • FIG. 12 is a schematic diagram of a display substrate provided by another embodiment.
  • the display substrate provided by this embodiment may include: a substrate, a driving structure layer, a planarization layer 21, an auxiliary layer 22, and a light emitting structure layer sequentially disposed on the substrate; the substrate may include a first substrate 10 and a buffer layer 11.
  • the driving structure layer may include an active layer 12, a first insulating layer 13, a first gate electrode 14, a second insulating layer 16, a third insulating layer 18, a source electrode 19 and a drain electrode 20,
  • the flat layer 21 is provided with a first via hole exposing the drain electrode 20, and the first via hole is formed after curing and polishing the flat layer 21.
  • the auxiliary layer 22 may include a first auxiliary electrode 221 and a second auxiliary electrode 222 that are independent of each other, and the light emitting structure layer may include an anode 31, a pixel defining layer 32, an organic light emitting layer 33 and a cathode 34.
  • the anode 31 may be disposed on the surface of the first auxiliary electrode 221 away from the substrate and electrically connected to the first auxiliary electrode 221, and the anode 31 may also be electrically connected to the first auxiliary electrode 221 through the first via hole.
  • the pixel defining layer 32 is provided with a second via hole exposing the second auxiliary electrode 222, and the cathode 34 may be electrically connected to the second auxiliary electrode 222 through the second via hole.
  • the flat layer is cured and polished, so that the flat layer is flatter, and color separation is avoided, resulting in uneven display.
  • punching after curing, polishing and flattening avoids the residue of polishing agent (or acid or alkali will cause certain corrosion and affect TFT characteristics), on the other hand, compared with punching before curing, it can reduce the change of pore diameter.
  • the first auxiliary electrode 221 and the second auxiliary electrode 222 reduce the IR voltage drop, and the auxiliary layer can be used as a mask during the manufacturing process, which simplifies the manufacturing process and reduces the cost.
  • the material of the flat layer 21 may include a black material to prevent light from affecting the gate wiring and reduce reflectivity.
  • the material of the flat layer 21 may include a non-photosensitive material. That is, the flat layer 21 may not contain photosensitive materials, which reduces the cost.
  • FIG. 13 is a schematic diagram of a display substrate provided by another embodiment.
  • the display substrate provided by this embodiment may include a base, a driving structure layer, a flat layer 21, and a light emitting structure layer sequentially disposed on the base;
  • the base may include a first base 10 and a buffer layer 11.
  • the driving structure layer may include an active layer 12, a first insulating layer 13, a first gate electrode 14, a second insulating layer 16, a third insulating layer 18, a source electrode 19 and a drain electrode 20, and the flat layer 21
  • a first via hole exposing the drain electrode 20 is provided, and the first via hole is formed after curing and polishing the flat layer 21.
  • the light emitting structure layer may include an anode 31, a pixel defining layer 32, an organic light emitting layer 33, and a cathode 34.
  • the anode 31 is disposed on the surface of the first auxiliary electrode 221 away from the substrate, and the anode 31 is electrically connected to the drain electrode 20 through the first via hole.
  • the flat layer is cured and polished and flattened, so that the flat layer is flatter, and color separation is avoided, resulting in uneven display.
  • punching after curing, polishing and flattening avoids the residue of polishing agent (or acid or alkali will cause certain corrosion and affect TFT characteristics), on the other hand, compared with punching before curing, it can reduce the change of pore diameter. , To avoid affecting the contact resistance and improve the display effect.
  • the second auxiliary electrode 222 may not be provided.
  • a display substrate which may include: a substrate, a driving structure layer sequentially disposed on the substrate, a flat layer 21, an auxiliary layer 22, and a light emitting structure layer; the substrate may include The first substrate 10 and the buffer layer 11, the driving structure layer may include an active layer 12, a first insulating layer 13, a first gate electrode 14, a second insulating layer 16, a third insulating layer 18, a source electrode 19 and leakage
  • the flat layer 21 is provided with a first via hole exposing the drain electrode 20, and the first via hole is formed after the flat layer 21 is cured and polished.
  • the light-emitting structure layer includes an anode 31, a pixel defining layer 32, an organic light-emitting layer 33, and a cathode 34.
  • the anode 31 may be disposed on a surface of the auxiliary layer 22 away from the substrate and electrically connected to the auxiliary layer 22, and the anode 31 may also be electrically connected to the drain electrode 20 through the first via hole.
  • the flat layer is cured and polished and flattened, so that the flat layer is flatter, and color separation is avoided, resulting in uneven display.
  • punching after curing, polishing and flattening on the one hand, avoids the residue of polishing agent (or acid or alkali will cause certain corrosion and affect TFT characteristics), on the other hand, compared with punching before curing, it can reduce the change of pore diameter.
  • the auxiliary layer can be used as a mask during the manufacturing process, which simplifies the manufacturing process and reduces the cost.
  • the auxiliary layer serves as the auxiliary electrode of the anode, which can reduce the IR voltage drop.
  • the embodiment of the present disclosure also provides a display device including the display substrate of the foregoing embodiment.
  • the display device may be an OLED display device, or other display devices.
  • the display device may be any product or component with a display function, such as a smart bracelet, a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种显示基板及其制备方法、显示装置。所述显示基板的制备方法包括：形成基底，在所述基底上形成驱动结构层，所述驱动结构层包括薄膜晶体管；在所述驱动结构层远离所述基底一侧形成平坦层，对所述平坦层进行固化和抛光磨平处理后，形成贯穿所述平坦层且暴露所述薄膜晶体管的第一极的第一过孔；在所述平坦层远离所述基底一侧形成发光结构层。

Description

显示基板及其制备方法、显示装置
本申请要求于2020年6月15日提交中国专利局、申请号为202010542262.6、发明名称为“一种显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术，尤指一种显示基板及其制备方法、显示装置。
背景技术
近年来，有机发光二极管(Organic Light-Emitting Diode，OLED)屏幕以其轻薄，优异显示效果，高对比度，广色域，柔性等一系列的优点受到人们的广泛关注，被认为是有望取代液晶的下一代显示器方案。随着对全面屏的需求，对屏幕厚度减薄的技术越来越受到消费者的欢迎。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板及其制备方法、显示装置。
一方面，本公开实施例提供了一种显示基板的制备方法，包括：
形成基底，在所述基底上形成驱动结构层，所述驱动结构层包括薄膜晶体管；
在所述驱动结构层远离所述基底一侧形成平坦层，对所述平坦层进行固化和抛光磨平处理后，形成贯穿所述平坦层且暴露所述薄膜晶体管的第一极的第一过孔；
在所述平坦层远离所述基底一侧形成发光结构层。
在一示例性实施例中，在所述平坦层远离所述基底一侧形成发光结构层前，还包括：
在所述平坦层和所述发光结构层之间形成辅助层。
在一示例性实施例中，所述形成贯穿所述平坦层且暴露所述薄膜晶体管的第一极的第一过孔包括：使用所述辅助层作为掩膜版刻蚀形成所述第一过孔。
在一示例性实施例中，所述辅助层的材料包括金属。
在一示例性实施例中，所述在所述平坦层和所述发光结构层之间形成辅助层包括：
在所述平坦层和所述发光结构层之间形成包括彼此独立的第一辅助电极和第二辅助电极的辅助层；
在所述平坦层远离所述基底一侧形成发光结构层包括：
在所述辅助层远离所述基底一侧形成第一电极，所述第一电极电连接所述第一辅助电极和所述薄膜晶体管的第一极；
在所述第一电极远离所述基底一侧形成像素界定层，所述像素界定层开设有暴露所述第二辅助电极的第二过孔；
在所述像素界定层远离所述基底一侧依次形成有机发光层和第二电极，所述第二电极通过所述第二过孔电连接所述第二辅助电极。
在一示例性实施例中，所述平坦层的材料包括黑色材料。
又一方面，本公开实施例提供一种显示基板，所述显示基板包括：基底、依次设置在所述基底上的驱动结构层、平坦层和发光结构层；所述驱动结构层包括薄膜晶体管，所述薄膜晶体管包括第一极，所述平坦层设置有暴露所述薄膜晶体管的第一极的第一过孔，且所述第一过孔在对所述平坦层固化和抛光磨平后形成。
在一示例性实施例中，所述显示基板还包括：设置在所述平坦层和所述发光结构层之间的辅助层。
在一示例性实施例中，所述辅助层的材料包括金属。
在一示例性实施例中，所述辅助层包括第一辅助电极；
所述发光结构层包括从靠近所述辅助层一侧到远离所述辅助层一侧依次设置的第一电极、像素界定层、有机发光层和第二电极，所述第一电极通过所述第一过孔与所述薄膜晶体管的第一极电连接，所述第一电极电连接所述第一辅助电极。
在一示例性实施例中，所述辅助层包括彼此独立的第一辅助电极和第二辅助电极；
所述发光结构层包括从靠近所述辅助层一侧到远离所述辅助层一侧依次设置的第一电极、像素界定层、有机发光层和第二电极，所述第一电极通过所述第一过孔与所述薄膜晶体管的第一极电连接，所述第一电极电连接所述第一辅助电极；所述像素界定层开设有暴露所述第二辅助电极的第二过孔；所述第二电极通过所述第二过孔电连接所述第二辅助电极。
在一示例性实施例中，所述第一电极设置在所述第一辅助电极表面。
在一示例性实施例中，所述平坦层的材料包括黑色材料。
在一示例性实施例中，所述平坦层的材料包括非光敏性材料。
再一方面，本公开实施例提供一种显示装置，包括上述实施例所述的显示基板。
本公开实施例其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开实施例而了解。本公开实施例的目的和优点可通过在说明书以及附图中所特别指出的结构来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开实施例技术方案的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释技术方案，并不构成对技术方案的限制。
图1为一技术方案提供的显示基板示意图；
图2为一实施例提供的显示基板的制备方法流程图；
图3为一实施例提供的形成基底图案后的示意图；
图4为一实施例提供的形成驱动结构层后的示意图；
图5为一实施例提供的形成平坦层后的示意图；
图6为一实施例提供的沉积辅助层后的示意图；
图7为一实施例提供的形成辅助层图案后的示意图；
图8为一实施例提供的形成第一过孔后的示意图；
图9为一实施例提供的形成阳极后的示意图；
图10为一实施例提供的形成发光结构层后的示意图；
图11为一实施例提供的形成封装层后的示意图；
图12为一实施例提供的显示基板示意图；
图13为另一实施例提供的显示基板示意图；
图14为又一实施例提供的显示基板示意图。
具体实施方式
下文中将结合附图对本公开实施例进行详细说明。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。 “上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，可以是第一极为漏电极、第二极为源电极，或者可以是第一极为源电极、第二极为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，第一电极可以是阳极，第二电极可以是阴极；或者，第一电极可以是阴极，第二电极可以是阳极，根据显示基板的发光结构而定。
有机发光显示基板中，通常用涂布RGB Color filter(红绿蓝彩色滤光片)来替代偏光片(Polarizer，POL)的作用，但因工艺水平的影响，阳极的不平坦会造成色分离，使得显示不均。
图1为一种技术方案中提供的显示基板的示意图。如图1所示，所述显示基板包括基底1、驱动结构层2和平坦层3，驱动结构层2包括薄膜晶体管(Thin Film Transistor，TFT)，因为区域化TFT设计的影响，TFT上方的平坦层3区域虽经过流平设计，但因为工艺偏差(floating)的影响，此处的高度相较于其他区域要高出0.2微米(μm)至1.2微米，造成平坦层3的不平坦化，从而造成色分离，使得显示不均。另外，该设计中，平坦层3打孔设计之后还要经过热烘烤固化，会造成孔径比的变化，变化范围大致在1％～10％之间，孔径比变化较大，导致阳极与薄膜晶体管接触电阻改变，影响显示效果。
本公开实施例中提供一种显示基板及其制备方法、显示装置，以满足使阳极平坦的要求，防止彩色滤光片结构(Color Filter on Encapsulation，COE)设计时因阳极不平坦造成的色分离现象，且能确保孔径比。
图2为本公开实施例提供的一种显示基板的制备方法流程图。如图2所 示，本公开实施例提供的显示基板的制备方法可以包括：
步骤201，形成基底，在所述基底上形成驱动结构层，所述驱动结构层包括薄膜晶体管，所述薄膜晶体管包括第一极；
步骤202，在所述驱动结构层远离所述基底一侧形成平坦层，对所述平坦层进行固化和抛光磨平处理后，形成贯穿所述平坦层且暴露所述薄膜晶体管的第一极的第一过孔；
步骤203，在所述平坦层远离所述基底一侧形成发光结构层。
本实施例提供的方案，对平坦层进行固化和抛光磨平处理，提高了平坦层的平坦度，避免色分离导致显示不均，提高显示效果。另外，在固化和抛光磨平后再打孔，一方面避免抛光剂(或酸或碱会造成一定的腐蚀，影响TFT特性)的残留，另一方面相比固化前打孔，可以降低孔径变化，避免影响接触电阻，提高显示效果。
在一示例性实施例中，所述第一极比如为漏电极，但本公开实施例不限于此，显示基板结构改变时，第一极可以是源电极。
在一示例性实施例中，在所述平坦层远离所述基底一侧形成发光结构层前，还可以包括：在所述平坦层和所述发光结构层之间形成辅助层。所述辅助层可以是绝缘的，或者，可以是导电的，或者，可以部分绝缘部分导电，等等。在其他实施例中，可以无辅助层。所述辅助层可以作为辅助电极，或者，可以作为后续流程中的掩膜版。
在一示例性实施例中，所述形成贯穿所述平坦层且暴露所述薄膜晶体管的第一极的第一过孔可以包括：使用所述辅助层作为掩膜版刻蚀形成所述第一过孔。所述辅助层在形成所述第一过孔前形成。本实施例中，使用辅助层作为掩膜版，可以简化制备流程，降低成本。在另一实施例中，可以不使用辅助层作为掩膜版。
在一示例性实施例中，所述辅助层的材料可以包括金属。辅助层使用金属制备时，可以作为辅助电极。比如，作为阳极的辅助电极，或者，作为阴极的辅助电极，或者，作为阳极的辅助电极和阴极的辅助电极，本实施例中，使用辅助电极，可以降低IR压降(IR Drop)。在其他实施例中，辅助层可 以使用非金属。
在一示例性实施例中，所述辅助层可以包括彼此独立的第一辅助电极和第二辅助电极；
所述在所述平坦层远离所述基底一侧形成发光结构层可以包括：
在所述辅助层远离所述基底一侧形成第一电极，所述第一电极可以电连接所述第一辅助电极和所述薄膜晶体管的第一极；
在所述第一电极远离所述基底一侧形成像素界定层，所述像素界定层开设有暴露所述第二辅助电极的第二过孔；
在所述像素界定层远离所述基底一侧依次形成有机发光层和第二电极，所述第二电极通过所述第二过孔电连接所述第二辅助电极。本实施例中，辅助层作为第一极的辅助电极和第二极的辅助电极，降低了IR Drop。另一实施例中，可以只有第一辅助电极。
下面通过一示例说明显示基板的制备过程。其中，本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光、显影等处理，本实施例中所说的蒸镀、沉积、涂覆、涂布等均是相关技术中成熟的制备工艺。
图3至图12为本实施例显示基板制备过程的示意图。显示基板的制备过程包括：
(1)形成基底图案。形成基底图案包括：在玻璃载板9上涂布一层柔性材料，固化成膜，形成第一基底10。在第一基底10沉积一层缓冲薄膜，形成覆盖整个第一基底10的缓冲层11图案。其中，柔性材料可以采用压敏胶(Pressure Sensitive Adhesive，简称PSA)、聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，形成柔性基底，如图3所示。缓冲薄膜可以采用氮化硅(SiNx)或氧化硅(SiOx)等，可以是单层，或者可以是氮化硅/氧化硅的多层结构。
(2)在基底上形成有源层、栅电极、源电极和漏电极图案。
如图4所示，在基底上形成有源层、栅电极、源电极和漏电极图案包括：
在形成上述结构的基础上，沉积一层有源层薄膜，通过构图工艺对有源层薄膜进行构图，在显示区域形成设置在缓冲层11上的有源层12图案；
依次沉积第一绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖有源层12的第一绝缘层13、设置在第一绝缘层13上的第一栅电极14、第二栅电极(未示出)和栅线(未示出)图案。
依次沉积第二绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一栅电极14和第二栅电极的第二绝缘层16以及设置在第二绝缘层16上的电容电极(未示出)图案，电容电极的位置与第二栅电极的位置相对应，电容电极与第二栅电极构成电容。
在形成上述结构的基础上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，在显示区域形成开设有过孔的第三绝缘层18图案，过孔中的第三绝缘层18、第二绝缘层16和第一绝缘层13被刻蚀掉，暴露出有源层12；
沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在显示区域形成源电极19、漏电极20和数据线(未示出)图案，源电极19和漏电极20分别通过过孔与有源层12连接。
通过上述过程，在基底上完成了显示区域的驱动结构层的制备。其中，驱动结构层包括有源层12、第一栅电极14、第二栅电极、电容电极、源电极19、漏电极20、栅线和数据线，栅线和数据线垂直交叉限定出子像素，由有源层12、第一栅电极14、源电极19和漏电极20构成的薄膜晶体管设置在子像素内。其中，第一绝缘层13和第二绝缘层16可称为栅绝缘层(GI)，第三绝缘层18可称为层间绝缘层(ILD)。
(4)形成平坦层图案。
形成平坦层图案包括：在形成上述结构的基础上，涂覆第四绝缘薄膜，进行烘烤固化成型，抛光磨平形成覆盖源电极19和漏电极20的平坦层21图案，如图5所示。本实施例中，通过抛光磨平可以提高平坦度，使得后续阳极平坦度相应提高。
在一示例性实施例中，抛光磨平可以是使用化学(使用抛光剂)或机械的方式进行。
在一示例性实施例中，所述第四绝缘薄膜可以使用黑色材料，防止光照对栅极走线造成影响，而且可以降低走线的反射率。此处黑色材料包括黑色和接近黑色的材料。所述黑色材料比如包括黑色的PI，硅氧烷基粘合剂，或者黑色的颜料，染料等。本公开实施例不限于此，可以使用非黑色材料，比如，透明材料，非黑色的防反射材料等等。
在一示例性实施例中，所述第四绝缘薄膜可以使用非光敏性材料，由于光敏性材料成本较高，使用非光敏性材料可以降低成本。常规的平坦层材料包含光敏性材料，因此，可以使用不含光敏性材料的材料制作平坦层。所述第四绝缘薄膜可以是黑色的非光敏性材料，或者，是非黑色的非光敏性材料。
(5)形成辅助层图案
所述形成辅助层图案包括：
沉积辅助层薄膜，如图6所示。所述辅助层薄膜比如为导电材料或绝缘材料，所述导电材料比如包括金属或导电薄膜(比如氧化铟锡(Indium Tin Oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)等)，所述金属比如包括镁(Mg)、银(Ag)、铝(Al)、铜(Cu)、锂(Li)等金属材料的一种，或上述金属的合金。所述绝缘材料比如包括无机绝缘材料，比如硅氮化物(SiNx)、硅氧化物(SiOx)、氮氧化硅等。
通过构图工艺对辅助层薄膜进行构图，生成包括第一辅助电极221和第二辅助电极222的辅助层，如图7所示。其中，第一辅助电极221可以与阳极电连接，第二辅助电极222可以与阴极电连接，从而降低IR压降。本公开实施例不限于此，可以只有第一辅助电极221与阳极电连接，或者，只有第二辅助电极222与阴极电连接。当只有第一辅助电极221与阳极电连接时，无第二过孔。当只有第二辅助电极222与阴极电连接时，辅助层可以部分使用绝缘材料(第一辅助电极221对应的部分)，部分使用金属(第二辅助电极222对应的部分)，等等。
以辅助层作为掩膜版，刻蚀(比如干刻)形成贯穿所述平坦层21的第一 过孔23，所述第一过孔23暴露出所述漏电极20，如图8所示。
本实施例中，使用辅助层作为掩膜版，避免了额外使用掩膜版，简化了流程，降低了成本。另外，在平坦层抛光磨平之后再形成过孔，相比形成第一过孔后再进行抛光磨平，本实施例提供的方案，不会有抛光剂的残留(抛光剂或酸或碱会造成一定的腐蚀，影响TFT特性)，不会对源漏电极造成损伤。另外，在烘烤固化后再打孔，对孔径比的影响变化量在2％以内，大大降低了孔径比的变化量，避免造成阳极与漏电极的接触电阻变化，提高了显示效果。
(6)形成阳极图案。
沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，在显示区域形成阳极31图案，阳极31通过第一过孔23与漏电极20连接，如图9所示。透明导电薄膜可以采用ITO或IZO或者ITO/Al(铝)/ITO多层复合材料。在另一实施例中，第二辅助电极222可以和阳极31同层设置。
(5)形成像素界定层、有机发光层和阴极图案。
形成像素界定层、有机发光层和阴极图案包括：在形成前述图案的基底上涂覆像素界定薄膜，通过光刻工艺在显示区域形成像素界定层(Pixel Define Layer，简称PDL)32图案，像素界定层32在每个子像素限定出暴露阳极31的像素开口区域以及第二过孔，所述第二过孔暴露出第二辅助电极222，其中，像素界定层32的材料可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。
依次蒸镀有机发光材料及阴极金属，形成有机发光层33和阴极34图案，有机发光层33与像素界定层32限定出的像素开口区域内的阳极31连接，阴极34设置在有机发光层33上，阴极34与第二辅助电极222电连接，如图10所示。其中，有机发光层33包括发光层(EML)。实际实施时，有机发光层33可以包括依次设置的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，提高电子和空穴注入发光层的效率，阴极34可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)、锂(Li)等金属材料的一种，或上述金属的合金。
(6)形成封装层图案。形成封装层图案包括：在形成前述图案的基底上，先沉积第一无机薄膜，形成第一无机层图案，采用喷墨打印方式在显示区域形成有机层，有机层仅形成在显示区域的第一无机层上。沉积第二无机薄膜，第二无机薄膜覆盖显示区域和非显示区域，形成第二无机层图案，如图11所示。这样，即完成包括无机/有机/无机三层结构的封装层35，中间的有机层仅形成在显示区域，上下两层无机层覆盖显示区域和非显示区域。其中，第一无机薄膜比如为氮氧化硅(SiON)，第二无机薄膜比如为氮化硅(SiNx)。
(9)剥离玻璃载板9，完成显示基板的制备，如图12所示。
本实施例所示结构及其制备过程仅仅是一种示例性说明。实际实施时，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，显示基板不仅可以顶发射结构，也可以是底发射结构。又如，薄膜晶体管可以是顶栅结构，或者，可以是底栅结构，或者，可以是双栅结构，或者，可以是单栅结构。再如，薄膜晶体管可以是非晶硅(a-Si)薄膜晶体管、低温多晶硅(LTPS)薄膜晶体管或氧化物(Oxide)薄膜晶体管，驱动结构层和发光结构层中还可以设置其它电极、引线和结构膜层。
图12为另一实施例提供的显示基板示意图。如图12所示，本实施例提供的显示基板可以包括：基底、依次设置在所述基底上的驱动结构层、平坦层21、辅助层22和发光结构层；所述基底可以包括第一基底10和缓冲层11，所述驱动结构层可以包括有源层12、第一绝缘层13、第一栅电极14、第二绝缘层16、第三绝缘层18、源电极19和漏电极20，所述平坦层21设置有暴露所述漏电极20的第一过孔，且所述第一过孔在对所述平坦层21固化和抛光磨平后形成。所述辅助层22可以包括彼此独立的第一辅助电极221和第二辅助电极222，所述发光结构层可以包括阳极31、像素界定层32、有机发光层33和阴极34。所述阳极31可以设置在所述第一辅助电极221远离所述基底一侧的表面，与所述第一辅助电极221电连接，所述阳极31还可以通过所述第一过孔电连接到所述漏电极20。所述像素界定层32设置有暴露所述第二辅助电极222的第二过孔，所述阴极34可以通过第二过孔与所述第二辅助电极222电连接。
本实施例提供的显示基板，对平坦层进行固化和抛光磨平处理，使得平 坦层更为平坦，避免了色分离，导致显示不均。另外，在固化和抛光磨平后再打孔，一方面避免抛光剂(或酸或碱会造成一定的腐蚀，影响TFT特性)的残留，另一方面相比固化前打孔，可以降低孔径变化，避免影响接触电阻，提高显示效果。另外，第一辅助电极221和第二辅助电极222降低了IR压降，且辅助层在制作过程中可以作为掩膜版，简化了制备过程，降低成本。
在一示例性实施例中，所述平坦层21的材料可以包括黑色材料，防止光照对栅极走线造成影响，以及，可以降低反射率。
在一示例性实施例中，所述平坦层21的材料可以包括非光敏性材料。即平坦层21可以不包含光敏性材料，降低成本。
在一示例性实施例中，可以不设置辅助层22。图13为另一实施例提供的显示基板示意图。如图13所示，本实施例提供的显示基板可以包括基底、依次设置在所述基底上的驱动结构层、平坦层21和发光结构层；所述基底可以包括第一基底10和缓冲层11，所述驱动结构层可以包括有源层12、第一绝缘层13、第一栅电极14、第二绝缘层16、第三绝缘层18、源电极19和漏电极20，所述平坦层21设置有暴露所述漏电极20的第一过孔，且所述第一过孔在对所述平坦层21固化和抛光磨平后形成。所述发光结构层可以包括阳极31、像素界定层32、有机发光层33和阴极34。所述阳极31设置在所述第一辅助电极221远离基底一侧的表面，所述阳极31通过所述第一过孔电连接到所述漏电极20。
本实施例提供的显示基板，对平坦层进行固化和抛光磨平处理，使得平坦层更为平坦，避免了色分离，导致显示不均。另外，在固化和抛光磨平后再打孔，一方面避免抛光剂(或酸或碱会造成一定的腐蚀，影响TFT特性)的残留，另一方面相比固化前打孔，可以降低孔径变化，避免影响接触电阻，提高显示效果。
在一示例性实施例中，可以不设置第二辅助电极222。如图14所示，本公开实施例提供一种显示基板，可以包括：基底、依次设置在所述基底上的驱动结构层、平坦层21、辅助层22和发光结构层；所述基底可以包括第一基底10和缓冲层11，所述驱动结构层可以包括有源层12、第一绝缘层13、第一栅电极14、第二绝缘层16、第三绝缘层18、源电极19和漏电极20，所 述平坦层21设置有暴露所述漏电极20的第一过孔，且所述第一过孔在对所述平坦层21固化和抛光磨平后形成。所述发光结构层包括阳极31、像素界定层32、有机发光层33和阴极34。所述阳极31可以设置在所述辅助层22远离基底一侧的表面，与所述辅助层22电连接，所述阳极31还通过所述第一过孔电连接到所述漏电极20。
本实施例提供的显示基板，对平坦层进行固化和抛光磨平处理，使得平坦层更为平坦，避免了色分离，导致显示不均。另外，在固化和抛光磨平后再打孔，一方面避免抛光剂(或酸或碱会造成一定的腐蚀，影响TFT特性)的残留，另一方面相比固化前打孔，可以降低孔径变化，避免影响接触电阻，提高显示效果。另外，辅助层在制备过程中可以作为掩膜版，简化了制作流程，降低成本。辅助层作为阳极的辅助电极，可以降低IR压降。
基于本公开实施例的技术构思，本公开实施例还提供了一种显示装置，包括前述实施例的显示基板。所述显示装置可以是OLED显示装置，或者，其他显示装置。所述显示装置可以为：智能手环，手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开实施例及实施例中的特征可以相互组合以得到新的实施例。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利 要求书所界定的范围为准。

Claims (15)

  1. 一种显示基板的制备方法，包括：
    形成基底，在所述基底上形成驱动结构层，所述驱动结构层包括薄膜晶体管，所述薄膜晶体管包括第一极；
    在所述驱动结构层远离所述基底一侧形成平坦层，对所述平坦层进行固化和抛光磨平处理后，形成贯穿所述平坦层且暴露所述薄膜晶体管的第一极的第一过孔；
    在所述平坦层远离所述基底一侧形成发光结构层。
  2. 根据权利要求1所述的显示基板的制备方法，其中，在所述平坦层远离所述基底一侧形成发光结构层前，还包括：
    在所述平坦层和所述发光结构层之间形成辅助层。
  3. 根据权利要求2所述的显示基板的制备方法，其中，所述形成贯穿所述平坦层且暴露所述薄膜晶体管的第一极的第一过孔包括：使用所述辅助层作为掩膜版刻蚀形成所述第一过孔。
  4. 根据权利要求2所述的显示基板的制备方法，其中，所述辅助层的材料包括金属。
  5. 根据权利要求2所述的显示基板的制备方法，其中，
    所述在所述平坦层和所述发光结构层之间形成辅助层包括：
    在所述平坦层和所述发光结构层之间形成包括彼此独立的第一辅助电极和第二辅助电极的辅助层；
    所述在所述平坦层远离所述基底一侧形成发光结构层包括：
    在所述辅助层远离所述基底一侧形成第一电极，所述第一电极电连接所述第一辅助电极和所述薄膜晶体管的第一极；
    在所述第一电极远离所述基底一侧形成像素界定层，所述像素界定层开设有暴露所述第二辅助电极的第二过孔；
    在所述像素界定层远离所述基底一侧依次形成有机发光层和第二电极，所述第二电极通过所述第二过孔电连接所述第二辅助电极。
  6. 根据权利要求1至5任一所述的显示基板的制备方法，其中，所述平坦层的材料包括黑色材料。
  7. 一种显示基板，包括：基底、依次设置在所述基底上的驱动结构层、平坦层和发光结构层；所述驱动结构层包括薄膜晶体管，所述薄膜晶体管包括第一极，所述平坦层设置有暴露所述薄膜晶体管的第一极的第一过孔，且所述第一过孔在对所述平坦层进行固化和抛光磨平处理后形成。
  8. 根据权利要求7所述的显示基板，其中，所述显示基板还包括：设置在所述平坦层和所述发光结构层之间的辅助层。
  9. 根据权利要求8所述的显示基板，其中，所述辅助层的材料包括金属。
  10. 根据权利要求8所述的显示基板，其中，所述辅助层包括第一辅助电极；
    所述发光结构层包括从靠近所述辅助层一侧到远离所述辅助层一侧依次设置的第一电极、像素界定层、有机发光层和第二电极，所述第一电极通过所述第一过孔与所述薄膜晶体管的第一极电连接，所述第一电极电连接所述第一辅助电极。
  11. 根据权利要求8所述的显示基板，其中，
    所述辅助层包括彼此独立的第一辅助电极和第二辅助电极；
    所述发光结构层包括从靠近所述辅助层一侧到远离所述辅助层一侧依次设置的第一电极、像素界定层、有机发光层和第二电极，所述第一电极通过所述第一过孔与所述薄膜晶体管的第一极电连接，所述第一电极电连接所述第一辅助电极；所述像素界定层开设有暴露所述第二辅助电极的第二过孔；所述第二电极通过所述第二过孔电连接所述第二辅助电极。
  12. 根据权利要求10或11所述的显示基板，其特征在于，所述第一电极设置在所述第一辅助电极表面。
  13. 根据权利要求7至11任一所述的显示基板，其中，所述平坦层的材料包括黑色材料。
  14. 根据权利要求7至11任一所述的显示基板，其中，所述平坦层的材料包括非光敏性材料。
  15. 一种显示装置，包括如权利要求7至14任一所述的显示基板。
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