WO2022048538A1 - 阵列基板及其制备方法、显示面板和背光模组 - Google Patents

阵列基板及其制备方法、显示面板和背光模组 Download PDF

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Publication number
WO2022048538A1
WO2022048538A1 PCT/CN2021/115688 CN2021115688W WO2022048538A1 WO 2022048538 A1 WO2022048538 A1 WO 2022048538A1 CN 2021115688 W CN2021115688 W CN 2021115688W WO 2022048538 A1 WO2022048538 A1 WO 2022048538A1
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Prior art keywords
layer
metal
copper
base substrate
array substrate
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PCT/CN2021/115688
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English (en)
French (fr)
Inventor
王珂
曹占锋
卢鑫泓
齐琪
曲燕
梁志伟
刘英伟
薛大鹏
王国强
汪建国
刘松
李永飞
曾亭
刘欢
董万如
桂和仁
杨健
胡海峰
江玉
徐鹏
储微微
高琪
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京东方科技集团股份有限公司
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Priority claimed from CN202010927576.8A external-priority patent/CN114156394A/zh
Priority claimed from CN202010927603.1A external-priority patent/CN114156395A/zh
Priority claimed from CN202010947439.0A external-priority patent/CN114171661A/zh
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/790,308 priority Critical patent/US20230043951A1/en
Publication of WO2022048538A1 publication Critical patent/WO2022048538A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a preparation method thereof, a display panel and a backlight module.
  • a metal wiring layer arranged on one side of the base substrate
  • a second planarization layer disposed on the side of the electrode layer away from the base substrate;
  • the material of the metal sub-layer is copper; the material of the conductive sub-layer is copper-nickel alloy.
  • the electrode layer may further include a palladium metal layer sandwiched between the metal sublayer and the conductive sublayer; the palladium metal layer is located and covers the metal sublayer away from the surface of the base substrate and the side surface of the metal sub-layer; the conductive sub-layer is located on and covers the surface of the palladium metal layer away from the base substrate.
  • the mass content of nickel in the conductive sub-layer is not less than 30%.
  • the mass content of nickel in the conductive sub-layer is not more than 80%.
  • the thickness of the conductive sub-layer is 500-2000 angstroms.
  • the material of the conductive sub-layer includes a metal oxide.
  • the material of the conductive sub-layer includes indium zinc oxide or indium tin oxide.
  • the array substrate includes a circuit board bonding area and a light emitting area, wherein the circuit board bonding area includes a plurality of pin pads for connecting with circuit board binding connection;
  • the light-emitting area includes a plurality of device pads, and the device pads are used for bonding and connection with the functional device;
  • the lead pad and the device pad are arranged on the electrode layer.
  • the circuit board bonding area further includes a first connection part, the first connection part is located on a side of the conductive sub-layer away from the base substrate; the first connection part It is used for bonding and connecting the conductive sublayer of the pin pad with the circuit board.
  • the material of the conductive sub-layer includes a metal oxide; the device pad is disposed on the metal sub-layer and exposed by the conductive sub-layer;
  • the light emitting area further includes a second connection part, the second connection part is located on the side of the metal sub-layer of the device pad away from the base substrate; the second connection part is used to make the device solder The metal sublayer of the disk is bonded to the functional device.
  • the material of the conductive sub-layer includes a copper-nickel alloy
  • the light emitting area further includes a second connection part, the second connection part is located on the side of the conductive sub-layer of the device pad away from the base substrate; the second connection part is used to make the device solder The conductive sublayer of the disk is bonded and connected to the functional device.
  • the base substrate exposes the surface of the lead pad close to the base substrate; the surface of the lead pad exposed by the base substrate is used for bonding and connection with the circuit board.
  • the pin pads are disposed on the metal wiring layer.
  • the electrode layer is provided with a plurality of device pads; the plurality of device pads are divided into a plurality of groups of device pads, and each group of the device pads includes a pair of cathode pads and anode pad;
  • the electrode layer further includes a second buffer metal layer located on a surface of the metal sublayer close to the base substrate.
  • the metal wiring layer includes a seed metal layer, a copper growth layer, and a second copper-nickel alloy layer sequentially stacked on one side of the base substrate.
  • a functional device layer is provided; the functional device layer is provided on the side of the second planarization layer away from the base substrate, and includes a plurality of functional devices electrically connected to the electrode layer.
  • a first buffer metal material layer and a conductive sub-material layer are sequentially formed on the side of the metal sub-layer away from the base substrate;
  • forming the palladium metal layer includes:
  • FIG. 9 is a schematic structural diagram of forming a copper electrode layer and a second buffer metal layer according to an embodiment of Example 1.
  • FIG. 9 is a schematic structural diagram of forming a copper electrode layer and a second buffer metal layer according to an embodiment of Example 1.
  • FIG. 10 is a schematic structural diagram of forming a first buffer metal material layer and a first copper-nickel alloy material layer according to an embodiment of Example 1.
  • FIG. 10 is a schematic structural diagram of forming a first buffer metal material layer and a first copper-nickel alloy material layer according to an embodiment of Example 1.
  • FIG. 12 is a schematic structural diagram of an array substrate according to an embodiment of Example 1.
  • FIG. 12 is a schematic structural diagram of an array substrate according to an embodiment of Example 1.
  • FIG. 35 is a schematic structural diagram of an array substrate according to an embodiment of the second embodiment.
  • FIG. 1 is an electron microscope image after etching of a metal layer composed of a stacked molybdenum-niobium alloy layer (MoNb), a copper metal layer (Cu) and a copper-nickel alloy layer (CuNi).
  • MoNb molybdenum-niobium alloy layer
  • Cu copper metal layer
  • CuNi copper-nickel alloy layer
  • the mass content of nickel in the copper-nickel alloy layer also often named as the weight content
  • the copper-nickel alloy layers form the roof structure.
  • FIG. 2 is an electron microscope image after etching of a metal layer composed of a stacked molybdenum-niobium alloy layer (MoNb), a copper metal layer (Cu) and a copper-nickel alloy layer (CuNi).
  • This embodiment provides an array substrate and a preparation method thereof.
  • the preparation method of the array substrate includes:
  • Step AS130 referring to FIG. 7, forming a first planarization layer A300 on the side of the metal wiring layer A200 away from the base substrate A100;
  • any film layer may include a side surface, a surface close to the base substrate, and a surface far away from the base substrate, wherein the surface close to the base substrate and the surface away from the base substrate are connected by the side surface of the film layer.
  • the thickness of any film layer is the dimension of the film layer in the direction perpendicular to the base substrate.
  • a base substrate A100 may be provided.
  • the base substrate A100 may be the base substrate A100 of an inorganic material or the base substrate A100 of an organic material.
  • the material of the base substrate A100 may be glass materials such as soda-lime glass (soda-lime glass), quartz glass, sapphire glass, etc., or may be stainless steel, aluminum, nickel and other metal materials.
  • the base substrate A100 may also be a flexible base substrate A100, for example, the material of the base substrate A100 may be polyimide (polyimide, PI).
  • the base substrate A100 may also be a composite of multi-layer materials.
  • the base substrate A100 may include a bottom film layer (Bottom Film) and a pressure-sensitive adhesive layer that are stacked in sequence. , a first polyimide layer and a second polyimide layer.
  • an insulating buffer layer A101 may also be formed on one side of the base substrate A100, for example, a silicon nitride layer, a silicon oxide layer or a silicon oxynitride layer may be formed ; Then, a metal wiring layer A200 is formed on the side of the insulating buffer layer A101 away from the base substrate A100.
  • the insulating buffer layer A101 can improve the stress applied to the base substrate when the metal wiring layer A200 is formed, and can isolate water vapor.
  • the material of the base substrate A100 is glass, so that the base substrate has a large size and low cost, and is convenient to be used as a backlight source of a direct type backlight module to reduce backlight The cost of the mod.
  • the material of the base substrate A100 is polyimide, so that the array substrate can be a flexible array substrate, which facilitates the fabrication of a flexible or foldable display panel from the array substrate.
  • a metal wiring layer A200 may be formed on one side of the base substrate A100.
  • the metal wiring layer A200 may include metal leads, and the metal leads may drive the respective functional devices A610 through the electrode layer A400.
  • the metal wiring layer A200 can be formed by deposition and patterning methods, wherein the deposition methods include but are not limited to sputtering, electroplating and electroless plating, and the patterning methods include but are not limited to photolithography, growth on the patterned seed layer A patterned growth layer is grown, a patterned metal pattern is grown under the definition of the pattern defining layer, and the like.
  • the metal wiring material layer includes at least a first copper metal material layer so that the metal leads have low resistance.
  • the thickness of the first copper metal material layer is not greater than 1 micrometer, so as to prevent excessive stress on the base substrate A100 during the process of forming the first copper metal material layer by sputtering. After the first copper metal material layer is patterned, a first copper metal layer is formed. In this way, in the prepared array substrate, the metal wiring layer A200 includes at least the first copper metal layer.
  • the metal wiring material layer may further include a first adhesion material layer located on the surface of the first copper metal material layer close to the base substrate A100, and the material of the first adhesion material layer may be molybdenum, molybdenum copper alloy, molybdenum Niobium alloys, molybdenum copper niobium alloys or other metals or metal alloys.
  • a first adhesive layer is formed. The first adhesion layer can improve the adhesion between the first copper metal layer and the base substrate A100 or the insulating buffer layer A101, and protect the metal copper from corrosion.
  • the metal wiring layer A200 may include the first adhesive layer and the first copper metal layer sequentially stacked on one side of the base substrate A100.
  • the metal wiring material layer may further include a second adhesion material layer located on the surface of the first copper metal material layer away from the base substrate A100, and the material of the second adhesion material layer may be molybdenum, molybdenum copper alloy, molybdenum Niobium alloys, molybdenum copper niobium alloys or other metals or metal alloys.
  • a second adhesive layer is formed after the second adhesive material layer is patterned.
  • the second adhesion layer can improve the adhesion between the first copper metal layer and the electrode layer A400, and protect the metal copper from corrosion.
  • the metal wiring layer A200 may include the first copper metal layer and the second adhesion layer sequentially stacked on one side of the base substrate A100.
  • the metal wiring layer A200 includes a molybdenum-niobium alloy layer, a copper metal layer, and a molybdenum-niobium alloy layer sequentially stacked on one side of the base substrate A100.
  • the metal wiring layer A200 can be prepared by the following methods:
  • a first metal wiring material layer is formed on one side of the base substrate A100, and the first metal wiring material layer includes a molybdenum-niobium alloy material layer, a copper metal material layer, and a molybdenum-niobium alloy material layer stacked in sequence. Then, a mask is used to pattern the first metal wiring material layer, so as to pattern the first metal wiring material layer into a first metal wiring layer.
  • the first metal wiring layer includes a stacked molybdenum-niobium alloy layer, a copper metal layer and a molybdenum-niobium alloy layer.
  • a second metal wiring material layer is formed on the side of the first metal wiring layer away from the base substrate A100, and the second metal wiring material layer includes a molybdenum-niobium alloy material layer, a copper metal material layer and a molybdenum-niobium alloy material layer stacked in sequence. Then, a patterning operation is performed on the second metal wiring material layer using the same mask, so as to pattern the second metal wiring material layer into a second metal wiring layer.
  • the second metal wiring layer includes a stacked molybdenum-niobium alloy layer, a copper metal layer and a molybdenum-niobium alloy layer.
  • the metal wiring layer A200 includes the stacked first metal wiring layer and the second metal wiring layer, and the patterns of the first metal wiring layer and the second metal wiring layer are the same.
  • the metal wiring layer A200 includes a molybdenum-niobium alloy layer, a copper metal layer, a molybdenum-niobium alloy layer, a molybdenum-niobium alloy layer, a copper metal layer, and a molybdenum-niobium alloy layer that are stacked in sequence. This can increase the thickness of the metal wiring layer A200, reduce the impedance of the metal wiring layer A200, and meet the electrical requirements of the array substrate.
  • the metal wiring layer A200 can be prepared by the following methods:
  • step AS210 a seed metal material layer is formed by sputtering on one side of the base substrate A100;
  • Step AS220 forming a pattern-defining layer on the surface of the seed metal material layer away from the base substrate A100, the material of the pattern-defining layer is a removable insulating material, and the pattern-defining layer is formed with a plurality of patterns exposing the seed metal material layer opening;
  • Step AS230 forming a copper growth material layer in the opening of the pattern defining layer by means of electroplating copper;
  • Step AS240 remove the pattern defining layer
  • step AS250 an etching method is used to remove the part of the seed metal material layer that is not covered by the copper growth material layer, so that the seed metal material layer is patterned into a seed metal layer; during the etching process, there is no need for the copper growth material layer.
  • the protection is performed, so that the surface of the copper growth material layer is partially etched to form a copper growth layer.
  • the seed metal material layer may include a second copper metal material layer, and the thickness of the second copper metal material layer is not greater than 1 micrometer.
  • the thickness of the second copper metal material layer is 2500 ⁇ 3500 angstroms.
  • the thickness of the second copper metal material layer is 3000 angstroms.
  • the seed metal material layer may further include a third adhesion material layer located on the surface of the second copper metal material layer close to the base substrate A100, and the material of the third adhesion material layer may be molybdenum, molybdenum copper alloy, molybdenum Niobium alloys, molybdenum copper niobium alloys or other metals or metal alloys.
  • a third adhesive layer is formed.
  • the seed metal layer may include the third adhesive layer and the second copper metal layer sequentially stacked on one side of the base substrate A100.
  • the material of the third adhesion layer is a molybdenum-niobium alloy, and the thickness is 250-350 angstroms.
  • the thickness of the third adhesion layer is 300 angstroms.
  • the material of the pattern defining layer may be an organic insulating material, for example, a photosensitive resin; it may also be an inorganic material, for example, a material such as silicon oxide.
  • the material of the pattern defining layer is photoresist.
  • the thickness of the pattern defining layer may be determined according to the thickness of the copper growth material layer, so that the thickness of the pattern defining layer is greater than the thickness of the copper growth material layer.
  • the thickness of the copper growth material layer can be determined according to the resistance requirement of the array substrate to the metal wiring layer A200. The lower the resistance required for the metal wiring layer A200, the larger the thickness of the copper growth material layer can be.
  • the thickness of the formed copper growth layer is 1.5-10 microns.
  • the metal wiring layer A200 can be provided with only one layer of metal leads, and there is no need to provide multiple layers of stacked metal leads to reduce impedance, which can reduce the fabrication process of the array substrate and the number of masks, and reduce the cost of the array substrate.
  • the copper growth layer can be formed by electroplating or electroless plating.
  • the thickness of the pattern defining layer is 7.5 microns, and the thickness of the copper growth material layer is 6.3 microns.
  • the thickness of the pattern defining layer is 3-4 micrometers, and the thickness of the copper growth material layer is 2.1 micrometers.
  • the material of the passivation layer is silicon nitride, and the thickness of the passivation layer is 900-1100 angstroms.
  • the metal wiring layer A200 can be prepared by the following methods:
  • the seed metal layer and the copper growth layer are prepared according to the methods shown in steps AS210 to AS250, and then the second copper-nickel alloy layer is formed by electroplating or electroless plating.
  • the second copper-nickel alloy layer covers the surface and side surfaces of the copper growth layer away from the base substrate A100, and may also cover part or all of the side surfaces of the seed metal layer. In this way, the second copper-nickel alloy layer can protect the seed metal layer and the copper growth layer, and prevent the seed metal layer and the copper growth layer from being oxidized during the baking process.
  • the prepared metal wiring layer A200 includes a seed metal layer, a copper growth layer and a second copper-nickel alloy layer sequentially stacked on one side of the base substrate A100, wherein the second copper-nickel alloy layer covers the copper growth layer and is far away from the lining The surface and side surfaces of the base substrate A100, and part or all of the side surfaces of the seed metal layer.
  • the mass content of nickel is not less than 30%. In this way, it can be ensured that the second copper-nickel alloy layer has an excellent anti-oxidation effect, and various problems caused by the copper-nickel alloy with high nickel content during etching can be avoided. Further, the mass content of nickel is greater than 80%.
  • the thickness of the second copper-nickel alloy layer is 500-2000 angstroms, so as to ensure that the second copper-nickel alloy layer has excellent anti-oxidation effect, and can avoid various problems caused by the etching of the high-thickness copper-nickel alloy layer. question.
  • the seed metal layer and the copper growth layer may be treated with a palladium salt solution to form a palladium activation layer covering the surface and side surfaces of the copper growth layer away from the base substrate A100 and at least part of the side surfaces of the seed metal layer;
  • the palladium activation layer is treated with an electroless plating solution containing copper salt, nickel salt, reducing agent, complexing agent and pH adjusting agent, and a second copper-nickel alloy layer is formed on the surface of the palladium activation layer far from the base substrate A100.
  • the first planarization layer A300 may be formed in step AS130, and no additional passivation layer is required. In this way, not only the anti-oxidation protection of copper in the metal wiring layer A200 can be improved, but also steps such as deposition and etching of the passivation layer can be reduced, the quality of the array substrate can be improved and the cost of the array substrate can be reduced.
  • a first planarization layer A300 may be formed on the side of the metal wiring layer A200 away from the base substrate A100.
  • the material of the first planarization layer A300 may be an organic material, for example, a photosensitive resin.
  • the thickness of the first planarization layer A300 is 3-7 microns.
  • the thickness of the first planarization layer A300 is 4.5-5.5 microns.
  • Via holes may be provided on the first planarization layer A300, so that the electrode layer A400 is electrically connected to the metal wiring layer A200.
  • the first planarization layer A300 may be provided with a first via hole and a second via hole, both of which expose at least part of the metal wiring layer A200.
  • the electrode layer A400 includes connection electrodes and bonding pads, wherein at least part of the connection electrodes are electrically connected to the metal wiring layer A200 through first vias, and the bonding pads are electrically connected to the metal wiring layer A200 through second vias.
  • the bonding pads are used for electrical connection with a circuit board (such as a flexible circuit board) or a driving chip, and at least part of the connection electrodes are used for electrical connection with functional devices.
  • an electrode layer A400 may be formed on a side of the first planarization layer A300 away from the base substrate A100.
  • the electrode layer A400 includes a copper electrode layer A410, a first buffer metal layer A420 and a first copper-nickel alloy layer A430 that are sequentially stacked on one side of the base substrate A100.
  • the first buffer metal layer A420 and the first copper-nickel alloy layer A430 are used together as an electrode protection layer to protect the copper electrode layer A410, avoid surface oxidation of the copper electrode layer A410, and improve the electrode layer A400 and the functional device layer A600 In particular, the adhesion between the electrode layer A400 and the solder layer is improved, and the peeling of the functional device A610 is avoided.
  • the first buffer metal layer A420 may also increase the adhesion between the copper electrode layer A410 and the first copper-nickel alloy layer A430.
  • the copper electrode layer A410 may be formed first, and then the first buffer metal layer A420 and the first copper-nickel alloy layer A430 covering the copper electrode layer A410 may be formed; or the same etching process may be performed.
  • a copper electrode layer A410, a first buffer metal layer A420 and a first copper-nickel alloy layer A430 are formed in sequence.
  • forming the electrode layer A400 on the side of the first planarization layer A300 away from the base substrate A100 includes the following steps:
  • Step AS310 referring to FIG. 8, forming a copper electrode material layer A411 (as a metal sub-material layer) on the side of the first planarization layer A300 away from the base substrate A100;
  • Step AS320 referring to FIG. 9, patterning the copper electrode material layer A411 to form the copper electrode layer A410 (as a metal sublayer);
  • Step AS330 referring to FIG. 10, sequentially forming a first buffer metal material layer A421 and a first copper-nickel alloy material layer A431 (as a conductive sub-material layer) on the side of the copper electrode layer A410 away from the base substrate A100;
  • Step AS340 referring to FIG. 11, patterning the first buffer metal material layer A421 and the first copper-nickel alloy material layer A431 to form the first buffer metal layer A420 and the first copper-nickel alloy layer A430 (as the conductive sub-layers) ); wherein, the orthographic projection of the copper electrode layer A410 on the base substrate A100 is located within the orthographic projection of the first buffer metal layer A420 on the base substrate A100.
  • a copper electrode material layer A411 may be formed by sputtering, and the thickness of the copper electrode material layer A411 may be determined according to requirements, for example, may be 2500 angstroms to 5000 angstroms. Preferably, the thickness of the copper electrode material layer A411 may be 3000 angstroms.
  • the copper electrode material layer A411 may be patterned by a photolithography process, and the patterned copper electrode material layer A411 becomes the copper electrode layer A410.
  • the copper electrode material layer A411 may be patterned by the following steps: forming a first positive photolithography on the surface of the copper electrode material layer A411 away from the base substrate A100 Adhesive layer; use a mask to expose the first positive photoresist layer at a first exposure intensity; develop the first positive photoresist layer; etch the copper electrode material layer A411 to form a copper electrode layer A410 ; Remove the first positive photoresist layer.
  • a portion of the first planarization layer A300 that is far away from the base substrate A100 may also be formed first.
  • a second buffer metal material layer A441 is formed on the side, and then a copper electrode material layer A411 is formed on the surface of the second buffer metal material layer A441 away from the base substrate A100.
  • the material of the second buffer metal material layer A441 is a mixture of one or more of molybdenum, molybdenum-niobium alloy, molybdenum-tungsten alloy, molybdenum-nickel-titanium alloy, and molybdenum-magnesium-aluminum alloy.
  • the second buffer metal material layer A441 may also be patterned simultaneously to form the second buffer metal layer A440.
  • the material of the second buffer metal material layer A441 itself is difficult to etch, since it is in contact with the copper electrode material layer A411 and is etched simultaneously, an electronic chemical effect will occur between the two, and the second buffer metal layer A411 will be etched simultaneously.
  • the electrons on the metal material layer A441 will be transferred to the copper electrode material layer A411 to increase the etching speed of the second buffer metal material layer A441.
  • the second buffer metal material layer A441 and the copper electrode material layer A411 can be kept synchronously etched, so that the surface of the second buffer metal layer A440 away from the base substrate A100 is substantially the same as the surface of the copper electrode layer A410 close to the base substrate A100 coincide.
  • the electrode layer A400 may include the second buffer metal layer A440, the copper electrode layer A410, the first buffer layer A440, the copper electrode layer A410, and the first buffer layer A440, which are sequentially stacked on the side of the first planarization layer A300 away from the base substrate A100.
  • the metal layer A420 and the first copper-nickel alloy layer A430 are sequentially stacked on the side of the first planarization layer A300 away from the base substrate A100.
  • a first buffer metal material layer A421 and a first copper-nickel alloy material layer A431 may be sequentially formed on the surface of the copper electrode layer A410 away from the base substrate A100 by sputtering.
  • the thickness of the first buffer metal material layer A421 is 100-500 angstroms; preferably, the thickness of the first buffer metal material layer A421 is 200-500 angstroms.
  • the thickness of the first copper-nickel alloy material layer A431 is 200-1000 angstroms; preferably, the thickness of the first copper-nickel alloy material layer A431 is 500-1000 angstroms.
  • the material of the first buffer metal material layer A421 is a molybdenum-niobium alloy. In this way, the material of the formed first buffer metal layer A420 is molybdenum-niobium alloy.
  • the first buffer metal material layer A421 and the first copper-nickel alloy material layer A431 may be patterned through a photolithography process to form a first buffer metal layer A420 and a first copper-nickel alloy layer A430.
  • the etching rates of the first buffer metal material layer A421 and the first copper-nickel alloy material layer A431 are similar, so the first copper-nickel alloy material layer A431 does not form a roof structure.
  • FIG. 17 is an electron microscope image of the first buffer metal layer A420 and the first copper-nickel alloy layer A430 formed after etching. It can be seen from FIG.
  • the orthographic projection of the copper electrode layer A410 on the base substrate A100 may be located within the orthographic projection of the first buffer metal layer A420 on the base substrate A100.
  • the first buffer metal layer A420 covers the surface of the copper electrode layer A410 away from the base substrate A100 and the side surface of the copper electrode layer A410
  • the first copper-nickel alloy layer A430 also covers the surface of the copper electrode layer A410 away from the base substrate A100 accordingly.
  • the side of the copper electrode layer A410; that is, the orthographic projection of the copper electrode layer A410 on the base substrate A100 is also located in the orthographic projection of the first copper-nickel alloy layer A430 on the base substrate A100
  • the first buffer metal layer A420 and the first copper-nickel alloy layer A430 cover the side surface of the copper electrode layer A410 and the surface of the copper electrode layer A410 away from the base substrate A100.
  • This enables the first copper-nickel alloy layer A430 to effectively protect the copper electrode layer A410 and prevent the copper electrode layer A410 from being oxidized.
  • the roof structure of the first copper-nickel alloy layer A430 can be avoided and the quality of the array substrate is reduced.
  • the first buffer metal material layer A421 and the first copper-nickel alloy material layer A431 may be patterned by the following method: the first copper-nickel alloy material layer A431 may be away from the base substrate A100 A second positive photoresist layer is formed on the surface of the film; a mask is used to expose the second positive photoresist layer at a second exposure intensity, wherein the second exposure intensity is less than the first exposure intensity; the second positive photoresist layer is exposed The first buffer metal material layer A421 and the first copper-nickel alloy material layer A431 are etched to form the first buffer metal layer A420 and the first copper-nickel alloy layer A430; the second positive light is removed resist layer.
  • the same mask plate may be used in step AS340 and step AS320, so as to reduce the number of mask plates and reduce the fabrication cost of the array substrate.
  • the pattern of the second positive photoresist layer after development in step AS340 is larger than that of the first positive photoresist layer after development in step AS320 and the pattern of the developed first positive photoresist layer is completely within the developed pattern of the second positive photoresist layer. This can ensure that the first buffer metal layer A420 can cover the copper electrode layer A410.
  • the edge of the orthographic projection of the copper metal layer on the base substrate A100 may be the same as the edge of the orthographic projection of the first metal buffer layer on the base substrate A100.
  • the minimum distance between the edges is not less than 1.5 microns.
  • the FICD (Final) of the first buffer metal layer A420 in the substructure Insection Critical Dimension the final critical dimension) d1 is at least 3 microns larger than the FICD d2 of the copper electrode layer A410 portion of the substructure.
  • forming the electrode layer A400 on the side of the first planarization layer A300 away from the base substrate A100 includes the following steps:
  • step AS410 referring to FIG. 13, a copper electrode material layer A411, a first buffer metal material layer A421 and a first copper-nickel alloy material layer A431 are sequentially formed on the side of the first planarization layer A300 away from the base substrate A100;
  • Step AS420 forming a photoresist layer on the side of the first copper-nickel alloy material layer A431 away from the base substrate A100;
  • Step AS430 exposing and developing the photoresist layer
  • Step AS440 referring to FIG. 14, etching the copper electrode material layer A411, the first buffer metal material layer A421 and the first copper-nickel alloy material layer A431 to form the copper electrode layer A410, the first buffer metal layer A420 and the first copper-nickel layer Alloy layer A430;
  • step AS450 the photoresist layer is removed.
  • a copper electrode material layer A411, a first buffer metal material layer A421 and a first copper-nickel alloy material layer A431 may be formed in sequence by a sputtering method.
  • the thickness of the first buffer metal material layer A421 is 200 ⁇ 500 angstroms.
  • the thickness of the first copper-nickel alloy material layer A431 is 500-1000 angstroms.
  • the material of the first buffer metal material layer A421 is a molybdenum-niobium alloy. In this way, the material of the formed first buffer metal layer A420 is molybdenum-niobium alloy.
  • a second buffer metal material layer A441 may also be formed on the side of the first planarization layer A300 away from the base substrate A100; Then, a copper electrode material layer A411 is formed on the side of the second buffer metal material layer A441 away from the base substrate A100.
  • the second buffer metal material layer A441 can be etched synchronously with the copper electrode material layer A411 in step AS440 to be patterned into the second buffer metal layer A440; then, in the prepared array substrate, the electrode layer A400 can include sequentially A second buffer metal layer A440, a copper electrode layer A410, a first buffer metal layer A420, and a first copper-nickel alloy layer A430 are stacked.
  • the material of the second buffer metal layer A440 is a mixture of one or more of molybdenum, molybdenum-niobium alloy, molybdenum-tungsten alloy, molybdenum-nickel-titanium alloy, and molybdenum-magnesium-aluminum alloy.
  • the copper electrode material layer A411, the first buffer metal material layer A421 and the first copper-nickel alloy material layer A431 may be etched at the same time, thereby forming an electrode layer A400 without a roof structure.
  • the etching rate of the first buffer metal material layer A421 and the first copper-nickel alloy material layer A431 without the copper metal material layer is lower than the etching rate of the copper metal material layer, when the first buffer metal material layer A431 is not
  • the copper metal material layer can generate electronic chemical effects with the first buffer metal material layer A421 and the first copper-nickel alloy material layer A431 .
  • the electrons on the first buffer metal material layer A421 can be transferred to the copper metal material layer, thereby increasing the etching rate of the first buffer metal material layer A421; the electrons on the first copper-nickel alloy material layer A431 can be Transfer to the copper metal material layer, thereby increasing the etching rate of the first copper-nickel alloy material layer A431.
  • the copper electrode material layer A411 , the first buffer metal material layer A421 and the first copper-nickel alloy material layer A431 may maintain substantially simultaneous etching.
  • the preparation rate of the layer A400 improves the quality of the array substrate and reduces the cost of the array substrate.
  • FIG. 16 is an electron microscope image of the electrode layer A400 prepared according to the method of step AS440.
  • the surface of the copper electrode layer A410 away from the base substrate A100 may substantially coincide with the surface of the first buffer metal layer A420 close to the base substrate A100; the surface of the first buffer metal layer A420 away from the base substrate A100 may be The surfaces of the copper-nickel alloy layer A430 close to the base substrate A100 are substantially coincident.
  • the electrode layer A400 further includes the second buffer metal layer A440
  • the surface of the second buffer metal layer A440 away from the base substrate A100 may substantially coincide with the surface of the copper electrode layer A410 close to the base substrate A100. It can be seen in FIG. 16 that although the copper electrode material layer A411, the first buffer metal material layer A421 and the first copper-nickel alloy material layer A431 are simultaneously etched, no roof structure is produced.
  • the copper etching solution can be used to etch the first copper-nickel alloy material layer A431 and the copper electrode material layer A411 at the same time, and the formed structure has no roof structure, so no need for The development of a new etching solution not only reduces the preparation cost of the array substrate, but also saves the time for developing a new etching solution, and ultimately reduces the cost of the array substrate.
  • the array substrate also does not need to provide an ITO (indium zinc oxide) layer in the binding area of the flexible circuit board to improve the adhesion with the flexible circuit board and improve the anti-oxidation effect, which can reduce the preparation process and cost of the array substrate.
  • a second planarization layer A500 may be formed on the side of the electrode layer A400 away from the base substrate A100.
  • the second planarization layer A500 may be formed with a plurality of via holes to expose part of the electrode layer A400 so that the exposed electrode layer A400 is electrically connected to the functional device A610.
  • the exposed electrode layer A400 is electrically connected to a circuit board or a driving chip.
  • the electrode layer includes a connection electrode and a bonding pad; the connection electrode includes a bonding area and a connection area.
  • the second planarization layer A500 may have third via holes and fourth via holes.
  • the third via hole can expose the bonding area of the connection electrode, so that the functional device is electrically connected to the connection electrode through the third via hole; the fourth via hole can expose the bonding pad, so that the circuit board or the driver chip can pass through the fourth via hole.
  • the holes are electrically connected to the bond pads.
  • connection electrodes can be divided into device pads and connection traces according to their positions and functions. Wherein, for any connection electrode, it may only include device pads or connection wires, or may include electrically connected device pads and connection wires. Wherein, at least part of the connection traces can be connected to the metal wiring layer, and at least part of the connection traces can be connected to the device pads.
  • part of the connection traces can be connected to different device pads, so that a plurality of device pads are electrically connected to each other, and at least part of the connection traces can be simultaneously the device pads and the metal wiring layer to make functional devices Electrically connected to the metal wiring layer.
  • the electrode layer A400 is provided with the first copper-nickel alloy layer A430, there is no need to worry that the copper electrode layer A410 will be oxidized, so there is no need to provide a passivation layer (silicon nitride layer, etc. for protection) on the side of the electrode layer A400 away from the layer substrate.
  • a passivation layer silicon nitride layer, etc. for protection
  • Inorganic protective layer of the electrode layer to avoid the problem of bubbling of the first planarization layer A300 caused by the passivation layer covering the first planarization layer A300. In this way, processes such as depositing the passivation layer, etching the passivation layer, etc. can be saved, and the production tact time of the array substrate can be improved to increase the productivity and reduce the cost, and can also improve the quality of the array substrate.
  • the second planarization layer A500 may be formed by a screen printing method.
  • white oil may be applied by screen printing to form the second planarization layer B500.
  • the white oil includes a photocurable resin or a photocurable monomer, and titanium dioxide particles dispersed in the resin.
  • the photocurable monomers may include, but are not limited to, acrylate-based monomers.
  • a functional device layer A600 may be provided on the side of the protective layer away from the base substrate A100.
  • the functional device layer A600 may include functional devices A610 distributed in an array, for example, including a light-emitting device for emitting light, an ultrasonic emitting device for emitting ultrasonic waves, a heating device for generating heat, or other current-driven functional devices A610, or Including microchips for driving or control, sensors for sensing brightness or temperature, etc.
  • the functional device A610 may be a micro light-emitting diode (Micro LED) or a mini light-emitting diode (Mini LED); the functional device A610 may be connected to the electrode layer through a mass transfer technique and a bonding process A400. Further, the functional device A610 may be electrically connected to the electrode layer A400 through a solder layer A700, and the solder layer A700 may include tin and indium. Exemplarily, the functional device A610 can be connected to the electrode layer A400 through processes such as printing soldering, die bonding, and reflow soldering.
  • part of the functional device may be a micro light emitting diode (Micro LED) or a mini light emitting diode (Mini LED); part of the functional device may be a microchip for controlling one or more light emitting diodes. Under the control of the microchip, the light-emitting diodes controlled by the microchip are controlled to emit light or not to emit light.
  • Micro LED micro light emitting diode
  • Mini LED mini light emitting diode
  • the array substrate includes:
  • the metal wiring layer A200 is arranged on one side of the base substrate A100;
  • the first planarization layer A300 is disposed on the side of the metal wiring layer A200 away from the base substrate A100;
  • the electrode layer A400 is disposed on the side of the first planarization layer A300 away from the base substrate A100; the electrode layer A400 includes a copper electrode layer A410, a first buffer metal layer A420 and a first copper electrode layer A410, a first buffer metal layer A420 and a first copper electrode layer A410 sequentially stacked on one side of the base substrate A100
  • the nickel alloy layer A430; the material of the first buffer metal layer A420 is a mixture of one or more of molybdenum, molybdenum-niobium alloy, molybdenum-tungsten alloy, molybdenum-nickel-titanium alloy, and molybdenum-magnesium-aluminum alloy;
  • the second planarization layer A500 is disposed on the side of the electrode layer A400 away from the base substrate A100;
  • the functional device layer A600 is disposed on the side of the second planarization layer A500 away from the base substrate A100, and includes a plurality of functional devices A610 electrically connected to the electrode layer A400.
  • the array substrate provided in this embodiment can be prepared by using the method for fabricating the array substrate described in the above-mentioned method for fabricating an array substrate in this embodiment. Therefore, it has the same or similar beneficial effects, and is not repeated in this embodiment.
  • the electrode layer A400 further includes a second buffer metal layer A440 located on the surface of the copper electrode layer A410 close to the base substrate A100.
  • the first buffer metal layer A420 and the first copper-nickel alloy layer A430 cover the side surface of the copper electrode layer A410 and the surface of the copper electrode layer A410 away from the base substrate A100.
  • the orthographic projection of the first copper-nickel alloy layer A430 on the copper electrode layer A410 is located in the copper electrode layer A410.
  • the thickness of the first buffer metal layer A420 is 100-500 angstroms.
  • the thickness of the first buffer metal layer A420 is 200 ⁇ 500 angstroms.
  • the thickness of the first copper-nickel alloy layer A430 is 200-1000 angstroms.
  • the thickness of the first copper-nickel alloy layer A430 is 500-1000 angstroms.
  • the mass content of nickel in the first copper-nickel alloy layer A430 is greater than 20%.
  • the mass content of nickel is 30% to 80%.
  • the embodiments of this embodiment further provide a display panel, which includes any of the array substrates described in the foregoing array substrate embodiments; wherein, the functional device A610 of the array substrate is a micro-LED or a mini-LED.
  • the display panel may be a mobile phone screen, a TV screen, a smart watch screen, an electronic picture screen, an electronic billboard or other types of display panels. Since the display panel has any of the array substrates described in the above-mentioned embodiments of the array substrate, it has the same beneficial effects, and details are not described herein again in this embodiment.
  • the functional device A610 on the array substrate includes micro-LEDs or mini-LEDs of various colors, such as red micro-LEDs or mini-LEDs, blue micro-LEDs or mini-LEDs and blue micro-LEDs Diodes or Mini LEDs.
  • This embodiment also provides a backlight module, which includes any of the array substrates described in the above-mentioned embodiments of the array substrate; wherein, the functional device A610 of the array substrate is a micro-LED or a mini-LED.
  • the backlight module can be a backlight module for a mobile phone screen, a backlight module for a TV screen, a backlight module for a computer screen, or a backlight module for other types of liquid crystal display panels. Since the backlight module has any of the array substrates described in the above-mentioned embodiments of the array substrate, it has the same beneficial effects, and details are not described herein again in this embodiment.
  • the thickness of the copper-nickel alloy shall not exceed 500 angstroms, and the mass content of nickel shall not exceed 20%. This is because the etching rate of copper-nickel alloys is lower than that of copper, and the higher the nickel content, the slower the etching rate.
  • the copper-nickel alloy layer Due to the difference in etching rate between copper-nickel alloy and copper, when etching the laminated copper metal layer and copper-nickel alloy layer, the copper-nickel alloy layer usually has a roof structure (Tip structure) remaining; and the higher the nickel content , the larger the roof structure; the larger the thickness of the copper-nickel alloy layer, the slower the etching rate and the larger the roof structure.
  • the roof structure may collapse, etc., which may lead to defects of the array substrate, seriously affect the productization of the array substrate, and reduce the quality of the array substrate.
  • FIG. 18-1 is an electron microscope image of a copper-nickel alloy layer (500 angstroms), a copper layer (6000 angstroms) and a copper-nickel alloy layer (500 angstroms) deposited in sequence on a glass substrate, wherein the copper-nickel alloy layer The mass content of nickel in the medium is 20%;
  • Figure 18-2 is the electron microscope image of the above metal layer after etching. In the electron microscope image, it can be clearly observed that the copper-nickel alloy layer forms a roof structure, and the size of the roof structure is 0.1 micron.
  • Figure 19-1 is the electron microscope image of the copper-nickel alloy layer (500 angstroms), the copper layer (6000 angstroms) and the copper-nickel alloy layer (500 angstroms) deposited in sequence on the glass substrate, wherein the quality of nickel in the copper-nickel alloy layer The content is 30%;
  • Figure 19-2 is the electron microscope image after the above metal layer is etched, it can be clearly observed that the copper-nickel alloy layer forms a roof structure, and the size of the roof structure is 0.15 microns. Comparing Fig. 18-2 and Fig. 19-2, it can be clearly seen that the larger the mass content of nickel in the copper-nickel alloy layer, the larger the size of the roof structure formed in the etching, and the greater the impact on the quality of the array substrate.
  • FIG. 20 is a photograph after high temperature baking when a copper-nickel alloy layer with a mass content of nickel of 10% is used to protect the copper-gold bar.
  • the brighter the color of the copper metal strip such as the EE position shown in Figure 20
  • the darker the copper metal strip such as the DD position shown in Figure 20
  • the higher the degree of surface oxidation the higher the degree of surface oxidation.
  • Figure 21 shows the copper metal layer (6000 angstroms) covered by the copper-nickel metal layer (500 angstroms) with a mass content of nickel of 20% before annealing, annealed at 150 °C for two hours in an air atmosphere, 250 °C nitrogen Pictures of three different situations annealed in the atmosphere for 30 minutes; the small black dots in the picture are the places where the copper metal layer is oxidized and blackened.
  • Figure 22 shows the copper metal layer (6000 angstroms) covered by the copper-nickel metal layer (500 angstroms) with a mass content of nickel of 35% before annealing, annealed in an air atmosphere at 150 °C for two hours, and annealed in a nitrogen atmosphere at 250 °C for 30 hrs.
  • this embodiment provides an array substrate and a preparation method thereof.
  • the preparation method of the array substrate includes:
  • Step BS130 as shown in FIG. 25 and FIG. 26 , a first planarization layer B300 is formed on the side of the metal wiring layer B200 away from the base substrate B100;
  • Step BS140 as shown in FIGS. 27 and 28 , a copper electrode layer B420 (as a metal sublayer) is formed on the side of the first planarization layer B300 away from the base substrate B100 , and the copper electrode layer B420 is electrically connected to the metal wiring layer B200 ;
  • Step BS150 as shown in FIG. 29 and FIG. 30 , a palladium metal layer B430 is formed, and the palladium metal layer B430 is located on and covers the surface of the copper electrode layer B420 away from the surface of the base substrate B100 and the side surface of the copper electrode layer B420;
  • Step BS160 as shown in FIG. 31 and FIG. 32, a first copper-nickel alloy layer B440 (as a conductive sub-layer) is formed by electroless plating, and the first copper-nickel alloy layer B440 is located and covers the palladium metal layer B430 away from the base substrate Surface of B100;
  • the electrode layer B400 is electrically connected to the metal wiring layer B200; the electrode layer B400 includes a copper electrode layer B420, a palladium metal layer B430 and a first copper-nickel alloy layer B440 stacked in sequence; wherein, the palladium metal layer B430 is located on and covers the copper electrode layer B420 is far from the surface of the base substrate B100 and the side of the copper electrode layer B420; the first copper-nickel alloy layer B440 is located on and covers the surface of the palladium metal layer B430 far away from the surface of the base substrate B100; the functional device layer B600 includes a plurality of electrical contacts with the electrode layer B400 Connected functional device B610.
  • any film layer may include a side surface, a surface close to the base substrate, and a surface far away from the base substrate, wherein the surface close to the base substrate and the surface away from the base substrate are connected by the side surface of the film layer.
  • the thickness of any film layer is the dimension of the film layer in the direction perpendicular to the base substrate.
  • the material of the base substrate B100 is glass.
  • the method for preparing the array substrate may further include: as shown in FIG. 26 , before forming the first planarization layer B300 , forming a passivation on the surface of the metal wiring layer B200 away from the base substrate B100 layer B210 to protect the metal wiring layer B200.
  • the material of the passivation layer B210 may be inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. In this way, in the prepared array substrate, a passivation layer B210 is provided between the metal wiring layer B200 and the first planarization layer B300.
  • the components of the electroless plating solution include: copper sulfate 0.08mol/L, nickel sulfate 0.03mol/L, sodium hypophosphite 0.7mol/L, sodium citrate 0.1mol/L, boric acid 0.5mol/L, polyethylene Diol 100mg/L.
  • the above-mentioned reaction is carried out near the palladium metal layer B430 and under the promotion of palladium, and the above-mentioned reaction does not substantially occur in the region without the palladium metal layer B430. Therefore, copper and nickel are deposited on the palladium metal layer B430, forming a first copper-nickel alloy layer B440.
  • the temperature of the electroless plating solution is 75-85°C, and the processing time is 20-40 minutes.
  • the substrate on which the palladium metal layer B430 is formed may be immersed in an electroless plating solution for the reaction.
  • the thickness of the first copper-nickel alloy layer B440 is 500-2000 angstroms, so as to ensure that the first copper-nickel alloy layer B440 has an excellent anti-oxidation effect, and can avoid various problems caused by the etching of the high-thickness copper-nickel alloy layer. kind of problem.
  • the method for preparing an array substrate may further include: forming a second planarizing layer B500 on the side of the electrode layer B400 away from the base substrate B100 ;
  • the planarization layer B500 may be an organic material, or an organic material doped with an inorganic material.
  • the second planarization layer B500 may have a partial area of the electrode layer B400 exposed, so that the exposed portion serves as a bonding pad to connect with the functional device B610.
  • the electrode layer B400 may also be formed with other structures, for example, a bonding pad for connecting with a driving chip or a circuit board may also be formed, which is not limited in this embodiment.
  • the array substrate provided in this embodiment can be prepared by using the method for fabricating the array substrate described in the above-mentioned method for fabricating an array substrate in this embodiment. Therefore, it has the same or similar beneficial effects, and is not repeated in this embodiment.
  • the electrode layer B400 further includes a second buffer metal layer B410, and the second buffer metal layer B410 is disposed on the surface of the copper electrode layer B420 close to the base substrate B100.
  • the mass content of nickel in the first copper-nickel alloy layer B440 is not less than 30%.
  • the mass content of nickel is not more than 80%.
  • the thickness of the first copper-nickel alloy layer B440 is 500-2000 angstroms.
  • the metal wiring layer B200 includes a seed metal layer, a copper growth layer and a second copper-nickel alloy layer sequentially stacked on one side of the base substrate B100.
  • the metal wiring layer B200 includes a seed metal layer and a copper growth layer sequentially stacked on one side of the base substrate B100; the array substrate further includes a passivation layer B210, which is provided on the between the metal wiring layer B200 and the first planarization layer B300.
  • the embodiments of this embodiment further provide a display panel, which includes any of the array substrates described in the foregoing array substrate embodiments; wherein, the functional device B610 of the array substrate is a micro-LED or a mini-LED.
  • the display panel may be a mobile phone screen, a TV screen, a smart watch screen, an electronic picture screen, an electronic billboard or other types of display panels. Since the display panel has any of the array substrates described in the above-mentioned embodiments of the array substrate, it has the same beneficial effects, and details are not described herein again in this embodiment.
  • the embodiments of this embodiment also provide a backlight module, which includes any array substrate described in the above-mentioned embodiments of the array substrate; wherein, the functional device B610 of the array substrate is a micro-LED or a mini-LED.
  • the backlight module can be a backlight module for a mobile phone screen, a backlight module for a TV screen, a backlight module for a computer screen, or a backlight module for other types of liquid crystal display panels. Since the backlight module has any of the array substrates described in the above-mentioned embodiments of the array substrate, it has the same beneficial effects, and details are not described herein again in this embodiment.
  • Mini-LED sub-millimeter light-emitting diode refers to light-emitting diodes with a size between 80 and 300um.
  • Mini-LED is used as the pixel point of the display panel to form a self-luminous display, a higher pixel density can be achieved compared to a small-pitch LED display.
  • an ultra-thin light source module can be made by arranging more dense light sources; combined with regional dimming technology, the display screen including the Mini-LED backlight module will be There are better contrast and high dynamic lighting rendering display effect.
  • Micro LEDs with a size of less than 80um can be directly used as pixels on display panels such as near-eye, wearable, and handheld terminals.
  • the circuit board is bound on the pads of the array substrate to be electrically connected to the circuit board by using a thermocompression method within a temperature range of 130° C. to 150° C.
  • the circuit board bonding area OA includes a plurality of pin pads C1, and the plurality of pin pads are used for bonding and connection with the circuit board; any one of the plurality of pin pads includes The first metal sub-layer C11 and the first conductive sub-layer C12 are stacked; the material of the first metal sub-layer includes metal or metal alloy; the first conductive sub-layer has oxidation resistance and covers the first metal sub-layer.
  • the light-emitting area OB includes a plurality of device pads, and the plurality of device pads are used for bonding and connection with a plurality of light-emitting units. It can be understood that, in other embodiments of the present disclosure, some device pads are used for electrical connection with light emitting units (eg, light emitting diodes), and some device pads are used for electrical connection with microchips that drive or control the light emitting units.
  • light emitting units eg, light emitting diodes
  • microchips that drive or control the light emitting units.
  • the material of the first metal sublayer includes metals, such as copper, aluminum, molybdenum, titanium, and the like. Considering the low resistivity and strong conductivity of copper, it is preferable to make the first metal sublayer of copper (for example, as the copper electrode layer in Embodiment 1); at this time, the material of the first conductive sublayer may be metal oxide or metal
  • the alloy, such as the metal oxide, may be indium zinc oxide (IZO) or indium tin oxide (ITO).
  • the array substrate may be a display array substrate or may be a backlight array substrate. If it is a display array substrate, the light emitting area OB constitutes a display area to realize a display screen. In the case of a backlight array substrate, the light emitting area OB is used to provide a light source.
  • the light-emitting color of the light-emitting region included in the array substrate is not limited here; the light-emitting region may be any one of a red light-emitting region, a green light-emitting region, or a blue light-emitting region.
  • the array substrate may include red light-emitting regions, green light-emitting regions or light-emitting regions of three light-emitting colors at the same time; of course, it may also include light-emitting regions of only one light-emitting color, for example, only include a plurality of red light-emitting regions, Either only a plurality of green light-emitting regions, or only a plurality of blue light-emitting regions are included. Specific can be determined according to actual requirements.
  • each light-emitting region may be controlled independently, or multiple light-emitting regions may be controlled simultaneously.
  • the array substrate may further include a base substrate C7, and a plurality of light-emitting units (located on the functional device layer) formed on the base substrate C7.
  • the light-emitting units The light emitting diode C6 as shown in FIG. 44 or FIG. 40 may be included.
  • the material of the substrate can be a rigid material, such as glass; or a flexible material, such as polyimide.
  • the array substrate may further include a microchip arranged on the same layer as the light-emitting unit, and the microchip is used to control the light-emitting unit. In this way, the light-emitting unit and the microchip can be used as the functional device of the array substrate, and the functional device layer can include the light-emitting unit and the microchip.
  • the cathode pad is marked as C2 ′
  • the anode pad is marked as C2
  • the film structure of the two is the same.
  • the device pads can be connected to connection wires provided on the same layer, so that the array substrate loads current or voltage to the functional devices bound on the device pads through the connection wires. It can be understood that, in some embodiments, there may be a portion of the connection traces that are not electrically connected to the device pads.
  • the array substrate includes a base substrate, a metal wiring layer, a first planarization layer, an electrode layer, a second planarization layer, and a functional device layer that are stacked.
  • the metal wiring layer is provided with metal leads
  • the electrode layer is provided with the above-mentioned device pads and connecting wires.
  • the functional device layer is provided with the above-mentioned light-emitting units, and in some cases may also include a microchip.
  • the pin pads and the device pads are arranged on the same layer, and both are located on the electrode layer.
  • the pin pads and the device pads are respectively disposed on the metal wiring layer and the electrode layer.
  • the electrode layer and the metal wiring layer are connected through a via hole passing through the first planarization layer.
  • the pin pads may be electrically connected to the metal leads through connection traces, or the pin pads may be directly electrically connected to the metal leads.
  • the connection trace may include a first connection trace and a second connection trace, the first connection trace may connect two device pads, so as to electrically connect the functional devices; the second connection trace may The metal leads and the device pads are connected such that the device pads are electrically connected to the metal leads.
  • the connection traces may further include third connection traces, and the third connection traces are connected to different metal leads, so that the metal leads on the metal wiring layer are bridged by the electrode layer.
  • the distribution structure and connection manner of the plurality of pin pads and the plurality of device pads in the above-mentioned array substrate are not limited. 38, the area OA is the circuit board binding area, the area OB is the light-emitting area, the multiple device pads can be divided into multiple groups of device pads, each group of device pads is used to bind a light-emitting diode. , and includes a pair of cathode pads C2' and anode pads C2.
  • the device pads of the adjacent two groups are connected in series through the trace C81 (belonging to the first connection trace); in the two groups of device pads connected in series, the anode pads of one group are connected to a trace C82 (belonging to the second connection trace).
  • the disk C1 is electrically connected.
  • the cathode pad C2', the anode pad C2, the pin pad C1, the trace C81 and the trace C82 are arranged in the same layer, use the same filling pattern, and are located on the electrode layer; the anode trace C51 and the cathode trace C52 is set on the same layer, using the same filling pattern, on the metal wiring layer.
  • FIG. 39 is a schematic cross-sectional view along the AA' direction in FIG. 38
  • FIG. 43 is another cross-sectional schematic view along the AA' direction in FIG. 38
  • FIG. 40 is after forming the light emitting diode C6 and the encapsulation layer C9 on the basis of FIG. Schematic diagram of the structure.
  • FIG. 44 is a schematic view of the structure after the light emitting diode C6 and the encapsulation layer C9 are formed on the basis of FIG. 43 .
  • the array substrate can drive the light-emitting unit in a passive manner, or the light-emitting unit can be provided by a driving circuit including a thin film transistor.
  • the signal, or alternatively, the signal can also be provided to the light-emitting unit via a microchip (microchip).
  • the array substrate includes a base substrate C7, the first conductive sub-layer C12 is located on a side away from the base substrate C7 relative to the first metal sub-layer C11, and the first conductive sub-layer C12 is located on the side away from the base substrate C7.
  • the materials of the layers include metal oxides or metal alloys.
  • the material of the first metal sub-layer includes copper
  • the material of the first conductive sub-layer includes indium zinc oxide or indium tin oxide.
  • indium zinc oxide is generally used to make the first conductive sublayer to avoid the occurrence of the first metal sublayer made of copper in the process of fabricating the array substrate. oxidation.
  • any one of the plurality of device pads includes a second metal sublayer C21, and the second metal sublayer C21 and the first metal sublayer C11 are arranged in the same layer as the metal of the electrode layer. sublayer.
  • the same layer setting refers to the one-time patterning process.
  • One patterning process refers to forming the desired pattern through one film formation and photolithography process.
  • One patterning process includes film formation, exposure, development, etching and stripping.
  • the second metal sub-layer is disposed on the same layer as the first metal sub-layer, so that the number of patterning processes can be reduced, the manufacturing process can be simplified, and the production cost can be greatly reduced.
  • the second metal sub-layer and the first metal sub-layer are arranged in the same layer, and the second conductive sub-layer and the first conductive sub-layer are arranged in the same layer (and are co-located in the conductive sub-layer), and the material of the second metal sub-layer includes copper,
  • the material of the second conductive sub-layer includes indium zinc oxide or indium tin oxide.
  • the solder paste cannot be directly disposed on the second conductive sub-layer , and the second conductive sub-layer in the device pad needs to be removed to expose the second metal sub-layer, thereby obtaining the display substrate as shown in FIG. 43 .
  • the material of the second metal sub-layer includes copper, and copper can be bonded with solder paste, so that the light-emitting unit is bonded to the second metal sub-layer through a reflow bonding process.
  • the circuit board is generally bonded to the first conductive sub-layer by heat-curing adhesive by means of hot pressing, and there is no need to remove the part of the first conductive sub-layer used for bonding with the circuit board.
  • the materials of the first metal sublayer and the second metal sublayer include copper.
  • the lead pad may also include a first buffer sublayer, and the first metal sublayer is located in the first buffer layer.
  • the device pad may also include a second buffer sublayer, and the second metal sublayer is located on the second buffer sublayer; the first buffer sublayer and the second buffer sublayer are arranged in the same layer, and the material can be It is an alloy containing molybdenum, such as molybdenum-titanium-nickel alloy.
  • the lead pads in the bonding area of the circuit board include a first metal sublayer and a first conductive sublayer, and the first conductive sublayer has oxidation resistance and covers the first metal sublayer; then, During the fabrication of the array substrate, when the light-emitting unit and the second metal sub-layer are bound in the light-emitting area, the first metal sub-layer in the bonding area of the circuit board will not be oxidized due to the protection of the first conductive sub-layer, thereby ensuring that The bonding quality of subsequent circuit boards, thereby improving product yield.
  • connection part is located on the side away from the substrate relative to the first conductive sub-layer.
  • the second step of the second planarization layer is optional.
  • the circuit board bonding area OA also includes a first connection part. (not shown, may be part of the solder layer in some embodiments for electrically connecting the circuit board to the pin pads) and a first portion C14 of the second planarization layer covering the plurality of pins the area between the lead pads and expose the surface of the lead pads and device pads.
  • the light emitting area OB further includes a second connection part (as shown in C10 in FIG. 44 , which may be a part of the solder layer in some embodiments, for electrically connecting the light emitting unit with the device pad) and a second connection part of the second planarization layer.
  • the second connection portion is located on a side away from the substrate relative to the second metal sub-layer, and the second portion of the second planarization layer covers the area between the plurality of device pads.
  • first portion C14 of the second planarization layer and the second portion C24 of the second planarization layer are disposed in the same layer, and can form a second planarization layer with an integrated structure.
  • the first part of the second planarization layer and the second part of the second planarization layer can protect the first wiring layer and the second wiring layer respectively, and at the same time play a flattening role, so as to facilitate subsequent processes.
  • It can be an organic material, such as: resin (Resin). Therefore, the second planarization layer may also be referred to as a protective layer, an organic protective layer, a resin layer, or the like.
  • the portion of the electrode layer covered by the first portion of the second planarization layer may serve as the first wiring layer, and the portion of the electrode layer covered by the second portion of the second planarization layer may serve as the first wiring layer. Second wiring layer.
  • the material of the first connection part may be thermal curing glue, and the material of the second connection part may be solder paste, copper paste, or the like.
  • a silicon oxynitride (SiON) insulating layer 104 is further provided between the second resin layer C105 (ie, the second part of the second planarization layer) and the electrode layer C103 (thick copper layer) (It can also be an inorganic protective layer, a passivation layer, etc.).
  • the second conductive sub-layer is disposed above the first metal sub-layer, the second metal sub-layer is well protected. Therefore, the array substrate removes the original process.
  • Silicon oxynitride insulating layer thus eliminating the PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) process and silicon oxynitride etching process in the original process, simplifying the original process flow and reducing manufacturing costs .
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • plasma enhanced chemical vapor deposition silicon oxynitride etching process
  • the array substrate may further include an encapsulation layer C9 covering the light-emitting unit C6 for protection and encapsulation, and the material of the encapsulation layer may be silica gel.
  • the array substrate may further include metal leads located on the substrate, and connection lines arranged on the same layer as the device pads.
  • the metal lead wire includes an anode wire C51 and a cathode wire C52
  • the connection wire includes a wire C81 and a wire C82.
  • the trace C82 includes a third metal sublayer C83 and a third conductive sublayer C84.
  • the third metal sublayer C83 and the second metal sublayer C21 are connected to each other and are located in the metal sublayer. In FIG. 43, a dotted line is used. separate.
  • the anode wiring C51 may only include a one-layer structure; alternatively, it may also include a first molybdenum-titanium-nickel alloy sublayer (equivalent to the first adhesion layer in Embodiment 1), a copper sublayer and a layered one in sequence. layer and a second molybdenum-titanium-nickel alloy sublayer (equivalent to the second adhesion layer in Example 1).
  • thick copper is used for the copper sub-layer (compared to the copper thickness of the first conductive sub-layer). The thickness of copper is related to the product size of the Mini-LED backplane. The greater the copper thickness.
  • the first molybdenum-titanium-nickel alloy sub-layer, the copper sub-layer, and the second molybdenum-titanium-nickel alloy sub-layer can be sequentially fabricated by a sputtering process, and the second molybdenum-titanium-nickel alloy sub-layer can protect the copper sub-layer and prevent surface oxidation of the copper sub-layer.
  • the array substrate may further include a first planarization layer C33 covering the metal leads, and the pin pads C1 and the device pads 2 are located between the first planarization layer C33.
  • the material of the first planarization layer may be an organic material, such as resin.
  • the first metal sub-layer C11 and the third metal sub-layer C83 are respectively electrically connected to the anode wiring C51 through via holes (not shown in FIG. 43 ) passing through the first planarization layer C33 .
  • the material of the first metal sub-layer includes copper or an alloy containing molybdenum
  • the material of the first conductive sub-layer includes an alloy containing copper and nickel
  • the lead pad may further include a first buffer sublayer, and the first metal sublayer is located on the first buffer sublayer.
  • the lead pad includes a first buffer sublayer (also called a buffer metal layer), a first metal sublayer (a copper layer, also called a copper electrode layer), and a first conductive sublayer (containing copper-nickel).
  • the alloy layer also known as the copper-nickel alloy layer
  • the material of the first buffer sublayer may be an alloy containing molybdenum, and its thickness may be The thickness range of the first metal sublayer may be The thickness range of the first conductive sublayer may be
  • the lead pad C1 includes a first metal sublayer (alloy layer containing molybdenum) C11 and a first conductive sublayer (containing an alloy layer containing molybdenum). Copper-nickel alloy layer) C12 two-layer structure.
  • the thickness of the first metal sub-layer may be The thickness range of the first conductive sublayer may be
  • the pin pad adopts a two-layer structure or a three-layer structure needs to be determined according to the resistance requirements.
  • the material of the first conductive sub-layer includes an alloy containing copper-nickel, and the target material ratio of the copper-nickel alloy can be selected according to resistance requirements and etching conditions. Theoretically, the higher the nickel content, the stronger the oxidation resistance. However, nickel is magnetic, and if the content of nickel is too high, on the one hand, it will increase the difficulty of making the target material, and on the other hand, it will increase the difficulty of subsequent patterning, so the ratio of nickel should not be too high.
  • any one of the plurality of device pads includes a second metal sub-layer C21 and a second conductive sub-layer C22 arranged in layers, and the second conductive sub-layer C22 is opposite to the second metal sub-layer.
  • C21 is located on the side away from the base substrate C7; wherein, the second metal sub-layer and the first metal sub-layer are arranged in the same layer, and the second conductive sub-layer and the first conductive sub-layer are arranged in the same layer.
  • the same layer setting refers to the one-time patterning process.
  • One patterning process refers to forming the desired pattern through one film formation and photolithography process.
  • One patterning process includes film formation, exposure, development, etching and stripping.
  • the second metal sublayer and the first metal sublayer are disposed on the same layer, and the second conductive sublayer and the first conductive sublayer are disposed on the same layer, thereby reducing the number of patterning processes, simplifying the manufacturing process, and greatly reducing production costs.
  • the device pad includes a second buffer sublayer, a second metal sublayer (copper layer, also known as copper electrode layer) and a second conductive sublayer (copper-nickel-containing alloy layer, also known as copper-nickel layer) alloy layer) three-layer structure.
  • the material of the first metal sublayer includes a molybdenum-containing alloy
  • the material of the second metal sublayer also includes a molybdenum-containing alloy
  • the device pad includes a second metal sublayer (molybdenum-containing alloy layer) and a second metal sublayer (molybdenum-containing alloy layer) and a second metal sublayer.
  • Conductive sub-layer (copper-nickel-containing alloy layer) two-layer structure.
  • the lead pads in the bonding area of the circuit board include a first metal sublayer and a first conductive sublayer, and the first conductive sublayer has oxidation resistance and covers the first metal sublayer; then, In the manufacturing process of the array substrate, when the light-emitting unit and the second conductive sub-layer are bound in the light-emitting region, if the material of the first metal sub-layer includes copper, the first conductive sub-layer plays a protective role on the first metal sub-layer, In this way, the oxidation of the first metal sublayer is avoided; if the material of the first metal sublayer includes an alloy containing molybdenum, and the material of the first conductive sublayer includes an alloy containing copper and nickel, the first conductive sublayer has oxidation resistance and will not Oxidation occurs.
  • both cases can avoid oxidation of the metal lead layer in the bonding area of the circuit board when the light-emitting unit and the second conductive sub-layer are bound in the light-emitting area; thus ensuring the bonding quality of the subsequent circuit boards, thereby improving the product quality. Rate.
  • the circuit board bonding area OA further includes a first connection part (not shown in FIG. 41 ), and a stacked first protective layer C13 (for example, an inorganic silicon nitride material is used as a material)
  • a stacked first protective layer C13 for example, an inorganic silicon nitride material is used as a material
  • the first portion of the protective layer) and the first portion C14 of the second planarization layer, the first connection portion is located on the side of the first conductive sub-layer away from the substrate, and the first planarization layer is located on the side of the first protective layer away from the substrate. side and cover the area between the multiple pin pads.
  • the light emitting area OB further includes a second connection part (marked as C10 in FIG. 40 ), a second protective layer 23 (eg, the second part of the inorganic protective layer using silicon nitride as a material) and a stacked second protective layer 23 ;
  • the second connection portion is located on the side of the second conductive sub-layer away from the substrate, the second protective layer covers the area between the plurality of device pads, and the second planarization layer is located on the side of the second conductive sub-layer away from the substrate.
  • the first protective layer and the second protective layer are arranged in the same layer, which can form a protective layer with an integrated structure, for example, an inorganic protective layer using silicon nitride as a material; the first part of the second flattening layer and the second flattening layer The second part of the device is arranged in the same layer, which can form a second planarization layer of an integrated structure.
  • the first protective layer and the second protective layer are provided in the same layer, and their materials may be silicon oxynitride, silicon nitride, etc.; the first part of the second planarization layer and the second planarization layer The second part of the layer is arranged in the same layer, and its material may be an organic material, such as resin, for planarization, so as to facilitate subsequent processes.
  • the material of the first connection portion may be thermal curing glue, and the material of the second connection portion may be solder paste, copper paste, or the like.
  • the array substrate may further include metal leads located on the substrate, and connection wires arranged on the same layer as the device pads.
  • the metal lead wire includes an anode wire C51 and a cathode wire C52
  • the connection wire includes a wire C81 and a wire C82.
  • the trace C82 includes a third metal sublayer C83 and a third conductive sublayer C84 , the third metal sublayer C83 and the second metal sublayer C21 are connected, and are separated by dotted lines in FIG. 43 .
  • the anode wiring C51 may only include a one-layer structure; or, may also include a first molybdenum alloy sub-layer and a copper sub-layer that are stacked in sequence. Further, in order to avoid oxidation of the copper sublayer, as shown in FIG. 39 , the array substrate may further include a passivation layer C34 covering the anode wiring C51 , and the material of the passivation layer C34 may be silicon oxynitride, silicon nitride, or the like. Further, for planarization to facilitate subsequent processes, as shown in FIG.
  • the array substrate may further include a first planarization layer C33 located on the passivation layer C34, and the pin pads and device pads are located on the first planarization layer C33.
  • the first metal sub-layer C11 and the third metal sub-layer C83 are respectively electrically connected to the anode wiring C51 through via holes passing through the passivation layer C34 and the first planarization layer C33.
  • the material of the first planarization layer may be an organic material, such as resin.
  • the anode traces may further include a second molybdenum alloy sub-layer on top of the copper sub-layer.
  • FIG. 39 illustrates that the array substrate includes a passivation layer and a first planarization layer as an example.
  • the array substrate may further include an insulating buffer layer between the base substrate and the metal leads, and the material of the insulating buffer layer may be polyimide or the like.
  • the material of the insulating buffer layer may also be an inorganic insulating material such as silicon oxide.
  • the array substrate further includes a base substrate C7; a plurality of pin pads C1 are exposed on the surface facing the base substrate C7 for binding the circuit board C5; A plurality of device pads (anode pad C2 and cathode pad C2') are exposed away from the surface of the base substrate C7 for binding the light emitting cells C6.
  • the pin pads C1 may be located on the metal wiring layer instead of the electrode layer.
  • the array substrate may further include a peeling layer C44, and the peeling layer C44 is located between the base substrate C7 and the lead pad C1.
  • the peeling layer C44 is located between the base substrate C7 and the lead pad C1.
  • the material of the release layer may be a mechanically releasable material.
  • the material of the substrate can be a rigid substrate, such as glass; it can also be a flexible substrate, such as polyimide.
  • FIGS. 47 to 50 the structures of the lead pads and the device pads are only schematically depicted, and the multi-layer structures included in the lead pads are not shown.
  • the pin pads include a first metal sublayer and a first conductive sublayer, so when binding the light-emitting unit and the second metal sublayer, the pin pads in the bonding area of the circuit board will not occur. oxidation, thereby ensuring the bonding quality of the subsequent circuit board and the first conductive sub-layer, thereby improving the product yield.
  • the circuit board is bound to the side of the first metal sub-layer close to the peeling layer, thereby reducing the non-light-emitting area on the light-emitting side, thereby realizing a narrower frame.
  • the array substrate further includes a first planarization layer C41 , an inorganic protective layer C43 and a second planarization layer C42 (also referred to as an organic layer, a resin layer, etc.) which are arranged in layers, wherein the first The planarization layer C41 covers the lead pads C1 , and the second planarization layer is located on the side of the inorganic protective layer away from the base substrate and covers the regions between the plurality of device pads.
  • the array substrate may further include traces C82 disposed on the same layer as the device pads, and the traces C82 are connected to the pin pads through vias (not shown in FIG.
  • the trace C82 is connected to the anode pad C2 and is separated by a dashed line in FIG. 50 .
  • the anode pad C2 and the cathode pad C2' are electrically connected to the anode and the cathode of the light emitting diode C6 through the second connection part C10, respectively, and the circuit board C5 is connected to the lead through the first connection part (not shown in FIG. 50 ).
  • the foot pad C1 is electrically connected.
  • the lead pads are located under the first planarization layer C41, and the device pads are located above the first planarization layer C41.
  • the material of the first metal sub-layer may be copper or an alloy containing molybdenum
  • the material of the first conductive sub-layer may be metal oxide (for example: indium zinc oxide, indium tin oxide) or metal alloy (for example, : alloys containing copper and nickel).
  • the lead pad may further include a molybdenum-containing alloy sublayer disposed under the first metal sublayer, so as to facilitate the fabrication of the first metal sublayer.
  • the array substrate further includes the first planarization layer, the inorganic protective layer, and the second planarization layer
  • the circuit board since the circuit board is bound to the side of the first metal sublayer close to the peeling layer, therefore, There is no need to set via holes in the regions of the first planarization layer, the inorganic protective layer, and the second planarization layer corresponding to the first metal sublayer to expose the pin pads; then, when binding the light-emitting unit and the second metal sublayer,
  • the first planarization layer, the inorganic protective layer, and the second planarization layer can protect the lead pad from being oxidized.
  • the lead pad can only include the first metal sublayer (for example, a copper sublayer). etc.) or the first conductive sub-layer (eg: copper-nickel sub-layer, etc.).
  • the material of the first planarization layer may be polyimide, and the material of the second planarization layer may be resin.
  • the device pad may include only one metal sublayer, and the metal sublayer may be a copper sublayer or an alloy sublayer containing copper (eg, an alloy sublayer containing copper and nickel); of course, it may also include multiple sublayers. Taking into account the full use of the original process as much as possible and reducing the production cost, the former is selected.
  • the array substrate may further include an encapsulation layer C9 covering the light-emitting unit to protect and encapsulate, and the material of the encapsulation layer may be silica gel.
  • the plurality of device pads are divided into multiple groups of device pads, and each group of device pads includes a pair of cathode pads C2' and anode pads C2.
  • the array substrate further includes a base substrate, metal leads, connection wires arranged on the same layer as the plurality of device pads, and a first planarization layer, wherein the metal wires are arranged close to the base substrate relative to the connection wires, and the first planarization layer
  • the metallization layer is disposed close to the base substrate relative to the connecting wires and covers the metal leads.
  • the metal leads are electrically connected to at least one of the plurality of pin pads for transmitting electrical signals provided by the circuit board.
  • connection traces are used to realize serial connection or parallel connection of multiple groups of device pads, and are also used to electrically connect with metal leads through vias penetrating the first planarization layer.
  • the specific connection manner of the above-mentioned groups of device pads is not limited.
  • FIG. 38 an example is shown in which two adjacent groups of device pads are connected in series.
  • the area OA is the circuit board binding area
  • the area OB is the light-emitting area
  • the plurality of device pads can be divided into multiple groups of device pads, each group of device pads is used to bind a light-emitting diode, and includes:
  • the cathode pad C2' and the anode pad C2 are arranged in pairs.
  • the metal leads may include anode traces C51 and cathode traces C52, and the connection traces include traces C81 and C82.
  • the device pads of the adjacent two groups are connected in series through the trace C81; in the two groups of device pads connected in series, the anode pads of one group are connected to a trace C82, and the trace C82 passes through the via hole passing through the first planarization layer C4 is electrically connected to the anode trace C51; the anode trace C51 is electrically connected to one pin pad C1 through a via hole (not shown in FIG.
  • the cathode pad of the other group is electrically connected to the other
  • the trace C82 is connected, and the trace C82 is electrically connected to the cathode trace C52 through another via hole C4 passing through the first planarization layer, and the cathode trace C52 passes through the via hole passing through the first planarization layer (not shown in FIG. 38 ).
  • ) is electrically connected to another pin pad C1.
  • the cathode pad C2', the anode pad C2, the pin pad C1, the trace C81 and the trace C82 are arranged on the same layer and use the same filling pattern; the anode trace C51 and the cathode trace C52 are set on the same layer , with the same fill pattern.
  • the above-mentioned array substrate may also include a passivation layer, and the passivation layer is located between the first planarization layer and the metal leads and covers the metal leads.
  • the connection traces need to pass through the passivation layer and the first planarization layer.
  • the vias are electrically connected to the metal leads.
  • This embodiment also provides a backlight module including the array substrate disclosed in the above embodiments.
  • the backlight module may further include structures such as a diffusion sheet, a driving circuit, etc., which can be determined according to actual needs, and will not be repeated here.
  • the backlight module can be used in any display device or component that needs to provide backlight.
  • the backlight module can be a rigid backlight module or a flexible backlight module (ie, bendable or foldable); no limitation is made here. .
  • ultra-thin light source modules can be made through denser light source arrangement; combined with regional dimming technology, including Mini-LED -The display of LED backlight module will have better contrast ratio and high dynamic lighting rendering display effect.
  • LCDs with Mini-LED backlight are far superior to current LCDs in terms of brightness, contrast, color reproduction and power consumption, and can even compete with active-matrix organic light-emitting diode displays in terms of contrast and power consumption.
  • the existing liquid crystal display production line can be used to control the production cost.
  • This embodiment also provides a display device, including the array substrate disclosed in the above embodiments, a circuit board and a plurality of light-emitting units; the circuit board is electrically connected to a plurality of pin pads of the array substrate, and the plurality of light-emitting units are connected to the array The plurality of device pads of the substrate are electrically connected.
  • the display device has the characteristics of high contrast ratio, good brightness and high degree of color reproduction.
  • the display device may be a rigid display device or a flexible display device (ie, bendable and foldable).
  • the display device can be any product or component with a display function, such as a TV, a digital camera, a mobile phone, and a tablet computer. It can be understood that, in some embodiments, the light emitting unit can be used as a part of the array substrate.
  • This embodiment further provides a method for manufacturing a display device, including:
  • the light-emitting unit includes a light-emitting diode
  • the plurality of device pads are divided into multiple groups of device pads, and each group of device pads includes a pair of cathode pads and anode pads, then the anode and cathode of the light-emitting diode are respectively Correspondingly electrically connected to the anode pad and the cathode pad.
  • a reflow soldering process can be used to complete the bonding.
  • functional devices such as light-emitting units can also be used as part of the array substrate; that is, step S1 and step S2 together form the array substrate required by the present disclosure.
  • the binding can be completed by means of hot pressing.
  • This embodiment provides a method for fabricating a display device.
  • the pin pads in the bonding area of the circuit board include a first metal sub-layer and a first conductive sub-layer, and the first conductive sub-layer
  • the layer has oxidation resistance and covers the first metal sub-layer; then, when step S2 is performed, the first conductive sub-layer in the bonding area of the circuit board will not be oxidized, thereby ensuring the bonding quality of the circuit board in the subsequent step S3 , thereby improving product yield.
  • This embodiment further provides a method for fabricating a display device.
  • the structure of an array substrate included in the display device may refer to FIG. 43 or FIG. 46 .
  • the method includes:
  • the metal sub-layer film for example, the copper electrode material layer in Embodiment 1 and the conductive sub-layer film can be deposited in one step by a sputtering process, and patterned by one-step etching with a copper etchant to form the first metal
  • the sublayer (equivalent to a part of the copper electrode layer in the first embodiment), the first conductive sublayer, the second metal sublayer (equivalent to a part of the copper electrode layer in the first embodiment) and the second conductive sublayer.
  • a mask needs to be used to form the desired pattern.
  • the pin pads and device pads formed by S11 respectively include a two-layer structure.
  • the materials of the first metal sub-layer and the second metal sub-layer include copper.
  • the lead pad may also include a first buffer sub-layer (equivalent to the second buffer in Embodiment 1).
  • the first metal sublayer is located on the first buffer sublayer; the device pad may also include a second buffer sublayer (equivalent to a part of the second buffer metal layer in the first embodiment), the second metal The sub-layer is located on the second buffer sub-layer; the first buffer sub-layer and the second buffer sub-layer are arranged in the same layer, and the material can be an alloy containing molybdenum, such as molybdenum-titanium-nickel alloy.
  • the buffer sublayer film, the metal sublayer film and the conductive sublayer film can be deposited in one step by a sputtering process, and the The copper etchant is patterned by one-step etching to form a first buffer sublayer, a second buffer sublayer, a first metal sublayer, a second metal sublayer, a first conductive sublayer and a second conductive sublayer.
  • the material of the second conductive sub-layer includes indium zinc oxide or indium tin oxide. Considering that indium zinc oxide has better conductivity and lower resistivity, it is generally made of indium zinc oxide. Indium zinc oxide can be etched by any acid. Referring to FIG. 42 , the part of the second conductive sub-layer that is used for binding with the light-emitting unit is etched away by the screen etching process, which is conducive to the subsequent use of solder paste to bind the light-emitting unit to the second conductive sub-layer through the reflow soldering process. Two metal sublayers. In Fig. 42, a tool C40 is used to push the indium zinc oxide etching paste C30 from the mask plate C20 to the area to be etched.
  • solder paste brushing, light-emitting diode bonding, reflow soldering, and silica gel packaging processes are performed in sequence to complete the binding of the light-emitting unit and the second metal sublayer, thereby forming the array substrate as shown in FIG. 44 . Since the first conductive sub-layer plays a protective role on the first metal sub-layer, oxidation of the first metal sub-layer in S13 can be avoided, thereby ensuring the bonding quality of subsequent circuit boards and improving product yield.
  • the circuit board and the first conductive sub-layer can be bound together through the first connection portion.
  • the fabrication method of the array substrate is simple and easy to implement and has strong operability.
  • the method further includes:
  • the materials of the first portion of the second planarization layer and the second portion of the second planarization layer may be organic materials, such as resins.
  • a mask plate needs to be used to form a desired pattern.
  • binding the light-emitting unit and the second metal sublayer includes:
  • solder paste is often used.
  • a reflow soldering solidification process can be used for bonding, wherein the peak temperature of the reflow soldering is about 240°C, and the holding time is 90s.
  • the light-emitting unit may be encapsulated with a packaging material such as silica gel to form an encapsulation layer C9 as shown in FIG. 44 .
  • a packaging material such as silica gel
  • the curing temperature of silica gel is 150°C and kept for 4h.
  • the method further includes:
  • a region corresponding to the first conductive sub-layer C12 in the first portion C14 of the second planarization layer is partially etched to form a first via hole to expose the lead pad. It should be noted that, before performing S16, the light-emitting area has been packaged. Since the encapsulation layer is relatively thick, the first via hole is formed by etching in S16, which has little effect on the light-emitting area, so there is no need to use an additional mask.
  • Binding the circuit board and the first conductive sub-layer includes:
  • the material of the first connection portion may be a thermosetting adhesive, and the circuit board may be bound by a hot pressing method, and the temperature is generally 130°C to 150°C.
  • the second via hole and the first via hole are respectively formed through S15 and S16, so that in S13, when binding the light-emitting unit and the second metal sub-layer, a second planarization layer is provided above the lead pad.
  • the first part, the first part of the second planarization layer, can protect the lead pad from oxidation. Therefore, when fabricated by this method, the lead pad can also include only the first metal sub-layer, and the first conductive sub-layer does not need to be provided.
  • the device pad can also only include the second metal sub-layer without the need to provide the second Conductive sublayer.
  • the pin pad since the pin pad includes a first metal sublayer and a first conductive sublayer, the first conductive sublayer has a good protective effect on the first metal sublayer, so S16 can also be merged into S15, that is, in S15 , the first via hole and the second via hole are formed at the same time to expose the lead pad and the device pad, and the formed array substrate structure can be referred to as shown in FIG. 43 .
  • the first conductive sub-layer has good oxidation resistance, and the oxidation of itself and the first metal sub-layer can be avoided. .
  • the manufacturing method In the manufacturing method, one mask is used in each of S11 and S15.
  • the manufacturing method further includes: forming metal leads, the metal leads include anode wiring C51 and cathode wiring (not shown in FIG. 46 ). Then, a total of 4 masks (4Mask) are required to form the array substrate shown in FIG. 46 .
  • the formed array substrate is as shown in FIG. 57, and generally four masks are used in the fabrication method including: S100, as shown in FIG. 51, forming a metal wiring layer C101 on the glass substrate C100; S101, forming as shown in the figure S102, forming an electrode layer C103 as shown in FIG. 52; S103, forming an inorganic protective layer C104 (also known as a silicon oxynitride insulating layer) as shown in FIG. 53; S104, A second planarization layer C105 as shown in FIG. 54 is formed, and holes are opened in the diode circuit board bonding area (LED Bonding Pad) and the flexible circuit board circuit board bonding area (FPC Bonding Pad) as shown in FIG.
  • S100 as shown in FIG. 51, forming a metal wiring layer C101 on the glass substrate C100
  • S101 forming as shown in the figure S102, forming an electrode layer C103 as shown in FIG. 52
  • S103 forming an inorganic protective layer C104 (also known as a silicon
  • the back-end process includes: brushing solder paste, transferring light-emitting diodes, reflow soldering, screen printing silica gel, and silica gel curing in sequence.
  • the completed array substrate is shown in Figure 57. Among them, the peak temperature of reflow soldering is about 240°C, and the holding time is 90s. The curing temperature of silica gel was 150°C for 4h.
  • the anode C108 and the cathode C109 of the micro light-emitting diode C107 are electrically connected to the electrode layer C103 through the solder paste C110 respectively, and the array substrate further includes a silica gel encapsulation layer C106 .
  • the method for fabricating an array substrate provided in this embodiment does not increase the number of masks, and at the same time can avoid the problem of oxidation of the first metal sub-layer made of copper in the process of fabricating the array substrate, thereby ensuring that the The bonding quality of the circuit board, thereby improving the product yield.
  • the second conductive sub-layer since the second conductive sub-layer is disposed above the first metal sub-layer, the second metal sub-layer has a good protection effect.
  • the manufacturing method of the array substrate removes the The process of the silicon oxynitride protective layer of the original process is eliminated, thereby eliminating the PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) process and the silicon oxynitride etching process in the original process, which simplifies the original process.
  • PECVD Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition
  • the process flow reduces the manufacturing cost.
  • This embodiment also provides a method for manufacturing a display device.
  • the structure of an array substrate included in the display device can be referred to as shown in FIG. 39 , and the method includes:
  • the metal sub-layer film and the conductive sub-layer film can be deposited in one step by a sputtering process, and patterned by one-step etching with an etching solution to form the first metal sub-layer, the first conductive sub-layer, the second metal sub-layer layer and the second conductive sublayer.
  • a mask is required to form the desired pattern.
  • the first wiring layer and the second wiring layer formed by S21 respectively include two-layer structures. If the materials of the first metal sub-layer and the second metal sub-layer include copper, in order to increase the adhesion of copper and reduce the difficulty of fabrication, the lead pad may also include a first buffer sub-layer, and the first metal sub-layer is located in the first buffer sub-layer. on the buffer sublayer; the device pad may further include a second buffer sublayer, and the second metal sublayer is located on the second buffer sublayer.
  • the buffer sublayer film, the metal sublayer film and the conductive sublayer film can be deposited in one step by a sputtering process, and the The etching solution is patterned by one-step etching to form a first buffer sublayer, a second buffer sublayer, a first metal sublayer, a second metal sublayer, a first conductive sublayer and a second conductive sublayer.
  • the lead pad includes a first metal sublayer (alloy layer containing molybdenum) and a first conductive sublayer (containing copper nickel).
  • the alloy layer) two-layer structure
  • the device pad includes a second metal sublayer (alloy layer containing molybdenum) and a second conductive sublayer (alloy layer containing copper and nickel) two-layer structure.
  • solder paste brushing, light emitting diode printing, reflow soldering, silicone packaging, etc. may be performed in sequence to complete the binding of the light emitting unit and the second metal sub-layer.
  • the first conductive sub-layer plays a protective role on the first metal sub-layer, so as to avoid oxidation of the first metal sub-layer; if the first metal sub-layer is The material includes an alloy containing molybdenum, the material of the first conductive sub-layer includes an alloy containing copper and nickel, and the first conductive sub-layer has oxidation resistance and will not be oxidized.
  • both cases can avoid oxidation of the metal lead layer in the bonding area of the circuit board when the light-emitting unit and the second conductive sub-layer are bound in the light-emitting area; thus ensuring the bonding quality of the subsequent circuit boards, thereby improving the product quality. Rate.
  • the circuit board and the first conductive sub-layer can be bound together through the first connection portion.
  • the fabrication method of the array substrate is simple and easy to implement and has strong operability.
  • the method before S22, before binding the light-emitting unit and the second conductive sub-layer, and in S21, after sequentially forming the metal thin film and the conductive thin film and patterning, the method further includes:
  • the material of the first thin film can be silicon oxynitride, silicon nitride, etc., used to form the first part of the inorganic protective layer and the second part of the inorganic protective layer; the material of the second thin film can be resin, used to form the second planarization layer the first part and the second part of the second planarization layer.
  • a mask plate needs to be used to form the desired pattern.
  • binding the light-emitting unit and the second conductive sub-layer includes:
  • the second connection part may be solder paste, copper paste, etc. In practice, solder paste is mostly used.
  • a reflow soldering solidification process can be used for bonding, wherein the temperature of the reflow soldering is 230-260°C, and the holding time is 90s.
  • the light-emitting unit is also encapsulated by packaging materials such as silica gel.
  • packaging materials such as silica gel.
  • the curing temperature of silica gel is 150°C and kept for 4h.
  • the method further includes:
  • the first connection part may be a thermosetting adhesive
  • the circuit board may be bound by a hot pressing method, and the temperature is generally 130°C to 150°C.
  • the second via hole and the first via hole are respectively formed through S24 and S25, so that when S22, binding the light-emitting unit and the second metal sub-layer, the first part of the inorganic protective layer is provided above the lead pad and the first part of the second planarization layer, the first part of the inorganic protective layer and the first part of the second planarization layer can protect the lead pad and prevent it from being oxidized. Therefore, when using this method, the lead pads can also only include copper sublayers or copper-containing alloy sublayers, and there is no need to provide a two-layer conductive structure. Correspondingly, the device pads can also include only copper sublayers or copper-containing alloy sublayers. .
  • the lead pad since the lead pad includes a first metal sublayer and a first conductive sublayer, the first conductive sublayer has a good protective effect on the first metal sublayer, so S25 can also be incorporated into S24, that is, in S24 , the first via hole and the second via hole are formed at the same time to expose the pin pad and the device pad. In this way, when binding the light-emitting unit and the second metal sub-layer in S22, even if the lead pad is partially exposed due to the first via hole, the first conductive sub-layer has good oxidation resistance, and it can avoid itself and the second metal sub-layer. A metal sublayer is oxidized.
  • the manufacturing method further includes: forming metal leads, passivation layer C34 and first planarization layer C33 respectively, wherein the metal leads include anode wiring C51 and cathode traces (not shown in Figure 39).
  • a mask is required to form the metal leads, and a mask is required to form the passivation layer and the first planarization layer. Then, a total of 4 masks (4Mask) are required to form the array substrate shown in FIG. 39 .
  • the method for fabricating an array substrate does not increase the number of masks, and at the same time can avoid the problem of oxidation of the first metal sub-layer made of copper in the process of fabricating the array substrate, thereby ensuring that the The bonding quality of the circuit board, thereby improving the product yield.
  • This embodiment further provides a method for fabricating a display device.
  • the structure of an array substrate included in the display device can be referred to as shown in FIG. 50 , and the method includes:
  • the material of the release layer may be a mechanically releasable material.
  • the material of the base substrate can be a rigid material, such as glass; or, it can also be a flexible material, such as polyimide (PI).
  • the lead pad includes a stacked first metal sublayer and a first conductive sublayer.
  • the formed array substrate can be referred to as shown in FIG. 47 .
  • a local laser lift-off (LLO) process and array substrate dicing are completed at the position of the circuit bonding board to obtain a single array substrate to be bonded, and then the single array substrate to be bonded is processed Subsequent binding process.
  • LLO local laser lift-off
  • solder paste brushing, light-emitting diode printing, reflow soldering, and silicone packaging processes can be performed in sequence to complete the binding of the light-emitting unit and the device pads.
  • S34 Remove at least a region of the substrate and the lift-off layer corresponding to the portion of the first metal sublayer used for bonding the circuit board (marked as C50 in FIG. 49 ), and expose part of the first metal sublayer.
  • partial cutting may be used to remove the area of the base substrate and the peeling layer corresponding to the part of the first metal sub-layer used for binding the circuit board.
  • the circuit board and the first metal sub-layer may be bound together through the first connection portion.
  • the formed lead pads include the first metal sublayer and the first conductive sublayer, then, when the light-emitting unit and the second metal sublayer are bound, the lead pads in the bonding area of the circuit board are not Oxidation occurs, thereby ensuring the bonding quality of the subsequent circuit board and the first conductive sub-layer, thereby improving product yield.
  • the circuit board is bound to the side of the first metal sub-layer close to the peeling layer, thereby reducing the non-light-emitting area on the light-emitting side, thereby realizing a narrower frame.
  • the array substrate further includes a first planarization layer C41, an inorganic protective layer C43, a second planarization layer C42, via holes (not marked in FIG. 50) and a second connection portion C10.
  • An organic layer covers the lead pads.
  • the device pad is located above the first planarization layer
  • the protective layer covers the device pad and the first planarization layer
  • the second planarization layer is located above the inorganic protective layer.
  • the via hole penetrates through the second planarization layer and the inorganic protective layer to expose the device pad, and the light emitting unit is electrically connected to the device pad through the second connection part.
  • the step of forming the lead pad on the peeling layer requires a mask; in addition, forming the device pad, forming the first planarization layer, forming the inorganic protective layer, the second planarizing layer and the via hole respectively require a mask. mask.
  • a total of 4 masks are required to form the array substrate shown in FIG. 50.
  • the number of masks is not increased, and the problem of oxidation of the pin pads during the production of the array substrate can be avoided at the same time. , so as to ensure the bonding quality of the circuit board, thereby improving the product yield.
  • the circuit board is bound to the side of the first metal sub-layer close to the peeling layer, thereby reducing the non-light-emitting area on the light-emitting side, thereby realizing a narrower frame.

Abstract

一种阵列基板及其制备方法、显示面板和背光模组，属于显示技术领域。该阵列基板可以包括依次层叠设置的衬底基板（A100）、金属布线层（A200）、第一平坦化层（A300）、电极层（A400）、第二平坦化层（A500）和功能器件层（A600）。其中，电极层（A400）包括依次层叠于衬底基板（A100）一侧的金属子层（A410）和导电子层（A430）；金属子层（A410）的材料包括金属或者金属合金；导电子层（A430）具有抗氧化性且覆盖金属子层（A410）。功能器件层（A600）设于第二平坦化层（A500）远离衬底基板（A100）的一侧，且包括多个与电极层（A400）电连接的功能器件。该阵列基板可以提高阵列基板的良率。

Description

阵列基板及其制备方法、显示面板和背光模组
交叉引用
本公开要求于2020年9月7日提交的申请号为202010927576.8且名称为“阵列基板及其制备方法、显示面板和背光模组”的中国专利申请、于2020年9月7日提交的申请号为202010927603.1且名称为“阵列基板及其制备方法、显示面板和背光模组”的中国专利申请、于2020年9月10日提交的申请号为202010947439.0且名称为“一种发光基板、显示装置及制作方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板及其制备方法、显示面板和背光模组。
背景技术
微发光二极管(Micro-LED，Micro Light Emitting Diode)背板可以包括依次层叠于衬底基板的金属布线层、第一平坦化层、电极层、第二平坦化层和微发光二极管层。然而，在制备过程中，电极层容易氧化，导致微发光二极管背板的良率降低和品质下降。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种阵列基板及其制备方法、显示面板和背光模组，提高阵列基板的良率。
根据本公开的一个方面，提供一种阵列基板，包括：
衬底基板；
金属布线层，设于所述衬底基板的一侧；
第一平坦化层，设于所述金属布线层远离所述衬底基板的一侧；
电极层，设于所述第一平坦化层远离所述衬底基板的一侧；所述电极层包括依次层叠于所述衬底基板一侧的金属子层和导电子层；所述金属子层的材料包括金属或者金属合金；所述导电子层具有抗氧化性且覆盖所述金属子层；
第二平坦化层，设于所述电极层远离所述衬底基板的一侧；
功能器件层，设于所述第二平坦化层远离所述衬底基板的一侧，且包括多个与所述电极层电连接的功能器件。
根据本公开的一些实施方式，所述金属子层的材料包括铜，所述导电子层的材料包括铜镍合金。
根据本公开的一些实施方式，所述金属子层的材料为铜；所述导电子层的材料为铜镍合金。
根据本公开的一些实施方式，所述电极层还可以包括夹设于所述金属子层和所述导电子层之间的第一缓冲金属层；所述第一缓冲金属层的材料为钼、钼铌合金、钼钨合金、钼镍钛合金、钼镁铝合金中的一种或者多种的混合。
根据本公开的一些实施方式，所述第一缓冲金属层和所述导电子层覆盖所述金属子层的侧面和所述金属子层远离所述衬底基板的表面。
根据本公开的一些实施方式，所述导电子层在所述金属子层上的正投影，位于所述金属子层内。
根据本公开的一些实施方式，所述第一缓冲金属层的厚度为100～500埃。
根据本公开的一些实施方式，所述导电子层的厚度为200～1000埃。
根据本公开的一些实施方式，所述电极层还可以包括夹设于所述金属子层和所述导电子层之间的钯金属层；所述钯金属层位于且覆盖所述金属子层远离所述衬底基板的表面和所述金属子层的侧面；所述导电子层位于且覆盖所述钯金属层远离所述衬底基板的表面。
根据本公开的一些实施方式，所述导电子层中，镍的质量含量不小于30％。
根据本公开的一些实施方式，所述导电子层中，镍的质量含量不大于 80％。
根据本公开的一些实施方式，所述导电子层的厚度为500～2000埃。
根据本公开的一些实施方式，所述导电子层的材料包括金属氧化物。
根据本公开的一些实施方式，所述导电子层的材料包括氧化铟锌或者氧化铟锡。
根据本公开的一些实施方式，所述阵列基板包括电路板绑定区和发光区，其中，所述电路板绑定区包括多个引脚焊盘，所述多个引脚焊盘用于与电路板绑定连接；
所述发光区包括多个器件焊盘，所述器件焊盘用于与所述功能器件绑定连接；
所述引脚焊盘和所述器件焊盘设置于所述电极层。
根据本公开的一些实施方式，所述电路板绑定区还包括第一连接部，所述第一连接部位于所述导电子层远离所述衬底基板的一侧；所述第一连接部用于使得所述引脚焊盘的导电子层与所述电路板绑定连接。
根据本公开的一些实施方式，所述导电子层的材料包括金属氧化物；所述器件焊盘设置于所述金属子层且被所述导电子层暴露；
所述发光区还包括第二连接部，所述第二连接部位于所述器件焊盘的金属子层远离所述衬底基板的一侧；所述第二连接部用于使得所述器件焊盘的金属子层与所述功能器件绑定连接。
根据本公开的一些实施方式，所述导电子层的材料包括铜镍合金；
所述发光区还包括第二连接部，所述第二连接部位于所述器件焊盘的导电子层远离所述衬底基板的一侧；所述第二连接部用于使得所述器件焊盘的导电子层与所述功能器件绑定连接。
根据本公开的一些实施方式，所述阵列基板包括多个引脚焊盘；
所述衬底基板暴露所述引脚焊盘靠近所述衬底基板的表面；被所述衬底基板暴露的所述引脚焊盘的表面，用于与所述电路板绑定连接。
根据本公开的一些实施方式，所述引脚焊盘设置于所述金属布线层。
根据本公开的一些实施方式，所述电极层设置有多个器件焊盘；所述多个器件焊盘分为多组器件焊盘，每组所述器件焊盘包括成对设置的阴极焊盘和阳极焊盘；
所述金属布线层设置有金属引线，所述电极层还设置有连接走线；
所述金属引线与所述多个引脚焊盘中的至少一个电连接，用于传输电路板提供的电信号；
所述连接走线用于实现多组所述器件焊盘的串联连接或者并联连接，且还用于通过贯穿所述第一平坦化层的过孔与所述金属引线电连接。
根据本公开的一些实施方式，所述电极层还包括位于所述金属子层靠近所述衬底基板的表面的第二缓冲金属层。
根据本公开的一些实施方式，所述金属布线层包括依次层叠于所述衬底基板的一侧的种子金属层、铜生长层和第二铜镍合金层。
根据本公开的一些实施方式，所述金属布线层包括依次层叠于所述衬底基板的一侧的种子金属层和铜生长层；
所述阵列基板还包括钝化层，钝化层设于所述金属布线层和所述第一平坦化层之间。
根据本公开的一些实施方式，所述阵列基板还包括夹设于所述电极层和所述第二平坦化层之间的无机保护层。
根据本公开的第二个方面，提供一种显示面板，包括上述的阵列基板；所述阵列基板的功能器件为微发光二极管或者迷你发光二极管。
根据本公开的第三个方面，提供一种背光模组，包括上述的阵列基板；所述阵列基板的功能器件为微发光二极管或者迷你发光二极管。
根据本公开的第四个方面，提供一种阵列基板的制备方法，包括：
提供一衬底基板；
在所述衬底基板的一侧形成金属布线层；
在所述金属布线层远离所述衬底基板的一侧形成第一平坦化层；
在所述第一平坦化层远离所述衬底基板的一侧形成电极层，所述电极层包括依次层叠于所述衬底基板一侧的金属子层、第一缓冲金属层和导电子层；所述第一缓冲金属层的材料为钼、钼铌合金、钼钨合金、钼镍钛合金、钼镁铝合金中的一种或者多种的混合；
在所述电极层远离所述衬底基板的一侧形成第二平坦化层；
设置功能器件层；所述功能器件层设于所述第二平坦化层远离所述衬底基板的一侧，且包括多个与所述电极层电连接的功能器件。
根据本公开的一种实施方式，在所述第一平坦化层远离所述衬底基板的一侧形成电极层包括：
在所述第一平坦化层远离所述衬底基板的一侧形成金属子材料层；
对所述金属子材料层进行图案化操作，形成所述金属子层；
在所述金属子层远离所述衬底基板的一侧依次形成第一缓冲金属材料层和导电子材料层；
对所述第一缓冲金属材料层和所述导电子材料层进行图案化操作，以形成所述第一缓冲金属层和所述导电子层；其中，所述金属子层在所述衬底基板上的正投影，位于所述第一缓冲金属层在所述衬底基板上的正投影内。
根据本公开的第五个方面，提供另一种阵列基板的制备方法，包括：
提供衬底基板；
在所述衬底基板的一侧形成金属布线层；
在所述金属布线层远离所述衬底基板的一侧形成第一平坦化层；
在所述第一平坦化层远离所述衬底基板的一侧形成金属子层，所述金属子层与所述金属布线层电连接；
形成钯金属层，所述钯金属层位于且覆盖所述金属子层远离所述衬底基板的表面和所述金属子层的侧面；
采用化学镀的方法形成导电子层，所述导电子层位于且覆盖所述钯金属层远离所述衬底基板的表面；
设置功能器件层；所述功能器件层设于所述导电子层远离所述衬底基板的一侧，且包括多个与所述导电子层电连接的功能器件。
根据本公开的一种实施方式，形成钯金属层包括：
用钯盐的溶液处理所述金属子层，在所述金属子层远离所述衬底基板的表面和所述金属子层的侧面形成所述钯金属层。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合 本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是相关技术中一种金属层刻蚀后的电镜图，其中，金属层包括层叠的钼铌合金层、铜金属层和铜镍合金层，铜镍合金层中镍的质量含量为5％。
图2是相关技术中一种金属层刻蚀后的电镜图，其中，金属层包括层叠的钼铌合金层、铜金属层和铜镍合金层，铜镍合金层中镍的质量含量为20％。
图3是相关技术中一种金属层刻蚀后的电镜图，其中，金属层包括层叠的钼铌合金层、铜金属层和铜镍合金层，铜镍合金层中镍的质量含量为30％。
图4是相关技术中一种金属层刻蚀后的电镜图，其中，金属层包括层叠的铜镍合金层、铜金属层和铜镍合金层，铜镍合金层中镍的质量含量为20％。
图5是实施例一的一种实施方式的阵列基板的制备方法的流程示意图。
图6是实施例一的一种实施方式的形成金属布线层的结构示意图。
图7是实施例一的一种实施方式的形成第一平坦化层的结构示意图。
图8是实施例一的一种实施方式的形成铜电极材料层和第二缓冲金属材料层的结构示意图。
图9是实施例一的一种实施方式的形成铜电极层和第二缓冲金属层的结构示意图。
图10是实施例一的一种实施方式的形成第一缓冲金属材料层和第一铜镍合金材料层的结构示意图。
图11是实施例一的一种实施方式的形成第一缓冲金属层和第一铜镍合金层的结构示意图。
图12是实施例一的一种实施方式的阵列基板的结构示意图。
图13是实施例一的一种实施方式的形成第二缓冲金属材料层、铜电极材料层、第一缓冲金属材料层和第一铜镍合金材料层的结构示意图。
图14是实施例一的一种实施方式的形成第二缓冲金属层、铜电极层、第一缓冲金属层和第一铜镍合金层的结构示意图。
图15是实施例一的一种实施方式的阵列基板的结构示意图。
图16是实施例一的一种实施方式的第二缓冲金属层、铜电极层、第一缓冲金属层和第一铜镍合金层的电镜图。
图17是实施例一的一种实施方式的第一缓冲金属层和第一铜镍合金层的电镜图。
图18-1为相关技术中，依次沉积于玻璃基板上依次沉积的铜镍合金层、铜层和铜镍合金层的电镜图，其中，铜镍合金层中镍的质量含量为20％；图18-2为图18-1的金属层经过刻蚀后的电镜图。
图19-1为相关技术中，依次沉积于玻璃基板上依次沉积的铜镍合金层、铜层和铜镍合金层的电镜图，其中，铜镍合金层中镍的质量含量为30％；图19-2为图19-1的金属层经过刻蚀后的电镜图。
图20为相关技术中，铜镍合金层保护的铜金属条在高温烘烤后的图片，其中，铜镍合金层中镍的质量含量为10％。
图21为铜镍合金层保护的铜金属层在经过不同的处理后的照片，其中，铜镍合金层中镍的质量含量为20％。
图22为铜镍合金层保护的铜金属层在经过不同的处理后的照片，其中，铜镍合金层中镍的质量含量为35％。
图23为实施例二的一种实施方式的阵列基板的制备方法的流程示意图。
图24为实施例二的一种实施方式的在衬底基板的一侧形成金属布线层的结构示意图。
图25为实施例二的一种实施方式的在金属布线层远离衬底基板的一侧形成第一平坦化层的结构示意图。
图26为实施例二的一种实施方式的在金属布线层远离衬底基板的一侧形成钝化层和第一平坦化层的结构示意图。
图27为实施例二的一种实施方式的在第一平坦化层远离衬底基板的一侧形成第二缓冲金属层和铜电极层的结构示意图。
图28为实施例二的一种实施方式的在第一平坦化层远离衬底基板的 一侧形成第二缓冲金属层和铜电极层的结构示意图。
图29为实施例二的一种实施方式的在铜电极层远离衬底基板的一侧形成钯金属层的结构示意图。
图30为实施例二的一种实施方式的在铜电极层远离衬底基板的一侧形成钯金属层的结构示意图。
图31为实施例二的一种实施方式的在钯金属层远离衬底基板的一侧形成第一铜镍合金层的结构示意图。
图32为实施例二的一种实施方式的在钯金属层远离衬底基板的一侧形成第一铜镍合金层的结构示意图。
图33为实施例二的一种实施方式的在第一铜镍合金层远离衬底基板的一侧形成第二平坦化层的结构示意图。
图34为实施例二的一种实施方式的在第一铜镍合金层远离衬底基板的一侧形成第二平坦化层的结构示意图。
图35为实施例二的一种实施方式的阵列基板的结构示意图。
图36为实施例二的一种实施方式的阵列基板的结构示意图。
图37为铜镍合金中镍的含量与化学镀液的pH的关系示意图。
图38为实施例三提供的一种阵列基板的局部结构示意图；
图39为沿图38的AA'方向的一种截面示意图；
图40为在图39的基础上形成发光二极管和封装层之后的结构示意图；
图41-图44为实施例三提供的一种阵列基板的制作流程结构示意图；
图45-图46为实施例三提供的再一种阵列基板的制作流程结构示意图；
图47-图50为实施例三提供的又一种阵列基板的制作流程结构示意图；
图51-图57为实施例三提供的另一种阵列基板的制作流程结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式 能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
微发光二极管(Micro-LED，Micro Light Emitting Diode)背板可以包括依次层叠于衬底基板的金属布线层、第一平坦化层、电极层、第二平坦化层和微发光二极管层。然而，在制备过程中，电极层容易氧化，导致微发光二极管背板的良率降低和品质下降。因此，本公开提供一种阵列基板以克服氧化导致的良率下降。
本公开提供的阵列基板可以包括依次层叠设置的衬底基板、金属布线层、第一平坦化层、电极层、第二平坦化层和功能器件层。其中，所述电极层包括依次层叠于所述衬底基板一侧的金属子层和导电子层；所述金属子层的材料包括金属或者金属合金；所述导电子层具有抗氧化性且覆盖所述金属子层。功能器件层设于所述第二平坦化层远离所述衬底基板的一侧，且包括多个与所述电极层电连接的功能器件。在本公开中，电极层通过设置导电子层以提高其抗氧化能力，进而提高阵列基板的良率。
实施例一
发明人发现，通过在铜金属层上制备铜镍合金，可以防止铜金属层的氧化。然而，铜镍合金的刻蚀速率低于铜的刻蚀速度，且镍含量越高则刻蚀速度越慢。在刻蚀层叠的铜金属层和铜镍合金层时，铜镍合金层通常会残留有屋顶结构(Tip结构)；且镍的含量越高，该屋顶结构越大；铜镍合金层的厚度越大，则刻蚀速率越慢，屋顶结构越大。该屋顶结构在阵列基板的使用过程中，可能会发生坍塌等，进而导致阵列基板出现不良，严重影响阵列基板的产品化，降低了阵列基板的品质。示例性的，参见图1～图4，这些含有铜镍合金层的金属层在刻蚀后均形成有屋顶结构。
图1为一个由层叠的钼铌合金层(MoNb)、铜金属层(Cu)和铜镍合金层(CuNi)组成的金属层刻蚀后的电镜图。其中，铜镍合金层中镍的质量含量(也常被命名为重量含量)为5％。在图1中，可以看到铜镍合金层形成屋顶结构。图2为一个由层叠的钼铌合金层(MoNb)、铜金属层(Cu)和铜镍合金层(CuNi)组成的金属层刻蚀后的电镜图。其中，铜镍合金层中镍的质量含量为20％。在图2中，可以看到铜镍合金层形成严重的屋顶结构。图3为一个由层叠的钼铌合金层(MoNb)、铜金属层(Cu)和铜镍合金层(CuNi)组成的金属层刻蚀后的电镜图。其中，铜镍合金层中镍的质量含量为30％。在图3中，可以看到铜镍合金层形成更严重的屋顶结构，且屋顶结构已经出现了坍塌。图4为一个由层叠的铜镍合金层(CuNi)、铜金属层(Cu)和铜镍合金层(CuNi)组成的金属层刻蚀后的电镜图。其中，铜镍合金层中镍的质量含量为20％。在图4中，可以看到铜镍合金层形成严重的屋顶结构。
本实施例提供一种阵列基板及其制备方法，参见图5，该阵列基板的制备方法包括：
步骤AS110，参见图6，提供一衬底基板A100；
步骤AS120，参见图6，在衬底基板A100的一侧形成金属布线层A200；
步骤AS130，参见图7，在金属布线层A200远离衬底基板A100的一侧形成第一平坦化层A300；
步骤AS140，参见图11和图14，在第一平坦化层A300远离衬底基板A100的一侧形成电极层A400，电极层A400包括依次层叠于衬底基板 A100一侧的铜电极层A410(可以作为金属子层)、第一缓冲金属层A420和第一铜镍合金层A430(可以作为导电子层)；第一缓冲金属层A420的材料为钼、钼铌合金、钼钨合金、钼镍钛合金、钼镁铝合金中的一种或者多种的混合；
步骤AS150，参见图12和图15，在电极层A400远离衬底基板A100的一侧形成第二平坦化层A500；
步骤AS160，参见图12和图15，设置功能器件层A600；功能器件层A600设于第二平坦化层A500远离衬底基板A100的一侧，且包括多个与电极层A400电连接的功能器件A610。
根据本实施例的阵列基板的制备方法，参见图12和图15，所制备出的阵列基板包括依次层叠的衬底基板A100、金属布线层A200、第一平坦化层A300、电极层A400、第二平坦化层A500和功能器件层A600；其中，电极层A400包括依次层叠于衬底基板A100一侧的铜电极层A410、第一缓冲金属层A420和第一铜镍合金层A430；第一缓冲金属层A420的材料为钼、钼铌合金、钼钨合金、钼镍钛合金、钼镁铝合金中的一种或者多种的混合；功能器件层A600包括多个与电极层A400电连接的功能器件A610。
在该阵列基板及其制备方法中，由于铜电极层A410和第一铜镍合金层A430之间设置有第一缓冲金属层A420，因此可以使得第一铜镍合金层A430具有良好的形貌，避免第一铜镍合金层A430在刻蚀时出现屋顶结构，改善电极层A400的形貌并提高阵列基板的品质。其中，第一铜镍合金层A430的设置不仅可以保护铜电极层A410，而且可以提高功能器件A610的附着力。
下面，结合附图对本实施例提供的阵列基板的制备方法的各个步骤的原理、细节和效果做进一步地解释和说明。
本实施例中，任意一个膜层可以包括侧面、靠近衬底基板的表面和远离衬底基板的表面，其中，靠近衬底基板的表面和远离衬底基板的表面通过膜层的侧面连接。在本实施例中，任意一个膜层的厚度为，该膜层在垂直于衬底基板方向的尺寸。
在步骤AS110中，参见图6，可以提供一衬底基板A100。衬底基板 A100可以为无机材料的衬底基板A100，也可以为有机材料的衬底基板A100。举例而言，在本实施例的一种实施方式中，衬底基板A100的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本实施例的另一种实施方式中，衬底基板A100的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。在本实施例的另一种实施方式中，衬底基板A100也可以为柔性衬底基板A100，例如衬底基板A100的材料可以为聚酰亚胺(polyimide，PI)。衬底基板A100还可以为多层材料的复合，举例而言，在本实施例的一种实施方式中，衬底基板A100可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
可选地，参见图6，在形成金属布线层A200之前，还可以在衬底基板A100的一侧形成一绝缘缓冲层A101，例如形成一层氮化硅层、氧化硅层或者氮氧化硅层；然后，在该绝缘缓冲层A101远离衬底基板A100的一侧形成金属布线层A200。该绝缘缓冲层A101可以改善形成金属布线层A200时施加至衬底基板的应力，以及可以隔绝水汽。
在本实施例的一种实施方式中，衬底基板A100的材料为玻璃，以使得该衬底基板具有大的尺寸和低的成本，便于作为一种直下式背光模组的背光源而降低背光模组的成本。
在本实施例的另一种实施方式中，衬底基板A100的材料聚酰亚胺，以使得该阵列基板可以为柔性阵列基板，便于该阵列基板制备柔性或者可折叠的显示面板。
在步骤AS120中，参见图6，可以在衬底基板A100的一侧形成金属布线层A200。金属布线层A200可以包括金属引线，金属引线可以通过电极层A400驱动各个功能器件A610。可以通过沉积和图案化的方法形成金属布线层A200，其中，沉积的方法包括但不限于溅射、电镀和化学镀，图案化的方法包括但不限于光刻、在图案化的种子层上生长出图案化的生 长层、在图案限定层的限定下生长出图案化的金属图案等。
举例而言，在一些实施方式中，可以通过如下方法制备金属布线层A200：在衬底基板A100的一侧溅射形成金属布线材料层，然后通过光刻工艺对该金属布线材料层进行图案化操作，以形成金属布线层A200。在该实施方式中，金属布线材料层可以包括一层金属材料，也可以包括多层层叠的金属材料。
优选地，金属布线材料层至少包括第一铜金属材料层，以使得金属引线具有低的电阻。第一铜金属材料层的厚度不大于1微米，以防止溅射形成第一铜金属材料层的过程中对衬底基板A100产生过大的应力。该第一铜金属材料层经过图案化处理后，形成第一铜金属层。如此，在所制备的阵列基板中，金属布线层A200至少包括第一铜金属层。
进一步优选地，金属布线材料层还可以包括位于第一铜金属材料层靠近衬底基板A100的表面的第一粘附材料层，第一粘附材料层的材料可以为钼、钼铜合金、钼铌合金、钼铜铌合金或者其他金属或者金属合金。该第一粘附材料层经过图案化处理后，形成第一粘附层。该第一粘附层可以提高第一铜金属层与衬底基板A100或者绝缘缓冲层A101之间的粘附力，并保护金属铜免受侵蚀。如此，在所制备的阵列基板中，金属布线层A200可以包括依次层叠于衬底基板A100一侧的第一粘附层和第一铜金属层。
进一步优选地，金属布线材料层还可以包括位于第一铜金属材料层远离衬底基板A100的表面的第二粘附材料层，第二粘附材料层的材料可以为钼、钼铜合金、钼铌合金、钼铜铌合金或者其他金属或者金属合金。该第二粘附材料层经过图案化处理后，形成第二粘附层。该第二粘附层可以提高第一铜金属层与电极层A400粘附力，并保护金属铜免受侵蚀。如此，在所制备的阵列基板中，金属布线层A200可以包括依次层叠于衬底基板A100一侧的第一铜金属层和第二粘附层。
示例性地，金属布线层A200包括依次层叠于衬底基板A100一侧的钼铌合金层、铜金属层和钼铌合金层。
再举例而言，在另一些实施方式中，可以通过如下方法制备金属布线层A200：
在衬底基板A100的一侧形成第一金属布线材料层，第一金属布线材 料层包括依次层叠的钼铌合金材料层、铜金属材料层和钼铌合金材料层。然后，采用一掩膜板对第一金属布线材料层进行图案化操作，以便将第一金属布线材料层图案化为第一金属布线层。其中，第一金属布线层包括层叠的钼铌合金层、铜金属层和钼铌合金层。
在第一金属布线层远离衬底基板A100的一侧形成第二金属布线材料层，第二金属布线材料层包括依次层叠的钼铌合金材料层、铜金属材料层和钼铌合金材料层。然后，采用同一掩膜板对第二金属布线材料层进行图案化操作，以便将第二金属布线材料层图案化为第二金属布线层。其中，第二金属布线层包括层叠的钼铌合金层、铜金属层和钼铌合金层。
如此，金属布线层A200包括层叠的第一金属布线层和第二金属布线层，且第一金属布线层和第二金属布线层的图案相同。整体上，金属布线层A200包括依次层叠的钼铌合金层、铜金属层、钼铌合金层、钼铌合金层、铜金属层、钼铌合金层。这可以增大金属布线层A200的厚度，降低金属布线层A200的阻抗，满足阵列基板的电学要求。
再举例而言，在另一些实施方式中，可以通过如下方法制备金属布线层A200：
步骤AS210，在衬底基板A100的一侧溅射形成种子金属材料层；
步骤AS220，在种子金属材料层远离衬底基板A100的表面形成一层图案限定层，图案限定层的材料为可去除的绝缘材料，且图案限定层形成有暴露种子金属材料层的多个图案化的开口；
步骤AS230，采用电镀铜的方法在图案限定层的开口内形成铜生长材料层；
步骤AS240，去除图案限定层；
步骤AS250，采用刻蚀的方法，去除种子金属材料层未被铜生长材料层覆盖的部分，使得种子金属材料层被图案化为种子金属层；在刻蚀的过程中，无需对铜生长材料层进行保护，因此铜生长材料层的表面被部分刻蚀，生成铜生长层。
在步骤AS210中，种子金属材料层可以包括第二铜金属材料层，第二铜金属材料层的厚度不大于1微米。优选地，第二铜金属材料层的厚度为2500～3500埃。示例性地，第二铜金属材料层的厚度为3000埃。该第二 铜金属材料层经过图案化处理后，形成第二铜金属层。如此，在所制备的阵列基板中，种子金属层可以包括第二铜金属层。
可选的，种子金属材料层还可以包括位于第二铜金属材料层靠近衬底基板A100的表面的第三粘附材料层，第三粘附材料层的材料可以为钼、钼铜合金、钼铌合金、钼铜铌合金或者其他金属或者金属合金。该第二粘附材料层经过图案化处理后，形成第三粘附层。如此，在所制备的阵列基板中，种子金属层可以包括依次层叠于衬底基板A100一侧的第三粘附层和第二铜金属层。优选地，第三粘附层的材料为钼铌合金，厚度为250～350埃。示例性地，第三粘附层的厚度为300埃。
在步骤AS220中，图案限定层的材料可以为有机绝缘材料，例如可以为光敏树脂；也可以为无机材料，例如可以为氧化硅等材料。优选地，图案限定层的材料为光刻胶。
在步骤AS220和步骤AS230中，图案限定层的厚度可以根据铜生长材料层的厚度确定，使得图案限定层的厚度大于铜生长材料层的厚度。铜生长材料层的厚度可以根据阵列基板对金属布线层A200的电阻要求确定。金属布线层A200要求电阻越低，则铜生长材料层的厚度可以越大。可选地，在步骤AS250中，所形成的铜生长层的厚度为1.5～10微米。如此，金属布线层A200可以仅仅设置一层金属引线，无需设置多层层叠的金属引线以降低阻抗，这可以减少阵列基板的制备工序和掩膜板数量，降低阵列基板的成本。可以通过电镀或者化学镀的方法形成铜生长层。
示例性地，在本实施例的一种实施方式中，图案限定层的厚度为7.5微米，铜生长材料层的厚度为6.3微米。示例性地，在本实施例的另一种实施方式中，图案限定层的厚度为3～4微米，铜生长材料层的厚度为2.1微米。
可选地，在该实施方式中，阵列基板的制备方法还可以包括：在形成第一平坦化层A300之前，在金属布线层A200远离衬底基板A100的表面形成钝化层，以保护金属布线层A200。钝化层的材料可以为氧化硅、氮化硅、氮氧化硅等无机绝缘材料。如此，所制备的阵列基板中，在金属布线层A200和第一平坦化层A300之间设置有钝化层。
示例性地，钝化层的材料为氮化硅，钝化层的厚度为900～1100埃。
再举例而言，在另一些实施方式中，可以通过如下方法制备金属布线 层A200：
按照步骤AS210～步骤AS250所示的方法制备种子金属层、铜生长层，然后通过电镀或者化学镀的方法形成第二铜镍合金层。其中，第二铜镍合金层覆盖铜生长层远离衬底基板A100的表面和侧面，还可以覆盖种子金属层的部分或者全部侧面。如此，第二铜镍合金层可以保护种子金属层和铜生长层，避免种子金属层和铜生长层在烘烤工艺中氧化。如此，所制备的金属布线层A200包括依次层叠于衬底基板A100的一侧的种子金属层、铜生长层和第二铜镍合金层，其中，第二铜镍合金层覆盖铜生长层远离衬底基板A100的表面和侧面、种子金属层的部分或者全部侧面。
优选地，第二铜镍合金层中，镍的质量含量不小于30％。如此，可以保证第二铜镍合金层具有优异的抗氧化效果，并可以避免高镍含量的铜镍合金在刻蚀时所产生的各种问题。进一步地，镍的质量含量大于80％。
优选地，第二铜镍合金层的厚度为500～2000埃，以保证第二铜镍合金层具有优异的抗氧化效果，并可以避免高厚度的铜镍合金在刻蚀时所产生的各种问题。
优选地，可以先用钯盐的溶液处理种子金属层和铜生长层，形成一覆盖铜生长层远离衬底基板A100的表面和侧面、种子金属层的至少部分侧面的钯活化层；然后，再用包含有铜盐、镍盐、还原剂、络合剂、pH调节剂的化学镀液处理钯活化层，在钯活化层远离衬底基板A100的表面形成第二铜镍合金层。
在该实施方式中，在形成金属布线层A200后，可以在步骤AS130中形成第一平坦化层A300，无需额外设置钝化层。如此，不仅可以提高对金属布线层A200中的铜的抗氧化保护，而且可以减少钝化层的沉积、刻蚀等步骤，提高阵列基板的品质并降低阵列基板的成本。
在步骤AS130中，参见图7，可以在金属布线层A200远离衬底基板A100的一侧形成第一平坦化层A300。第一平坦化层A300的材料可以为有机材料，例如可以为光敏树脂。
可选的，第一平坦化层A300的厚度为3～7微米。优选地，第一平坦化层A300的厚度为4.5～5.5微米。
第一平坦化层A300上可以设置有过孔，以便电极层A400与金属布 线层A200电连接。举例而言，第一平坦化层A300可以设置有第一过孔和第二过孔，第一过孔和第二过孔均暴露至少部分金属布线层A200。电极层A400包括有连接电极和绑定焊盘，其中，至少部分连接电极通过第一过孔与金属布线层A200电连接，绑定焊盘通过第二过孔与金属布线层A200电连接。绑定焊盘用于与电路板(例如柔性电路板)或者驱动芯片电连接，至少部分连接电极用于与功能器件电连接。
在步骤AS140中，可以在第一平坦化层A300远离衬底基板A100的一侧形成电极层A400。其中，电极层A400包括依次层叠于衬底基板A100一侧的铜电极层A410、第一缓冲金属层A420和第一铜镍合金层A430。其中，第一缓冲金属层A420和第一铜镍合金层A430作共同作为电极保护层，用于保护铜电极层A410，避免铜电极层A410的表面氧化，并提高电极层A400与功能器件层A600之间的粘附力，尤其是提高电极层A400与焊锡层之间的粘附力，避免功能器件A610剥落。第一缓冲金属层A420还可以增加铜电极层A410和第一铜镍合金层A430之间的粘附力。
可选的，在形成电极层A400时，可以先形成铜电极层A410，然后再形成覆盖铜电极层A410的第一缓冲金属层A420和第一铜镍合金层A430；也可以在同一刻蚀过程中形成依次层叠的铜电极层A410、第一缓冲金属层A420和第一铜镍合金层A430。
在一些实施方式中，在第一平坦化层A300远离衬底基板A100的一侧形成电极层A400包括如下步骤：
步骤AS310，参见图8，在第一平坦化层A300远离衬底基板A100的一侧形成铜电极材料层A411(作为金属子材料层)；
步骤AS320，参见图9，对铜电极材料层A411进行图案化操作，形成铜电极层A410(作为金属子层)；
步骤AS330，参见图10，在铜电极层A410远离衬底基板A100的一侧依次形成第一缓冲金属材料层A421和第一铜镍合金材料层A431(作为导电子材料层)；
步骤AS340，参见图11，对第一缓冲金属材料层A421和第一铜镍合金材料层A431进行图案化操作，以形成第一缓冲金属层A420和第一铜镍合金层A430(作为导电子层)；其中，铜电极层A410在衬底基板A100 上的正投影，位于第一缓冲金属层A420在衬底基板A100上的正投影内。
在步骤AS310中，可以通过溅射的方法形成铜电极材料层A411，该铜电极材料层A411的厚度可以根据需求确定，例如可以为2500埃～5000埃。优选地，铜电极材料层A411的厚度可以为3000埃。
在步骤AS320中，可以通过光刻工艺对铜电极材料层A411进行图案化操作，图案化的铜电极材料层A411成为铜电极层A410。
示例性地，在本实施例的一种实施方式中，可以通过如下步骤对铜电极材料层A411进行图案化操作：在铜电极材料层A411远离衬底基板A100的表面形成第一正性光刻胶层；采用掩膜板，在第一曝光强度下对第一正性光刻胶层进行曝光；第一正性光刻胶层进行显影；刻蚀铜电极材料层A411以形成铜电极层A410；去除第一正性光刻胶层。
可选地，在本实施例的一种实施方式中，参见图8，在步骤AS310中，在形成铜电极材料层A411之前，还可以先在第一平坦化层A300远离衬底基板A100的一侧形成第二缓冲金属材料层A441，然后再在第二缓冲金属材料层A441远离衬底基板A100的表面形成铜电极材料层A411。其中，第二缓冲金属材料层A441的材料为钼、钼铌合金、钼钨合金、钼镍钛合金、钼镁铝合金中的一种或者多种的混合。在步骤AS320中，在对铜电极材料层A411进行图案化操作时，第二缓冲金属材料层A441也可以被同步地图案化，形成第二缓冲金属层A440。在刻蚀过程中，尽管第二缓冲金属材料层A441的材料本身刻蚀困难，但是由于其与铜电极材料层A411接触且同步刻蚀，因此两者之间会产生电子化学效应，第二缓冲金属材料层A441上的电子会向铜电极材料层A411转移而增大第二缓冲金属材料层A441的刻蚀速度。由此，第二缓冲金属材料层A441和铜电极材料层A411可以保持同步刻蚀，并使得第二缓冲金属层A440远离衬底基板A100的表面与铜电极层A410靠近衬底基板A100的表面基本重合。如此，本实施例所制备的阵列基板中，电极层A400可以包括依次层叠于第一平坦化层A300远离衬底基板A100的一侧的第二缓冲金属层A440、铜电极层A410、第一缓冲金属层A420和第一铜镍合金层A430。
在步骤AS330中，参见图10，可以通过溅射的方法在铜电极层A410远离衬底基板A100的表面依次形成第一缓冲金属材料层A421和第一铜 镍合金材料层A431。可选地，第一缓冲金属材料层A421的厚度为100～500埃；优选地，第一缓冲金属材料层A421的厚度为200～500埃。可选地，第一铜镍合金材料层A431的厚度为200～1000埃；优选地，第一铜镍合金材料层A431的厚度为500～1000埃。优选地，第一缓冲金属材料层A421的材料为钼铌合金。如此，所形成的第一缓冲金属层A420的材料为钼铌合金。
在步骤AS340中，可以通过光刻工艺对第一缓冲金属材料层A421和第一铜镍合金材料层A431进行图案化操作，形成第一缓冲金属层A420和第一铜镍合金层A430。在刻蚀的过程中，第一缓冲金属材料层A421和第一铜镍合金材料层A431的刻蚀速率相近，因此第一铜镍合金材料层A431不会形成屋顶结构。图17为刻蚀后形成的第一缓冲金属层A420和第一铜镍合金层A430的电镜图。根据图17可以看出，第一缓冲金属层A420远离衬底基板A100的表面与第一铜镍合金层A430靠近衬底基板A100的表面基本重合。其中，可以使得铜电极层A410在衬底基板A100上的正投影，位于第一缓冲金属层A420在衬底基板A100上的正投影内。如此，第一缓冲金属层A420覆盖铜电极层A410远离衬底基板A100的表面和铜电极层A410的侧面，第一铜镍合金层A430也相应地覆盖铜电极层A410远离衬底基板A100的表面和铜电极层A410的侧面；即铜电极层A410在衬底基板A100上的正投影，也位于第一铜镍合金层A430在衬底基板A100上的正投影内
如此，在该实施方式中，阵列基板的电极层A400中，第一缓冲金属层A420和第一铜镍合金层A430覆盖铜电极层A410的侧面和铜电极层A410远离衬底基板A100的表面。这使得第一铜镍合金层A430可以有效地保护铜电极层A410，避免铜电极层A410被氧化。不仅如此，由于第一缓冲金属材料层A421和第一铜镍合金材料层A431的刻蚀速率相近，可以避免第一铜镍合金层A430出现屋顶结构而降低阵列基板的品质。
示例性地，在步骤AS340中，可以通过如下方法对第一缓冲金属材料层A421和第一铜镍合金材料层A431进行图案化操作：可以在第一铜镍合金材料层A431远离衬底基板A100的表面形成第二正性光刻胶层；采用掩膜板，在第二曝光强度下对第二正性光刻胶层进行曝光，其中，第二 曝光强度小于第一曝光强度；第二正性光刻胶层进行显影；刻蚀第一缓冲金属材料层A421和第一铜镍合金材料层A431，以形成第一缓冲金属层A420和第一铜镍合金层A430；去除第二正性光刻胶层。其中，步骤AS340和步骤AS320可以采用同一掩膜板，以减少掩模板的数量并降低阵列基板的制备成本。
由于采用同一掩膜板，且在步骤AS340中采用较弱的曝光强度，因此步骤AS340中显影后的第二正性光刻胶层的图案大于步骤AS320中显影后的第一正性光刻胶层的图案，且显影后的第一正性光刻胶层的图案完全位于显影后的第二正性光刻胶层的图案内。这可以保证第一缓冲金属层A420能够包覆铜电极层A410。
优选地，为了保证步骤AS320和步骤AS340能够共用同一掩膜板，可以使得铜金属层在衬底基板A100上的正投影的边缘，与第一金属缓冲层在衬底基板A100上的正投影的边缘之间的距离的最小值不小于1.5微米。换言之，参见图11，对于电极层A400的任意一个子结构，例如任意一个焊盘、连接电极或者其他位于电极层A400的子结构，该子结构中的第一缓冲金属层A420部分的FICD(Final Insection Critical Dimension，最终关键尺寸)d1比该子结构的铜电极层A410部分的FICD d2要大至少3微米。
在另外一些实施方式中，在第一平坦化层A300远离衬底基板A100的一侧形成电极层A400包括如下步骤：
步骤AS410，参见图13，在第一平坦化层A300远离衬底基板A100的一侧依次形成铜电极材料层A411、第一缓冲金属材料层A421和第一铜镍合金材料层A431；
步骤AS420，在第一铜镍合金材料层A431远离衬底基板A100的一侧形成光刻胶层；
步骤AS430，对光刻胶层进行曝光和显影；
步骤AS440，参见图14，刻蚀铜电极材料层A411、第一缓冲金属材料层A421和第一铜镍合金材料层A431，以形成铜电极层A410、第一缓冲金属层A420和第一铜镍合金层A430；
步骤AS450，去除光刻胶层。
在步骤AS410中，可以采用溅射的方法依次形成铜电极材料层A411、第一缓冲金属材料层A421和第一铜镍合金材料层A431。可选地，第一缓冲金属材料层A421的厚度为200～500埃。可选地，第一铜镍合金材料层A431的厚度为500～1000埃。优选地，第一缓冲金属材料层A421的材料为钼铌合金。如此，所形成的第一缓冲金属层A420的材料为钼铌合金。
可选地，在本实施例的一种实施方式中，在形成铜电极材料层A411之前，还可以在第一平坦化层A300远离衬底基板A100的一侧形成第二缓冲金属材料层A441；然后，在第二缓冲金属材料层A441远离衬底基板A100的一侧形成铜电极材料层A411。如此，该第二缓冲金属材料层A441可以在步骤AS440中与铜电极材料层A411同步刻蚀，被图案化为第二缓冲金属层A440；则所制备的阵列基板中，电极层A400可以包括依次层叠的第二缓冲金属层A440、铜电极层A410、第一缓冲金属层A420和第一铜镍合金层A430。其中，第二缓冲金属层A440的材料为钼、钼铌合金、钼钨合金、钼镍钛合金、钼镁铝合金中的一种或者多种的混合。
在步骤AS440中，可以同时对铜电极材料层A411、第一缓冲金属材料层A421和第一铜镍合金材料层A431进行刻蚀，并进而形成没有屋顶结构的电极层A400。在该步骤中，尽管第一缓冲金属材料层A421和第一铜镍合金材料层A431在没有铜金属材料层时的刻蚀速率小于铜金属材料层的刻蚀速率，但是，当第一缓冲金属材料层A421夹设于铜金属材料层和第一铜镍合金材料层A431之间时，铜金属材料层可以与第一缓冲金属材料层A421和第一铜镍合金材料层A431产生电子化学效应。在刻蚀时，第一缓冲金属材料层A421上的电子可以转移至铜金属材料层，进而使得第一缓冲金属材料层A421的刻蚀速率增加；第一铜镍合金材料层A431上的电子可以转移至铜金属材料层，进而使得第一铜镍合金材料层A431的刻蚀速率增加。最终，铜电极材料层A411、第一缓冲金属材料层A421和第一铜镍合金材料层A431可以保持基本同步的刻蚀。这不仅克服了铜镍合金层与铜金属层同时刻蚀时容易产生屋顶结构的缺陷，而且克服了铜镍合金层刻蚀速率过慢的缺陷，最终可以改善电极层A400的形貌和提高电极层A400的制备速率，提高阵列基板的品质并降低阵列基板的成本。
图16为根据步骤AS440的方法所制备的电极层A400的电镜图。参 见图16，铜电极层A410远离衬底基板A100的表面可以与第一缓冲金属层A420靠近衬底基板A100的表面基本重合；第一缓冲金属层A420远离衬底基板A100的表面可以与第一铜镍合金层A430靠近衬底基板A100的表面基本重合。当电极层A400还包括第二缓冲金属层A440时，该第二缓冲金属层A440远离衬底基板A100的表面可以与铜电极层A410靠近衬底基板A100的表面基本重合。在图16中可以看出，尽管铜电极材料层A411、第一缓冲金属材料层A421和第一铜镍合金材料层A431进行同时刻蚀，但是并没有产生屋顶结构。
因此，在本实施例提供的阵列基板的制备方法，可以采用铜刻蚀液同时刻蚀第一铜镍合金材料层A431和铜电极材料层A411，且所形成的结构无屋顶结构，因此可以无需开发新的刻蚀液，不仅降低了阵列基板的制备成本，而且可以节省研发新的刻蚀液的时间，最终降低阵列基板的成本。不仅如此，该阵列基板还无需在柔性电路板绑定区设置ITO(氧化铟锌)层以改善与柔性电路板的粘附力并提高抗氧化效果，可以减少阵列基板的制备工序和制备成本。
在步骤AS150中，参见图12和图15，可以在电极层A400远离衬底基板A100的一侧形成第二平坦化层A500。第二平坦化层A500可以形成有多个过孔以暴露部分电极层A400，以便暴露的电极层A400与功能器件A610电连接。在一些实施方式中，暴露的电极层A400与电路板或者驱动芯片电连接。举例而言，电极层包括连接电极和绑定焊盘；连接电极包括绑定区和连接区。第二平坦化层A500可以具有第三过孔和第四过孔。其中，第三过孔可以暴露连接电极的绑定区，以便功能器件通过第三过孔与连接电极电连接；第四过孔可以暴露绑定焊盘，以便电路板或者驱动芯片通过第四过孔与绑定焊盘电连接。
可以理解的是，连接电极被第三过孔暴露的绑定区部分，可以作为器件焊盘；连接电极未被第三过孔和第四过孔暴露的部分，例如被第二平坦化层覆盖的部分，可以作为连接走线。如此，连接电极可以根据位置和功能，分为器件焊盘和连接走线。其中，对于任意一个连接电极，其既可以仅仅包括器件焊盘或者连接走线，也可以包括电连接的器件焊盘和连接走线。其中，至少部分连接走线可以与金属布线层连接，至少部分连接走线 可以与器件焊盘连接。当然的，在一些实施方式中，部分连接走线可以连接不同的器件焊盘，以使得多个器件焊盘相互电连接，至少部分连接走线可以同时器件焊盘和金属布线层以使得功能器件与金属布线层电连接。
由于电极层A400设置有第一铜镍合金层A430，因此无需担心铜电极层A410会被氧化，所以无需在电极层A400远离层基板的一侧设置钝化层(氮化硅层等用于保护电极层的无机保护层)，避免钝化层覆盖第一平坦化层A300而导致第一平坦化层A300鼓泡的问题。如此，不仅可以节省沉积钝化层、刻蚀钝化层等工序，提高阵列基板的生产节拍以提高产能和降低成本，而且可以提高阵列基板的品质。
可选地，在一些实施方式中，可以通过丝网印刷的方法形成第二平坦化层A500。如此，可以减少掩膜板的数量并降低阵列基板的制备成本。具体的，可以通过丝网印刷的方式涂覆白油以形成第二平坦化层B500。其中，白油包括可光固化的树脂或者可光固化的单体，以及分散于树脂中的二氧化钛颗粒。可选地，可光固化的单体可以包括但不限于丙烯酸酯类单体。
在步骤AS160中，参见图12和图15，可以在保护层远离衬底基板A100的一侧设置功能器件层A600。功能器件层A600可以包含有阵列分布的功能器件A610，例如包括用于发光的发光器件、用于发出超声波的超声波发射器件、用于产生热量的加热器件或者其他电流驱动的功能器件A610，还可以包括用于驱动或者控制的微芯片、用于感测亮度或者温度的传感器等。
在本公开的一种实施方式中，功能器件A610可以为微发光二极管(Micro LED)或者迷你发光二极管(Mini LED)；可以通过巨量转移技术和绑定工艺，将功能器件A610连接至电极层A400。进一步地，功能器件A610可以通过焊锡层A700与电极层A400电连接，焊锡层A700可以包括锡和铟。示例性的，可以通过印刷锡焊、固晶、回流焊等工序，实现将功能器件A610连接于电极层A400。
在本公开的另一种实施方式中，部分功能器件可以为微发光二极管(Micro LED)或者迷你发光二极管(Mini LED)；部分功能器件可以为用于控制一个或者多个发光二极管的微芯片。在微芯片的控制下，微芯片 所控制的发光二极管受控的发光或者不发光。
需要说明的是，尽管在附图中以特定顺序描述了本实施例中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本实施例的一部分。
本实施例还提供一种阵列基板，参见图12和图15，阵列基板包括：
衬底基板A100；
金属布线层A200，设于衬底基板A100的一侧；
第一平坦化层A300，设于金属布线层A200远离衬底基板A100的一侧；
电极层A400，设于第一平坦化层A300远离衬底基板A100的一侧；电极层A400包括依次层叠于衬底基板A100一侧的铜电极层A410、第一缓冲金属层A420和第一铜镍合金层A430；第一缓冲金属层A420的材料为钼、钼铌合金、钼钨合金、钼镍钛合金、钼镁铝合金中的一种或者多种的混合；
第二平坦化层A500，设于电极层A400远离衬底基板A100的一侧；
功能器件层A600，设于第二平坦化层A500远离衬底基板A100的一侧，且包括多个与电极层A400电连接的功能器件A610。
本实施例提供的阵列基板，能够采用本实施例上述阵列基板的制备方法实施方式所描述的阵列基板的制备方法进行制备，因此具有相同或者类似的有益效果，本实施例在此不再赘述。
在本实施例的一种实施方式中，电极层A400还包括位于铜电极层A410靠近衬底基板A100的表面的第二缓冲金属层A440。
在本实施例的一种实施方式中，第一缓冲金属层A420和第一铜镍合金层A430覆盖铜电极层A410的侧面和铜电极层A410远离衬底基板A100的表面。
在本实施例的一种实施方式中，第一铜镍合金层A430在铜电极层A410上的正投影，位于铜电极层A410内。
在本实施例的一种实施方式中，第一缓冲金属层A420的厚度为 100～500埃。优选地，第一缓冲金属层A420的厚度为200～500埃。
在本实施例的一种实施方式中，第一铜镍合金层A430的厚度为200～1000埃。优选地，第一铜镍合金层A430的厚度为500～1000埃。
在本实施例的一种实施方式中，第一铜镍合金层A430中，镍的质量含量大于20％。优选地，第一铜镍合金层A430中，镍的质量含量为30％～80％。
本实施例提供的阵列基板的其他细节和效果已经记载于上述阵列基板的制备方法实施方式中，或者根据上述阵列基板的制备方法实施方式的记载可以明确推导出来，本实施例在此不再赘述。
本实施例实施方式还提供一种显示面板，该显示面板包括上述阵列基板实施方式所描述的任意一种阵列基板；其中，阵列基板的功能器件A610为微发光二极管或者迷你发光二极管。该显示面板可以为手机屏幕、电视机屏幕、智能手表屏幕、电子画屏、电子广告牌或者其他类型的显示面板。由于该显示面板具有上述阵列基板实施方式所描述的任意一种阵列基板，因此具有相同的有益效果，本实施例在此不再赘述。优选的，该阵列基板上的功能器件A610包括多种不同颜色的微发光二极管或者迷你发光二极管，例如包括红色微发光二极管或者迷你发光二极管、蓝色微发光二极管或者迷你发光二极管和蓝色微发光二极管或者迷你发光二极管。
本实施例还提供一种背光模组，该背光模组包括上述阵列基板实施方式所描述的任意一种阵列基板；其中，阵列基板的功能器件A610为微发光二极管或者迷你发光二极管。该背光模组可以为手机屏幕的背光模组、电视机屏幕的背光模组、电脑屏幕的背光模组或者其他类型的液晶显示面板的背光模组。由于该背光模组具有上述阵列基板实施方式所描述的任意一种阵列基板，因此具有相同的有益效果，本实施例在此不再赘述。
实施例二
发明人发现，可以通过在第二铜金属层的表面覆盖铜镍合金层提高第二铜金属层的抗氧化能力。铜镍合金的厚度不超过500埃，镍的质量含量不超过20％。这是由于，铜镍合金的刻蚀速率低于铜的刻蚀速度，且镍含量越高则刻蚀速度越慢。由于铜镍合金和铜之间刻蚀速率的不同，在刻蚀 层叠的铜金属层和铜镍合金层时，铜镍合金层通常会残留有屋顶结构(Tip结构)；且镍的含量越高，该屋顶结构越大；铜镍合金层的厚度越大，则刻蚀速率越慢，屋顶结构越大。该屋顶结构在阵列基板的使用过程中，可能会发生坍塌等，进而导致阵列基板出现不良，严重影响阵列基板的产品化，降低了阵列基板的品质。
示例性地，图18-1为在玻璃基板上依次沉积的铜镍合金层(500埃)、铜层(6000埃)和铜镍合金层(500埃)的电镜图，其中，铜镍合金层中镍的质量含量为20％；图18-2为上述金属层刻蚀后的电镜图，该电镜图中可以明显观察到铜镍合金层形成有屋顶结构，屋顶结构的尺寸为0.1微米。图19-1为在玻璃基板上依次沉积的铜镍合金层(500埃)、铜层(6000埃)和铜镍合金层(500埃)的电镜图，其中，铜镍合金层中镍的质量含量为30％；图19-2为上述金属层刻蚀后的电镜图，该电镜图中可以明显观察到铜镍合金层形成有屋顶结构，屋顶结构的尺寸为0.15微米。比较图18-2和图19-2可以明确知晓，铜镍合金层中镍的质量含量越大，刻蚀中形成的屋顶结构的尺寸越大，对阵列基板的品质的影响越大。
在相关技术中，铜镍合金层中的镍含量一般为10％，以尽量改善其刻蚀后的形貌。然而，这类铜镍合金层对铜金属层的保护效果较差。图20为采用镍的质量含量为10％的铜镍合金层保护铜金条时，在高温烘烤后的照片。在该照片中，铜金属条的颜色越亮(例如图20中所示的EE位置)，则其表面的氧化程度越低；铜金属条的颜色越暗(例如图20中所示的DD位置)，则其表面的氧化程度越高。根据图20可以看出，当采用镍的质量含量为10％的铜镍合金层保护铜金属时，铜金属在高温下发生了明显的氧化变黑(如图20中DD位置所示)的现象。
发明人在测试中发现，铜镍合金中的镍含量越大，其对铜金属的保护效果越好。示例性地，图21给出了镍的质量含量为20％的铜镍金属层(500埃)覆盖的铜金属层(6000埃)在退火前、150℃空气氛围中退火两小时、250℃氮气氛围中退火30分钟三种不同情形下的图片；图片中的小黑点，为铜金属层发生氧化变黑的位置。图22给出了镍的质量含量为35％的铜镍金属层(500埃)覆盖的铜金属层(6000埃)在退火前、150℃空气氛围中退火两小时、250℃氮气氛围中退火30分钟三种不同情形下的图片； 图片中的小黑点，为铜金属层发生氧化变黑的位置。比较图21和图22可以看出，铜镍金属层中的镍含量越高，铜金属层越不容易发生氧化。
基于上述发现，本实施例提供了一种阵列基板及其制备方法，如图23所示，该阵列基板的制备方法包括：
步骤BS110，如图24所示，提供衬底基板B100；
步骤BS120，如图24所示，在衬底基板B100的一侧形成金属布线层B200；
步骤BS130，如图25和图26所示，在金属布线层B200远离衬底基板B100的一侧形成第一平坦化层B300；
步骤BS140，如图27和图28所示，在第一平坦化层B300远离衬底基板B100的一侧形成铜电极层B420(作为金属子层)，铜电极层B420与金属布线层B200电连接；
步骤BS150，如图29和图30所示，形成钯金属层B430，钯金属层B430位于且覆盖铜电极层B420远离衬底基板B100的表面和铜电极层B420的侧面；
步骤BS160，如图31和图32所示，采用化学镀的方法形成第一铜镍合金层B440(作为导电子层)，第一铜镍合金层B440位于且覆盖钯金属层B430远离衬底基板B100的表面；
步骤BS170，如图35和图36所示，设置功能器件层B600；功能器件层B600设于第一铜镍合金层B440远离衬底基板B100的一侧，且包括多个与第一铜镍合金层B440电连接的功能器件B610。
根据本实施例提供的阵列基板的制备方法，可以采用化学镀的方法形成第一铜镍合金层B440，可以避免第一铜镍合金层B440出现屋顶结构，能够改善第一铜镍合金层B440的形貌，因此可以提高阵列基板的质量。
如图35和图36所示，根据本实施例提供的阵列基板的制备方法，所制备的阵列基板包括依次层叠于衬底基板B100一侧的金属布线层B200、第一平坦化层B300、电极层B400和功能器件层B600。其中，电极层B400与金属布线层B200电连接；电极层B400包括依次层叠的铜电极层B420、钯金属层B430和第一铜镍合金层B440；其中，钯金属层B430位于且覆盖铜电极层B420远离衬底基板B100的表面和铜电极层B420的侧面；第 一铜镍合金层B440位于且覆盖钯金属层B430远离衬底基板B100的表面；功能器件层B600包括多个与电极层B400电连接的功能器件B610。该阵列基板可以通过上述的阵列基板的制备方法进行制备，因此其第一铜镍合金层B440不会出现屋顶结构，可以避免屋顶结构断裂而导致的不良，提高阵列基板的良率和质量。
下面，结合附图对本实施例提供的阵列基板的制备方法的各个步骤的原理、细节和效果做进一步地解释和说明。
本实施例中，任意一个膜层可以包括侧面、靠近衬底基板的表面和远离衬底基板的表面，其中，靠近衬底基板的表面和远离衬底基板的表面通过膜层的侧面连接。在本实施例中，任意一个膜层的厚度为，该膜层在垂直于衬底基板方向的尺寸。
在步骤BS110中，如图24所示，可以提供一衬底基板B100。本实施例二中的衬底基板B100可以与实施例一种的衬底基板A100的结构、材料等相同，本公开在此不再赘述。
可选地，在形成金属布线层B200之前，在衬底基板B100的一侧形成一绝缘缓冲层，例如形成一层氮化硅层、氧化硅层或者氮氧化硅层；然后，在该绝缘缓冲层远离衬底基板B100的一侧形成金属布线层B200。
优选地，衬底基板B100的材料为玻璃。
在步骤BS120中，如图24所示，可以在衬底基板B100的一侧形成金属布线层B200。金属布线层B200可以包括金属引线，金属引线可以通过电极层B400驱动各个功能器件B610。可以通过沉积和图案化的方法形成金属布线层B200，其中，沉积的方法包括但不限于溅射、电镀和化学镀，图案化的方法包括但不限于光刻、在图案化的种子层上生长出图案化的生长层、在图案限定层的限定下生长出图案化的金属图案等。
可选地，可以采用实施例一中所描述的任意一种形成金属布线层A200的方法，来形成本实施例二中的金属布线层B200；本实施例二对这些形成金属布线层的各种方法不再一一详述。
在步骤BS130中，如图25和图26所示，可以在金属布线层B200远离衬底基板B100的一侧形成第一平坦化层B300。第一平坦化层B300的材料可以为有机材料，例如可以为光敏树脂。
可选的，第一平坦化层B300的厚度为3～7微米。优选地，第一平坦化层B300的厚度为4.5～5.5微米。
可以理解的是，第一平坦化层B300上可以设置有过孔，以便电极层B400与金属布线层B200电连接。
可选地，在一些实施方式中，阵列基板的制备方法还可以包括：如图26所示，在形成第一平坦化层B300之前，在金属布线层B200远离衬底基板B100的表面形成钝化层B210，以保护金属布线层B200。钝化层B210的材料可以为氧化硅、氮化硅、氮氧化硅等无机绝缘材料。如此，所制备的阵列基板中，在金属布线层B200和第一平坦化层B300之间设置有钝化层B210。
示例性地，钝化层B210的材料为氮化硅，钝化层B210的厚度为900～1100埃。
在步骤BS140中，如图27和图28所示，可以在第一平坦化层B300远离衬底基板B100的一侧形成铜电极层B420，铜电极层B420与金属布线层B200电连接。
可选的，可以通过溅射的方法形成一层铜电极材料层(作为金属子材料层)，然后对铜电极材料层进行图案化操作，以形成铜电极层B420(作为金属子层)。铜电极层B420的厚度可以为2500～3500埃。示例性地，铜电极层B420的厚度为3000埃。
可选地，在步骤BS140中还可以包括：如图27和图28所示，在形成铜电极层B420时，还形成位于铜电极层B420靠近衬底基板B100的表面的第二缓冲金属层B410。第二缓冲金属层B410的材料可以为钼、钼铜合金、钼铌合金、钼铜铌合金或者其他金属或者金属合金。示例性地，第二缓冲金属层B410的材料为钼铌合金，厚度为250～350埃。示例性地，第二缓冲金属层B410的厚度为300埃。可以理解的是，第二缓冲金属层B410可以提高铜电极层与第一平坦化层B300之间的结合强度，并实现对铜电极层的保护；因此，第二缓冲金属层B410还可以被称为金属粘附层、金属保护层等。
可选地，可以通过如下方法形成层叠的第二缓冲金属层B410和铜电极层B420：在第一平坦化层B300远离衬底基板B100的一侧形成层叠的 第二缓冲金属材料层和铜电极材料层，然后对第二缓冲金属材料层和铜电极材料层进行图案化操作，以形成第二缓冲金属层B410和铜电极层B420。可以理解的是，第二缓冲金属材料层可以提高铜电极材料层与第一平坦化层B300之间的结合强度，并实现对铜电极材料层的保护；因此，第二缓冲金属材料层还可以被称为金属粘附材料层、金属保护材料层等。
在步骤BS150中，如图29和图30所示，可以形成钯金属层B430，钯金属层B430位于且覆盖铜电极层B420远离衬底基板B100的表面和铜电极层B420的侧面。
可选地，可以用钯盐的溶液处理铜电极层B420，在铜电极层B420远离衬底基板B100的表面和铜电极层B420的侧面形成钯金属层B430。
示例性地，可以将形成有铜电极层B420的基板浸入到氯化钯溶液中，使得铜电极层B420的远离衬底基板B100的表面和侧面均发生如下化学反应：
Pd 2++Cu＝Pd↓+Cu 2+
在该反应中，置换出的钯沉积在铜电极层B420的远离衬底基板B100的表面和侧面，形成钯金属层B430，钯金属层B430在后续的化学镀中起到活化铜电极层B420的作用。而基板未形成有铜电极层B420的区域没有钯被置换出来，因此这些区域没有钯金属层B430。如此，所形成的钯金属层B430位于且覆盖铜电极层B420远离衬底基板B100的表面和铜电极层B420的侧面，即钯金属层B430完全覆盖铜电极层B420远离衬底基板B100的表面和铜电极层B420的侧面，且不位于铜电极层B420以外的位置。换言之，钯金属层B430在衬底基板B100上的正投影，与铜电极层B420在衬底基板B100上的正投影重合。可以理解的是，钯金属层B430主要起到活化的作用，因此其还可以被称之为钯活化层、钯催化层等。钯金属层B430的厚度可以比较小，例如可以为几个或者几十个原子的厚度；当然的，钯金属层B430也可以具有较厚的厚度。
可以理解的是，当在铜电极层B420和第一平坦化层B300之间具有含有铜的第二缓冲金属层B410时，钯金属层B430还可以位于且覆盖第二缓冲金属层B410的侧面。即钯金属层B430在衬底基板B100上的正投影，与铜电极层B420和第二缓冲金属层B410在衬底基板B100上的总正 投影重合。当然地，钯金属层B430也可以不覆盖第二缓冲金属层B410。
可选地，形成钯金属层B430的方法可以与形成钯活化层的方法相同。
在步骤BS160中，如图31和图32所示，可以采用化学镀的方法形成第一铜镍合金层B440，第一铜镍合金层B440位于且覆盖钯金属层B430远离衬底基板B100的表面。
可选地，可以用包含有铜盐、镍盐、还原剂、络合剂、pH调节剂的化学镀液处理钯金属层B430，在钯金属层B430远离衬底基板B100的表面形成第一铜镍合金层B440。在钯金属层B430的附近，铜离子和镍离子与还原剂发生氧化还原反应，分别生成铜和镍并沉积于钯金属层B430的表面，形成第一铜镍合金层B440。
进一步地，铜盐可以为硫酸铜。镍盐可以为硫酸镍。还原剂可以为次磷酸钠。络合剂可以选自丙氨酸、甘氨酸、苹果酸、琥珀酸和柠檬酸中的一种或者多种。pH调节剂可以选自氢氧化钠或者氢氧化钾。
进一步地，化学镀液中还可以包括有稳定剂，例如包括有硼酸。
在本实施例的一种实施方式中，化学镀液的组分包括：硫酸铜0.06～0.10mol/L，硫酸镍0.02～0.04mol/L，次磷酸钠0.55～0.85mol/L，柠檬酸钠0.08～0.12mol/L，硼酸0.4～0.6mol/L，聚乙二醇80～120mg/L；化学镀液中还包括pH调节剂。
示例性地，化学镀液的组分包括：硫酸铜0.08mol/L，硫酸镍0.03mol/L，次磷酸钠0.7mol/L，柠檬酸钠0.1mol/L，硼酸0.5mol/L，聚乙二醇100mg/L。
当用该化学镀液处理钯金属层B430时，可以发生如下反应：
(1)铜沉积反应：
Figure PCTCN2021115688-appb-000001
(2)镍沉积反应：
Figure PCTCN2021115688-appb-000002
上述反应在钯金属层B430附近并在钯的促进下进行，在没有钯金属层B430的区域基本不发生上述反应。因此铜和镍沉积于钯金属层B430，形成第一铜镍合金层B440。
可选地，在处理钯金属层B430时，化学镀液的温度为75～85℃，处 理时间为20～40分钟。可以将生成有钯金属层B430的基板浸入化学镀液中进行反应。如此，第一铜镍合金层B440的厚度为500～2000埃，以保证第一铜镍合金层B440具有优异的抗氧化效果，并可以避免高厚度的铜镍合金在刻蚀时所产生的各种问题。
第一铜镍合金层B440的厚度越厚，对铜电极层B420的保护效果越好。
参见图37，当化学镀液的pH值不同时，第一铜镍合金层B440中的镍质量含量不同。可以通过pH调节剂调节化学镀液的pH值，进而调节第一铜镍合金层B440中的镍质量含量。可以理解是，学镀液学镀液中包括次磷酸根，在化学镀铜镍过程中，次磷酸根可以少量地被还原为磷单质而沉积在金属中，使得铜镍合金中含有少量的磷。
可选地，化学镀液的pH不小于8。如此，第一铜镍合金层B440中，镍的质量含量为不小于30％，这可以保证第一铜镍合金层B440具有优异的抗氧化效果，并可以避免高镍含量的铜镍合金在刻蚀时所产生的各种问题。
可选地，化学镀液的pH不大于10。如此，第一铜镍合金层B440中，镍的质量含量为不大于80％。
优选地，化学镀液的pH为8～10。如此，第一铜镍合金层B440中，镍的质量含量为30％～80％。第一铜镍合金层B440中的镍含量越高，则其防氧化效果越好。
根据本实施例提供的形成第一铜镍合金层B440的方法，可以采用化学镀的方法在铜电极层B420的侧面和远离衬底基板B100的表面形成铜镍合金，实现对铜电极层B420的全面保护。该方法只需要在现有的电镀设备的盛液槽中进行即可，无需额外投资新的设备，可以实现对设备的最大利用并降低制备成本。不仅如此，利用化学镀的方法形成第一铜镍合金层B440，可以提高第一铜镍合金层B440的厚度和镍的含量，实现更好的保护效果。不仅如此，由于无需通过刻蚀的方法形成第一铜镍合金层B440，因此第一铜镍合金层B440不会出现屋顶结构，可以提高阵列基板的质量。该第一铜镍合金层B440还可以提高功能器件B610的粘附强度，避免功能器件B610从电极层B400剥离。
可选地，第一铜镍合金层B440的制备方法和第二铜镍合金层的制备方法相同。
本实施例提供的阵列基板的制备方法，如图33和图34所示，在步骤BS170之前还可以包括：在电极层B400远离衬底基板B100的一侧形成第二平坦化层B500，第二平坦化层B500可以为有机材料，或者掺杂有无机材料的有机材料。该第二平坦化层B500可以暴露有电极层B400的部分区域，使得被暴露的部分作为绑定焊盘以与功能器件B610连接。当然地，电极层B400还可以形成有其他结构，例如还可以形成有用于与驱动芯片或者电路板连接的绑定焊盘等，本实施例对此不做限定。
在本实施例的一种实施方式中，可以通过丝网印刷的方法涂覆白油以形成第二平坦化层B500。其中，白油包括可光固化的树脂或者可光固化的单体，以及分散于树脂中的二氧化钛颗粒。可选地，可光固化的单体可以包括但不限于丙烯酸酯类单体。
在该实施方式中，由于第一铜镍合金层B440具有大的厚度和高的镍含量，因此其可以有效保护铜电极层B420，在电极层B400远离衬底基板B100的一侧无需额外设置钝化层和有机封装层以保护铜电极层B420，可以减少两个膜层和一次图案化工序，降低阵列基板的制备成本。
在步骤BS170中，如图35和图36所示，可以在第二平坦化层B500远离衬底基板B100的一侧设置功能器件层B600。功能器件层B600可以包含有阵列分布的功能器件B610，例如包括用于发光的发光器件(亦可以称为发光单元)、用于发出超声波的超声波发射器件、用于产生热量的加热器件或者其他电流驱动的功能器件B610。
可选地，功能器件B610可以为微发光二极管(Micro LED)或者迷你发光二极管(Mini LED)；可以通过巨量转移和绑定工艺完成功能器件B610与电极层B400的电连接。进一步地，功能器件B610可以通过焊锡层B700与电极层B400电连接，焊锡层可以包括锡和铟。示例性的，可以通过印刷锡焊、固晶、回流焊等工序，实现将功能器件B610连接于电极层B400。
需要说明的是，尽管在附图中以特定顺序描述了本实施例中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤， 或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本实施例的一部分。
参见图35和图36，本实施例还提供一种阵列基板，包括衬底基板B100、金属布线层B200、第一平坦化层B300、电极层B400和功能器件层B600；金属布线层B200设于衬底基板B100的一侧；第一平坦化层B300设于金属布线层B200远离衬底基板B100的一侧；电极层B400设于第一平坦化层B300远离衬底基板B100的一侧且与金属布线层B200电连接；电极层B400包括依次层叠的铜电极层B420、钯金属层B430和第一铜镍合金层B440；其中，钯金属层B430位于且覆盖铜电极层B420远离衬底基板B100的表面和铜电极层B420的侧面；第一铜镍合金层B440位于且覆盖钯金属层B430远离衬底基板B100的表面；功能器件层B600设于电极层B400远离衬底基板B100的一侧，包括多个与电极层B400电连接的功能器件B610。
本实施例提供的阵列基板，能够采用本实施例上述阵列基板的制备方法实施方式所描述的阵列基板的制备方法进行制备，因此具有相同或者类似的有益效果，本实施例在此不再赘述。
在本实施例的一种实施方式中，电极层B400还包括第二缓冲金属层B410，第二缓冲金属层B410设于铜电极层B420靠近衬底基板B100的表面。
在本实施例的一种实施方式中，第一铜镍合金层B440中，镍的质量含量不小于30％。
在本实施例的一种实施方式中，第一铜镍合金层B440中，镍的质量含量不大于80％。
在本实施例的一种实施方式中，第一铜镍合金层B440的厚度为500～2000埃。
在本实施例的一种实施方式中，金属布线层B200包括依次层叠于衬底基板B100的一侧的种子金属层、铜生长层和第二铜镍合金层。
在本实施例的一种实施方式中，金属布线层B200包括依次层叠于衬底基板B100的一侧的种子金属层和铜生长层；阵列基板还包括钝化层 B210，钝化层B210设于金属布线层B200和第一平坦化层B300之间。
本实施例提供的阵列基板的其他细节和效果已经记载于上述阵列基板的制备方法实施方式中，或者根据上述阵列基板的制备方法实施方式的记载可以明确推导出来，本实施例在此不再赘述。
本实施例实施方式还提供一种显示面板，该显示面板包括上述阵列基板实施方式所描述的任意一种阵列基板；其中，阵列基板的功能器件B610为微发光二极管或者迷你发光二极管。该显示面板可以为手机屏幕、电视机屏幕、智能手表屏幕、电子画屏、电子广告牌或者其他类型的显示面板。由于该显示面板具有上述阵列基板实施方式所描述的任意一种阵列基板，因此具有相同的有益效果，本实施例在此不再赘述。
本实施例实施方式还提供一种背光模组，该背光模组包括上述阵列基板实施方式所描述的任意一种阵列基板；其中，阵列基板的功能器件B610为微发光二极管或者迷你发光二极管。该背光模组可以为手机屏幕的背光模组、电视机屏幕的背光模组、电脑屏幕的背光模组或者其他类型的液晶显示面板的背光模组。由于该背光模组具有上述阵列基板实施方式所描述的任意一种阵列基板，因此具有相同的有益效果，本实施例在此不再赘述。
实施例三
Mini-LED(亚毫米发光二极管)是指尺寸在80～300um之间的发光二极管。在Mini-LED作为显示面板的像素点构成自发光显示器时，相比于小间距LED显示器，可以实现更高的像素密度。在Mini-LED作为光源应用在背光模组中时，可以通过更加密集的光源排布来制作超薄的光源模组；再配合区域调光技术，使得包括Mini-LED背光模组的显示屏将有更好的对比度和高动态光照渲染显示效果。而尺寸小于80um的micro LED微型发光二极管，可以直接作为近眼、穿戴、手持终端等显示面板的像素点。
本实施例中所述的阵列基板，可以指用作提供光源的基板，也可以指用于显示的基板，对比不做限定。因此，在本实施例中，阵列基板也可以被称为发光基板。
相关技术中，为了完成Mini/Micro LED与阵列基板的绑定，需要在 阵列基板上待与Mini/Micro LED电气连接的焊盘上设置锡膏，接着将Mini/Micro LED转移到阵列基板上对应的位置，然后在230℃-260℃的温度范围内通过回流焊方式完成Mini/Micro LED与阵列基板的固定。接着，在130℃-150℃的温度范围内使用热压方式将电路板绑定在阵列基板待与电路板电气连接的焊盘上。
发明人发现，由于绑定Mini/Micro LED和电路板到阵列基板需要使用不同的工艺条件，无法同步实现二者的绑定，因而在其中一者进行绑定时，与另外一者对应的阵列基板上的焊盘处的金属极易发生氧化，进而导致后续无法保证良好的电气连接，从而降低产品良率。
本实施例提供了一种阵列基板，阵列基板可以被配置为用于显示或提供背光，包括电路板绑定区和发光区。
参考图39和图43所示，电路板绑定区OA包括多个引脚焊盘C1，多个引脚焊盘用于与电路板绑定连接；多个引脚焊盘中的任一个包括层叠设置的第一金属子层C11和第一导电子层C12；第一金属子层的材料包括金属或者金属合金；第一导电子层具有抗氧化性、且覆盖第一金属子层。
发光区OB包括多个器件焊盘，多个器件焊盘用于与多个发光单元绑定连接。可以理解的是，在本公开的其他实施方式中，部分器件焊盘用于与发光单元(例如发光二极管)电连接，部分器件焊盘用于与驱动或者控制发光单元的微芯片电连接。
第一金属子层的材料包括金属，例如：铜、铝、钼、钛等。考虑到铜的电阻率低，导电性强，优选铜制作第一金属子层(例如作为实施例一中的铜电极层)；此时，第一导电子层的材料可以是金属氧化物或者金属合金，例如金属氧化物可以是氧化铟锌(IZO)或者氧化铟锡(ITO)。若第一金属子层的材料包括金属合金，例如：含钼的合金；此时，第一导电子层的材料可以是金属合金，示例的，该金属合金是含铜合金，例如含铜镍的合金(例如使得第一金属子层作为实施例一种的第一铜镍合金层)。第一导电子层具有抗氧化性和导电性，从而能够避免在制作阵列基板的过程中出现氧化的问题。从而第一导电子层可以起到保护第一金属子层的作用，避免在制作阵列基板的过程中第一金属子层发生氧化。
本实施例中，阵列基板可以为显示阵列基板或可以为背光阵列基板。若为显示阵列基板，则发光区OB构成显示区，以实现显示画面。若为背光阵列基板，则发光区OB用于提供光源。
这里对于阵列基板包括的发光区的发光颜色不做限定；发光区可以是红色发光区、绿色发光区或者蓝色发光区中的任一种。该阵列基板可以同时包括红色发光区、绿色发光区或者蓝色发光区三种发光颜色的发光区；当然，也可以仅包括一种发光颜色的发光区，例如：仅包括多个红色发光区，或者仅包括多个绿色发光区，或者仅包括多个蓝色发光区。具体可以根据实际要求确定。
多个发光区的控制方式不做限定，示例的，可以独立控制每个发光区，或者多个发光区被同时控制等。
本公开提供的实施例中，如图40和图44所示，阵列基板还可以包括衬底基板C7、以及形成在衬底基板C7之上的多个发光单元(位于功能器件层)，发光单元可以包括如图44或者图40所示的发光二极管C6。其中，衬底的材料可以是刚性材料，如玻璃；还或者是柔性材料，如聚酰亚胺。可以理解的是，在一些实施方式中，阵列基板还可以包括与发光单元同层设置的微芯片，微芯片用于控制发光单元。这样，发光单元和微芯片可以作为阵列基板的功能器件，功能器件层可以包括发光单元和微芯片。
需要说明的是，由于发光二极管包括阳极和阴极，因此一个发光二极管需要通过两个器件焊盘完成绑定。上述多个器件焊盘可以分为多组器件焊盘，每组器件焊盘用于绑定一个发光二极管，且包括成对设置的阴极焊盘和阳极焊盘，其中与发光二极管的阴极绑定的器件焊盘称为阴极焊盘，与发光二极管的阳极绑定的器件焊盘称为阳极焊盘。本实施例的附图中，为了明确区分阴极焊盘和阳极焊盘，采用不同标记说明，具体的，参考图38和图39所示，阴极焊盘标记为C2'，阳极焊盘标记为C2，但是两者包括的膜层结构相同。其中，器件焊盘可以与同层设置的连接走线连接，以便阵列基板通过连接走线向器件焊盘上绑定的功能器件加载电流或者电压。可以理解的是，在一些实施方式中，可以存在一部分连接走线不与器件焊盘电连接。
在本实施例的一种实施方式中，阵列基板包括层叠设置的衬底基板、金属布线层、第一平坦化层、电极层、第二平坦化层和功能器件层。其中，金属布线层设置有金属引线，电极层设置有上述的器件焊盘和连接走线。功能器件层设置有上述的发光单元，在某些情况下还可以包括微芯片。在一种可行方式中，引脚焊盘和器件焊盘同层设置，均位于电极层。在另一种可行方式中，引脚焊盘和器件焊盘分别设置于金属布线层和电极层。
其中，电极层与金属布线层之间通过贯穿第一平坦化层的过孔连接接。示例性地，引脚焊盘可以通过连接走线与金属引线电连接，或者引脚焊盘与金属引线直接电连接。再示例性地，连接走线可以包括第一连接走线和第二连接走线，第一连接走线可以连接两个器件焊盘，以使得功能器件之间电连接；第二连接走线可以连接金属引线和器件焊盘，以使得器件焊盘与金属引线电连接。在一些情形下，连接走线还可以包括第三连接走线，第三连接走线连接不同的金属引线，以利于金属布线层上的金属引线通过电极层跨接。第二平坦化层上可以设置有暴露器件焊盘的过孔，以利于功能器件与器件焊盘的绑定连接。第二平坦化层上还可以设置有暴露引脚焊盘的过孔，以利于引脚焊盘与电路板的引脚之间的绑定。
上述阵列基板中多个引脚焊盘和多个器件焊盘的分布结构和连接方式不做限定。示例的，参考图38所示，区域OA为电路板绑定区，区域OB为发光区，多个器件焊盘可以分为多组器件焊盘，每组器件焊盘用于绑定一个发光二极管、且包括成对设置的阴极焊盘C2’和阳极焊盘C2。相邻两组的器件焊盘通过走线C81(属于第一连接走线)串联；串联的两组器件焊盘中，其中一组的阳极焊盘与一条走线C82(属于第二连接走线)连接、并通过过孔C4与阳极走线C51(属于金属引线)电连接，阳极走线C51通过过孔(图38未示出)与一个引脚焊盘C1电连接；另一组的阴极焊盘与另一条走线C82连接、并通过另一过孔C4与阴极走线C52(属于金属引线)电连接，阴极走线C52通过过孔(图38未示出)与另一引脚焊盘C1电连接。图38中，阴极焊盘C2’、阳极焊盘C2、引脚焊盘C1、走线C81和走线C82同层设置，采用相同的填充图案， 位于电极层；阳极走线C51和阴极走线C52同层设置，采用相同的填充图案，位于金属布线层。
图39为图38中沿AA'方向的一种截面示意图，图43为图38中沿AA'方向的另一种截面示意图，图40是在图39基础上形成发光二极管C6和封装层C9之后的结构示意图。图44是在图43基础上形成发光二极管C6和封装层C9之后的结构示意图。
可以理解的是，本实施例不对阵列基板的驱动方式进行限定，可以如图38所示，阵列基板采用无源的方式驱动发光单元，或者，也可以通过包括薄膜晶体管的驱动电路向发光单元提供信号，或者，还可以通过微型芯片(微芯片)向发光单元提供信号。
本实施例提供了一种阵列基板，该阵列基板中，由于电路板绑定区的引脚焊盘包括第一金属子层和第一导电子层，而第一导电子层具有抗氧化性、且覆盖第一金属子层；那么，该阵列基板的制作过程中，在发光区将发光单元与器件焊盘绑定连接时，电路板绑定区的第一导电子层不会发生氧化，从而保证后续电路板的绑定质量，进而提高产品良率。
可选的，参考图39和图43所示，该阵列基板包括衬底基板C7，第一导电子层C12相对于第一金属子层C11位于远离衬底基板C7的一侧，第一导电子层的材料包括金属氧化物或者金属合金。
可选的，第一金属子层的材料包括铜，第一导电子层的材料包括氧化铟锌或者氧化铟锡。考虑到氧化铟锌具有更好的导电性和更低的电阻率，一般多采用氧化铟锌制作第一导电子层，以避免在制作阵列基板的过程中采用铜制作的第一金属子层发生氧化。
进一步可选的，参考图43所示，多个器件焊盘中的任一个包括第二金属子层C21，第二金属子层C21与第一金属子层C11同层设置，作为电极层的金属子层。
同层设置是指采用一次构图工艺制作。一次构图工艺是指经过一次成膜和光刻工艺形成所需要的图案。一次构图工艺包括成膜、曝光、显影、刻蚀和剥离等工艺。第二金属子层与第一金属子层同层设置，从而可以降低构图工艺的次数，简化制作工艺，大幅降低生产成本。
需要说明的是，制作如图43所示的显示基板时，可以先制作如图 41所示的显示基板。图41中，器件焊盘包括第二金属子层C21和第二导电子层C22，其中，第二金属子层与第一金属子层同层设置，第二导电子层与第一导电子层同层设置。本公开提供的实施例中，第一金属子层的材料包括铜，第一导电子层的材料包括氧化铟锌或者氧化铟锡。而第二金属子层与第一金属子层同层设置，第二导电子层与第一导电子层同层设置(而共同位于导电子层)，则第二金属子层的材料包括铜，第二导电子层的材料包括氧化铟锌或者氧化铟锡。那么，后续若采用回流焊工艺完成发光单元与阵列基板的绑定，则需要在发光单元和阵列基板的器件焊盘之间设置锡膏。由于氧化铟锌或氧化铟锡无法与锡膏实现良好可固定的接触界面，而第二导电子层的材料包括氧化铟锌或者氧化铟锡，因此不能在第二导电子层上直接设置锡膏，而需要将器件焊盘中的第二导电子层去除，以露出第二金属子层，从而得到如图43所示的显示基板。第二金属子层的材料包括铜，铜可以与锡膏固晶，从而通过回流焊固晶工艺将发光单元绑定至第二金属子层。而电路板一般通过热固化胶，采用热压方式与第一导电子层绑定，无需将第一导电子层中用于与电路板绑定的部分去除。
另外，第一金属子层和第二金属子层的材料包括铜，为了增大铜的附着力，降低制作难度，引脚焊盘还可以包括第一缓冲子层，第一金属子层位于第一缓冲子层之上；器件焊盘还可以包括第二缓冲子层，第二金属子层位于第二缓冲子层之上；第一缓冲子层和第二缓冲子层同层设置，材料可以是含钼的合金，例如：钼钛镍合金。可以理解的是，第一缓冲子层和第二缓冲子层能够提高第一金属子层和第二金属子层的粘附力，因此还可以被称为金属粘附层。示例性地，第一缓冲子层和第二缓冲子层可以位于实施例一中所述的第二缓冲金属层。
该阵列基板中，由于电路板绑定区的引脚焊盘包括第一金属子层和第一导电子层，而第一导电子层具有抗氧化性、且覆盖第一金属子层；那么，阵列基板的制作过程中，在发光区绑定发光单元和第二金属子层时，电路板绑定区的第一金属子层由于受到第一导电子层的保护，不会发生氧化，从而保证后续电路板的绑定质量，进而提高产品良率。
连接部相对于第一导电子层位于远离衬底的一侧，第二平坦化层的 第进一步可选的，参考图39-图46所示，电路板绑定区OA还包括第一连接部(未示出，在一些实施方式中可以为焊锡层的一部分，用于使得电路板与引脚焊盘电连接)和第二平坦化层的第一部分C14，第一一部分覆盖多个引脚焊盘之间的区域，并露出引脚焊盘和器件焊盘的表面。
发光区OB还包括第二连接部(如图44中的C10，在一些实施方式中可以为焊锡层的一部分，用于使得发光单元与器件焊盘电连接)和第二平坦化层的第二部分C24，第二连接部相对于第二金属子层位于远离衬底的一侧，第二平坦化层的第二部分覆盖多个器件焊盘之间的区域。
其中，第二平坦化层的第一部分C14和第二平坦化层的第二部分C24同层设置，可以形成一体结构的第二平坦化层。
第二平坦化层的第一部分和第二平坦化层的第二部分可以分别对第一走线层和第二走线层起到保护作用，同时起到平坦作用，以利于后续工艺，其材料可以是有机材料，例如：树脂(Resin)。因此，第二平坦化层还可以被称为保护层、有机保护层、树脂层等。在本公开的一种实施方式中，电极层被第二平坦化层的第一部分覆盖的部分可以作为第一走线层，电极层被第二平坦化层的第二部分覆盖的部分可以作为第二走线层。
可选地，第一连接部的材料可以是热固化胶，第二连接部的材料可以是锡膏、铜膏等。
相关技术中，如图57所示，第二树脂层C105(即第二平坦化层的第二部分)和电极层C103(厚铜层)之间还设置有氮氧化硅(SiON)绝缘层104(亦可以成为无机保护层、钝化层等)。但是在本实施例提供的阵列基板中，由于第一金属子层上方设置有第二导电子层，对第二金属子层起到很好的保护作用，因此，阵列基板去掉了原有制程的氮氧化硅绝缘层，从而省去了原有工艺中PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)工艺和氮氧化硅刻蚀工艺，简化了原有工艺流程，降低了制造成本。
需要说明的是，参考图44所示，阵列基板还可以包括位于覆盖发光单元C6的封装层C9，以起到保护和封装作用，该封装层的材料可以是硅胶。
为了便于驱动，阵列基板还可以包括位于衬底之上的金属引线、与器件焊盘同层设置的连接走线。参考图38所示，金属引线包括阳极走线C51和阴极走线C52，连接走线包括走线C81和走线C82。参考图43所示，走线C82包括第三金属子层C83和第三导电子层C84，第三金属子层C83和第二金属子层C21相连而均位于金属子层，图43中用虚线分开。
参考图43所示，阳极走线C51可以仅包括一层结构；或者，还可以包括依次层叠设置的第一钼钛镍合金子层(相当于实施例一中的第一粘附层)、铜子层和第二钼钛镍合金子层(相当于实施例一中的第二粘附层)。为了减少压降(IR Drop)，铜子层采用厚铜(相比第一导电子层的铜厚度而言)，铜的厚度与Mini-LED背板的产品尺寸相关，尺寸越大，所需的铜厚度越大。可以采用溅射工艺依次制作第一钼钛镍合金子层、铜子层、第二钼钛镍合金子层，第二钼钛镍合金子层可以保护铜子层，防止铜子层表面氧化。
进一步的，为了保护和绝缘金属引线，参考图43所示，阵列基板还可以包括覆盖金属引线的第一平坦化层C33，引脚焊盘C1和器件焊盘2位于第一平坦化层C33之上，第一平坦化层的材料可以是有机材料，例如：树脂。参考图43所示，第一金属子层C11和第三金属子层C83通过贯穿第一平坦化层C33的过孔(图43未示出)分别与阳极走线C51电连接。
本公开提供的实施例中，第一金属子层的材料包括铜或含钼的合金，第一导电子层的材料包括含铜镍的合金。
若第一金属子层的材料包括铜，为了增大铜的附着力，降低制作难度，引脚焊盘还可以包括第一缓冲子层，第一金属子层位于第一缓冲子层之上。此时，引脚焊盘包括第一缓冲子层(亦可以称为缓冲金属层)、第一金属子层(铜层，亦可以称为铜电极层)和第一导电子层(含铜镍的合金层，亦可以称为铜镍合金层)三层结构。其中，第一缓冲子层的材料可以是含钼的合金，其厚度可以是
Figure PCTCN2021115688-appb-000003
第一金属子层的厚度范围可以是
Figure PCTCN2021115688-appb-000004
第一导电子层的厚度范围可以是
Figure PCTCN2021115688-appb-000005
若第一金属子层的材料包括含钼的合金，此时，参考图39所示，引 脚焊盘C1包括第一金属子层(含钼的合金层)C11和第一导电子层(含铜镍的合金层)C12两层结构。其中，第一金属子层的厚度可以是
Figure PCTCN2021115688-appb-000006
第一导电子层的厚度范围可以是
Figure PCTCN2021115688-appb-000007
引脚焊盘具体采用两层结构还是三层结构，需要根据电阻要求确定。
第一导电子层的材料包括含铜镍的合金，其铜镍合金的靶材配比可以按照电阻要求和刻蚀情况进行选择。理论上，镍的含量越高，其抗氧化性越强。但是镍具有磁性，镍的含量过高，一方面会增大制作靶材的难度，另一方面，会增大后续图案化的难度，因此镍的配比不能太高。申请人经过大量研究发现，配比范围可以在Cu∶Ni＝70∶30～95∶5之间选择，在配比范围内，可以确保铜镍合金表面在300℃的温度下不发生氧化。目前Cu∶Ni＝80∶20的铜镍合金可以在230°的环境下，耐高温半个小时不被氧化。表一为不同配比情况下电阻的差异。
表一
材料 膜厚/A 方块电阻(Ω/□)
Cu 880 0.35
CuNi(70∶30) 800 5.3
CuNi(90∶10) 3800 0.4
CuNi(95∶5) 3300 0.38
可选的，参考图39所示，多个器件焊盘中的任一个包括层叠设置的第二金属子层C21和第二导电子层C22，第二导电子层C22相对于第二金属子层C21位于远离衬底基板C7的一侧；其中，第二金属子层与第一金属子层同层设置，第二导电子层与第一导电子层同层设置。
同层设置是指采用一次构图工艺制作。一次构图工艺是指经过一次成膜和光刻工艺形成所需要的图案。一次构图工艺包括成膜、曝光、显影、刻蚀和剥离等工艺。第二金属子层与第一金属子层同层设置，第二导电子层与第一导电子层同层设置，从而可以降低构图工艺的次数，简化制作工艺，大幅降低生产成本。
第二金属子层与第一金属子层同层设置。若第一金属子层的材料包 括铜，此时，第二金属子层的材料也包括铜，为了增大铜的附着力，降低制作难度，器件焊盘还可以包括第二缓冲子层(亦可以称为缓冲金属层)，第二金属子层位于第二缓冲子层之上。第二缓冲子层与第一缓冲子层同层设置。此时，器件焊盘包括第二缓冲子层、第二金属子层(铜层，亦可以称为铜电极层)和第二导电子层(含铜镍的合金层，亦可以称为铜镍合金层)三层结构。若第一金属子层的材料包括含钼的合金，此时，第二金属子层的材料也包括含钼的合金，器件焊盘包括第二金属子层(含钼的合金层)和第二导电子层(含铜镍的合金层)两层结构。各子层厚度范围可以参考前述引脚焊盘包括的各子层厚度范围，这里不再赘述。
第二导电子层与第一导电子层同设置，若第一导电子层的材料包括含铜镍的合金，此时，第二导电子层的材料也包括含铜镍的合金，其含铜镍的合金中铜镍的配比范围可以参考前述第一导电子层的相关说明，这里不再赘述。
该阵列基板中，由于电路板绑定区的引脚焊盘包括第一金属子层和第一导电子层，而第一导电子层具有抗氧化性、且覆盖第一金属子层；那么，阵列基板的制作过程中，在发光区绑定发光单元和第二导电子层时，若第一金属子层的材料包括铜，则第一导电子层对第一金属子层起到保护作用，从而避免第一金属子层发生氧化；若第一金属子层的材料包括含钼的合金，第一导电子层的材料包括含铜镍的合金，第一导电子层具有抗氧化性，不会发生氧化。综上，两种情况均可以避免在发光区绑定发光单元和第二导电子层时，电路板绑定区的金属引线层发生氧化；从而保证后续电路板的绑定质量，进而提高产品良率。
进一步可选的，参考图39所示，电路板绑定区OA还包括第一连接部(图41未示出)、以及层叠设置的第一保护层C13(例如采用氮化硅作为材料的无机保护层的第一部分)和第二平坦化层的第一部分C14，第一连接部位于第一导电子层中远离衬底的一侧，第一平坦层位于第一保护层中远离衬底的一侧、且覆盖多个引脚焊盘之间的区域。
参考图39所示，发光区OB还包括第二连接部(图40标记为C10)、以及层叠设置的第二保护层23(例如采用氮化硅作为材料的无机保护层 的第二部分)和第二平坦化层的第二部分C24，第二连接部位于第二导电子层中远离衬底的一侧，第二保护层覆盖多个器件焊盘之间的区域，第二平坦层位于第二保护层中远离衬底的一侧。
其中，第一保护层和第二保护层同层设置，可以形成一体结构的保护层，例如形成采用氮化硅作为材料的无机保护层；第二平坦化层的第一部分和第二平坦化层的第二部分同层设置，可以形成一体结构的第二平坦化层。
在本实施例的一种实施方式中，第一保护层和第二保护层同层设置，其材料可以是氮氧化硅、氮化硅等；第二平坦化层的第一部分和第二平坦化层的第二部分同层设置，其材料可以是有机材料，例如：树脂，用于平坦化，以利于后续工艺。
在本实施例的一种实施方式中，第一连接部的材料可以是热固化胶，第二连接部的材料可以是锡膏、铜膏等。
阵列基板还可以包括位于衬底之上的金属引线、与器件焊盘同层设置的连接走线。参考图38所示，金属引线包括阳极走线C51和阴极走线C52，连接走线包括走线C81和走线C82。参考图39所示，走线C82包括第三金属子层C83和第三导电子层C84，第三金属子层C83和第二金属子层C21相连，图43中用虚线分开。
参考图39所示，金属引线中，阳极走线C51可以仅包括一层结构；或者，还可以包括依次层叠设置的第一钼合金子层和铜子层。进一步的，为了避免铜子层发生氧化，参考图39所示，阵列基板还可以包括覆盖阳极走线C51的钝化层C34，钝化层C34的材料可以是氮氧化硅、氮化硅等。更进一步的，为了平坦化以利于后续工艺，参考图39所示，阵列基板还可以包括位于钝化层C34之上的第一平坦化层C33，引脚焊盘和器件焊盘位于第一平坦化层C33之上，第一金属子层C11和第三金属子层C83通过贯穿钝化层C34和第一平坦化层C33的过孔分别与阳极走线C51电连接。第一平坦化层的材料可以是有机材料，例如：树脂。需要说明的是，阳极走线还可以进一步分别包括位于铜子层之上的第二钼合金子层，此时，铜子层受到第二钼合金子层的保护，那么，后续无需再形成钝化层。图39以阵列基板包括钝化层和第一平坦化层为例进行绘示。 另外，为了提高金属布线层的附着力，降低应力，阵列基板还可以包括位于衬底基板和金属引线之间的绝缘缓冲层，该绝缘缓冲层的材料可以是聚酰亚胺等材料。当然的，在本实施例的其他实施方式中，该绝缘缓冲层的材料也可以是氧化硅等无机绝缘材料。
本实施例的另一种实施方式中，参考图50所示，阵列基板还包括衬底基板C7；多个引脚焊盘C1面向衬底基板C7的表面露出以用于绑定电路板C5；多个器件焊盘(阳极焊盘C2和阴极焊盘C2’)远离衬底基板C7的表面露出以用于绑定发光单元C6。进一步地，参见图50，引脚焊盘C1可以位于金属布线层而非设置于电极层。
参考图50所示，该阵列基板还可以包括剥离层C44，剥离层C44位于衬底基板C7和引脚焊盘C1之间。衬底基板C7和剥离层C44中，至少对应引脚焊盘C1中用于绑定电路板C5的部分的区域(图49中标记C50)被去除。剥离层的材料可以是可机械剥离材料。衬底基板的材料可以是刚性衬底，例如：玻璃；还可以是柔性衬底，例如：聚酰亚胺。
需要说明的是，图47-图50中，仅示意性的绘示出引脚焊盘和器件焊盘的结构，并未体现出引脚焊盘包括的多层结构。
该阵列基板中，引脚焊盘包括第一金属子层和第一导电子层，那么，在绑定发光单元和第二金属子层时，电路板绑定区的引脚焊盘不会发生氧化，从而保证后续电路板和第一导电子层的绑定质量，进而提高产品良率。另外，该阵列基板中，将电路板绑定至第一金属子层中靠近剥离层的一侧，从而减小了出光侧的非发光面积，进而可以实现更窄的边框。
进一步的，参考图50所示，阵列基板还包括第一平坦化层C41、以及层叠设置的无机保护层C43和第二平坦化层C42(亦成为有机层、树脂层等)，其中，第一平坦化层C41覆盖引脚焊盘C1，第二平坦化层位于无机保护层中远离衬底基板的一侧、且覆盖多个器件焊盘之间的区域。参考图50所示，该阵列基板还可以包括与器件焊盘同层设置的走线C82，走线C82通过贯穿第一平坦化层C41的过孔(图50未示出)与引脚焊盘C1电连接。走线C82与阳极焊盘C2相连，图50中用虚线分开。该阵列基板中，阳极焊盘C2和阴极焊盘C2’分别通过第二连接部C10与发光二极管C6的阳极和阴极电连接，电路板C5通过第一连接部(图 50未示出)与引脚焊盘C1电连接。该阵列基板中，引脚焊盘位于第一平坦化层C41的下方，器件焊盘位于第一平坦化层C41的上方。
引脚焊盘中，第一金属子层的材料可以是铜或者含钼的合金，第一导电子层的材料可以是金属氧化物(例如：氧化铟锌、氧化铟锡)或者金属合金(例如：含铜镍的合金)。若第一金属子层的材料包括铜，此时，引脚焊盘还可以包括设置在第一金属子层下方的含钼的合金子层，以利于制作第一金属子层。需要说明的是，在阵列基板还包括第一平坦化层、无机保护层、第二平坦化层的情况下，由于电路板绑定至第一金属子层中靠近剥离层的一侧，因此，无需在第一平坦化层、无机保护层、第二平坦化层对应第一金属子层的区域设置过孔以露出引脚焊盘；那么，在绑定发光单元和第二金属子层时，第一平坦化层、无机保护层、第二平坦化层可以对引脚焊盘起到保护作用，防止其氧化，此时，引脚焊盘可以仅包括第一金属子层(例如：铜子层等)或者第一导电子层(例如：铜镍子层等)。第一平坦化层的材料可以是聚酰亚胺，第二平坦化层的材料可以是树脂。
器件焊盘可以仅包括一层金属子层，该金属子层可以是铜子层或者含铜的合金子层(例如：含铜镍的合金子层)；当然也可以包括多层子层。考虑到尽可能充分利用原有工艺，降低制作成本，选择前者。
需要说明的是，参考图50所示，阵列基板还可以包括位于覆盖发光单元的封装层C9，以起到保护和封装作用，该封装层的材料可以是硅胶。
可选的，参考图38所示，多个器件焊盘分为多组器件焊盘，每组器件焊盘包括成对设置的阴极焊盘C2’和阳极焊盘C2。
阵列基板还包括衬底基板、金属引线、与多个器件焊盘同层设置的连接走线、以及第一平坦化层，其中，金属引线相对于连接走线靠近衬底基板设置，第一平坦化层相对于连接走线靠近衬底基板设置、且覆盖金属引线。
金属引线与多个引脚焊盘中的至少一个电连接，用于传输电路板提供的电信号。
连接走线用于实现多组器件焊盘的串联连接或者并联连接，且还用于通过贯穿第一平坦化层的过孔与金属引线电连接。
上述多组器件焊盘的具体连接方式不做限定。图38中以相邻两组器件焊盘串联为例进行绘示。参考图38所示，区域OA为电路板绑定区，区域OB为发光区，多个器件焊盘可以分为多组器件焊盘，每组器件焊盘用于绑定一个发光二极管、且包括成对设置的阴极焊盘C2’和阳极焊盘C2。金属引线可以包括阳极走线C51和阴极走线C52，连接走线包括走线C81和走线C82。相邻两组的器件焊盘通过走线C81串联；串联的两组器件焊盘中，其中一组的阳极焊盘与一条走线C82连接，走线C82通过贯穿第一平坦化层的过孔C4与阳极走线C51电连接；阳极走线C51通过贯穿第一平坦化层的过孔(图38未示出)与一个引脚焊盘C1电连接；另一组的阴极焊盘与另一条走线C82连接，该走线C82通过另一贯穿第一平坦化层的过孔C4与阴极走线C52电连接，阴极走线C52通过贯穿第一平坦化层的过孔(图38未示出)与另一引脚焊盘C1电连接。图38中，阴极焊盘C2’、阳极焊盘C2、引脚焊盘C1、走线C81和走线C82同层设置，采用相同的填充图案；阳极走线C51和阴极走线C52同层设置，采用相同的填充图案。
当然，上述阵列基板还可以包括钝化层，钝化层位于第一平坦化层和金属引线之间、且覆盖金属引线，此时，连接走线需要通过贯穿钝化层和第一平坦化层的过孔与金属引线电连接。
本实施例还提供了一种背光模组，包括上述实施例中公开的阵列基板。
根据相关技术可知，该背光模组还可以包括扩散片、驱动电路等结构，具体可以根据实际需要确定，这里不再赘述。
该背光模组可用于需要提供背光的任何显示装置或者部件中，该背光模组可以是刚性的背光模组，也可以是柔性的背光模组(即可弯曲、可折叠)；这里不做限定。
相比于传统的背光模组，在Mini-LED作为光源应用在背光模组中时，可以通过更加密集的光源排布来制作超薄的光源模组；再配合区域调光技术，使得包括Mini-LED背光模组的显示屏将有更好的对比度和高动态光照渲染显示效果。采用Mini-LED背光的液晶显示器，在亮度、对比度、色彩还原度和功耗方面远远优于目前的液晶显示器，甚至在对 比度、功耗等方面可以与有源矩阵有机发光二极管显示屏竞争，同时还能利用现有液晶显示器产线控制生产成本。
本实施例中涉及的阵列基板的结构，可以参考上述实施例中关于阵列基板的相关说明，这里不再赘述。
本实施例还提供了一种显示装置，包括上述实施例中公开的阵列基板、电路板和多个发光单元；电路板与阵列基板的多个引脚焊盘电连接，多个发光单元与阵列基板的多个器件焊盘电连接。
该显示装置具有对比度高、亮度好、色彩还原度高等特点。该显示装置可以是刚性的显示装置，也可以是柔性的显示装置(即可弯曲、可折叠)。该显示装置可以是电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。可以理解的是，在一些实施方式中，可以将发光单元作为阵列基板的一部分。
本实施例中涉及的阵列基板的结构，可以参考上述实施例中关于阵列基板的相关说明，这里不再赘述。
本实施例又提供了一种显示装置的制作方法，包括：
S1、形成如上述实施例公开的阵列基板。
S2、绑定多个发光单元和阵列基板的多个器件焊盘。
具体的，若发光单元包括发光二极管，多个器件焊盘分为多组器件焊盘，每组器件焊盘包括成对设置的阴极焊盘和阳极焊盘，则将发光二极管的阳极和阴极分别与阳极焊盘和阴极焊盘对应电连接。该步骤中，可以采用回流焊工艺完成绑定。当然的，在一些实施方式中，也可以将发光单元等功能器件作为阵列基板的一部分；即，步骤S1和步骤S2一起形成本公开所需的阵列基板。
S3、绑定电路板和阵列基板的多个引脚焊盘。
该步骤中，可以采用热压方式完成绑定。
本实施例提供了一种显示装置的制作方法，通过步骤S1形成的阵列基板中，电路板绑定区的引脚焊盘包括第一金属子层和第一导电子层，而第一导电子层具有抗氧化性、且覆盖第一金属子层；那么，在执行步骤S2时，电路板绑定区的第一导电子层不会发生氧化，从而保证后续步骤S3中电路板的绑定质量，进而提高产品良率。
本实施例再提供了一种显示装置的制作方法，该显示装置包括的阵列基板的结构可以参考图43或者图46所示，该方法包括：
S11、依次形成金属薄膜和导电薄膜并图案化，得到如图41所示的第一金属子层C11、第二金属子层C21、位于第一金属子层C11之上的第一导电子层C12和位于第二金属子层C21之上的第二导电子层C22。
这里，可以采用溅射工艺一步沉积金属子层薄膜(例如实施例一中的铜电极材料层)和导电子层薄膜，并可以采用铜刻蚀液一步刻蚀进行图案化，以形成第一金属子层(相当于实施例一中的铜电极层的一部分)、第一导电子层、第二金属子层(相当于实施例一中的铜电极层的一部分)和第二导电子层。该S11中需要使用一道掩膜板(Mask)以形成所需图案。
需要说明的是，通过S11形成的引脚焊盘和器件焊盘分别包括两层结构。第一金属子层和第二金属子层的材料包括铜，为了增大铜的附着力，降低制作难度，引脚焊盘还可以包括第一缓冲子层(相当实施例一中的第二缓冲金属层的一部分)，第一金属子层位于第一缓冲子层之上；器件焊盘还可以包括第二缓冲子层(相当实施例一中的第二缓冲金属层的一部分)，第二金属子层位于第二缓冲子层之上；第一缓冲子层和第二缓冲子层同层设置，材料可以是含钼的合金，例如：钼钛镍合金。若引脚焊盘和器件焊盘还分别包括第一缓冲子层和第二缓冲子层，则可以采用溅射工艺一步沉积缓冲子层薄膜、金属子层薄膜和导电子层薄膜，并可以采用铜刻蚀液一步刻蚀进行图案化，以形成第一缓冲子层、第二缓冲子层、第一金属子层、第二金属子层、第一导电子层和第二导电子层。
S12、去除第二导电子层中用于与发光单元绑定的部分(即去除器件焊盘所在位置的第二导电子层)，以得到图43所示的阵列基板。
第二导电子层的材料包括氧化铟锌或者氧化铟锡，考虑到氧化铟锌具有更好的导电性和更低的电阻率，一般多采用氧化铟锌制作。氧化铟锌可以被任何一种酸性物质刻蚀。可以参考图42所示，采用网刻工艺刻蚀掉第二导电子层中用于与发光单元绑定的部分，从而有利于后续采用锡膏通过回流焊固晶工艺将发光单元绑定至第二金属子层。图42中，采 用工具C40将氧化铟锌刻蚀膏C30从掩膜板C20上推至待刻蚀区。
S13、绑定发光单元和第二金属子层。
具体的，依次进行刷锡膏、发光二极管打件、回流焊、硅胶封装工艺等，以完成发光单元和第二金属子层的绑定，从而形成如图44所示的阵列基板。由于第一导电子层对第一金属子层起到保护作用，可以避免在S13中第一金属子层发生氧化，进而保证后续电路板的绑定质量，提高产品良率。
S14、绑定电路板和第一导电子层。
具体的，可以通过第一连接部将电路板和第一导电子层绑定在一起。
该阵列基板的制作方法简单易实现、可操作性强。
可选的，在S12、去除第二导电子层中用于与发光单元绑定的部分之前、且在S11、依次形成金属薄膜和导电薄膜并图案化之后，方法还包括：
S15、形成有机薄膜并图案化，得到第二平坦化层的第一部分和如图43所示的第二平坦化层的第二部分C24，第二平坦化层的第二部分在对应第二金属子层的区域设置第二过孔，以露出器件焊盘。
第二平坦化层的第一部分和第二平坦化层的第二部分的材料可以是有机材料，例如：树脂。该S15中，需要使用一道掩膜板以形成所需图案。
此时，S13、绑定发光单元和第二金属子层包括：
S131、在第二过孔内形成第二连接部，第二连接部与第二金属子层电连接。这里第二连接部的材料可以是锡膏、铜膏等，实际多采用锡膏。
S132、在第二连接部之上绑定发光单元。
具体的，可以采用回流焊固晶工艺绑定，其中，回流焊峰值温度在240℃左右，保持时间90s。
当然在S132之后，为了更好地保护发光单元，还会采用硅胶等封装材料对发光单元进行封装，形成如图44所示的封装层C9。一般硅胶固化温度为150℃，保持4h。
可选的，在S13、绑定发光单元和第二金属子层之后，且在S14、绑定电路板和第一导电子层之前，方法还包括：
结合图45和图46，S16、部分刻蚀第二平坦化层的第一部分C14中对应第一导电子层C12的区域，形成第一过孔，以露出引脚焊盘。需要说明的是，在进行S16之前，发光区已经完成封装。由于封装层比较厚，S16中刻蚀形成第一过孔，对发光区的影响较小，因此不需要额外使用掩膜板。
S14、绑定电路板和第一导电子层包括：
S141、在第一过孔内形成第一连接部，第一连接部与第一导电子层电连接。
S142、在第一连接部之上绑定电路板。
这里，第一连接部的材料可以是热固化胶，可以采用热压方式绑定电路板，温度一般为130℃～150℃。
需要说明的是，通过S15和S16分别形成第二过孔和第一过孔，这样在S13、绑定发光单元和第二金属子层时，引脚焊盘上方设置有第二平坦化层的第一部分，第二平坦化层的第一部分对引脚焊盘可以起到保护作用，防止其发生氧化。因此，采用该方法制作时，引脚焊盘也可以仅包括第一金属子层，无需设置第一导电子层，相应地，器件焊盘也可以仅包括第二金属子层，无需设置第二导电子层。
另外，由于引脚焊盘包括第一金属子层和第一导电子层，第一导电子层对第一金属子层起到很好的保护作用，因此S16还可以并入S15，即在S15中，同时形成第一过孔和第二过孔，以露出引脚焊盘和器件焊盘，形成的阵列基板结构可参考图43所示。这样在S13、绑定发光单元和第二金属子层时，即使引脚焊盘露出，但是由于第一导电子层具有很好的抗氧化性，也可以避免自身和第一金属子层发生氧化。
制作方法中，在S11、S15中各使用一道掩膜板。另外，若要形成如图46所示的阵列基板，在S11之前，该制作方法还包括：形成金属引线，金属引线包括阳极走线C51和阴极走线(图46未示出)。那么，形成图46所示的阵列基板总计需要4道掩膜板(4Mask)。
相关技术中，形成的阵列基板如图57所示，一般采用4道掩膜板制作方法包括：S100、如图51所示，在玻璃衬底C100上形成金属布线层C101；S101、形成如图52所示的第一平坦化层C102；S102、形成如图 52所示的电极层C103；S103、形成如图53所示的无机保护层C104(亦称为氮氧化硅绝缘层)；S104、形成如图54所示的第二平坦化层C105，并如图55所示在二极管电路板绑定区(LED Bonding Pad)和柔性电路板电路板绑定区(FPC Bonding Pad)开孔；S105、对开孔区域进行干法刻蚀，以露出薄铜层，从而形成如图56所示的Mini-LED阵列基板(未绑定功能器件)。接着，进行后段工艺。后段工艺包括：依次进行刷锡膏、转移发光二极管、回流焊固晶、丝网印刷硅胶、硅胶固化。完成后的阵列基板如图57所示。其中回流焊峰值温度在240℃左右，保持时间90s。硅胶固化温度150℃，保持4h。这些温度制程会导致柔性电路板电路板绑定区的铜表面变成深红色，发生氧化，从而引起后续柔性电路板的绑定不良，降低产品良率。图57中，微发光二极管C107的阳极C108、阴极C109分别通过锡膏C110与电极层C103电连接，该阵列基板还包括硅胶封装层C106。
与相关技术相比，本实施例提供的阵列基板制作方法并未增加掩膜板的数量，同时能够避免在制作阵列基板的过程中采用铜制作的第一金属子层发生氧化的问题，从而保证电路板的绑定质量，进而提高产品良率。另外，在本实施例提供的阵列基板中，由于第一金属子层上方设置有第二导电子层，对第二金属子层起到很好的保护作用，因此，阵列基板的制作方法中去掉了原有制程的氮氧化硅保护层的工艺，从而省去了原有工艺中PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)工艺和氮氧化硅刻蚀工艺，简化了原有工艺流程，降低了制造成本。
本实施例还提供了一种显示装置的制作方法，该显示装置包括的阵列基板的结构可以参考图39所示，该方法包括：
S21、依次形成金属薄膜和导电薄膜并图案化，得到第一金属子层、第二金属子层、位于第一金属子层之上的第一导电子层和位于第二金属子层之上的第二导电子层。
这里，可以采用溅射工艺一步沉积金属子层薄膜和导电子层薄膜，并可以采用刻蚀液一步刻蚀进行图案化，以形成第一金属子层、第一导电子层、第二金属子层和第二导电子层。该S21中需要使用一道掩膜板 以形成所需图案。
需要说明的是，通过S21形成的第一走线层和第二走线层分别包括两层结构。若第一金属子层和第二金属子层的材料包括铜，为了增大铜的附着力，降低制作难度，引脚焊盘还可以包括第一缓冲子层，第一金属子层位于第一缓冲子层之上；器件焊盘还可以包括第二缓冲子层，第二金属子层位于第二缓冲子层之上。若引脚焊盘和器件焊盘还分别包括第一缓冲子层和第二缓冲子层，则可以采用溅射工艺一步沉积缓冲子层薄膜、金属子层薄膜和导电子层薄膜，并可以采用刻蚀液一步刻蚀进行图案化，以形成第一缓冲子层、第二缓冲子层、第一金属子层、第二金属子层、第一导电子层和第二导电子层。
若第一金属子层和第二金属子层的材料包括含钼的合金，此时，引脚焊盘包括第一金属子层(含钼的合金层)和第一导电子层(含铜镍的合金层)两层结构，器件焊盘包括第二金属子层(含钼的合金层)和第二导电子层(含铜镍的合金层)两层结构。
S22、绑定发光单元和第二导电子层。
具体的，可以依序进行刷锡膏、发光二极管打件、回流焊、硅胶封装工艺等，以完成发光单元和第二金属子层的绑定。在进行S22时，若第一金属子层的材料包括铜，则第一导电子层对第一金属子层起到保护作用，从而避免第一金属子层发生氧化；若第一金属子层的材料包括含钼的合金，第一导电子层的材料包括含铜镍的合金，第一导电子层具有抗氧化性，不会发生氧化。综上，两种情况均可以避免在发光区绑定发光单元和第二导电子层时，电路板绑定区的金属引线层发生氧化；从而保证后续电路板的绑定质量，进而提高产品良率。
S23、绑定电路板和第一导电子层。
具体的，可以通过第一连接部将电路板和第一导电子层绑定在一起。
阵列基板的制作方法简单易实现、可操作性强。
可选的，在S22、绑定发光单元和第二导电子层之前、且在S21、依次形成金属薄膜和导电薄膜并图案化之后，方法还包括：
S24、依次形成第一薄膜和第二薄膜并图案化，得到无机保护层的第一部分、无机保护层的第二部分、第二平坦化层的第一部分、第二平坦 化层的第二部分和第二过孔，第二过孔贯穿第二平坦化层的第二部分和无机保护层的第一部分，以露出器件焊盘。
第一薄膜的材料可以是氮氧化硅、氮化硅等，用于形成无机保护层的第一部分和无机保护层的第二部分；第二薄膜材料可以是树脂，用于形成第二平坦化层的第一部分和第二平坦化层的第二部分。该S24中，需要使用一道掩膜板以形成所需图案。
S22、绑定发光单元和第二导电子层包括：
S221、在第二过孔内形成第二连接部，第二连接部与第二导电子层电连接。这里第二连接部可以是锡膏、铜膏等，实际多采用锡膏。
S222、在第二连接部之上绑定发光单元。
具体的，可以采用回流焊固晶工艺绑定，其中，回流焊的温度为230～260℃，保持时间90s。
当然在S222之后，为了更好地保护发光单元，还会采用硅胶等封装材料对发光单元进行封装。一般硅胶固化温度为150℃，保持4h。
在S22、绑定发光单元和第二导电子层之后，且在S23、绑定电路板和第一导电子层之前，方法还包括：
S25、部分刻蚀无机保护层的第一部分和第二平坦化层的第一部分中对应第一导电子层的区域，形成第一过孔，以露出引脚焊盘。需要说明的是，在进行S25之前，发光区已经完成封装。由于封装层比较厚，S25中刻蚀形成第一过孔，对发光区的影响较小，因此不需要额外使用掩膜板。
S23、绑定电路板和第一导电子层包括：
S231、在第一过孔内形成第一连接部，第一连接部与第一导电子层电连接。
S232、在第一连接部之上绑定电路板。
这里，第一连接部可以是热固化胶，可以采用热压方式绑定电路板，温度一般为130℃～150℃。
需要说明的是，通过S24和S25分别形成第二过孔和第一过孔，这样在S22、绑定发光单元和第二金属子层时，引脚焊盘上方设置有无机保护层的第一部分和第二平坦化层的第一部分，无机保护层的第一部分 和第二平坦化层的第一部分对引脚焊盘可以起到保护作用，防止其发生氧化。因此，采用该方法制作时，引脚焊盘也可以仅包括铜子层或者含铜合金子层，无需设置两层导电结构，相应地，器件焊盘也可以仅包括铜子层或者含铜合金子层。
另外，由于引脚焊盘包括第一金属子层和第一导电子层，第一导电子层对第一金属子层起到很好的保护作用，因此S25还可以并入S24，即在S24中，同时形成第一过孔和第二过孔，以露出引脚焊盘和器件焊盘。这样在S22、绑定发光单元和第二金属子层时，即使引脚焊盘由于第一过孔露出一部分，但是由于第一导电子层具有很好的抗氧化性，也可以避免自身和第一金属子层发生氧化。
制作方法中，在S21、S24中各使用一道掩膜板。另外，若要形成如图39所示的阵列基板，在S21之前，该制作方法还包括：分别形成金属引线、钝化层C34和第一平坦化层C33，其中，金属引线包括阳极走线C51和阴极走线(图39未示出)。形成金属引线需要使用一道掩膜板，形成钝化层和第一平坦化层需要使用一道掩膜板。那么，形成图39所示的阵列基板总计需要4道掩膜板(4Mask)。
与相关技术相比，本实施例提供的阵列基板制作方法并未增加掩膜板的数量，同时能够避免在制作阵列基板的过程中采用铜制作的第一金属子层发生氧化的问题，从而保证电路板的绑定质量，进而提高产品良率。
本实施例又提供了一种显示装置的制作方法，该显示装置包括的阵列基板的结构可以参考图50所示，该方法包括：
S31、在衬底基板上形成剥离层，剥离层位于电路板绑定区和发光区。
剥离层的材料可以是可机械剥离材料。衬底基板的材料可以是刚性材料，例如：玻璃；或者，还可以是柔性材料，例如：聚酰亚胺(PI)。
S32、在剥离层之上形成引脚焊盘C1和器件焊盘(阴极焊盘C2’和阳极焊盘C2)；引脚焊盘包括层叠设置的第一金属子层和第一导电子层。形成的阵列基板可参考图47所示。
在进行绑定工艺之前，参考图48所示，在电路绑定板位置完成局部激光剥离(LLO)工艺和阵列基板切割，以得到单个待绑定阵列基板， 然后对单个待绑定阵列基板进行后续绑定工艺。
S33、绑定发光单元和器件焊盘。
具体的，可以依序进行刷锡膏、发光二极管打件、回流焊、硅胶封装工艺等，以完成发光单元和器件焊盘的绑定。
S34、至少去除衬底和剥离层中对应第一金属子层中用于绑定电路板的部分的区域(图49中标记C50)，并露出部分第一金属子层。
具体的，可以采用局部切割，去除衬底基板和剥离层中对应第一金属子层中用于绑定电路板的部分的区域。
S35、绑定电路板和第一金属子层。
具体的，可以通过第一连接部将电路板和第一金属子层绑定在一起。
在该方法中，形成的引脚焊盘包括第一金属子层和第一导电子层，那么，在绑定发光单元和第二金属子层时，电路板绑定区的引脚焊盘不会发生氧化，从而保证后续电路板和第一导电子层的绑定质量，进而提高产品良率。另外，该方法中，将电路板绑定至第一金属子层中靠近剥离层的一侧，从而减小了出光侧的非发光面积，进而可以实现更窄的边框。
进一步可选的，参考图50所示，阵列基板还包括第一平坦化层C41、无机保护层C43、第二平坦化层C42、过孔(图50未标记)和第二连接部C10，第一有机层覆盖引脚焊盘。器件焊盘位于第一平坦化层的上方，保护层覆盖器件焊盘和第一平坦化层，第二平坦化层位于无机保护层的上方。过孔贯穿第二平坦化层和无机保护层，以露出器件焊盘，发光单元通过第二连接部与器件焊盘电连接。
那么，在剥离层之上形成引脚焊盘的步骤需要一道掩膜板；另外，形成器件焊盘，形成第一平坦化层，形成无机保护层、第二平坦化层和过孔分别需要一道掩膜板。则形成图50所示的阵列基板共计需要4道掩膜板，与相关技术相比，并未增加掩膜板的数量，同时能够避免在制作阵列基板的过程中引脚焊盘发生氧化的问题，从而保证电路板的绑定质量，进而提高产品良率。另外，该方法中，将电路板绑定至第一金属子层中靠近剥离层的一侧，从而减小了出光侧的非发光面积，进而可以实现更窄的边框。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (31)

  1. 一种阵列基板，包括：
    衬底基板；
    金属布线层，设于所述衬底基板的一侧；
    第一平坦化层，设于所述金属布线层远离所述衬底基板的一侧；
    电极层，设于所述第一平坦化层远离所述衬底基板的一侧；所述电极层包括依次层叠于所述衬底基板一侧的金属子层和导电子层；所述金属子层的材料包括金属或者金属合金；所述导电子层具有抗氧化性且覆盖所述金属子层；
    第二平坦化层，设于所述电极层远离所述衬底基板的一侧；
    功能器件层，设于所述第二平坦化层远离所述衬底基板的一侧，且包括多个与所述电极层电连接的功能器件。
  2. 根据权利要求1所述的阵列基板，其中，所述金属子层的材料包括铜，所述导电子层的材料包括铜镍合金。
  3. 根据权利要求1所述的阵列基板，其中，所述金属子层的材料为铜；所述导电子层的材料为铜镍合金。
  4. 根据权利要求3所述的阵列基板，其中，所述电极层还可以包括夹设于所述金属子层和所述导电子层之间的第一缓冲金属层；所述第一缓冲金属层的材料为钼、钼铌合金、钼钨合金、钼镍钛合金、钼镁铝合金中的一种或者多种的混合。
  5. 根据权利要求4所述的阵列基板，其中，所述第一缓冲金属层和所述导电子层覆盖所述金属子层的侧面和所述金属子层远离所述衬底基板的表面。
  6. 根据权利要求4所述的阵列基板，其中，所述导电子层在所述金属子层上的正投影，位于所述金属子层内。
  7. 根据权利要求4所述的阵列基板，其中，所述第一缓冲金属层的厚度为100～500埃。
  8. 根据权利要求4所述的阵列基板，其中，所述导电子层的厚度为200～1000埃。
  9. 根据权利要求3所述的阵列基板，其中，所述电极层还可以包括 夹设于所述金属子层和所述导电子层之间的钯金属层；所述钯金属层位于且覆盖所述金属子层远离所述衬底基板的表面和所述金属子层的侧面；所述导电子层位于且覆盖所述钯金属层远离所述衬底基板的表面。
  10. 根据权利要求9所述的阵列基板，其中，所述导电子层中，镍的质量含量不小于30％。
  11. 根据权利要求9所述的阵列基板，其中，所述导电子层中，镍的质量含量不大于80％。
  12. 根据权利要求9所述的阵列基板，其中，所述导电子层的厚度为500～2000埃。
  13. 根据权利要求1所述的阵列基板，其中，所述导电子层的材料包括金属氧化物。
  14. 根据权利要求13所述的阵列基板，其中，所述导电子层的材料包括氧化铟锌或者氧化铟锡。
  15. 根据权利要求1～14任意一项所述的阵列基板，其中，所述阵列基板包括电路板绑定区和发光区，其中，所述电路板绑定区包括多个引脚焊盘，所述多个引脚焊盘用于与电路板绑定连接；
    所述发光区包括多个器件焊盘，所述器件焊盘用于与所述功能器件绑定连接；
    所述引脚焊盘和所述器件焊盘设置于所述电极层。
  16. 根据权利要求15所述的阵列基板，其中，所述电路板绑定区还包括第一连接部，所述第一连接部位于所述导电子层远离所述衬底基板的一侧；所述第一连接部用于使得所述引脚焊盘的导电子层与所述电路板绑定连接。
  17. 根据权利要求16所述的阵列基板，其中，所述导电子层的材料包括金属氧化物；所述器件焊盘设置于所述金属子层且被所述导电子层暴露；
    所述发光区还包括第二连接部，所述第二连接部位于所述器件焊盘的金属子层远离所述衬底基板的一侧；所述第二连接部用于使得所述器件焊盘的金属子层与所述功能器件绑定连接。
  18. 根据权利要求16所述的阵列基板，其中，所述导电子层的材料 包括铜镍合金；
    所述发光区还包括第二连接部，所述第二连接部位于所述器件焊盘的导电子层远离所述衬底基板的一侧；所述第二连接部用于使得所述器件焊盘的导电子层与所述功能器件绑定连接。
  19. 根据权利要求1～14任意一项所述的阵列基板，其中，所述阵列基板包括多个引脚焊盘；
    所述衬底基板暴露所述引脚焊盘靠近所述衬底基板的表面；被所述衬底基板暴露的所述引脚焊盘的表面，用于与所述电路板绑定连接。
  20. 根据权利要求19所述的阵列基板，其中，所述引脚焊盘设置于所述金属布线层。
  21. 根据权利要求1～14任意一项所述的阵列基板，其中，所述电极层设置有多个器件焊盘；所述多个器件焊盘分为多组器件焊盘，每组所述器件焊盘包括成对设置的阴极焊盘和阳极焊盘；
    所述金属布线层设置有金属引线，所述电极层还设置有连接走线；
    所述金属引线与所述多个引脚焊盘中的至少一个电连接，用于传输电路板提供的电信号；
    所述连接走线用于实现多组所述器件焊盘的串联连接或者并联连接，且还用于通过贯穿所述第一平坦化层的过孔与所述金属引线电连接。
  22. 根据权利要求1～14任意一项所述的阵列基板，其中，所述电极层还包括位于所述金属子层靠近所述衬底基板的表面的第二缓冲金属层。
  23. 根据权利要求1～14任意一项所述的阵列基板，其中，所述金属布线层包括依次层叠于所述衬底基板的一侧的种子金属层、铜生长层和第二铜镍合金层。
  24. 根据权利要求1～14任意一项所述的阵列基板，其中，所述金属布线层包括依次层叠于所述衬底基板的一侧的种子金属层和铜生长层；
    所述阵列基板还包括钝化层，钝化层设于所述金属布线层和所述第一平坦化层之间。
  25. 根据权利要求1～14任意一项所述的阵列基板，其中，所述阵列基板还包括夹设于所述电极层和所述第二平坦化层之间的无机保护层。
  26. 一种显示面板，包括权利要求1～25任意一项所述的阵列基板； 所述阵列基板的功能器件为微发光二极管或者迷你发光二极管。
  27. 一种背光模组，包括权利要求1～25任意一项所述的阵列基板；所述阵列基板的功能器件为微发光二极管或者迷你发光二极管。
  28. 一种权利要求4所述的阵列基板的制备方法，包括：
    提供一衬底基板；
    在所述衬底基板的一侧形成金属布线层；
    在所述金属布线层远离所述衬底基板的一侧形成第一平坦化层；
    在所述第一平坦化层远离所述衬底基板的一侧形成电极层，所述电极层包括依次层叠于所述衬底基板一侧的金属子层、第一缓冲金属层和导电子层；所述第一缓冲金属层的材料为钼、钼铌合金、钼钨合金、钼镍钛合金、钼镁铝合金中的一种或者多种的混合；
    在所述电极层远离所述衬底基板的一侧形成第二平坦化层；
    设置功能器件层；所述功能器件层设于所述第二平坦化层远离所述衬底基板的一侧，且包括多个与所述电极层电连接的功能器件。
  29. 根据权利要求28所述的阵列基板的制备方法，其中，在所述第一平坦化层远离所述衬底基板的一侧形成电极层包括：
    在所述第一平坦化层远离所述衬底基板的一侧形成金属子材料层；
    对所述金属子材料层进行图案化操作，形成所述金属子层；
    在所述金属子层远离所述衬底基板的一侧依次形成第一缓冲金属材料层和导电子材料层；
    对所述第一缓冲金属材料层和所述导电子材料层进行图案化操作，以形成所述第一缓冲金属层和所述导电子层；其中，所述金属子层在所述衬底基板上的正投影，位于所述第一缓冲金属层在所述衬底基板上的正投影内。
  30. 一种权利要求9所述的阵列基板的制备方法，包括：
    提供衬底基板；
    在所述衬底基板的一侧形成金属布线层；
    在所述金属布线层远离所述衬底基板的一侧形成第一平坦化层；
    在所述第一平坦化层远离所述衬底基板的一侧形成金属子层，所述金属子层与所述金属布线层电连接；
    形成钯金属层，所述钯金属层位于且覆盖所述金属子层远离所述衬底基板的表面和所述金属子层的侧面；
    采用化学镀的方法形成导电子层，所述导电子层位于且覆盖所述钯金属层远离所述衬底基板的表面；
    设置功能器件层；所述功能器件层设于所述导电子层远离所述衬底基板的一侧，且包括多个与所述导电子层电连接的功能器件。
  31. 根据权利要求30所述的阵列基板的制备方法，其中，形成钯金属层包括：
    用钯盐的溶液处理所述金属子层，在所述金属子层远离所述衬底基板的表面和所述金属子层的侧面形成所述钯金属层。
PCT/CN2021/115688 2020-09-07 2021-08-31 阵列基板及其制备方法、显示面板和背光模组 WO2022048538A1 (zh)

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