WO2023065341A1 - 一种发光基板及显示装置 - Google Patents

一种发光基板及显示装置 Download PDF

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Publication number
WO2023065341A1
WO2023065341A1 PCT/CN2021/125854 CN2021125854W WO2023065341A1 WO 2023065341 A1 WO2023065341 A1 WO 2023065341A1 CN 2021125854 W CN2021125854 W CN 2021125854W WO 2023065341 A1 WO2023065341 A1 WO 2023065341A1
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WIPO (PCT)
Prior art keywords
layer
light
pads
emitting
oxidation protection
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PCT/CN2021/125854
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English (en)
French (fr)
Inventor
姚念琦
杨锦
宁策
贺家煜
黄杰
胡合合
赵坤
李菲菲
李正亮
袁广才
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/125854 priority Critical patent/WO2023065341A1/zh
Priority to CN202180003038.2A priority patent/CN116368631A/zh
Publication of WO2023065341A1 publication Critical patent/WO2023065341A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, in particular to a light-emitting substrate and a display device.
  • Mini/Micro LED light-emitting substrates have high requirements on the resistance of metal wiring, so copper metal is often used as wiring material.
  • Mini/Micro LED bonding, flexible printed circuit board or integrated circuit bonding need to be carried out separately.
  • Embodiments of the present disclosure provide a light-emitting substrate and a display device.
  • the light-emitting substrate can avoid oxidation of pads in the light-emitting region, thereby ensuring reliable electrical connection between the light-emitting unit and the light-emitting substrate, thereby improving product yield.
  • An oxidation protection layer located on the side of the first pad away from the base substrate, the plurality of first pads are used to bind and connect to a plurality of light-emitting units through the oxidation protection layer; the oxidation protection
  • the material of the layer includes CuNiX, wherein X includes one of Al, Sn, Pb, Au, Ag, In, Zn, Bi, Mg, Ga, V, W, Y, Zr, Mo, Nb, Pt, Co, Sb or Any combination of elements.
  • the oxidation protection layer has a thickness of 10 nm-100 nm.
  • the sum of the mass fraction of Ni and the mass fraction of X accounts for 10%-90%.
  • the mass fraction of Cu accounts for 20%-95%
  • the mass fraction of Ni accounts for 5%-80%
  • the mass fraction of X accounts for 10%-40%.
  • the atomic ratio of Ni and X is 2-4.
  • the base substrate further has a binding area, and the binding area includes a plurality of second pads located on the base substrate, so The plurality of second pads are used for binding connection with the circuit board; the second pads are located on the same film layer as the first pads, and the side of the second pads away from the base substrate has The oxidation protection layer.
  • the above-mentioned light-emitting substrate provided by the embodiments of the present disclosure further includes a first wiring layer located between the first pad and the base substrate, and the first wiring layer includes a stacked The first sub-metal layer, the first sub-wiring layer and the second sub-metal layer;
  • the first pad is electrically connected to the second sub-metal layer, and the second pad is electrically connected to the second sub-metal layer;
  • Materials of the first sub-metal layer and the second sub-metal layer include molybdenum-niobium alloy, and materials of the first sub-trace layer include copper.
  • the light-emitting region further includes: a first passivation layer located between the first wiring layer and the first pad, located on the The first flat layer between the first passivation layer and the first pads is located on the side of the oxidation protection layer away from the base substrate and covers the second layer of the area between the plurality of first pads. a planar layer, and a first connecting portion located on the oxidation protection layer.
  • the binding area further includes: a second passivation layer located between the first wiring layer and the second pad, located on the A third planar layer between the second passivation layer and the second pads, located on the side of the oxidation protection layer facing away from the base substrate and covering the first part of the area between the plurality of second pads Four planar layers, and a second connecting portion located on the oxidation protection layer;
  • the third flat layer is set on the same layer as the first flat layer
  • the fourth flat layer is set on the same layer as the second flat layer
  • the second passivation layer is set on the same layer as the first passivation layer. layer settings.
  • the plurality of first pads are divided into multiple groups of first pads, and each group of first pads includes cathode pads arranged in pairs and anode pad;
  • the light-emitting substrate further includes a second wiring layer arranged on the same layer as the plurality of first pads, the side of the second wiring layer away from the base substrate has the oxidation protection layer, the The second wiring layer is used to realize the series connection or parallel connection of multiple groups of the first pads, and the second wiring layer is also used to pass through the first flat layer and the first passivation layer.
  • the via holes are electrically connected to the first wiring layer.
  • the above-mentioned light-emitting substrate provided by the embodiments of the present disclosure further includes a protection layer located on the side of the oxidation protection layer away from the base substrate, the protection layer exposes the oxidation protection layer, and the protection Layer materials include silicon nitride or silicon oxide.
  • an embodiment of the present disclosure also provides a display device, including: the light-emitting substrate according to any one of the above, a circuit board, and a plurality of light-emitting units;
  • the plurality of light-emitting units are electrically connected to the plurality of first pads of the light-emitting substrate through the oxidation protection layer, and the circuit board is electrically connected to the plurality of second pads of the light-emitting substrate through the oxidation protection layer. connect.
  • the light emitting unit is a Mini LED or a Micro LED.
  • Fig. 1 is a kind of sectional schematic diagram along the AA ' direction of Fig. 6;
  • Fig. 2A is a schematic diagram of the reflectance-wavelength variation relationship of the CuNi alloy thin film after deposition and at a temperature of 150°C;
  • FIG. 2B is a schematic diagram of the reflectance-wavelength variation relationship of an oxidation protective layer whose material is CuNiAl provided by an embodiment of the present disclosure under different conditions;
  • Figure 3A is the surface color of the film after depositing CuNiAl
  • Figure 3B is the surface color of the CuNiAl alloy film at 150°C in an air atmosphere for 60 minutes;
  • Figure 3C is the surface color of the CuNiAl alloy film at 260°C and nitrogen atmosphere for 30 minutes;
  • FIG. 5A is a microscopic photo of the oxidation protection layer provided by an embodiment of the present disclosure after it is connected with a micro light-emitting diode;
  • FIG. 5B is a microscope photo of the interface after the micro light-emitting diode and the oxidation protection layer provided by the embodiment of the present disclosure are separated from each other;
  • FIG. 6 is a schematic top view of a light-emitting substrate provided by an embodiment of the present invention.
  • Fig. 7 is another schematic cross-sectional view along the AA' direction of Fig. 6 .
  • Mini-LED submillimeter light-emitting diode refers to a miniature light-emitting diode with a size between 80 and 300um.
  • Mini-LEDs are used as the pixels of the display panel to form a self-luminous display, it can achieve a higher pixel density than a small-pitch LED display.
  • an ultra-thin light source module can be made through a more dense light source arrangement; combined with the regional dimming technology, the display including the Mini-LED backlight module will There are better contrast ratios and HDR display effects.
  • Micro LEDs with a size of less than 80um can be directly used as pixels for display panels such as near-eye, wearable, and handheld terminals.
  • the light-emitting substrate provided in the present invention may refer to a substrate used to provide a light source, or may refer to a substrate used for display, which is not limited thereto.
  • the binding of Mini/Micro LEDs and circuit boards to the light-emitting substrate requires different process conditions, the binding of the two cannot be realized simultaneously.
  • the bonding pad material of the board is easily oxidized under the process conditions corresponding to the bonding Mini/Micro LED, which makes it impossible to ensure that the circuit board can achieve a good electrical connection with the light-emitting substrate, thereby reducing the product yield. It is understandable that if the light-emitting substrate is first bound to the circuit board and then bound to the Mini/Micro LED, the same problem will exist.
  • An embodiment of the present disclosure provides a light-emitting substrate that can be configured to display or provide a backlight. As shown in FIG. 1 , the light-emitting substrate includes:
  • a base substrate 1, the base substrate 1 has a light emitting area A1;
  • the oxidation protection layer 3 is located on the side of the first pads (2 and 2') away from the base substrate 1, and the multiple first pads (2 and 2') are used to communicate with the plurality of light emitting units ( Fig. 1 is not shown) bonding connection;
  • the material of oxidation protection layer 3 comprises CuNiX, and wherein X comprises Al, Sn, Pb, Au, Ag, In, Zn, Bi, Mg, Ga, V, W, Y, Zr, One of Mo, Nb, Pt, Co, Sb or any combination of elements.
  • an oxidation protection layer made of CuNiX is prepared on the first pads (2 and 2').
  • X includes one of Al, Sn, Pb, Au, Ag, In, Zn, Bi, Mg, Ga, V, W, Y, Zr, Mo, Nb, Pt, Co, Sb or any combination of elements, because Ni and X have oxidation resistance, so as to prevent the surface oxidation of the oxidation protection layer.
  • the embodiments of the present disclosure add an anti-oxidation CuNiX alloy film layer on the first pad to achieve oxidation resistance without an additional anti-oxidation process, which greatly simplifies the process flow and reduces mass production costs; and, the implementation of the present disclosure
  • the CuNiX alloy thin film can be deposited by target sputtering, without the need to use anti-oxidation processes such as Ni-Au or Copper Preservatives (Organic Solderability Preservatives, OSP) after making pads in related technologies, which reduces costs and improves productivity. Productivity.
  • the CuNiX oxidation protection layer provided by the embodiments of the present disclosure has better oxidation resistance in a high-temperature environment.
  • the light-emitting substrate provided by the embodiment of the present invention may be a display substrate or may be a backlight substrate. If it is a display substrate, the light-emitting area A1 constitutes a display area, and the light-emitting units are sub-pixels, thereby realizing a display screen. If it is a backlight substrate, the light-emitting area A1 is used to provide a light source to cooperate with the passive display panel to realize display.
  • the light emitting color of the light emitting region included in the light emitting substrate may be any one of a red light emitting region, a green light emitting region or a blue light emitting region.
  • the light-emitting substrate may include light-emitting areas of three light-emitting colors: a red light-emitting area, a green light-emitting area, or a blue light-emitting area; of course, it may also only include a light-emitting area of one light-emitting color, for example: only include a plurality of red light-emitting areas, Either only a plurality of green light-emitting regions is included, or only a plurality of blue light-emitting regions are included. The details can be determined according to actual requirements.
  • each light emitting area may be controlled independently, or multiple light emitting areas may be controlled simultaneously.
  • the material of the base substrate may be a rigid material, such as glass, quartz, plastic, or a printed circuit board; or may be a flexible material, such as polyimide.
  • the thickness should not be too thick to avoid increasing the difficulty of etching so that the pattern morphology cannot be guaranteed, and it should not be too thin, otherwise the anti-oxidation performance will be poor. Therefore, considering the two factors of process realization and anti-oxidation performance, the embodiment of the present disclosure will oxidize the protective layer
  • the thickness of 3 is set to 10nm-100nm, such as 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm.
  • the oxidation protection layer 3 can be obtained by sputtering an alloy target, or co-sputtering a single metal target, which can be selected according to actual needs.
  • the oxidation protection layer 3 in the above light-emitting substrate provided by the embodiment of the present invention, as shown in FIG. 1 , in the material of the oxidation protection layer 3 , the sum of the mass fraction of Ni and the mass fraction of X accounts for 10%-90%.
  • the inventors have found through tests that when the mass fraction of Cu accounts for 20% to 95%, the mass fraction of Ni accounts for 5% to 80%, and the mass fraction of X accounts for 10% to 40%, the oxidation protection layer 3 has a better anti-oxidation effect. Oxidation properties.
  • the oxidation protection layer 3 in the above light-emitting substrate provided by the embodiment of the present invention, in the oxidation protection layer made of CuNiX, when the atomic ratio of Ni to X is in the range of about 2 to 4, the oxidation protection layer 3 has a relatively Good antioxidant properties.
  • FIG. 2A is a CuNi alloy film formed by a sputtering process at room temperature (for example at 10°C-50°C, such as 25°C, 30°C) and after forming the above CuNi alloy film
  • FIG. 2A is a CuNi alloy film formed by a sputtering process at room temperature (for example at 10°C-50°C, such as 25°C, 30°C) and after forming the above CuNi alloy film.
  • FIG. 2B is a schematic diagram of the reflectance-wavelength change relationship of the CuNiAl alloy oxidation protection layer provided by the embodiment of the present disclosure under different conditions, including CuNiAl alloy
  • the reflectance of the CuNi alloy thin film decreases significantly at 150°C, indicating that the CuNi alloy is oxidized at 150°C, while the CuNiAl of the disclosed embodiment is at 150°C , 250°C, the reflectivity has no obvious change, so CuNiAl in the embodiment of the present disclosure still has good oxidation resistance at 150°C and 250°C;
  • Figure 3B is the surface color of the CuNiAl alloy film in the air at 150°C for 60 minutes
  • Figure 3C is the alloy film of the CuNiAl alloy film in the nitrogen atmosphere at 260°C for 30 minutes
  • Surface color it can be seen that the surface color of the CuNiAl alloy film does not change significantly after being exposed to air at 150°C for 60 minutes and in N at 260°C for 30 minutes, indicating that the surface of the CuNiAl alloy film has not been oxidized. Therefore, the oxidation protection layer whose material is CuNiAl alloy provided by the embodiment of the present disclosure has better oxidation resistance in high temperature environment.
  • the material of the first pads (2 and 2') includes Cu
  • the material of the oxidation protection layer 3 is CuNiAl as an example.
  • Electron micrograph (SEM) as shown in Figure 4 shows that the bottom layer is a buffer layer (the third sub-metal layer 53 introduced later), which is the first pad 2 formed by Cu on the third sub-metal layer 53, with a thickness of On the left and right, the oxidation protection layer 3 formed by CuNiAl alloy on the first pad 2 has a thickness of Left and right, and the photoresist layer 60 located on the side of the oxidation protection layer 3 away from the first pad 2 , the photoresist layer 60 is used for patterning the oxidation protection layer 3 .
  • SEM Electron micrograph
  • Retaining the photoresist layer 60 in the SEM image is to confirm the CD Bias (indicated by 1) after the first pad 2 is etched.
  • CD Bias is the size of the first pad 2 before etching minus the size after etching, CD Bias In the range of 0.5 ⁇ m to 2 ⁇ m, the etched appearance of the first pad 2 is good.
  • the CD Bias 1 value measured in this disclosure is 0.74 ⁇ m, which is in the range of 0.5 ⁇ m to 2 ⁇ m, so the etched shape of the first pad 2 is good. Good looking.
  • the oxidation protection layer 3, the first pad 2, and the third sub-metal layer 53 are formed by the same patterning process, that is, their respective film layers are patterned simultaneously in a wet etching process, from It can be seen from FIG. 4 that there is no Tip (roof structure) in the appearance of the oxidation protection layer 3 after etching, and there is no Undercut (undercut) or Tail (tail) in the appearance of the third sub-metal layer 53 after etching. Therefore, the oxidation protection layer 3 , the first pad 2 and the third sub-metal layer 53 all have good etching morphology.
  • the first pad 2 includes opposite first main surfaces 201 and second main surfaces 202 , and side surfaces 203 connecting the first main surfaces 201 and the second main surfaces 202 , and the first main surfaces 210 are opposite to each other.
  • the angle ⁇ between the tangent line 2 of the side surface 203 at any point and the plane where the third sub-metal layer 53 is located determines the coverage of subsequent film layers.
  • the film layer (such as the oxidation protection layer 3) has a problem of poor lapping.
  • the maximum value of ⁇ needs to be between 30° and 80°. If it is higher than 80°, there may be a problem of poor lapping of subsequent film layers.
  • FIG. 5A is a microscopic photo of the pin of the micro light emitting diode 100 fixedly connected to the oxidation protection layer 3 provided by the embodiment of the present disclosure through a soldering metal 70 (such as tin), and FIG.
  • a soldering metal 70 such as tin
  • FIG. Microscopic photo of micro-LED 100 and oxidation protection layer 3 separated from each other in 5A it can be seen that after micro-LED 100 is separated from oxidation protection layer 3, solder metal 70 remaining on the surface of oxidation protection layer 3 and oxidation protection layer 3 are separated.
  • the surface of layer 3 reacts to form a good intermetallic compound IMC after being fixed and connected by the reflow soldering process, and has good wettability.
  • a plurality of second pads 4 are used for binding connection with the circuit board (not shown in Figure 1); the second pads 4 are located in the same film layer as the first pads (2 and 2'), and The side of the second pad 4 facing away from the base substrate 1 has an oxidation protection layer 3 .
  • the fact that the second pad 4 and the first pad (2 and 2') are located in the same film layer means that the two are made by one patterning process.
  • One patterning process refers to forming the required pattern through one film forming and photolithography process.
  • a patterning process includes film formation, exposure, development, etching and stripping.
  • the second pad 4 is located in the same film layer as the first pad (2 and 2'), so that the number of patterning processes can be reduced, the manufacturing process can be simplified, and the production cost can be greatly reduced.
  • the side of the second pad 4 away from the base substrate 1 can also be provided with an oxidation protection layer 3, so the surface of the second pad 4 also has oxidation resistance; therefore, during the manufacturing process of the light-emitting substrate, the binding area A2
  • the second bonding pad 4 will not be oxidized, so that the problem of oxidation in the process of manufacturing the light-emitting substrate can be avoided, and the stability of the second bonding pad 4 can be improved.
  • the first wiring layer 5 includes a stacked first sub-metal layer 51, a first sub-wiring layer 52 and a second sub-metal layer 53; wherein, the first pad (2 and 2') and the second pad 4 are respectively electrically connected to different conductive patterns/conductive lines in the second sub-metal layer 53.
  • the material of the first sub-metal layer 51 and the second sub-metal layer 53 includes molybdenum-niobium alloy, which has adhesiveness and enhances the adhesion between the first wiring layer 5 and the base substrate 1 .
  • a buffer layer can be provided between the base substrate 1 and the first wiring layer 5 to relieve the stress, in addition, the first sub-metal layer 51 made of molybdenum-niobium alloy can also enhance the adhesion between the first wiring layer 5 and the buffer layer, and the material of the buffer layer is, for example, silicon nitride.
  • the second sub-metal layer 53 made of molybdenum-niobium alloy is connected to the first pad 2'. Since the molybdenum-niobium alloy has adhesiveness, it can ensure that the first wiring layer 5 and the first pad 2' are connected firmly, and The molybdenum-niobium alloy has conductivity, which can ensure the conductivity between the first pad 2' and the first wiring layer 5; the material of the first sub-wiring layer 52 can include copper, and copper has good conductivity, which can To ensure the electrical connection between the film layers, the small resistance of copper can reduce the current loss during operation, and the low price of copper can reduce the production cost of the array substrate.
  • the second sub-metal layer 53 made of molybdenum-niobium alloy can protect the copper of the first sub-wiring layer 52 and prevent the copper from being oxidized.
  • the material of the first sub-wiring layer 52 can include copper. Copper has good electrical conductivity, which can ensure the electrical connection between the film layers. The small resistance of copper can reduce the current loss during operation, and the price of copper is low, which can reduce the cost of the light-emitting substrate. production cost.
  • the thickness of the first sub-wiring layer 52 may be 1 ⁇ m ⁇ 3 ⁇ m.
  • the thickness of the first pads (2 and 2') may be 1000 angstroms to 8000 angstroms, and the thickness of the oxidation protection layer 3 may be 500 angstroms to 1500 angstroms.
  • the second pad 4 is an example of a film layer set on the same layer as the first pad (2 and 2').
  • the second pad 4 can also be used only It is arranged on the same layer as the first wiring layer 5 , or the second pad 4 adopts a film layer arranged on the same layer as the first wiring layer 5 and the first pads ( 2 and 2 ′).
  • the light-emitting area A1 further includes: The first passivation layer 6, the first flat layer 7 between the first passivation layer 6 and the first pads (2 and 2'), is located on the side of the oxidation protection layer 3 away from the base substrate 1 and covers a plurality of The second planar layer 8 in the region between the first pads ( 2 and 2 ′), and the first connecting portion 9 on the oxidation protection layer 3 .
  • FIG. 1 is a schematic cross-sectional view along the AA' direction in FIG. 6, and the first wiring layer 5 may include an anode wiring 54 and a cathode wiring 55 (not shown in FIG. Both the line 54 and the cathode wiring 55 are set by stacking the first sub-metal layer 51, the first sub-wiring layer 52 and the second sub-metal layer 53.
  • the first sub-wiring layer The thickness of 52 is greater than the thickness of the first pads (2 and 2'), and the thickness of the first sub-wiring layer 52 is positively related to the product size of the Mini-LED backplane.
  • the first sub-metal layer 51, the first sub-wiring layer 52 and the second sub-metal layer 53 can be fabricated in sequence by using a sputtering process, and the second sub-metal layer 53 can protect the first sub-wiring layer 52 and prevent the first sub-wiring layer from The surface of the line layer 52 is oxidized.
  • the first passivation layer 6 includes a part between the anode trace 54 and the cathode trace 55, and separates adjacent traces to avoid mistakes in adjacent traces.
  • the material of the first passivation layer 6 can be silicon nitride, silicon oxide, silicon oxynitride and the like.
  • the first flat layer 7 covers the area between the anode wiring 54 and the cathode wiring 55, and the first flat layer 7 may be an organic film, which is used to fill the gap area between the wiring and avoid large step differences in subsequent processes To ensure that the displacement of the light-emitting unit does not occur when the light-emitting unit is bound, thereby improving the flatness of the array substrate; at the same time, the first flat layer 7 can also play an insulating role.
  • the material of the first connecting portion 9 on the oxidation protection layer 3 is a solder metal material, such as tin, tin-copper alloy, tin-silver alloy, copper, and the like.
  • the thickness of the first passivation layer 6 may range from 1000 angstroms to 4000 angstroms.
  • a third planar layer 20 located between the second passivation layer 10 and the second pads 4, located on the side of the oxidation protection layer 3 facing away from the base substrate 1 and covering the area between the plurality of second pads 4
  • the fourth planar layer 30, and the second connection portion 40 located on the oxidation protection layer 3;
  • the third planar layer 20 is set on the same layer as the first planar layer 7, and can form an integrated structure.
  • Its material can be an organic material, such as: resin, used for planarization, to facilitate subsequent processes (such as the first pad 2, the second pad 4, etc.);
  • the fourth planar layer 30 and the second planar layer 8 are arranged in the same layer, and can form an integrated structure, and its material can be an organic material, such as: resin, used for planarization, to facilitate subsequent processes (such as protection layer 50);
  • the second passivation layer 10 and the first passivation layer 6 are arranged in the same layer, and can form an integrated structure, and its material can be silicon oxynitride, silicon nitride, silicon oxide, etc.
  • the thickness of the second passivation layer 10 may be 1000 angstroms to 9000 angstroms.
  • the above-mentioned light-emitting substrate provided by the embodiments of the present disclosure may further include a plurality of light-emitting units, and the light-emitting units may include micro light-emitting diodes 100 as shown in FIG. 7 . It should be noted that since the micro light emitting diode 100 includes an anode pin and a cathode pin, one micro light emitting diode 100 needs to be bonded through two first pads.
  • each first pad group is used to bind a miniature light emitting diode, and includes a cathode pad and an anode pad arranged in pairs, wherein The first pad bound to the cathode pin of the micro light emitting diode is called the cathode pad, and the first pad bound to the anode pin of the micro light emitting diode is called the anode pad.
  • each first pad group includes a cathode pad 2 ′ and an anode pad 2 arranged in pairs, and the cathode pad 2 ′ and the anode pad 2 include the same film layer structure.
  • the micro light emitting diode 100 is bound to the cathode pad 2 ′ and the anode pad 2 through the first connection portion 9 and the oxidation protection layer 3 .
  • the material of the first connection part 9 generally includes metallic nickel
  • the material of the oxidation protection layer 3 provided in the embodiment of the present disclosure is CuNiX
  • Ni in the oxidation protection layer 3 can be combined with Ni in the first connection part 9 to improve Adhesion between the first connection part 9 and the oxidation protection layer 3 .
  • the circuit board 200 is bound and connected to the second pad 4 through the second connecting portion 40, the oxidation protection layer 3, and specifically, the circuit board 200 includes a printed circuit board, a flexible circuit board, an integrated circuit chip, etc.
  • the material of the second connecting portion 40 may be thermosetting glue or anisotropic conductive glue.
  • the plurality of first pads (2 and 2') are divided into multiple groups of first pads, and each group of first pads
  • the pads include a pair of cathode pads 2' and anode pads 2;
  • the light-emitting substrate also includes a second wiring layer arranged on the same layer as the plurality of first pads (2 and 2').
  • the second wiring layer has an oxidation protection layer 3 on the side away from the base substrate 1.
  • the second wiring layer The layer is used to realize the series connection or parallel connection of multiple groups of first pads (2 and 2'), and the second wiring layer is also used to pass through the first flat layer 7 and the first passivation layer 6 through the via hole and
  • the first wiring layer 5 is electrically connected.
  • the second wiring layer includes wiring 11 and wiring 12 .
  • the wiring 12 and the first pad 2 ′ are integrated, and the wiring 12 and the first pad 2 ′ are separated by a dotted line in FIG. 1 .
  • FIG. 6 The specific connection manner of the above multiple first pad groups is not limited.
  • two adjacent first pad groups are connected in series as an example for illustration.
  • a plurality of first pads (2 and 2') can be divided into a plurality of first pad groups, and each first pad group is used to bind a miniature light-emitting diode, and includes The cathode pad 2' and the anode pad 2 are arranged in pairs.
  • the first wiring layer 5 may include an anode wiring 54 and a cathode wiring 55 .
  • the first pads of two adjacent groups are connected in series through a wire 11; as shown in FIG. 1 and FIG.
  • the wiring 12 is electrically connected to the anode wiring 54 through the via hole V1 passing through the first passivation layer 6 and the first planar layer 7; the anode wiring 54 passes through the via hole passing through the first passivation layer 6 and the first planar layer 7 (not shown in FIG. 1 ) is electrically connected with a second pad 4; the cathode pad of another group is connected with another wiring 12, and this wiring 12 passes through another through the first passivation layer 6 and the first flat
  • the via hole V1 of the layer 7 is electrically connected to the cathode wiring 55, and the cathode wiring 55 passes through the via hole (not shown in FIG. electrical connection.
  • the cathode pad 2', the anode pad 2, the second pad 4, the wiring 11 and the wiring 12 are arranged on the same layer, and the same filling pattern is used to indicate the cathode pad 2', the anode pad 2, the second pad
  • the two pads 4 , the wires 11 and 12 ; the anode wire 54 and the cathode wire 55 are arranged on the same layer, and the same filling pattern is used to indicate the anode wire 54 and the cathode wire 55 .
  • the present disclosure does not limit the driving method of the light-emitting substrate. As shown in FIG. , or, it is also possible to provide a signal to the light-emitting unit through a microchip.
  • each microchip when the signal is provided to the light-emitting unit through the microchip, each microchip includes a plurality of pins, and the light-emitting substrate further includes a third pad located in the light-emitting area for binding connection with the pins of the microchip.
  • the structure of the third bonding pad is similar to that of the first bonding pad, and can be manufactured using the same film layer structure as the first bonding pad.
  • the plurality of light emitting units can be divided into a plurality of lamp areas, each lamp area includes at least one light emitting unit, and each microchip is used to drive the light emitting unit of at least one lamp area to emit light.
  • a protective layer 50 located on the side of the oxidation protective layer 3 away from the base substrate 1 is also included, and the protective layer 50 exposes the oxidation
  • the material of the protection layer 3 and the protection layer 50 may include silicon oxynitride, silicon nitride or silicon oxide.
  • the light-emitting unit can be a mini light-emitting diode (English: Mini Light Emitting Diode, referred to as: MiniLED), also known as a submillimeter light-emitting diode, or a micro light-emitting diode (English: Mini Light Emitting Diode). : Micro Light Emitting Diode, referred to as: Micro LED).
  • MiniLED Mini Light Emitting Diode
  • Micro LED Micro Light Emitting Diode
  • the light-emitting unit can use Mini LEDs.
  • the size and pitch of Mini LEDs are small, which can not only make the number of local dimming zones (Local Dimming Zones) more detailed, Achieve high-dynamic range (High-Dynamic Range, HDR) to present high-contrast effects, and can also shorten the optical distance (Optical Distance, OD) to reduce the thickness of the whole machine to meet the thinning requirements.
  • an embodiment of the present invention also provides a display device, including: the above-mentioned light-emitting substrate, a circuit board and a plurality of light-emitting units provided by the embodiment of the present invention, and the light-emitting unit can adopt Mini LED or Micro LED;
  • the multiple light emitting units are electrically connected to the multiple first pads of the light emitting substrate through the oxidation protection layer, and the circuit is electrically connected to the multiple second pads of the light emitting substrate through the oxidation protection layer.
  • the display device has the characteristics of high contrast, good brightness, high color reproduction and the like.
  • the display device may be a rigid display device or a flexible display device (ie, bendable or foldable).
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be regarded as limitations on the present invention.
  • the problem-solving principle of the display device is similar to that of the above-mentioned light-emitting substrate, so the implementation of the display device can refer to the implementation of the above-mentioned light-emitting substrate, and repeated descriptions will not be repeated here.
  • an oxidation protection layer made of CuNiX is prepared on the first pad, where X includes Al, Sn, Pb, One of Au, Ag, In, Zn, Bi, Mg, Ga, V, W, Y, Zr, Mo, Nb, Pt, Co, Sb or any combination of elements, because Ni and X have oxidation resistance, to play To prevent the surface oxidation of the oxidation protection layer.
  • the embodiments of the present disclosure add an anti-oxidation CuNiX alloy film layer on the first pad to achieve oxidation resistance without an additional anti-oxidation process, which greatly simplifies the process flow and reduces mass production costs; and, the implementation of the present disclosure
  • the CuNiX alloy film can be deposited by target sputtering, which improves the feasibility of mass production.
  • the CuNiX oxidation protection layer provided by the embodiments of the present disclosure has better oxidation resistance in a high-temperature environment.

Abstract

一种发光基板及显示装置，该发光基板包括：衬底基板（1），衬底基板（1）具有发光区（A1）；多个第一焊盘（2，2'），位于衬底基板（1）的一侧，且位于发光区（A1），第一焊盘（2，2'）的材料包括Cu；氧化防护层（3），位于第一焊盘（2，2'）背离衬底基板（1）的一侧，多个第一焊盘（2，2'）用于通过氧化防护层（3）与多个发光单元绑定连接；氧化防护层（3）的材料包括CuNiX，其中X包括Al、Sn、Pb、Au、Ag、In、Zn、Bi、Mg、Ga、V、W、Y、Zr、Mo、Nb、Pt、Co、Sb其中之一或任意组合元素。

Description

一种发光基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种发光基板及显示装置。
背景技术
Mini/Micro LED发光基板对金属走线的电阻有较高要求，故常用铜金属作为配线材料。在发光基板的制作过程中，需要分别进行Mini/Micro LED绑定、柔性印刷电路板或集成电路绑定。
发明内容
本公开实施例提供一种发光基板及显示装置，该发光基板能够避免发光区的焊盘发生氧化的问题，从而保证发光单元与发光基板的可靠电气连接，进而提高产品良率。
本公开实施例提供的一种发光基板，包括：
衬底基板，所述衬底基板具有发光区；
多个第一焊盘，位于所述衬底基板的一侧，且位于所述发光区，所述第一焊盘的材料包括Cu；
氧化防护层，位于所述第一焊盘背离所述衬底基板的一侧，所述多个第一焊盘用于通过所述氧化防护层与多个发光单元绑定连接；所述氧化防护层的材料包括CuNiX，其中X包括Al、Sn、Pb、Au、Ag、In、Zn、Bi、Mg、Ga、V、W、Y、Zr、Mo、Nb、Pt、Co、Sb其中之一或任意组合元素。
可选地，在本公开实施例提供的上述发光基板中，所述氧化防护层的厚度为10nm-100nm。
可选地，在本公开实施例提供的上述发光基板中，所述氧化防护层的材料中，Ni的质量分数和X的质量分数之和占10％～90％。
可选地，在本公开实施例提供的上述发光基板中，Cu的质量分数占20％～95％，Ni的质量分数占5％～80％，X的质量分数占10％～40％。
可选地，在本公开实施例提供的上述发光基板中，Ni和X的原子比为2～4。
可选地，在本公开实施例提供的上述发光基板中，所述衬底基板还具有绑定区，所述绑定区包括位于所述衬底基板之上的多个第二焊盘，所述多个第二焊盘用于与电路板绑定连接；所述第二焊盘与所述第一焊盘位于同一膜层，所述第二焊盘背离所述衬底基板的一侧具有所述氧化防护层。
可选地，在本公开实施例提供的上述发光基板中，还包括位于所述第一焊盘与所述衬底基板之间的第一走线层，所述第一走线层包括层叠设置的第一子金属层、第一子走线层和第二子金属层；其中，
所述第一焊盘和所述第二子金属层电连接，所述第二焊盘和所述第二子金属层电连接；
所述第一子金属层和所述第二子金属层的材料包括钼铌合金，所述第一子走线层的材料包括铜。
可选地，在本公开实施例提供的上述发光基板中，所述发光区还包括：位于所述第一走线层和所述第一焊盘之间的第一钝化层，位于所述第一钝化层和所述第一焊盘之间的第一平坦层，位于所述氧化防护层背离所述衬底基板一侧且覆盖所述多个第一焊盘之间区域的第二平坦层，以及位于所述氧化防护层上的第一连接部。
可选地，在本公开实施例提供的上述发光基板中，所述绑定区还包括：位于所述第一走线层和所述第二焊盘之间的第二钝化层，位于所述第二钝化层和所述第二焊盘之间的第三平坦层，位于所述氧化防护层背离所述衬底基板一侧且覆盖所述多个第二焊盘之间区域的第四平坦层，以及位于所述氧化防护层上的第二连接部；其中，
所述第三平坦层与所述第一平坦层同层设置，所述第四平坦层与所述第二平坦层同层设置，所述第二钝化层与所述第一钝化层同层设置。
可选地，在本公开实施例提供的上述发光基板中，所述多个第一焊盘分 为多组第一焊盘，每组所述第一焊盘包括成对设置的阴极焊盘和阳极焊盘；
所述发光基板还包括与所述多个第一焊盘同层设置的第二走线层，所述第二走线层背离所述衬底基板的一侧具有所述氧化防护层，所述第二走线层用于实现多组所述第一焊盘的串联连接或者并联连接，且所述第二走线层还用于通过贯穿所述第一平坦层和所述第一钝化层的过孔与所述第一走线层电连接。
可选地，在本公开实施例提供的上述发光基板中，还包括位于所述氧化防护层背离所述衬底基板一侧的保护层，所述保护层露出所述氧化防护层，所述保护层的材料包括氮化硅或氧化硅。
相应地，本公开实施例还提供了一种显示装置，包括：如上述任一项所述的发光基板、电路板和多个发光单元；
所述多个发光单元通过所述氧化防护层与所述发光基板的多个第一焊盘电连接，所述电路板通过所述氧化防护层与所述发光基板的多个第二焊盘电连接。
可选地，在本公开实施例提供的上述显示装置中，所述发光单元为Mini LED或Micro LED。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为沿图6的AA’方向的一种截面示意图；
图2A为CuNi合金薄膜在沉积后以及150℃温度下的反射率-波长变化关系示意图；
图2B为本公开实施例提供的材料为CuNiAl的氧化防护层在不同条件下的反射率-波长变化关系示意图；
图3A为沉积CuNiAl后薄膜的表面颜色；
图3B为CuNiAl合金薄膜在150℃、空气氛围下60分钟的表面颜色；
图3C为CuNiAl合金薄膜在260℃、氮气氛围下30分钟的表面颜色；
图4为本公开实施例提供的第一焊盘/氧化防护层(即Cu/CuNiAl)的叠层刻蚀扫描电子显微镜照片；
图5A为本公开实施例提供的氧化防护层上与微型发光二极管连接后的显微镜照片；
图5B为本公开实施例提供的微型发光二极管与氧化防护层相互分离后的界面显微镜照片；
图6为本发明实施例提供的一种发光基板的俯视结构示意图；
图7为沿图6的AA’方向的又一种截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是 示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
Mini-LED(亚毫米发光二极管)是指尺寸在80～300um之间的微型发光二极管。在Mini-LED作为显示面板的像素点构成自发光显示器时，相比于小间距LED显示器，可以实现更高的像素密度。在Mini-LED作为光源应用在背光模组中时，可以通过更加密集的光源排布来制作超薄的光源模组；再配合区域调光技术，使得包括Mini-LED背光模组的显示屏将有更好的对比度和高动态光照渲染显示效果。而尺寸小于80um的micro LED微型发光二极管，可以直接作为近眼、穿戴、手持终端等显示面板的像素点。
本发明提供的发光基板，可以指用作提供光源的基板，也可以指用于显示的基板，对此不作限定。
相关技术中，为了完成Mini/Micro LED与发光基板的绑定，需要在发光基板上待与Mini/Micro LED电气连接的焊盘上设置锡膏，接着将Mini/Micro LED转移到发光基板上对应的位置，然后在230℃-260℃的温度范围内通过回流焊方式完成Mini/Micro LED与发光基板的固定。而电路板绑定在发光基板待与电路板电气连接的焊盘上，是在130℃-150℃的温度范围内通过热压方式实现。
由于绑定Mini/Micro LED和电路板到发光基板需要使用不同的工艺条件，无法同步实现二者的绑定，因而例如在先绑定Mini/Micro LED的情况下，发光基板上的待与电路板绑定的焊盘材料在绑定Mini/Micro LED所对应工艺条件的下极易发生氧化，进而导致无法保证电路板能够与发光基板实现良好的电气连接，从而降低产品良率。可以理解的是，如果先将发光基板先与电路板绑定再与Mini/Micro LED绑定，也会存在同样的问题。
本公开实施例提供了一种发光基板，该发光基板可以被配置为用于显示或提供背光，如图1所示，该发光基板包括：
衬底基板1，衬底基板1具有发光区A1；
多个第一焊盘(2和2')，位于衬底基板1的一侧，且位于发光区A1，第 一焊盘(2和2')的材料包括Cu；
氧化防护层3，位于第一焊盘(2和2')背离衬底基板1的一侧，多个第一焊盘(2和2')用于通过氧化防护层3与多个发光单元(图1未示出)绑定连接；氧化防护层3的材料包括CuNiX，其中X包括Al、Sn、Pb、Au、Ag、In、Zn、Bi、Mg、Ga、V、W、Y、Zr、Mo、Nb、Pt、Co、Sb其中之一或任意组合元素。
本公开实施例提供的上述发光基板，在采用Cu材料制备完第一焊盘(2和2')后，在第一焊盘(2和2')上制备一层材料包括CuNiX的氧化防护层，其中X包括Al、Sn、Pb、Au、Ag、In、Zn、Bi、Mg、Ga、V、W、Y、Zr、Mo、Nb、Pt、Co、Sb其中之一或任意组合元素，由于Ni和X具有抗氧化性，以起到防止氧化防护层表面氧化的作用。另外，本公开实施例通过在第一焊盘上增加防氧化的CuNiX合金膜层，无需额外防氧化工艺即可实现抗氧化性，大大简化了工艺流程，降低量产成本；并且，本公开实施例可以通过靶材溅射的方式沉积CuNiX合金薄膜，无需相关技术中在制作焊盘之后再采用化镍金或护铜剂(Organic Solderability Preservatives，OSP)等防氧化工艺，降低了成本，提高了生产效率。并且，本公开实施例提供的CuNiX氧化防护层在高温环境下具有较好的抗氧化性。
本发明实施例提供的发光基板可以为显示基板或可以为背光基板。若为显示基板，则发光区A1构成显示区，发光单元即为子像素，从而实现显示画面。若为背光基板，则发光区A1用于提供光源，以配合被动式显示面板实现显示。
这里对于发光基板包括的发光区的发光颜色不做限定；发光区可以是红色发光区、绿色发光区或者蓝色发光区中的任一种。该发光基板可以同时包括红色发光区、绿色发光区或者蓝色发光区三种发光颜色的发光区；当然，也可以仅包括一种发光颜色的发光区，例如：仅包括多个红色发光区，或者仅包括多个绿色发光区，或者仅包括多个蓝色发光区。具体可以根据实际要求确定。
发光区的控制方式不作限定，示例性的，可以每个发光区被独立控制，或者多个发光区被同时控制等。
具体地，衬底基板的材料可以是刚性材料，如玻璃、石英、塑料、印刷电路板；或者可以是柔性材料，如聚酰亚胺。
在具体实施时，在本公开实施例提供的上述发光基板中，如图1所示，氧化防护层3主要起到保护第一焊盘(2和2’)的作用，因此氧化防护层3的厚度不能太厚，避免增加刻蚀难度从而无法保证图案形貌，也不能太薄，否则抗氧化性能不佳，因此综合考虑工艺实现和抗氧化性能两个因素，本公开实施例将氧化防护层3的厚度设置为10nm-100nm，例如10nm、20nm、30nm、40nm、50nm、60nm、70nm、80nm、90nm、100nm。
具体地，氧化防护层3可以通过合金靶材溅射的方式得到，还可以通过单金属靶材共溅射的方式得到，可以根据实际需要进行选择。
在具体实施时，在本发明实施例提供的上述发光基板中，如图1所示，氧化防护层3的材料中，Ni的质量分数和X的质量分数之和占10％～90％。发明人经过测试发现，当Cu的质量分数占20％～95％，Ni的质量分数占5％～80％，X的质量分数占10％～40％时，氧化防护层3具有较好的抗氧化性能。
在具体实施时，在本发明实施例提供的上述发光基板中，在材料为CuNiX的氧化防护层中，Ni和X的原子比的取值范围大约在2～4时，氧化防护层3具有较好的抗氧化性能。
相关技术中公开了采用CuNi合金作为氧化防护层的方案，可通过反射率测试对金属表面的氧化情况进行分析，当膜层发生氧化后，其表面成分发生变化，反射率出现明显降低。如图2A、图2B所示，图2A为CuNi合金薄膜在室温(例如在10℃-50℃，例如25℃，30℃)下通过溅射工艺形成的CuNi合金薄膜以及形成上述CuNi合金薄膜后在150℃空气氛围中60min的反射率-波长变化关系示意图，图2B为本公开实施例提供的材料为CuNiAl合金的氧化防护层在不同条件下的反射率-波长变化关系示意图，其中包括CuNiAl合 金薄膜在室温下通过溅射工艺形成后薄膜的反射率变化曲线、CuNiTi合金薄膜沉积后在150℃空气中60分钟后的反射率变化曲线以及CuNiTi合金薄膜沉积后在250℃空气中30分钟后的反射率变化曲线，从图2A和图2B可以看出，CuNi合金薄膜在150℃下发生明显的反射率下降，说明CuNi合金在150℃下即发生氧化，而本公开实施例的CuNiAl在150℃、250℃下反射率均没有明显变化，因此本公开实施例的CuNiAl在150℃、250℃下仍具有较好的抗氧化性；并且如图3A-图3C所示，图3A为沉积CuNiAl合金薄膜后未进行热处理的合金薄膜表面颜色，图3B为CuNiAl合金薄膜在150℃空气中60分钟后的合金薄膜表面颜色，图3C为CuNiAl合金薄膜在260℃的氮气氛围中30分钟后的合金薄膜表面颜色，可以看出CuNiAl合金薄膜在150℃空气中60分钟和260℃N 2中30分钟后合金薄膜表面颜色未发生明显变化，说明CuNiAl合金薄膜表面未发生氧化。因此本公开实施例提供的材料为CuNiAl合金的氧化防护层在高温环境下具有较佳的抗氧化性。
在具体实施时，在本公开实施例提供的上述发光基板中，如图1所示，第一焊盘(2和2’)的材料包括Cu，以氧化防护层3的材料为CuNiAl为例，通过一次刻蚀工艺同时形成第一焊盘(2和2’)的图案以及氧化防护层3的图案后，第一焊盘(2和2’)和氧化防护层3构成的叠层结构的扫描电子显微镜照片(SEM)如图4所示，示意出底层为缓冲层(后续介绍的第三子金属层53)，为第三子金属层53上由Cu形成的第一焊盘2，厚度为
Figure PCTCN2021125854-appb-000001
左右，位于第一焊盘2上由CuNiAl合金形成的氧化防护层3，厚度为
Figure PCTCN2021125854-appb-000002
左右，以及位于氧化防护层3背离第一焊盘2一侧的光刻胶层60，光刻胶层60用于图案化氧化防护层3。在SEM图中保留光刻胶层60是为了确认第一焊盘2刻蚀后的CD Bias(1表示)，CD Bias为第一焊盘2刻蚀前尺寸减去刻蚀后尺寸，CD Bias在0.5μm～2μm范围内时第一焊盘2的刻蚀形貌良好，本公开测得的CD Bias 1值为0.74μm，在0.5μm～2μm范围内，因此第一焊盘2刻蚀形貌良好。
在一些实施例中，氧化防护层3、第一焊盘2、第三子金属层53采用同 一次构图工艺制作形成，即其各自所在膜层采用一次湿法刻蚀工艺中同时形成图案，从图4可以看出，氧化防护层3的刻蚀后形貌没有出现Tip(屋顶结构)，并且第三子金属层53的刻蚀后形貌没有出现Undercut(底切)或Tail(尾部)，因此氧化防护层3、第一焊盘2、第三子金属层53均具有良好的刻蚀形貌。
如图4所示，第一焊盘2包括相对的第一主表面201和第二主表面202，以及连接第一主表面201和第二主表面202的侧表面203，第一主表面210相对于第二主表面202更靠近第三子金属层53，侧表面203在任一点的切线2与第三子金属层53所在平面之间的夹角β决定后序膜层的覆盖性，为避免后续膜层(如氧化防护层3)出现搭接不良的问题，β的最大值需要在30°～80°之间，若高于80°可能存在后续膜层搭接不良的问题，从本公开实施例测得的SEM照片(图4)可以看出，β为33.1°左右，说明刻蚀界面良好，说明本公开实施例在第一焊盘2上增加的氧化防护层3不会出现膜层搭接不良的问题，在后续沉积钝化层时，如果β太大，或者氧化防护层3上有Tip，则需要较厚的钝化层才能覆盖上，才能避免膜层断裂，而本公开实施例中测得的β为33.1°左右，因此不会对后续膜层(如钝化层)的沉积产生影响。
如图5A和图5B所示，图5A为微型发光二极管100的引脚通过焊接金属70(例如锡)与本公开实施例提供的氧化防护层3固定连接后的显微镜照片，图5B为将图5A中的微型发光二极管100与氧化防护层3相互分离后的显微镜照片，可以看到，在微型发光二极管100与氧化防护层3分离后，残留在氧化防护层3表面的焊接金属70与氧化防护层3表面在通过回流焊工艺固定连接后反应形成了良好的金属间化合物IMC，且有较好的润湿性。
在具体实施时，在本公开实施例提供的上述发光基板中，如图1所示，衬底基板1还具有绑定区A2，绑定区A2包括位于衬底基板1之上的多个第二焊盘4，多个第二焊盘4用于与电路板(图1未示出)绑定连接；第二焊盘4与第一焊盘(2和2’)位于同一膜层，第二焊盘4背离衬底基板1的一侧具有氧化防护层3。具体地，第二焊盘4与第一焊盘(2和2’)位于同一膜层是 指二者采用一次构图工艺制作。一次构图工艺是指经过一次成膜和光刻工艺形成所需要的图案。一次构图工艺包括成膜、曝光、显影、刻蚀和剥离等工艺。第二焊盘4与第一焊盘(2和2’)位于同一膜层，从而可以降低构图工艺的次数，简化制作工艺，大幅降低生产成本。同时，第二焊盘4远离衬底基板1的一侧也可以设置氧化防护层3，因此第二焊盘4表面也具有抗氧化性；因此，该发光基板的制作过程中，绑定区A2的第二焊盘4不会发生氧化，从而能够避免在制作发光基板的过程中出现氧化的问题，提高第二焊盘4的稳定性。
在具体实施时，在本公开实施例提供的上述发光基板中，如图1所示，还包括位于第一焊盘(2和2’)与衬底基板1之间的第一走线层5，第一走线层5包括层叠设置的第一子金属层51、第一子走线层52和第二子金属层53；其中，第一焊盘(2和2')和第二焊盘4分别和第二子金属层53中的不同导电图案/导电线路电连接。
第一子金属层51和第二子金属层53的材料包括钼铌合金，钼铌合金具有粘附性，增强第一走线层5和衬底基板1之间的附着力。在一些情况下，为了防止第一走线层5的整体面积过大导致使得衬底基板1受到过大应力产生破片，则可以在衬底基板1和第一走线层5之间设置缓冲层来缓解应力，另外材料包括钼铌合金的第一子金属层51还可以增强第一走线层5和缓冲层之间的附着力，缓冲层的材料例如是氮化硅。同时材料包括钼铌合金的第二子金属层53与第一焊盘2'连接，由于钼铌合金具有粘附性，可以保证第一走线层5和第一焊盘2'连接稳固，并且钼铌合金具有导电性，可以保证第一焊盘2'和第一走线层5之间的导电性；第一子走线层52的材料可以包括铜，铜具有很好的导电性，可以确保膜层间的电连接，铜的电阻小可以减少工作时电流损耗，铜的价格低，可以降低阵列基板的制作成本。另外，材料包括钼铌合金的第二子金属层53可以保护第一子走线层52的铜，避免铜被氧化。第一子走线层52的材料可以包括铜，铜具有很好的导电性，可以确保膜层间的电连接，铜的电阻小可以减少工作时电流损耗，铜的价格低，可以降低发 光基板的制作成本。
在具体实施时，如图1所示，第一子走线层52的厚度可以为1μm～3μm。
在具体实施时，如图1所示，第一焊盘(2和2’)的厚度可以为1000埃～8000埃，氧化防护层3的厚度可以为500埃～1500埃。
在具体实施时，如图1所示，第二焊盘4是采用与第一焊盘(2和2’)同层设置的膜层为例的，当然，第二焊盘4也可以采用仅与第一走线层5同层设置，或第二焊盘4同时采用包括与第一走线层5以及第一焊盘(2和2’)同层设置的膜层。
在具体实施时，在本公开实施例提供的上述发光基板中，如图1所示，发光区A1还包括：位于第一走线层5和第一焊盘(2和2’)之间的第一钝化层6，位于第一钝化层6和第一焊盘(2和2’)之间的第一平坦层7，位于氧化防护层3背离衬底基板1一侧且覆盖多个第一焊盘(2和2’)之间区域的第二平坦层8，以及位于氧化防护层3上的第一连接部9。
其中，如图6所示，图1为图6中沿AA'方向的截面示意图，第一走线层5可以包括阳极走线54和阴极走线55(图1未示出)，即阳极走线54和阴极走线55均采用叠层的第一子金属层51、第一子走线层52和第二子金属层53设置，为了减少压降(IR Drop)，第一子走线层52的厚度大于第一焊盘(2和2’)的厚度，第一子走线层52的厚度与Mini-LED背板的产品尺寸正相关。可以采用溅射工艺依次制作第一子金属层51、第一子走线层52和第二子金属层53，第二子金属层53可以保护第一子走线层52，防止第一子走线层52表面氧化。
在具体实施时，如图1所示，第一钝化层6包括位于阳极走线54和阴极走线55之间的部分，以及隔开相邻走线，避免相邻的走线出现错误的电连接，第一钝化层6的材料可以是氮化硅、氧化硅、氮氧化硅等。第一平坦层7覆盖阳极走线54和阴极走线55之间的区域，该第一平坦层7可以是有机膜，用于填平走线之间的缝隙区域，避免使后续工艺出现大段差，保证发光单元绑定时不会发生发光单元位移的问题，从而提高阵列基板的平整度；同时第 一平坦层7也可以起到绝缘的作用。
具体地，如图1所示，氧化防护层3上的第一连接部9的材料为焊接金属材料，例如为锡、锡铜合金、锡银合金、铜等。
具体地，如图1所示，第一钝化层6的厚度可以为1000埃～4000埃。
在具体实施时，在本公开实施例提供的上述发光基板中，如图1所示，绑定区A1还包括：位于第一走线层5和第二焊盘4之间的第二钝化层10，位于第二钝化层10和第二焊盘4之间的第三平坦层20，位于氧化防护层3背离衬底基板1一侧且覆盖多个第二焊盘4之间区域的第四平坦层30，以及位于氧化防护层3上的第二连接部40；其中，
第三平坦层20与第一平坦层7同层设置，可以形成一体结构，其材料可以是有机材料，例如：树脂，用于平坦化，以利于后续工艺(例如第一焊盘2、第二焊盘4等)的制作；第四平坦层30与第二平坦层8同层设置，可以形成一体结构，其材料可以是有机材料，例如：树脂，用于平坦化，以利于后续工艺(例如保护层50)的制作；第二钝化层10与第一钝化层6同层设置，可以形成一体结构，其材料可以是氮氧化硅、氮化硅、氧化硅等。
具体地，如图1所示，第二钝化层10的厚度可以为1000埃～9000埃。
在具体实施时，在本公开实施例提供的上述发光基板中，还可以包括多个发光单元，发光单元可以包括如图7所示的微型发光二极管100。需要说明的是，由于微型发光二极管100包括阳极引脚和阴极引脚，因此一个微型发光二极管100需要通过两个第一焊盘完成绑定。上述多个第一焊盘可以分为多个第一焊盘组，每个第一焊盘组用于绑定一个微型发光二极管、且包括成对设置的阴极焊盘和阳极焊盘，其中与微型发光二极管的阴极引脚绑定的第一焊盘称为阴极焊盘，与微型发光二极管的阳极引脚绑定的第一焊盘称为阳极焊盘。如图6所示，每个第一焊盘组包括成对设置的阴极焊盘2'和阳极焊盘2，阴极焊盘2'和阳极焊盘2包括的膜层结构相同。
如图7所示，微型发光二极管100通过第一连接部9、氧化防护层3与阴极焊盘2'和阳极焊盘2绑定。由于第一连接部9的材料中一般包括金属镍， 因此本公开实施例提供的氧化防护层3的材料为CuNiX，氧化防护层3中的Ni可以和第一连接部9中的Ni结合，提高第一连接部9与氧化防护层3之间的粘附力。
如图7所示，电路板200通过第二连接部40、氧化防护层3与第二焊盘4绑定连接，具体地，电路板200包括印刷电路板、柔性电路板、集成电路芯片等，第二连接部40的材料可以是热固化胶或异方性导电胶。
在具体实施时，在本发明实施例提供的上述发光基板中，如图1和6所示，多个第一焊盘(2和2')分为多组第一焊盘，每组第一焊盘包括成对设置的阴极焊盘2'和阳极焊盘2；
发光基板还包括与多个第一焊盘(2和2')同层设置的第二走线层，第二走线层背离衬底基板1的一侧具有氧化防护层3，第二走线层用于实现多组第一焊盘(2和2')的串联连接或者并联连接，且第二走线层还用于通过贯穿第一平坦层7和第一钝化层6的过孔与第一走线层5电连接。
具体地，如图1和图6所示，第二走线层包括走线11和走线12。如图1所示，走线12和第一焊盘2'为一体结构，图1中用虚线分开走线12和第一焊盘2'。
上述多个第一焊盘组的具体连接方式不做限定。图6中以相邻两个第一焊盘组串联为例进行示意。如图1和图6所示，多个第一焊盘(2和2')可以分为多个第一焊盘组，每个第一焊盘组用于绑定一个微型发光二极管、且包括成对设置的阴极焊盘2'和阳极焊盘2。第一走线层5可以包括阳极走线54和阴极走线55。相邻两组的第一焊盘通过走线11串联；如图1和图6所示，串联的两个第一焊盘组中，其中一组的阳极焊盘2与一条走线12连接，走线12通过贯穿第一钝化层6和第一平坦层7的过孔V1与阳极走线54电连接；阳极走线54通过贯穿第一钝化层6和第一平坦层7的过孔(图1未示出)与一个第二焊盘4电连接；另一组的阴极焊盘与另一条走线12连接，该走线12通过另一贯穿第一钝化层6和第一平坦层7的过孔V1与阴极走线55电连接，阴极走线55通过贯穿第一钝化层6和第一平坦层7的过孔(图1未示出)与 另一第二焊盘4电连接。图6中，阴极焊盘2'、阳极焊盘2、第二焊盘4、走线11和走线12同层设置，采用相同的填充图案示意阴极焊盘2'、阳极焊盘2、第二焊盘4、走线11和走线12；阳极走线54和阴极走线55同层设置，采用相同的填充图案示意阳极走线54和阴极走线55。
可以理解的是，本公开不对发光基板的驱动方式进行限定，可以如图6所示，发光基板采用无源的方式驱动发光单元，或者，也可以通过包括薄膜晶体管的驱动电路向发光单元提供信号，或者，还可以通过微型芯片向发光单元提供信号。
具体地，当通过微型芯片向发光单元提供信号时，每个微型芯片包括多个引脚，发光基板上还包括位于发光区的第三焊盘，用于与微型芯片的引脚绑定连接。第三焊盘的结构与第一焊盘的结构类似，可以采用与第一焊盘相同的膜层结构制作。多个发光单元可以划分为多个灯区，每个灯区包括至少一个发光单元，每个微型芯片用于驱动至少一个灯区的发光单元发光。
在具体实施时，在本发明实施例提供的上述发光基板中，如图1和图7所示，还包括位于氧化防护层3背离衬底基板1一侧的保护层50，保护层50露出氧化防护层3，保护层50的材料可以包括氮氧化硅、氮化硅或氧化硅。
在具体实施时，在本公开实施例提供的上述发光基板中，发光单元可以为迷你发光二极管(英文：Mini Light Emitting Diode，简称：MiniLED)，又称次毫米发光二极管，或微型发光二极管(英文：Micro Light Emitting Diode，简称：Micro LED)。
当本发明实施例提供的发光基板作为背光源时，发光单元可以采用Mini LED，Mini LED的尺寸和节距(Pitch)小，不仅能将调光分区数(Local Dimming Zones)做得更细致，达到高动态范围(High-Dynamic Range，HDR)呈现高对比度效果，还能缩短光学距离(Optical Distance，OD)以降低整机的厚度达到薄型化需求。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括：本发明实施例提供的上述发光基板、电路板和多个发光单元，发光单元可以采用 Mini LED或Micro LED；
多个发光单元通过氧化防护层与发光基板的多个第一焊盘电连接，电路通过氧化防护层与发光基板的多个第二焊盘电连接。
该显示装置具有对比度高、亮度好、色彩还原度高等特点。该显示装置可以是刚性的显示装置，也可以是柔性的显示装置(即可弯曲、可折叠)。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。该显示装置解决问题的原理与前述发光基板相似，因此该显示装置的实施可以参见前述发光基板的实施，重复之处在此不再赘述。
本公开实施例提供的发光基板及显示装置，在采用Cu材料制备完第一焊盘后，在第一焊盘上制备一层材料包括CuNiX的氧化防护层，其中X包括Al、Sn、Pb、Au、Ag、In、Zn、Bi、Mg、Ga、V、W、Y、Zr、Mo、Nb、Pt、Co、Sb其中之一或任意组合元素，由于Ni和X具有抗氧化性，以起到防止氧化防护层表面氧化的作用。另外，本公开实施例通过在第一焊盘上增加防氧化的CuNiX合金膜层，无需额外防氧化工艺即可实现抗氧化性，大大简化了工艺流程，降低量产成本；并且，本公开实施例可以通过靶材溅射的方式沉积CuNiX合金薄膜，提高了量产可行性。并且，本公开实施例提供的CuNiX氧化防护层在高温环境下具有较好的抗氧化性。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (13)

  1. 一种发光基板，其中，包括：
    衬底基板，所述衬底基板具有发光区；
    多个第一焊盘，位于所述衬底基板的一侧，且位于所述发光区，所述第一焊盘的材料包括Cu；
    氧化防护层，位于所述第一焊盘背离所述衬底基板的一侧，所述多个第一焊盘用于通过所述氧化防护层与多个发光单元绑定连接；所述氧化防护层的材料包括CuNiX，其中X包括Al、Sn、Pb、Au、Ag、In、Zn、Bi、Mg、Ga、V、W、Y、Zr、Mo、Nb、Pt、Co、Sb其中之一或任意组合元素。
  2. 如权利要求1所述的发光基板，其中，所述氧化防护层的厚度为10nm-100nm。
  3. 如权利要求1所述的发光基板，其中，所述氧化防护层的材料中，Ni的质量分数和X的质量分数之和占10％～90％。
  4. 如权利要求3所述的发光基板，其中，Cu的质量分数占20％～95％，Ni的质量分数占5％～80％，X的质量分数占10％～40％。
  5. 如权利要求3所述的发光基板，其中，Ni和X的原子比为2～4。
  6. 如权利要求1-5任一项所述的发光基板，其中，所述衬底基板还具有绑定区，所述绑定区包括位于所述衬底基板之上的多个第二焊盘，所述多个第二焊盘用于与电路板绑定连接；所述第二焊盘与所述第一焊盘位于同一膜层，所述第二焊盘背离所述衬底基板的一侧具有所述氧化防护层。
  7. 如权利要求6所述的发光基板，其中，还包括位于所述第一焊盘与所述衬底基板之间的第一走线层，所述第一走线层包括层叠设置的第一子金属层、第一子走线层和第二子金属层；其中，
    所述第一焊盘和所述第二子金属层电连接，所述第二焊盘和所述第二子金属层电连接；
    所述第一子金属层和所述第二子金属层的材料包括钼铌合金，所述第一 子走线层的材料包括铜。
  8. 如权利要求7所述的发光基板，其中，所述发光区还包括：位于所述第一走线层和所述第一焊盘之间的第一钝化层，位于所述第一钝化层和所述第一焊盘之间的第一平坦层，位于所述氧化防护层背离所述衬底基板一侧且覆盖所述多个第一焊盘之间区域的第二平坦层，以及位于所述氧化防护层上的第一连接部。
  9. 如权利要求8所述的发光基板，其中，所述绑定区还包括：位于所述第一走线层和所述第二焊盘之间的第二钝化层，位于所述第二钝化层和所述第二焊盘之间的第三平坦层，位于所述氧化防护层背离所述衬底基板一侧且覆盖所述多个第二焊盘之间区域的第四平坦层，以及位于所述氧化防护层上的第二连接部；其中，
    所述第三平坦层与所述第一平坦层同层设置，所述第四平坦层与所述第二平坦层同层设置，所述第二钝化层与所述第一钝化层同层设置。
  10. 如权利要求8所述的发光基板，其中，所述多个第一焊盘分为多组第一焊盘，每组所述第一焊盘包括成对设置的阴极焊盘和阳极焊盘；
    所述发光基板还包括与所述多个第一焊盘同层设置的第二走线层，所述第二走线层背离所述衬底基板的一侧具有所述氧化防护层，所述第二走线层用于实现多组所述第一焊盘的串联连接或者并联连接，且所述第二走线层还用于通过贯穿所述第一平坦层和所述第一钝化层的过孔与所述第一走线层电连接。
  11. 如权利要求7-10任一项所述的发光基板，其中，还包括位于所述氧化防护层背离所述衬底基板一侧的保护层，所述保护层露出所述氧化防护层，所述保护层的材料包括氮化硅或氧化硅。
  12. 一种显示装置，其中，包括：如权利要求1-11任一项所述的发光基板、电路板和多个发光单元；
    所述多个发光单元通过所述氧化防护层与所述发光基板的多个第一焊盘电连接，所述电路板通过所述氧化防护层与所述发光基板的多个第二焊盘电 连接。
  13. 如权利要求12所述的显示装置，其中，所述发光单元为Mini LED或Micro LED。
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CN113096549A (zh) * 2021-03-31 2021-07-09 合肥鑫晟光电科技有限公司 一种驱动背板及显示装置
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CN105350046A (zh) * 2015-10-23 2016-02-24 衢州顺络电路板有限公司 用于取代金手指的线路板及其制造方法
US20190326329A1 (en) * 2018-04-19 2019-10-24 Innolux Corporation Electronic device
CN113096549A (zh) * 2021-03-31 2021-07-09 合肥鑫晟光电科技有限公司 一种驱动背板及显示装置
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