WO2023184505A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023184505A1
WO2023184505A1 PCT/CN2022/084883 CN2022084883W WO2023184505A1 WO 2023184505 A1 WO2023184505 A1 WO 2023184505A1 CN 2022084883 W CN2022084883 W CN 2022084883W WO 2023184505 A1 WO2023184505 A1 WO 2023184505A1
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Prior art keywords
layer
conductive
conductive pad
base substrate
sub
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PCT/CN2022/084883
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English (en)
French (fr)
Inventor
赵雪
谢晓冬
何敏
张新秀
杜兆宜
庞斌
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方瑞晟科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/084883 priority Critical patent/WO2023184505A1/zh
Priority to CN202280000643.9A priority patent/CN117178363A/zh
Publication of WO2023184505A1 publication Critical patent/WO2023184505A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/142—Energy conversion devices

Definitions

  • the present application relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display device.
  • Mini LED Mini Light Emitting Diode, sub-millimeter light-emitting diode
  • Micro LED Micro Light Emitting Diode, micro light-emitting diode
  • the chip welding process is an important step in preparing the above two types of display products.
  • the chip is prone to poor conduction problems during the welding or repair process, resulting in poor connection between the chip and the array substrate of the display product, thereby causing the display Product yield is reduced and quality deteriorates.
  • an array substrate including:
  • a first conductive layer located on one side of the base substrate, includes a plurality of conductive pad groups, and the conductive pad group includes at least one conductive pad;
  • the second conductive layer is located on the side of the first conductive layer facing away from the base substrate, and the orthographic projection of at least a partial area of each conductive pad in the conductive pad group on the base substrate is consistent with the Orthographic projections of the second conductive layer on the base substrate do not overlap with each other;
  • the thickness of the first conductive layer in the direction perpendicular to the plane of the base substrate is greater than or equal to the thickness of the second conductive layer in the direction perpendicular to the plane of the base substrate.
  • the array substrate further includes a first insulating layer located between the first conductive layer and the second conductive layer, the first insulating layer having a plurality of openings, and the The opening exposes at least a portion of the conductive pad;
  • the orthographic projection of the partial area of the conductive pad exposed by the opening on the base substrate does not overlap with the orthographic projection of the second conductive layer on the base substrate.
  • the array substrate includes a display area
  • the conductive pad group includes a first conductive pad group
  • the first conductive pad group is located in the display area.
  • the first conductive pad group includes a first conductive pad, and an orthographic projection of the first conductive pad on the base substrate at least in the area exposed by the opening is consistent with the Orthographic projections of the second conductive layer on the base substrate do not overlap with each other.
  • the array substrate includes a display area and a peripheral area surrounding the display area; the conductive pad group includes a second conductive pad group, and the second conductive pad group is located in the peripheral area .
  • the second conductive pad group includes a second conductive pad and a third conductive pad
  • the orthographic projection of other areas of the second conductive pad on the base substrate is the same as that of the second conductive layer on the base substrate.
  • the orthographic projections partially overlap;
  • the orthographic projection of the third conductive pad on the base substrate and the orthographic projection of the second conductive layer on the base substrate do not overlap with each other.
  • the second conductive layer includes a plurality of connection lines located in the peripheral area, the second conductive pad is electrically connected to the connection line, and the second conductive pad is located in the peripheral area.
  • the orthographic projection on the base substrate partially overlaps the orthographic projection of the connecting line on the base substrate.
  • the array substrate includes a shielding line, and the peripheral area includes a binding area located on one side of the display area;
  • the main structure of the shielded wire is located in the area other than the binding area in the peripheral area, and both ends of the shielded wire extend to the binding area; the two ends of the shielded wire pass through the
  • the connecting wire is electrically connected to the second conductive pad.
  • the shielded wire covers at least part of each of the connecting wires, and the shielded wire is in direct contact with each of the connecting wires.
  • the first conductive layer includes a first conductive part, the first conductive part includes a ground line located in the display area; the connection line is electrically connected to the ground line.
  • the connecting lines located in the peripheral area except the binding area are electrically connected to the ground line through via holes; the connecting lines located in the binding area
  • the connecting wire is electrically connected to the ground wire through the shielded wire.
  • the peripheral area includes a fan-out area, the fan-out area is located between the binding area and the display area, the fan-out area includes fan-out traces; the third fan-out area is located between the binding area and the display area.
  • Three conductive pads are electrically connected to the first conductive part through the fan-out traces.
  • the binding area includes a first binding sub-area and a second binding sub-area, and the first binding sub-area is located away from the second binding sub-area and the display one side of the district;
  • each of the second conductive pads is located in the first binding sub-region, and each of the third conductive pads is located in the second binding sub-region.
  • each of the second conductive pads is arranged in the same direction, and each of the third conductive pads is arranged in the same direction. Along the arrangement direction of the second conductive pads, every two adjacent conductive pads are arranged in the same direction. There is a first gap between the second conductive pads, and a second gap between every two adjacent third conductive pads along the arrangement direction of the third conductive pads;
  • the number of sub-layers of the first insulating layer filled in the first gap and the second gap are the same, and the number of sub-layers of the first insulating layer filled in the second gap is greater than that of the first gap.
  • the first insulating layer includes a first inorganic sub-layer, a first organic sub-layer, a second organic sub-layer and a second inorganic sub-layer arranged in sequence, and the first inorganic sub-layer in direct contact with the first conductive layer;
  • the orthographic projection of the first organic sub-layer on the base substrate does not overlap with the portion of the base substrate located in the binding area.
  • the orthographic projection of the first organic sub-layer and the second inorganic sub-layer on the base substrate is the same as the orthogonal projection of the second conductive pad on the base substrate. Projections do not overlap;
  • Orthographic projections of the first organic sub-layer and the second inorganic sub-layer on the base substrate and orthographic projections of the third conductive pad on the base substrate do not overlap with each other.
  • At least the first inorganic sub-layer, the second organic sub-layer and the second inorganic sub-layer are arranged in sequence in the first gap, and at least The first inorganic sub-layer, the second organic sub-layer and the second inorganic sub-layer are arranged in sequence.
  • the array substrate further includes a second insulating layer, the second insulating layer is located on a side of the second conductive layer facing away from the base substrate;
  • the second insulating layer fills the first gap and the second gap, and the orthographic projection of the second insulating layer on the base substrate is consistent with at least part of the second conductive pad group.
  • the orthographic projections on the substrate do not overlap with each other.
  • the second insulating layer includes a third inorganic sub-layer and a third organic sub-layer, and the third organic sub-layer is located on a side of the third inorganic sub-layer facing away from the base substrate. one side;
  • the third inorganic sub-layer and the third organic sub-layer are also arranged in sequence in the first gap and the second gap, and the part of the third inorganic sub-layer located in the gap is in contact with the second inorganic sub-layer.
  • the portions of the sublayers located within the gap are in direct contact.
  • the distance between the part of the third organic sub-layer located in the gap and away from the surface of the base substrate and the base substrate along the thickness direction of the base substrate is less than Or equal to the distance between the part of the second organic sub-layer located on the second conductive pad group and away from the surface of the base substrate along the thickness direction of the base substrate to the base substrate.
  • the second insulating layer covers a partial area of the connecting line
  • the shielding wire covers a partial area of the connecting line
  • the partial position of the orthographic outer contour of the second insulating layer on the base substrate is the same as the partial position of the orthographic outer contour of the shielding line on the base substrate. Roughly tangent.
  • the orthographic projection of the second insulating layer on the base substrate overlaps with the orthographic projection of the partial area of the second conductive pad on the base substrate;
  • the orthographic projection of the second insulating layer on the base substrate does not overlap with the orthographic projection of the surface of the third conductive pad away from the base substrate on the base substrate.
  • the array substrate further includes a protective layer covering the area of the first conductive pad exposed at the opening, and the material of the protective layer includes a conductive material.
  • embodiments of the present application provide a display device, including a light-emitting device and an array substrate as described above, where the light-emitting device is electrically connected to the first conductive pad group of the array.
  • the display device further includes a circuit board electrically connected to the second conductive pad group of the array substrate.
  • embodiments of the present application provide a method for preparing an array substrate, which is used to prepare the array substrate as described above.
  • the method includes:
  • the first conductive layer including a plurality of conductive pad groups, the conductive pad group including at least one conductive pad;
  • the first inorganic sub-film and the second inorganic sub-film are patterned to obtain the first inorganic sub-layer and the second inorganic sub-layer; wherein the first insulating layer includes the first inorganic sub-layer. sub-layer, the first organic sub-layer, the second organic sub-layer and the second inorganic sub-layer, the first insulating layer having a plurality of openings exposing at least a portion of the conductive pad area.
  • FIGS. 1A-2B and 9 are schematic structural diagrams of five array substrates in related technologies provided by embodiments of the present application.
  • Figures 3 and 4 are schematic structural diagrams of two first conductive pad groups provided by embodiments of the present application.
  • Figure 5 is a cross-sectional structural view along the A1A2 direction of Figure 4.
  • Figure 6 is a schematic structural diagram of an array substrate for mounting components provided by an embodiment of the present application.
  • Figure 7 is a top structural view of an array substrate provided by an embodiment of the present application.
  • Figure 8 is a schematic structural diagram of a second conductive pad group in the peripheral area of an array substrate according to an embodiment of the present application.
  • Figure 10 is a partial enlarged view of a second conductive pad group provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of a shielded wire located in the peripheral area provided by an embodiment of the present application.
  • Figure 12 is a schematic structural diagram of another shielded line located in the peripheral area provided by an embodiment of the present application.
  • Figure 13 is another cross-sectional structural view along the A1A2 direction of Figure 4;
  • Figure 14 is a cross-sectional structural view along the B1B2 direction in Figure 10 or Figure 11;
  • Figure 15 is a top structural view of a display area provided by an embodiment of the present application.
  • Figure 16 is a top structural view of another display area provided by an embodiment of the present application.
  • An embodiment of the present application provides an array substrate, as shown in Figure 5 and Figure 14, including:
  • the first conductive layer 3 is located on one side of the base substrate 1 and includes a plurality of conductive pad groups W1 and/or W2.
  • the conductive pad groups W1 and/or W2 include at least one conductive pad;
  • the second conductive layer 5 is located on the side of the first conductive layer 3 facing away from the base substrate 1 .
  • the orthographic projection of at least part of each conductive pad in the conductive pad group W1 or W2 on the base substrate 1 is exactly the same as the second conductive layer 5 Orthographic projections on the base substrate do not overlap each other;
  • the thickness of the first conductive layer 3 in the direction perpendicular to the plane of the base substrate 1 is greater than or equal to the thickness of the second conductive layer 5 in the direction perpendicular to the plane of the base substrate 1 .
  • FIG. 5 is a cross-sectional structural view along the A1A2 direction of FIG. 4 .
  • the array substrate may be a sub-millimeter light emitting diode (Mini Light Emitting Diode, Mini LED for short) array substrate; or, the array substrate may be a Micro Light Emitting Diode (Micro LED for short) Array substrate.
  • Mini LED is about 100-300 ⁇ m
  • Micro LED is below 100 ⁇ m.
  • the above-mentioned base substrate 1 may be a glass-based substrate.
  • the base substrate 1 may include an organic resin material such as epoxy resin, triazine, silicone resin, or polyimide.
  • the base substrate 1 may be an FR4 type printed circuit board (PCB), or may be an easily deformable flexible PCB.
  • the base substrate 1 may include a ceramic material such as silicon nitride, AlN, or Al2O3, or a metal or metal compound.
  • the base substrate 1 may be a metal core printed circuit board (MCPCB) or a metal copper clad laminate (MCCL).
  • the array substrate includes a double layer of conductive layers, such as a first conductive layer 3 and a second conductive layer 5, to jointly form a conductive pattern.
  • the thickness of the first conductive layer 3 ranges from 1.5 to 7 ⁇ m, and its material includes copper (Cu).
  • a laminated material such as MoNb/Cu/MoNb can be formed by sputtering, and the bottom layer Used to improve adhesion, the middle layer Cu is used to transmit electrical signals, and the top layer Used to prevent oxidation.
  • the first conductive layer 3 can also be formed by electroplating. Specifically, a seed layer MoNiTi is first formed to increase the grain nucleation density, and then the anti-oxidation layer MoNiTi is formed after Cu electroplating.
  • the first conductive layer 3 may be used to provide various signal lines, such as ground lines, driving lines, and power lines.
  • the first conductive layer 3 may include a plurality of conductive pad groups, each conductive pad group including at least one conductive pad.
  • the conductive pad may be one of a pad or a binding terminal.
  • the conductive pad in the first conductive layer 3 includes a partial area exposed by the opening K in the first insulating layer 4, and a portion covered by the insulating layer located around the opening. area.
  • the first conductive layer 3 may include multiple conductive pad groups including but not limited to the following three situations:
  • the conductive pad group in the first conductive layer includes the first conductive pad group W1 located in the display area.
  • the conductive pad group in the first conductive layer includes a second conductive pad group W2 located in the binding area.
  • the conductive pad group may simultaneously include a first conductive pad group W1 located in the display area and a second conductive pad group W2 located in the binding area.
  • the first conductive pad group W1 is used to electrically connect components
  • the second conductive pad group W2 is used to electrically connect the array substrate and the circuit board to input electrical signals into the array substrate.
  • Components may include light emitting devices and driver chips.
  • the light-emitting device may include a Mini LED light-emitting device or a Micro LED light-emitting device.
  • each first conductive pad group W1 The number of conductive pads included in each first conductive pad group W1 is not limited here. The details can be determined according to product design.
  • the first conductive pad group W1 includes a first conductive pad, and the first conductive pad includes a pad H.
  • the second conductive pad group W2 includes a second conductive pad and a third conductive pad, the second conductive pad includes the bonding terminal BD2 , and the third conductive pad includes the bonding terminal BD1 .
  • the first conductive pad group W1 may include two conductive pads; or, the first conductive pad group W1 may include four conductive pads; or , the first conductive pad group W1 may include six conductive pads.
  • the array substrate also includes a conductive island Mark located in the first conductive layer as shown in Figure 3 or Figure 4, which is used as an alignment mark in subsequent processes.
  • the thickness of the second conductive layer 5 is approximately
  • the material of the second conductive layer 5 includes copper (Cu), and its structure can be, for example, a stacked structure of MoNb/Cu/CuNi.
  • the bottom layer MoNb is used to improve adhesion
  • the middle layer Cu is used to transmit electrical signals
  • the top layer CuNi can be used for both. Anti-oxidation and improved firmness.
  • the second conductive layer 5 may be used to provide leads or traces for connection.
  • Cu1 represents the first conductive layer 3 and Cu2 represents the second conductive layer 5.
  • the plane where the base substrate 1 is located refers to: although the base substrate 1 has a three-dimensional structure, its thickness is usually thin relative to the length and width. It can be understood that the base substrate 1 is a trend The structure of the array substrate is a planar structure, so other structural features in the array substrate are described here with the plane of the base substrate 1 as a reference. In practical applications, the base substrate 1 is not a plane.
  • a first insulating layer 4 is disposed between the first conductive layer 3 and the second conductive layer 5; wherein the first insulating layer 4 may include an inorganic sub-layer and an organic sub-layer.
  • Figure 2B shows the film structure of the binding area in the related art.
  • the overall film layer in the binding area is thicker. Under such circumstances, it is very easy for the film layer to fall off during the bonding process. For example, part of the second conductive layer 5 in the bonding area falls off, resulting in abnormal conduction between the array substrate and the circuit board.
  • the first conductive layer 3 is arranged in a direction perpendicular to the plane of the base substrate 1.
  • the thickness is greater than or equal to the thickness of the second conductive layer 5 in the direction perpendicular to the plane of the base substrate 1, and the conductive pad group is arranged in the first conductive layer 3.
  • the conductive pad group includes a In the case of conductive pads, as shown in Figure 6, it can greatly reduce the probability that the connection layer M3 formed during the array substrate repair (Rework) process penetrates the first conductive pad, and improves the problem of poor conduction of the first conductive pad. , improving the repair yield of the array substrate.
  • connection layer M3 includes an intermetallic compound generated at high temperature between the soldering material and the material of the first conductive pad.
  • the conductive pad group includes conductive pads located in the bonding area, since part of the first conductive layer 3 is used as the second conductive pad in the bonding area and the third conductive pad in the bonding area, relatively Compared with the bonding terminal composed of two conductive layers in the related art, the overall film thickness in the area where the second conductive pad and the third conductive pad are located is reduced, thereby improving the bonding process.
  • the problem of local film layer peeling caused by thicker film layers and a larger number of film layers reduces the difficulty of the bonding process and improves the quality of the array substrate.
  • the array substrate further includes a first insulating layer 4 located between the first conductive layer 3 and the second conductive layer 5.
  • the first insulating layer Having a plurality of openings K, the openings K exposing at least part of the conductive pad;
  • the orthographic projection of the partial area of the conductive pad exposed by the opening K on the base substrate 1 does not overlap with the orthographic projection of the second conductive layer 5 on the base substrate 1 .
  • FIG. 5 and FIG. 13 show that the opening K exposes a partial area of each first conductive pad in the first conductive pad group W1. It can be understood that the opening K exposes the first conductive pad for use with components.
  • FIG. 14 shows that the opening K exposes a partial area of each conductive pad in the second conductive pad group W2.
  • the opening K exposes a partial area of the second conductive pad, or the opening K exposes a third conductive pad. Part of the conductive pad.
  • the size of the opening K in the first insulating layer 4 is not limited here.
  • the openings on the conductive pads in the first conductive pad group W are connected together to form a large-sized opening.
  • the openings of each conductive pad in the second conductive pad group W2 are independently arranged.
  • the depth of the openings located on the second conductive pad group W2 ranges from 0.5 ⁇ m to 3 ⁇ m.
  • the array substrate includes a display area
  • the conductive pad group includes a first conductive pad group
  • the first conductive pad group is located in the display area.
  • the array substrate includes a peripheral area surrounding the display area; the conductive pad group includes a second conductive pad group, and the second conductive pad group is located in the peripheral area.
  • the conductive pad group may simultaneously include a first conductive pad group W1 located in the display area and a second conductive pad group W2 located in the binding area.
  • the conductive pad group includes the first conductive pad group W1 and the second conductive pad group.
  • Group W2 the first insulating layer 4 includes a plurality of sub-layers;
  • the number of sub-layers in the portion of the first insulating layer 4 located between the conductive pads in the first conductive pad group W1 is greater than or equal to the number of sub-layers in the portion of the first insulating layer 4 located between the conductive pads in the second conductive pad group W2 The number of sub-layers between parts.
  • the number of sub-layers of the portion of the first insulating layer 4 located between two adjacent first conductive pad groups W1 is equal to the number of sub-layers of the first insulating layer 4 located between the conductive pads in the first conductive pad group W1 Parts have an equal number of sublayers.
  • the number of sub-layers in the portion of the first insulating layer 4 located between two adjacent first conductive pad groups is 4 layers, and the portion of the first insulating layer 4 located between the conductive pads in the first conductive pad group
  • the number of sub-layers is 4 layers, and the number of sub-layers of the portion of the first insulating layer 4 located between the conductive pads in the second conductive pad group W2 is 3 layers.
  • the sub-layers of the portion of the first insulating layer 4 located between two adjacent first conductive pad groups are, in order, the first inorganic sub-layer 41, the first organic sub-layer 42, the second organic sub-layer 43 and the third inorganic sub-layer 41.
  • Two inorganic sub-layers 44 however, the sub-layers of the portion of the first insulating layer 4 located between the conductive pads in the second conductive pad group W2 are the first inorganic sub-layer 41, the second organic sub-layer 43 and the second inorganic sub-layer 44 in sequence. Sublayer 44.
  • the material of the inorganic sub-layer in the first insulating layer 4 may include any one of silicon nitride, silicon oxide, and silicon oxynitride, and the material of the organic sub-layer in the first insulating layer 4 may be any one of silicon nitride, silicon oxide, and silicon oxynitride. Includes resin.
  • the first organic sub-layer 42 is provided near the location of the first conductive pad group W1 located in the display area. However, there is no first organic sub-layer 42 located near the location of the second conductive pad group W2 located in the peripheral area.
  • the first organic sub-layer 42 is provided so that during the process of preparing the array substrate, the first organic sub-layer 42 fills the uneven areas existing in the display area so that the surface of the substrate tends to be flat.
  • the organic material of the second organic sub-layer 43 has better leveling properties and is easier to flow into the grooves existing in the binding area, thereby filling the gaps between the conductive pads in the second conductive pad group W2 in the binding area. The gap is to facilitate the subsequent bonding process, reduce the difficulty of the bonding process, and improve the yield of the bonding process.
  • the conductive pad group includes a first conductive pad group
  • the area between two adjacent first conductive pads in the first conductive pad group has a gap
  • an insulating layer is also provided in the gap.
  • the first inorganic sub-layer 41, the first organic sub-layer 42, the second organic sub-layer 43 and the second inorganic sub-layer 44 are arranged in this gap in sequence.
  • the leveling property of the material of the second organic sub-layer 43 in the array substrate can be further improved, promoting the material of the second organic sub-layer 43 to flow more fully from the display area to the peripheral area, and reducing the difficulty of the preparation process;
  • the possible short circuit between two adjacent conductive pads in the same first conductive pad W1 is avoided, thereby improving the production yield of the array substrate.
  • the first conductive pad group W1 includes the first conductive pad.
  • the orthographic projection of the first conductive pad, such as the pad H as shown in FIG. 13 , at least in the area exposed by the opening K on the base substrate 1 and the orthographic projection of the second conductive layer 5 on the base substrate 1 are different from each other. overlap.
  • the first conductive pad is disposed in the display area for installing components.
  • the orthographic projection of the first insulating layer 4 on the base substrate 1 overlaps with the orthographic projection of the edge region of the first conductive pad group on the base substrate 1 .
  • the orthographic projection of the first organic sub-layer 42 on the base substrate 1 does not overlap with the orthographic projection of the first conductive pad group on the base substrate 1.
  • the first inorganic sub-layer 41 and the second organic sub-layer 42 do not overlap with each other.
  • the orthographic projections of the layer 43 and the second inorganic sub-layer 44 on the base substrate 1 respectively overlap with the orthographic projections of the first conductive pad group on the base substrate 1, and the first inorganic sub-layer 41 and the second organic sub-layer 43 overlap with the orthographic projection of the first conductive pad group on the base substrate 1.
  • the layer 43 and the second inorganic sub-layer 44 cover the edge area of each first conductive pad in the first conductive pad group, such as the pad H.
  • the first insulating layer 4 between two adjacent first conductive pads in the first conductive pad group W1 is not shown in FIG. 13 , and its film layer structure is similar to the film layer structure of the edge region of the first conductive pad group.
  • the second conductive layer 5 includes a bonding pad.
  • the second conductive layer 5 includes a bonding pad.
  • the thickness of the second insulating layer 6 covering the edge of the pad is thin, metal ions can easily penetrate the second insulating layer 6 and be deposited between the edge of the pad and the second insulating layer 6.
  • the subsequent process After the part of the nickel gold layer deposited between the edge of the pad and the second insulating layer 6 falls off, it will cause the two adjacent pads to be connected, causing a short circuit problem.
  • the first conductive pad such as the pad H
  • the first conductive layer 3 is covered with the first insulating layer
  • the number of sub-layers of the second insulating layer is smaller. Since the number of sub-layers of the first insulating layer 4 is larger than the number of sub-layers of the second insulating layer 6, the thickness of the insulating layer covering the edge of the first conductive pad is thicker, so that the edge of the first conductive pad has multiple protective layers.
  • the second conductive pad group W2 includes a second conductive pad and a third conductive pad
  • the orthographic projection of other areas of the second conductive pad on the base substrate 1 is consistent with the second conductive layer.
  • the orthographic projections of 5 on the base substrate 1 partially overlap; wherein, the opening of the first insulating layer 4 is not drawn in FIGS. 7 and 11 .
  • the second conductive layer 5 includes a plurality of connection lines P1 and P2 located in the peripheral area, the second conductive pad, such as the binding electrode BD2, is electrically connected to the connection lines P1 and P2, and the third
  • the orthographic projection of the two conductive pads, such as the bonding electrode BD2 on the base substrate 1 partially overlaps the orthographic projection of the connection line P1 on the base substrate 1 .
  • the orthographic projection of the third conductive pad, such as the bonding electrode BD1 , on the base substrate 1 does not overlap with the orthographic projection of the second conductive layer 5 on the base substrate.
  • the second conductive pad and the third conductive pad are provided in the binding area for binding with the external circuit board.
  • the second conductive pad group by arranging the conductive pad group to include a second conductive pad group, the second conductive pad group includes a second conductive pad and a third conductive pad.
  • the binding terminal in the related art as shown in Figure 2B For part of the first conductive layer and part of the second conductive layer, embodiments of the present application provide a reduction in the overall film thickness in the area where the second conductive pad and the third conductive pad are located, thereby improving the bonding process due to The problem of local film peeling caused by thicker film layers and a large number of film layers reduces the difficulty of the bonding process and improves the quality of the array substrate.
  • the array substrate includes a shielded line CS, and the peripheral area (including B1, B2, F, and Z) includes a binding area (including B1 and B2) located on one side of the display area AA. );
  • the main structure of the shielded wire CS is located in areas F and Z other than the binding area in the peripheral area. Both ends of the shielded wire CS extend to the binding areas B1 and B2; the two ends of the shielded wire CS pass through the binding areas respectively.
  • the connection line P1 of the area is electrically connected to the second conductive pad.
  • the shielded wire CS covers at least part of the connection lines P1 and P2, and the shielded wire CS is in direct contact with the connection lines P1 and P2.
  • the shielded line CS covers at least a partial area of each connection line P1 and P2, including but is not limited to the following situations: the shielded line CS covers a partial area of each connection line; or the shielded line CS covers a portion of each connection line. All areas.
  • the shielded wire CS when the shielded wire CS covers the entire area of each connection line, the shielded wire CS is in direct contact with a partial area of the connecting line and is also in contact with a partial area of the surface of the second insulating layer 6 away from the connecting line.
  • the specific situation will be described below in conjunction with the positional relationship between the shielded wire CS and the second insulating layer 6 .
  • the orthographic projection shape of the shielding line CS on the base substrate 1 is an unclosed ring shape.
  • the material of the shielding line CS includes conductive glue, such as silver glue.
  • the thickness of the silver glue can be about 200 ⁇ m, and the size of the silver glue in the direction from the display area to the peripheral area can be about 500 ⁇ m.
  • “left and right” refers to the dimensional error caused by fluctuations in the preparation process, which is within the acceptable range of the product.
  • a protective layer or cover plate can also be provided on the shielded wire CS to avoid damage to the shielded wire CS.
  • the material of the protective layer and the cover plate can be an inorganic material, such as glass, silicon nitride, silicon oxide or silicon oxynitride; of course, the material of the protective layer and the cover plate can also be an organic material, such as resin.
  • the first conductive layer 3 includes a first conductive part, and the first conductive part includes a ground line GND located in the display area AA; the connection lines P1 and P2 are electrically connected to the ground line GND. connect.
  • the first conductive part may also include drive lines VLED and power lines PWR as shown in Figure 15; or, the first conductive part may also include drive lines VR and VGB, and data lines as shown in Figure 16 DATA, vertical power line VCC-V.
  • the power line in Figure 16 also includes a horizontal power line VCC-H located in the second conductive layer 5.
  • the vertical power line VCC-V is electrically connected to the horizontal power line VCC-H through the via hole VIA.
  • the horizontal power line VCC -H is electrically connected to the first conductive pad.
  • the first conductive part also includes a first lead 31 and a second lead 32
  • the second conductive layer also includes a trace 51, in which the first conductive pad group W1 used to install the driver chip first passes through
  • the connection traces such as the connection traces 51 located in the second conductive layer 5, are electrically connected to the first conductive pad group W1 for installing the light-emitting device, and are then electrically connected to the driving line VLED through the connection traces 51;
  • the first conductive part also includes first leads 31 and second leads 32
  • the second conductive layer also includes traces 51 , in which the first conductive pad group W1 for mounting the driver chip is first connected with the first conductive pad group W1 for mounting the driver chip.
  • the first conductive pad group W1 of the light-emitting device is electrically connected, and then is electrically connected to the driving line VR or VGB through the connecting wire 51.
  • the array substrate shown in Figure 16 includes two driving lines, and the light-emitting device whose emitting color is red A driving line VR is connected, and the green and blue light-emitting devices share a driving line VGB.
  • the first conductive pad goes in a direction parallel to the base substrate 1 to the nearest second conductive layer (such as a trace). 51) there is a distance between them.
  • the first conductive pad is moved in a direction parallel to the base substrate 1 to the nearest second conductive layer. The larger the distance, the better. This is to prevent metal ions from penetrating into the vicinity of the second conductive layer and affecting the electrical properties of the second conductive layer when the protective layer is formed on the first conductive pad.
  • connection line includes a connection line P1 located in the binding area and a connection line P2 located outside the binding area.
  • the connection line P2 located in the area Z in the peripheral area except the bonding area is directly electrically connected to the ground line GND through a via hole (not shown in Figure 7);
  • the connection line P1 located in the bonding area is connected to the ground line GND through the shielded line CS.
  • the ground wire GND is electrically connected.
  • the ground wire GND is drawn as an example extending in the vertical direction.
  • the connection line P2 is set on the upper side of the display area AA, and the connection line P2 is set on the upper side of the display area AA. lower side. In practical applications, the connection line P2 can be set on the left side of the display area AA, or can also be set on the right side of the display area.
  • the connecting wire P2 is set at one end of the ground wire GND and is electrically connected to the ground wire GND through a via.
  • the shielded wire CS covers part of the connecting wire P2, and the connecting wire P1 is set at one end of the ground wire GND. Near the other end, the connection wire P1 is electrically connected to the ground wire GND through the shielded wire CS.
  • the connecting wires P1 and P2 are both electrically connected to the shielded wire CS, and each connecting wire P1 and P2 is directly or indirectly electrically connected to the ground wire GND, so that the shielded wire CS is electrically connected to the ground wire GND. .
  • the shielded wire CS by arranging the shielded wire CS, the antistatic capability of the array substrate can be improved; on the other hand, by electrically connecting the shielded wire CS with the ground wire GND, the resistance of the ground wire GND can be reduced and the signal transmission capability of the line can be improved.
  • a partial area of the first conductive layer or the second conductive layer is used as a shielding line.
  • the shielding line CS is not provided in the first conductive layer 3 and the second conductive layer 5, and
  • the material of the shielding line CS is conductive glue instead of metal material.
  • the peripheral area includes a fan-out area F.
  • the fan-out area F is located between the binding area (including B1 and B2) and the display area AA.
  • the fan-out area F includes a fan-out area.
  • Outgoing trace FL; the third conductive pad, such as BD1, is electrically connected to the first conductive part through the fan-out trace FL.
  • the first conductive part includes a ground line GND, and a third conductive pad, such as BD1 , is electrically connected to the ground line GND through the fan-out line FL.
  • the first conductive part may further include a driving line VLED and a power line PWR as shown in FIG. 15 .
  • a part of the third conductive pad, such as BD1 is electrically connected to the drive line VLED through the fan-out trace FL, and another part of the third conductive pad, such as BD1, is electrically connected to the power line PWR through the fan-out trace FL.
  • the first conductive part may also include driving lines VR and VGB, a data line DATA, and a vertical power line VCC-V as shown in FIG. 16 .
  • a part of the third conductive pad, such as BD1 is electrically connected to the drive lines VR and VGB through the fan-out trace FL.
  • Another part of the third conductive pad, such as BD1 is electrically connected to the data line DATA through the fan-out trace FL.
  • Another part of the third conductive pad is electrically connected to the data line DATA through the fan-out trace FL.
  • Pads, such as BD1 are electrically connected to vertical power lines VCC-V through fan-out traces FL.
  • the first conductive portion may also include some Dummy traces.
  • a part of the third conductive pad, such as BD1 is electrically connected to the Dummy trace through the fan-out trace FL.
  • the description related to “a part of the third conductive pad, another part of the third conductive pad, and another part of the third conductive pad” in the embodiments of the present application does not mean that only these three parts of the third conductive pad are included.
  • the pads, in some embodiments, may also include a fourth part and a third conductive pad, and the details may be determined according to the actual situation.
  • the meanings of relevant descriptions elsewhere in this application are similar to those here, and will not be described again.
  • the fan-out trace FL may be located in the first conductive layer 3; or the fan-out trace FL may be located in the second conductive layer 5; or a part of the fan-out trace FL is located in the first conductive layer 3, Another part of the fan-out trace FL is located on the second conductive layer 5 .
  • the specifics can be determined based on actual product requirements and are not limited here.
  • the binding area includes a first binding sub-area B1 and a second binding sub-area B2, and the first binding sub-area B1 is located in the second binding sub-area B1.
  • the sub-area B2 is on the side away from the display area AA; wherein, each second conductive pad, such as BD2, is located in the first binding sub-area B1, and each third conductive pad, such as BD1, is located in the second binding sub-area B2.
  • Both the second conductive pad and the third conductive pad include bonding terminals.
  • the second conductive pads are arranged in sequence along the same direction, such as the OA direction, and the third conductive pads are arranged in sequence along the same direction, such as the OA direction.
  • the arrangement direction of the second conductive pads can also be other than the OA direction
  • the arrangement direction of the third conductive pads can also be other directions except the OA direction, and the details can be determined according to the actual situation.
  • this application does not limit whether the arrangement direction of the second conductive pads and the arrangement direction of the third conductive pads are the same.
  • each second conductive pad and each third conductive pad are arranged in two rows in the first binding sub-area B1 and the second binding sub-area B2, so that the second binding sub-area
  • Each third conductive pad in area B2 is electrically connected to the fan-out line FL, and the fan-out line FL is electrically connected to one end of the ground line GND; so that each second conductive pad in the first binding sub-area B1 passes through the connection line P1 in sequence , the shielded wire CS is electrically connected to the other end of the ground wire GND.
  • each third conductive pad may be disposed in a left region of each second conductive pad, and another part of each third conductive pad may be disposed in a right region of each second conductive pad, so that The size of the peripheral area is further reduced.
  • the second conductive pads are arranged in sequence along the same direction, such as the OA direction, and the third conductive pads are arranged in sequence along the same direction, such as the OA direction; along In the arrangement direction OA of the second conductive pads, there is a first gap between every two adjacent second conductive pads, such as between BD2. Along the arrangement direction OA of the third conductive pads, there is a first gap between every two adjacent third conductive pads.
  • the number of sub-layers of the first insulating layer 4 filled in the first gap and the second gap is the same, and the number of sub-layers of the first insulating layer 4 filled in the second gap is the same.
  • the number of layers is greater than the number of sub-layers of the first insulating layer located on the surface of the second conductive pad group W2 facing away from the base substrate 1 .
  • the thickness of each sub-layer in the first insulating layer 4 filled in the first gap in a direction perpendicular to the plane of the base substrate 1 is approximately equal to the thickness of the first insulating layer 4 filled in the second gap.
  • the thickness of each sub-layer in the direction perpendicular to the plane of the base substrate 1 where approximately equal means that the thickness fluctuates within an allowable error range due to fluctuations in the preparation process. The meaning of the plane where the substrate substrate is located is similar to the previous one and will not be described again.
  • the second conductive pad group W2 includes a second conductive pad and a third conductive pad, wherein the number of sub-layers of the first insulating layer 4 located on the surface portion of the second conductive pad away from the base substrate 1 is equal to The number of sub-layers of the first insulating layer 4 located on the side of the third conductive pad facing away from the base substrate 1 .
  • the thickness of the sub-layer of the first insulating layer 4 located at the portion of the surface of the second conductive pad facing away from the base substrate 1 is approximately equal to the thickness of the first insulating layer 4 along a direction perpendicular to the plane of the base substrate 1 The thickness of the sub-layer located on the side of the third conductive pad facing away from the base substrate 1 .
  • the first insulating layer 4 can fill the first gap. and the second gap, to avoid the impact of the existing gap on the alignment process during the bonding process, improve the yield of the bonding process, and reduce the difficulty of the bonding process; on the other hand, when the second conductive pad group W2 is away from the substrate Part of the surface of the substrate 1 is provided with fewer or thinner sub-layers of the first insulating layer 4, so that the thickness of the film layer on the second conductive pad group W2 in the binding area is thinner to avoid interference with the circuit board or flexible circuit board.
  • the film layer in the binding area may partially detach or be poorly bound.
  • the first insulating layer 4 includes a first inorganic sub-layer 41 , a first organic sub-layer 42 , a second organic sub-layer 43 and a second inorganic sub-layer 41 .
  • the inorganic sub-layer 44, the first inorganic sub-layer 41 and the first conductive layer are in direct contact;
  • FIG. 14 is a cross-sectional view along the B1B2 direction in FIG. 10 or 11.
  • the orthographic projection of the first organic sub-layer 42 on the base substrate 1 intersects with the portion of the base substrate 1 located in the binding area. No overlap.
  • the orthographic projection of the first organic sub-layer 42 on the base substrate 1 overlaps with the portion of the base substrate 1 located in the display area.
  • the distance h1 between the surface of the first organic sublayer 42 facing away from the base substrate 1 and the base substrate 1 along the thickness direction of the base substrate 1 is less than or equal to the first conductive pad,
  • the pad H is the distance h2 from the surface away from the base substrate 1 to the base substrate 1 in the direction of the thickness of the base substrate 1 .
  • the first organic sub-layer 42 is not provided in the portion of the array substrate located in the binding area, but the first organic sub-layer 42 is provided in the portion of the array substrate located in the display area.
  • the first organic sub-layer 42 is provided in the display area as shown in Figure 13, but is not provided in the binding area as shown in Figure 14.
  • the first organic sub-layer 42 is provided to first fill the grooves existing in the display area, so that the surface of the substrate tends to be flat.
  • the organic material of the second organic sub-layer 43 has better leveling properties and can flow into the binding area more easily to fill the first gap L1 and the second gap L2 existing in the binding area. It should be noted that the above filling is not necessarily full.
  • the orthographic projection of the first organic sub-layer 42 and the second inorganic sub-layer 44 on the base substrate is aligned with the second conductive pad, such as BD2, on the substrate.
  • the orthographic projections on the base substrate 1 do not overlap with each other; the orthographic projections of the first organic sub-layer 42 and the second inorganic sub-layer 44 on the base substrate 1 and the third conductive pad, such as BD1, on the base substrate 1 Orthographic projections do not overlap each other.
  • the first organic sub-layer 42 and the second inorganic sub-layer 44 are not provided on the surface of the second conductive pad away from the base substrate 1 and on the surface of the third conductive pad away from the base substrate 1 , to thin the thickness of the film layer where the second conductive pad and the third conductive pad are located, so as to facilitate the binding of the second conductive pad and the third conductive pad to the output terminals in the circuit board respectively, while reducing the difficulty of the binding process.
  • At least a first inorganic sub-layer 41 , a second organic sub-layer 43 and a second inorganic sub-layer 44 are provided in the first gap L1 in sequence, and in the second gap L2 At least a first inorganic sub-layer 41, a second organic sub-layer 43 and a second inorganic sub-layer 44 are provided in sequence.
  • the minimum distance h3 between the surface of the second inorganic sub-layer 44 facing away from the base substrate 1 and the base substrate 1 along the thickness direction of the base substrate 1 is smaller than the second conductive pad (or the third conductive pad).
  • the distance h4 between the surface of the conductive pad (conductive pad) facing away from the base substrate 1 and the base substrate 1 along the thickness direction of the base substrate 1 is smaller than the second conductive pad (or the third conductive pad).
  • the array substrate further includes a second insulating layer 6 , and the second insulating layer 6 is located on the side of the second conductive layer 5 facing away from the base substrate 1 ;
  • the second insulating layer 6 fills the first gap L1 and the second gap L2, and the orthogonal projection of the second insulating layer 6 on the base substrate 1 is the same as the orthogonal projection of at least part of the second conductive pad group W2 on the base substrate. Do not overlap with each other.
  • the second insulating layer 6 includes a third inorganic sub-layer 61 and a third organic sub-layer 62, and the third organic sub-layer 62 is located on the side of the third inorganic sub-layer 61 away from the base substrate 1;
  • a third inorganic sub-layer 61 and a third organic sub-layer 62 are also disposed in the first gap L1 and the second gap L2 in sequence.
  • the portion of the third inorganic sub-layer 61 located in the gaps L1 and L2 and the second inorganic sub-layer 44 are located The portions within gaps L1 and L2 are in direct contact.
  • the orthographic projection of the second insulating layer 4 on the base substrate 1 overlaps with the orthographic projection of a partial area of the second conductive pad, such as a partial area of BD2, on the base substrate 1, And the orthographic projection of the second insulating layer 4 on the base substrate 1 does not overlap with the orthographic projection of another part of the second conductive pad on the base substrate 1; The orthographic projection does not overlap with the orthographic projection of the surface of the third conductive pad, such as BD1, away from the base substrate 1 on the base substrate.
  • the second insulating layer 4 may cover part of the second conductive pad within the dotted frame area in FIG. 12 , and expose the remaining portion of the second conductive pad. Area is used to cover the shield wire CS. In this way, the exposed part of the second conductive pad can be prevented from being oxidized or corroded, thereby protecting the second conductive pad.
  • the second insulating layer in order to reduce the difficulty of the preparation process, can be provided within the dotted line frame in Figure 12. That is to say, the second insulating layer 4 can cover part of each second conductive pad, and also It can extend to cover the area between two adjacent second conductive pads.
  • the second insulating layer 6 is not provided in the area where the third conductive pad, such as BD1 , is located.
  • the distance h5 between the portion of the third organic sub-layer 62 located in the gaps L1 and L2 away from the surface of the base substrate 1 along the thickness direction of the base substrate 1 and the base substrate 1 is less than or equal to The portion of the second organic sub-layer 43 located on the second conductive pad group (including the second conductive pad and the third conductive pad) away from the surface of the base substrate 1 along the thickness direction of the base substrate 1 to between the base substrate 1 Distance h6.
  • the distance h5 between the part of the third organic sub-layer 62 located in the gaps L1 and L2 away from the surface of the base substrate 1 along the thickness direction of the base substrate 1 and the base substrate 1 is equal to the position of the second organic sub-layer 43 .
  • the distance h6 from the surface of the second conductive pad group (including the second conductive pad and the third conductive pad) away from the base substrate 1 along the thickness direction of the base substrate 1 to the base substrate 1 is drawn as an example.
  • the first gap L1 and the second gap L2 are filled as flatly as possible through the first insulating layer 4 and the second insulating layer 6, but the third organic sub-layer 62 in the gap cannot be made to protrude from the third gap.
  • the part of the second organic sub-layer 43 located on the second conductive pad group can improve the accuracy of the alignment process in the bonding process. In addition, it can also avoid the second conductive pad caused by the insulating layer filled in the gap being too high. The group is poorly bonded to the circuit board.
  • the second insulating layer 6 covers part of the connection line P2, and the shielding wire CS covers part of the connection line P2.
  • the partial position of the orthographic projection of the second insulating layer 6 on the base substrate 1 overlaps with the partial position of the orthographic projection of the shielding line CS on the base substrate 1 .
  • the second insulating layer 6 covers a part of the connecting line and is in direct contact with this area
  • the shielding line CS covers another part of the connecting line and is in direct contact with this area.
  • the shielding line CS also extends to the second The insulating layer 6 is away from a part of the surface of the connecting line and is in direct contact with this part of the second insulating layer 6 .
  • the sum of the line width d3 of the shielding line CS and the width d4 of the portion of the second insulating layer 6 covering the connection line P2 is greater than the length d5 of the connection line P2.
  • the line width d3 of the shielding line CS is equal to The sum of the widths d4 of the portions of the second insulating layer 6 covering the connection line P2 is equal to the length d5 of the connection line P2.
  • a portion of the orthographic outline of the second insulating layer 6 on the base substrate 1 is substantially tangent to a portion of the orthographic outline of the shielding line CS on the base substrate 1 . In this way, the exposed part of the second conductive pad can be prevented from being oxidized or corroded, thereby protecting the second conductive pad.
  • Approximately tangent means that the partial position of the orthographic projection outer contour of the second insulating layer 6 on the base substrate 1 and the partial position of the orthographic outer contour of the shielding line CS on the base substrate 1 fluctuate within the allowable error range. .
  • the dimension d2 of the connection line P2 located in the peripheral area except the binding area along the direction OA perpendicular to the reference plane is less than or equal to the edge of the ground line GND.
  • the dimension d6 in the direction OA perpendicular to the reference plane, and the dimension d2 of the connection line P1 electrically connected to the second conductive pad in the direction OA perpendicular to the reference plane is less than or equal to the size of the second conductive pad in the direction OA perpendicular to the reference plane.
  • d1; the extension direction OB of the connecting line and the thickness direction OC of the base substrate 1 are respectively parallel to the reference surface.
  • connection line covering the area on the side of the second conductive pad or the area covering the side of the ground line
  • causing climbing causing cracks or breaks in some areas of the connection line, thereby improving the quality of the array substrate.
  • the array substrate further includes a protective layer M4.
  • the protective layer M4 covers the first conductive pad, such as the pad H, and the area exposed at the opening K, protecting
  • the material of layer M4 includes electrically conductive material.
  • the number of pads included in a first conductive pad group W1 is not limited here. For example, it can be 2, 3, 4, 6 or 8, and the specific number can be determined according to the actual situation.
  • the material of the protective layer M4 includes nickel and/or gold.
  • the welding material preferentially reacts with the material of the protective layer M4 to generate a metal interlayer compound to form the connecting layer M3 to play a connecting role.
  • the protective layer M4 plays a role in connecting the first conductive pad. Protection, wherein the connection layer M3 includes a metal interlayer compound.
  • the array substrate provided by the embodiment of the present application also includes Dummy bonding electrodes (Dummy BD1) and some Dummy traces. Of course, it also includes other structures and components such as the black matrix layer 8 and the buffer layer 2 in Figure 2A. Here Only the structures and components related to the invention are introduced. For other structures and components included in the array substrate, reference can be made to related technologies.
  • Embodiments of the present application provide a display device, including a light-emitting device and the above array substrate, and the light-emitting device is electrically connected to the first conductive pad group.
  • the display device may further include a driving chip for providing a driving signal to the display device.
  • the light-emitting device may include a Mini LED light-emitting device or a Micro LED light-emitting device.
  • Mini LED is about 100-300 ⁇ m
  • Micro LED is below 100 ⁇ m.
  • the cross-sectional size (parameters such as length, width, diagonal or diameter) of the light-emitting device is between about 100 ⁇ m and about 300 ⁇ m; the thickness of the light-emitting device is, for example, 100 ⁇ m.
  • “About” includes but is not limited to the following situations: Affected by fluctuations in the manufacturing process, the size of the component fluctuates. It should be noted that the size fluctuation is within the allowable error range.
  • the display device further includes a circuit board, and the circuit board is electrically connected to the second conductive pad group.
  • the circuit board may include a flexible circuit board.
  • the number of circuit boards included in the display device is not limited here, and can be determined based on actual conditions.
  • the display device can be used as a backlight device, or the display device can also be directly used as a display, which is not limited here.
  • the first conductive layer 3 of the array substrate is usually provided with signal lines with high resistance requirements such as ground lines and driving lines.
  • the thickness in the direction perpendicular to the plane of the base substrate 1 is greater than or equal to the thickness of the second conductive layer 5 in the direction perpendicular to the plane of the base substrate 1.
  • the conductive pad group is arranged in the first conductive layer 3.
  • connection layer M3 includes an intermetallic compound generated at high temperature between the soldering material and the material of the first conductive pad.
  • part of the first conductive layer 3 is used as the second conductive pad of the bonding area and the third conductive pad of the bonding area, compared with the bonding terminal composed of two conductive layers in the related art,
  • the embodiments of the present application provide a reduction in the overall film thickness in the area where the second conductive pad and the third conductive pad are located, thereby improving local problems caused by thicker film layers and a larger number of film layers during the bonding process.
  • the problem of film layer peeling reduces the difficulty of the bonding process and improves the quality of the display device prepared from the array substrate.
  • display devices which can be televisions, laptops, tablets, wearable display devices, mobile phones, car displays, navigation, e-books, digital photo frames, advertising light boxes, and any other device with display functions. product or part.
  • Embodiments of the present application provide a method for preparing an array substrate, which is used to prepare the array substrate as mentioned above.
  • the method includes:
  • the first conductive layer includes a plurality of conductive pad groups, and the conductive pad group includes at least one conductive pad;
  • thin film refers to the entire film layer formed before patterning.
  • a patterned first organic sub-layer and a patterned second organic sub-layer are first prepared so that the second inorganic film covers the first conductive layer.
  • the second inorganic film is patterned, so that during the formation of the second conductive layer, the second inorganic film protects the exposed partial areas of the first conductive layer (for example, the exposed areas of the conductive pads). (partial area of the first conductive layer) plays a protective role to avoid corrosion to the exposed partial area of the first conductive layer, thereby improving the reliability of the array substrate.

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Abstract

本申请提供了一种阵列基板及其制备方法、显示装置，涉及显示技术领域，包括：衬底基板；第一导电层，位于衬底基板的一侧，包括多个导电垫组，导电垫组包括至少一个导电垫；第二导电层，位于第一导电层背离衬底基板的一侧，导电垫组中各导电垫的至少部分区域在衬底基板上的正投影与第二导电层在衬底基板上的正投影互不交叠；其中，第一导电层在沿垂直于衬底基板所在平面方向上的厚度大于或等于第二导电层在沿垂直于衬底基板所在平面方向上的厚度。该阵列基板的修复良率高，品质好。

Description

阵列基板及其制备方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
随着显示技术的快速发展，Mini LED(Mini Light Emitting Diode，次毫米发光二极管)和Micro LED(Micro Light Emitting Diode，微型发光二极管)的显示产品引起人们广泛的关注。芯片的焊接过程是制备上述两类显示产品的重要步骤，相关技术中，芯片在焊接或修复过程中极易出现导通不良的问题，造成芯片与显示产品的阵列基板的连接不良，进而造成显示产品良率降低、品质下降。
发明内容
本申请的实施例采用如下技术方案：
第一方面，本申请的实施例提供了一种阵列基板，包括：
衬底基板；
第一导电层，位于所述衬底基板的一侧，包括多个导电垫组，所述导电垫组包括至少一个导电垫；
第二导电层，位于所述第一导电层背离所述衬底基板的一侧，所述导电垫组中各所述导电垫的至少部分区域在所述衬底基板上的正投影与所述第二导电层在所述衬底基板上的正投影互不交叠；
其中，所述第一导电层在沿垂直于所述衬底基板所在平面方向上的厚度大于或等于所述第二导电层在沿垂直于所述衬底基板所在平面方向上的厚度。
在本申请的一些实施例中，所述阵列基板还包括位于所述第一导电层和所述第二导电层之间的第一绝缘层，所述第一绝缘层具有多个开口，所述开口暴露出所述导电垫的至少部分区域；
其中，所述导电垫由所述开口暴露出的部分区域在所述衬底基板上 的正投影与所述第二导电层在所述衬底基板上的正投影互不交叠。
在本申请的一些实施例中，所述阵列基板包括显示区，所述导电垫组包括第一导电垫组，所述第一导电垫组位于所述显示区。
在本申请的一些实施例中，所述第一导电垫组包括第一导电垫，所述第一导电垫至少在所述开口暴露出的区域在所述衬底基板上的正投影与所述第二导电层在所述衬底基板上的正投影互不交叠。
在本申请的一些实施例中，所述阵列基板包括显示区以及围绕所述显示区的周边区；所述导电垫组包括第二导电垫组，所述第二导电垫组位于所述周边区。
在本申请的一些实施例中，所述第二导电垫组包括第二导电垫和第三导电垫；
除所述开口暴露出的所述第二导电垫的区域外，所述第二导电垫的其它区域在所述衬底基板上的正投影与所述第二导电层在所述衬底基板上的正投影部分交叠；
所述第三导电垫在所述衬底基板上的正投影与所述第二导电层在所述衬底基板上的正投影互不交叠。
在本申请的一些实施例中，所述第二导电层包括位于所述周边区的多条连接线，所述第二导电垫与所述连接线电连接，且所述第二导电垫在所述衬底基板上的正投影与所述连接线在所述衬底基板上的正投影部分交叠。
在本申请的一些实施例中，所述阵列基板包括屏蔽线，所述周边区包括位于所述显示区一侧的绑定区；
所述屏蔽线的主体结构位于所述周边区中除所述绑定区之外的区域，所述屏蔽线的两端延伸至所述绑定区；所述屏蔽线的两端分别通过所述连接线与所述第二导电垫电连接。
在本申请的一些实施例中，所述屏蔽线覆盖各所述连接线的至少部分区域，且所述屏蔽线与各所述连接线直接接触。
在本申请的一些实施例中，所述第一导电层包括第一导电部，所述第一导电部包括位于所述显示区的接地线；所述连接线与所述接地线电 连接。
在本申请的一些实施例中，位于所述周边区除所述绑定区之外的区域中的所述连接线通过过孔与所述接地线电连接；位于所述绑定区的所述连接线通过所述屏蔽线与所述接地线电连接。
在本申请的一些实施例中，所述周边区包括扇出区，所述扇出区位于所述绑定区与所述显示区之间，所述扇出区包括扇出走线；所述第三导电垫通过所述扇出走线与所述第一导电部电连接。
在本申请的一些实施例中，所述绑定区包括第一绑定子区和第二绑定子区，所述第一绑定子区位于所述第二绑定子区远离所述显示区的一侧；
其中，各所述第二导电垫位于所述第一绑定子区，各所述第三导电垫位于所述第二绑定子区。
在本申请的一些实施例中，各所述第二导电垫沿同一方向排列，各所述第三导电垫沿同一方向排列，沿所述第二导电垫的排列方向上，每相邻两个所述第二导电垫之间具有第一间隙，沿所述第三导电垫的排列方向上，每相邻两个所述第三导电垫之间具有第二间隙；
所述第一间隙和所述第二间隙中填充的所述第一绝缘层的子层数量相同，且所述第二间隙中填充的所述第一绝缘层的子层数量大于所述第一绝缘层位于所述第二导电垫组背离所述衬底基板的表面的部分的子层数量。
在本申请的一些实施例中，所述第一绝缘层包括依次设置的第一无机子层、第一有机子层、第二有机子层和第二无机子层，所述第一无机子层和所述第一导电层直接接触；
其中，所述第一有机子层在所述衬底基板上的正投影与所述衬底基板位于所述绑定区的部分互不交叠。
在本申请的一些实施例中，所述第一有机子层和所述第二无机子层在所述衬底基板上的正投影与所述第二导电垫在所述衬底基板上的正投影互不交叠；
所述第一有机子层和所述第二无机子层在所述衬底基板上的正投 影与所述第三导电垫在所述衬底基板上的正投影互不交叠。
在本申请的一些实施例中，所述第一间隙内至少依次设置有所述第一无机子层、所述第二有机子层和所述第二无机子层，所述第二间隙内至少依次设置有所述第一无机子层、所述第二有机子层和所述第二无机子层。
在本申请的一些实施例中，所述阵列基板还包括第二绝缘层，所述第二绝缘层位于所述第二导电层背离所述衬底基板的一侧；
其中，所述第二绝缘层填充所述第一间隙和所述第二间隙，且所述第二绝缘层在所述衬底基板上的正投影与至少部分所述第二导电垫组在所述衬底基板上的正投影互不交叠。
在本申请的一些实施例中，所述第二绝缘层包括第三无机子层和第三有机子层，所述第三有机子层位于所述第三无机子层背离所述衬底基板的一侧；
所述第一间隙和所述第二间隙内还依次设置有所述第三无机子层和所述第三有机子层，所述第三无机子层位于间隙内的部分与所述第二无机子层位于所述间隙内的部分直接接触。
在本申请的一些实施例中，所述第三有机子层位于所述间隙的部分远离所述衬底基板的表面沿所述衬底基板厚度方向上到所述衬底基板之间的距离小于或等于所述第二有机子层位于所述第二导电垫组上的部分远离所述衬底基板的表面沿所述衬底基板厚度方向上到所述衬底基板之间的距离。
在本申请的一些实施例中，所述第二绝缘层覆盖所述连接线的部分区域，所述屏蔽线覆盖所述连接线的部分区域。
在本申请的一些实施例中，所述第二绝缘层在所述衬底基板上的正投影外轮廓的部分位置与所述屏蔽线在所述衬底基板上的正投影外轮廓的部分位置大致相切。
在本申请的一些实施例中，所述第二绝缘层在所述衬底基板上的正投影与所述第二导电垫的部分区域在所述衬底基板上的正投影交叠；
所述第二绝缘层在所述衬底基板上的正投影与所述第三导电垫远 离衬底基板的表面在所述衬底基板上的正投影互不交叠。
在本申请的一些实施例中，所述阵列基板还包括保护层，所述保护层覆盖所述第一导电垫在所述开口处暴露出的区域，所述保护层的材料包括导电材料。
第二方面，本申请的实施例提供了一种显示装置，包括发光器件以及如上所述的阵列基板，所述发光器件与所述阵列的第一导电垫组电连接。
在本申请的一些实施例中，所述显示装置还包括电路板，所述电路板与所述阵列基板的第二导电垫组电连接。
第三方面，本申请的实施例提供了一种阵列基板的制备方法，应用于制备如前文所述的阵列基板，所述方法包括：
提供所述衬底基板；
形成所述第一导电层，所述第一导电层包括多个导电垫组，所述导电垫组包括至少一个导电垫；
在所述第一导电层上依次形成第一无机子薄膜、图案化的第一有机子层、图案化的第二有机子层和第二无机子薄膜；
形成所述第二导电层；
对所述第一无机子薄膜和所述第二无机子薄膜进行图案化处理，得到所述第一无机子层和所述第二无机子层；其中，第一绝缘层包括所述第一无机子层、所述第一有机子层、所述第二有机子层和所述第二无机子层，所述第一绝缘层具有多个开口，所述开口暴露出所述导电垫的至少部分区域。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1A-图2B、图9为本申请的实施例提供的相关技术中的五种阵列基板的结构示意图；
图3和图4为本申请的实施例提供的两种第一导电垫组的结构示意图；
图5为图4沿A1A2方向的一种截面结构图；
图6为本申请的实施例提供的一种安装元器件的阵列基板的结构示意图；
图7为本申请的实施例提供的一种阵列基板的俯视结构图；
图8为本申请的实施例提供的一种阵列基板周边区的第二导电垫组的结构示意图；
图10为本申请的实施例提供的一种第二导电垫组的局部放大图；
图11为本申请的实施例提供的一种位于周边区的屏蔽线的结构示意图；
图12为本申请的实施例提供的另一种位于周边区的屏蔽线的结构示意图；
图13为图4沿A1A2方向的另一种截面结构图；
图14为图10或图11中沿B1B2方向的一种截面结构图；
图15为本申请的实施例提供的一种显示区的俯视结构图；
图16为本申请的实施例提供的另一种显示区的俯视结构图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本 申请保护的范围。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本申请的示意性图解，并非一定是按比例绘制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在本申请的实施例中，采用“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行部分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
本申请的实施例提供了一种阵列基板，结合图5和图14所示，包括：
衬底基板1；
第一导电层3，位于衬底基板1的一侧，包括多个导电垫组W1和/或W2，导电垫组W1和/或W2包括至少一个导电垫；
第二导电层5，位于第一导电层3背离衬底基板1的一侧，导电垫组W1或W2中各导电垫的至少部分区域在衬底基板1上的正投影与第二导电层5在衬底基板上的正投影互不交叠；
其中，第一导电层3在沿垂直于衬底基板1所在平面方向上的厚度大于或等于第二导电层5在沿垂直于衬底基板1所在平面方向上的厚度。
图5为图4沿A1A2方向的一种截面结构图。
在示例性的实施例中，上述阵列基板可以为次毫米发光二极管 (Mini Light Emitting Diode，简称Mini LED)阵列基板；或者，上述阵列基板可以为微型发光二极管(Micro Light Emitting Diode，简称Micro LED)阵列基板。其中，Mini LED的尺寸约为100-300μm，Micro LED的尺寸为100μm以下。
在示例性的实施例中，上述衬底基板1可以为玻璃基衬底。
在一些示例实施例中，衬底基板1可以包括诸如环氧树脂、三嗪、硅树脂或聚酰亚胺的有机树脂材料。例如，衬底基板1可以是FR4类型印刷电路板(PCB)，或者可以是易于变形的柔性PCB。
在一些示例实施例中，衬底基板1可以包括诸如氮化硅、AlN或Al2O3的陶瓷材料，或者包括金属或金属化合物。例如，衬底基板1可以是金属芯印刷电路板(MCPCB)或金属覆铜层压板(MCCL)。
在示例性的实施例中，阵列基板包括双层的导电层，例如，第一导电层3和第二导电层5，以共同形成导电图案。
示例性的，第一导电层3的膜层厚度范围为1.5～7μm，其材料包括铜(Cu)。具体的，可以通过溅射的方式形成例如MoNb/Cu/MoNb的叠层材料，底层
Figure PCTCN2022084883-appb-000001
用于提高粘附力，中间层Cu用于传递电信号，顶层
Figure PCTCN2022084883-appb-000002
用于防氧化。或者，还可以通过电镀的方式形成第一导电层3，具体的，先形成种子层MoNiTi提高晶粒成核密度，电镀Cu之后再形成防氧化层MoNiTi。
在示例性的实施例中，第一导电层3可以用于设置各种信号线，例如，接地线、驱动线和电源线。
在示例性的实施例中，第一导电层3可以包括多个导电垫组，每个导电垫组包括至少一个导电垫。其中，导电垫可以为焊盘或绑定端子中的一种。
示例性的，如图13和图14所示，第一导电层3中的导电垫包括由第一绝缘层4中的开口K暴露出的部分区域，以及被位于开口周围的绝缘层覆盖的部分区域。
第一导电层3可以包括多个导电垫组包括但不限于以下三种情况：
第一种，第一导电层中的导电垫组包括位于显示区的第一导电垫组 W1。
第二种，第一导电层中的导电垫组包括位于绑定区的第二导电垫组W2。
第三种，导电垫组可以同时包括位于显示区的第一导电垫组W1和位于绑定区的第二导电垫组W2。
其中，第一导电垫组W1用于与元器件电连接，第二导电垫组W2用于将阵列基板与电路板电连接，以向阵列基板中输入电信号。元器件可以包括发光器件和驱动芯片。
例如，发光器件可以包括Mini LED发光器件或者Micro LED发光器件。
这里对于每个第一导电垫组W1中包括的导电垫的数量不进行限定。具体可以根据产品设计确定。
在一些实施例中，如图13所示，第一导电垫组W1包括第一导电垫，第一导电垫包括焊盘H。
在一些实施例中，如图7所示，第二导电垫组W2包括第二导电垫和第三导电垫，第二导电垫包括绑定端子BD2，第三导电垫包括绑定端子BD1。
示例性的，参考图3、图4、图15或图16所示，第一导电垫组W1中可以包括两个导电垫；或者，第一导电垫组W1中可以包括四个导电垫；或者，第一导电垫组W1中可以包括六个导电垫。
需要说明的是，阵列基板中还包括如图3或如图4所示的位于第一导电层中的导电岛Mark，用作后续工艺中的对位标记。
在示例性的实施例中，第二导电层5的厚度约为
Figure PCTCN2022084883-appb-000003
第二导电层5的材料包括铜(Cu)，其结构可以为例如MoNb/Cu/CuNi的叠层结构，底层MoNb用于提高粘附力，中间层Cu用于传递电信号，顶层CuNi可兼顾防氧化和提高牢固性。
在示例性的实施例中，第二导电层5可以用于设置起到连接作用的引线或走线。
需要说明的是，本申请的实施例以第一导电层3和第二导电层5的 材料均包括铜为例进行说明，故在本申请的附图中，Cu1代表第一导电层3，Cu2代表第二导电层5。
还需要说明的是，衬底基板1所在平面指的是：尽管衬底基板1为三维立体结构，但通常相对于长度和宽度，其厚度较薄，可以理解为衬底基板1是一个趋向于平面的结构，故而此处以衬底基板1所在平面为参照对阵列基板中的其它结构特征进行描述。在实际应用中，衬底基板1并不是一个平面。
在示例性的实施例中，第一导电层3和第二导电层5之间设置有第一绝缘层4；其中，第一绝缘层4可以包括无机子层和有机子层。
参考图1A和图1B所示，相关技术中，在第二导电层5中设置焊盘时，在制备阵列基板的过程中，当安装在焊盘上的元器件7发生异常需要拆除时，拆除的过程会在焊盘上形成凹坑，此时，焊盘的最小厚度非常薄，在重新焊接元器件的过程中，焊接材料和剩余的焊盘材料在高温下发生反应生成金属间化合物，极容易穿透焊盘，焊盘发生断裂的风险非常高。
图2B示出了相关技术中绑定区的膜层结构，结合图2B和图9所示，由于绑定区的绑定电极需要与电路板电连接，在绑定区整体膜层较厚的情况下，绑定过程中极易发生膜层脱落的情况，例如，绑定区的第二导电层5的部分区域脱落，以致阵列基板与电路板导通异常。
在本申请的实施例中，由于第一导电层3中通常设置接地线、驱动线等对电阻要求较高的信号线，第一导电层3在沿垂直于衬底基板1所在平面方向上的厚度大于或等于第二导电层5在沿垂直于衬底基板1所在平面方向上的厚度，将导电垫组设置在第一导电层3中，第一方面，在导电垫组包括位于显示区的导电垫的情况下，如图6所示，可以大大降低了在阵列基板修复(Rework)过程中形成的连接层M3穿透第一导电垫的概率，改善了第一导电垫导通不良的问题，提高了阵列基板的修复良率。其中，连接层M3包括焊接材料与第一导电垫的材料在高温下生成的金属间化合物。第二方面，在导电垫组包括位于绑定区的导电垫的情况下，由于将第一导电层3的部分区域作为绑定区的第二导电垫和 绑定区的第三导电垫，相较于相关技术中由两层导电层构成的绑定端子，本申请的实施例提供的第二导电垫和第三导电垫所在的区域的整体膜层厚度降低，从而改善了在绑定工艺过程中由于膜层较厚大、膜层数量较多造成的局部膜层脱落的问题，降低了绑定的工艺难度，提高了阵列基板的品质。
在本申请的一些实施例中，参考图5、图13和图14所示，阵列基板还包括位于第一导电层3和第二导电层5之间的第一绝缘层4，第一绝缘层具有多个开口K，开口K暴露出导电垫的至少部分区域；
其中，导电垫由开口K暴露出的部分区域在衬底基板1上的正投影与第二导电层5在衬底基板1上的正投影互不交叠。
示例性的，图5和图13示出了开口K暴露出第一导电垫组W1中的各第一导电垫的部分区域，可以理解，开口K暴露出了第一导电垫用于与元器件接触的连接面，其中，该连接面在衬底基板1上的正投影与第二导电层5在衬底基板1上的正投影互不交叠。
示例性的，图14示出了开口K暴露出第二导电垫组W2中的各导电垫的部分区域，例如，开口K暴露出第二导电垫的部分区域，或者，开口K暴露出第三导电垫的部分区域。
这里对于上述第一绝缘层4中的开口K的尺寸不进行限定。图13中，第一导电垫组W中各导电垫上的开口连通在一起构成一个大尺寸的开口。图14中，第二导电垫组W2中各导电垫的开口独立设置。
在示例性的实施例中，位于第二导电垫组W2上的开口的深度范围为0.5μm-3μm。
在一些实施例中，阵列基板包括显示区，导电垫组包括第一导电垫组，第一导电垫组位于显示区。
在一些实施例中，阵列基板包括围绕显示区的周边区；导电垫组包括第二导电垫组，第二导电垫组位于周边区。
在一些实施例中，导电垫组可以同时包括位于显示区的第一导电垫组W1和位于绑定区的第二导电垫组W2，导电垫组包括第一导电垫组W1和第二导电垫组W2，第一绝缘层4包括多个子层；
在一些实施例中，对比图13和图14可知，第一绝缘层4位于相邻两个第一导电垫组W1之间的部分的子层数量大于或等于第一绝缘层4位于第二导电垫组W2中各导电垫之间的部分的子层数量。
在一些实施例中，第一绝缘层4位于第一导电垫组W1中各导电垫之间的部分的子层数量大于或等于第一绝缘层4位于第二导电垫组W2中各导电垫之间的部分的子层数量。
在一些实施例中，第一绝缘层4位于相邻两个第一导电垫组W1之间的部分的子层数量与第一绝缘层4位于第一导电垫组W1中各导电垫之间的部分的子层数量相等。
示例性的，第一绝缘层4位于相邻两个第一导电垫组之间的部分的子层数量为4层，第一绝缘层4位于第一导电垫组中的导电垫之间的部分的子层数量为4层，第一绝缘层4位于第二导电垫组W2中各导电垫之间的部分的子层数量为3层。
示例性的，第一绝缘层4位于相邻两个第一导电垫组之间的部分的子层依次为第一无机子层41、第一有机子层42、第二有机子层43和第二无机子层44，然而，第一绝缘层4位于第二导电垫组W2中各导电垫之间的部分的子层依次为第一无机子层41、第二有机子层43和第二无机子层44。
在示例性的实施例中，第一绝缘层4中的无机子层的材料可以包括氮化硅、氧化硅和氮氧化硅中的任意一种，第一绝缘层4中的有机子层的材料包括树脂。
对比图13和图14可知，在位于显示区的第一导电垫组W1所在的位置附近设置有第一有机子层42，然而，在位于周边区的第二导电垫组W2所在的位置附近未设置第一有机子层42，这样，在制备阵列基板的过程中，第一有机子层42填充显示区内存在的不平坦区域，使得基板的表面趋于平坦，在制备第二有机子层43时，第二有机子层43的有机材料流平性更好，更容易流入绑定区中存在的凹槽中，从而填充绑定区中第二导电垫组W2中的各导电垫之间的间隙，以利于后续绑定工艺，降低绑定工艺难度，提高绑定过程的良率。
示例性的，在导电垫组包括第一导电垫组的情况下，第一导电垫组中相邻两个第一导电垫之间的区域具有间隙，该间隙中也设置有绝缘层，具体的，该间隙中依次设置有第一无机子层41、第一有机子层42、第二有机子层43和第二无机子层44。这样，一方面，可以进一步的提高第二有机子层43的材料在阵列基板中的流平性，促进第二有机子层43的材料更充足的从显示区流入周边区，降低制备工艺难度；另一方面，避免同一第一导电垫W1中每相邻两个导电垫之间可能发生短路的情况，提高阵列基板的制备良率。
在本申请的一些实施例中，在导电垫组包括第一导电垫组的情况下，第一导电垫组W1包括第一导电垫。
第一导电垫，例如如图13所示的焊盘H，至少在开口K暴露出的区域在衬底基板1上的正投影与第二导电层5在衬底基板1上的正投影互不交叠。
示例性的，第一导电垫设置在显示区，用于安装元器件。
参考图13所示，第一绝缘层4在衬底基板1上的正投影与第一导电垫组的边缘区域在衬底基板1上的正投影存在交叠。
示例性的，第一有机子层42在衬底基板1上的正投影与第一导电垫组在衬底基板1上的正投影互不交叠，第一无机子层41、第二有机子层43和第二无机子层44在衬底基板1上的正投影分别与第一导电垫组在衬底基板1上的正投影部分交叠，且第一无机子层41、第二有机子层43和第二无机子层44覆盖第一导电垫组中各第一导电垫，例如焊盘H的边缘区域。图13中未示意出第一导电垫组W1中相邻两个第一导电垫之间的第一绝缘层4，其膜层结构与第一导电垫组的边缘区域的膜层结构类似。
在相关技术中，参考图2A所示，第二导电层5包括焊盘，在阵列基板的制备过程中，为了提高修复良率，在焊盘背离衬底基板1的表面制备镍金层时，由于焊盘边缘上覆盖的第二绝缘层6的厚度较薄，金属离子极易穿透第二绝缘层6，沉积在焊盘边缘与第二绝缘层6之间的位置，在后续工艺中，沉积在焊盘边缘与第二绝缘层6之间部分镍金层脱 落后，会导致相邻两个焊盘导通，造成短路的问题。
在本申请的实施例中，通过将第一导电垫例如焊盘H设置在第一导电层3中，使得第一导电层3上覆盖第一绝缘层，相较于将焊盘做在第二导电层5中，第二绝缘层的子层数量较少，由于第一绝缘层4的子层数量较第二绝缘层6的子层数量多，使得第一导电垫边缘覆盖的绝缘层的厚度较厚，这样，第一导电垫的边缘具有多层保护层，在制备第一导电垫的保护层M4(镍和/或金)时，金属离子不易穿透第一无机子层41、第二有机子层43和第二无机子层44渗入第一导电垫上，避免了第一导电垫边缘区域形成镍金，从而避免相邻的第一导电垫之间发生短路。
在本申请的一些实施例中，在导电垫组包括第二导电垫组的情况下，第二导电垫组W2包括第二导电垫和第三导电垫；
如图7和图11所示，除开口K暴露出的第二导电垫，例如绑定电极BD2的区域外，第二导电垫的其它区域在衬底基板1上的正投影与第二导电层5在衬底基板1上的正投影部分交叠；其中，图7和图11中并未绘制出第一绝缘层4的开口。
示例性的，如图7所示，第二导电层5包括位于周边区的多条连接线P1和P2，第二导电垫，例如绑定电极BD2，与连接线P1和P2电连接，且第二导电垫，例如绑定电极BD2，在衬底基板1上的正投影与连接线P1在衬底基板1上的正投影部分交叠。
第三导电垫，如图7所示，例如绑定电极BD1，在衬底基板1上的正投影与第二导电层5在衬底基板上的正投影互不交叠。
示例性的，第二导电垫和第三导电垫设置在绑定区，用于与外接电路板绑定在一起。
在本申请的实施例中，通过设置导电垫组包括第二导电垫组，第二导电垫组包括第二导电垫和第三导电垫，相较于如图2B相关技术中的绑定端子包括部分第一导电层和部分第二导电层而言，本申请的实施例提供的第二导电垫和第三导电垫所在的区域的整体膜层厚度降低，从而改善了在绑定工艺过程中由于膜层较厚大、膜层数量较多造成的局部膜层脱落的问题，降低了绑定的工艺难度，提高了阵列基板的品质。
在本申请的一些实施例中，参考图7所示，阵列基板包括屏蔽线CS，周边区(包括B1、B2、F和Z)包括位于显示区AA一侧的绑定区(包括B1和B2)；
屏蔽线CS的主体结构位于周边区中除绑定区之外的区域F和Z中，屏蔽线CS的两端延伸至绑定区B1和B2中；屏蔽线CS的两端分别通过位于绑定区的连接线P1与第二导电垫电连接。
在本申请的一些实施例中，参考图7所示，屏蔽线CS覆盖各连接线P1和P2的至少部分区域，且屏蔽线CS与各连接线P1和P2直接接触。
在示例性的实施例中，屏蔽线CS覆盖各连接线P1和P2的至少部分区域包括但不限于以下情况：屏蔽线CS覆盖各连接线的部分区域；或者，屏蔽线CS覆盖各连接线的全部区域。
需要说明的是，在屏蔽线CS覆盖各连接线的全部区域的情况下，屏蔽线CS和连接线的部分区域直接接触，还和第二绝缘层6远离连接线的表面的部分区域接触。具体情况结合下文中屏蔽线CS与第二绝缘层6的位置关系进行说明。
在示例性的实施例中，屏蔽线CS在衬底基板1上的正投影形状为不封闭的环形。
在示例性的实施例中，屏蔽线CS的材料包括导电胶，例如银胶。
再例如，银胶的厚度可为200μm左右，银胶沿显示区指向周边区的方向上的尺寸可为500μm左右。其中，“左右”的指的是由于制备工艺波动造成的尺寸误差，在产品的可接受范围。
在实际应用中，屏蔽线CS上还可以设置一层保护层或盖板，以避免屏蔽线CS损坏。
该保护层和盖板的材料可以为无机材料，例如，玻璃、氮化硅、氧化硅或氮氧化硅；当然，该保护层和盖板的材料还可以为有机材料，例如树脂。
在本申请的一些实施例中，参考图7所示，第一导电层3包括第一导电部，第一导电部包括位于显示区AA的接地线GND；连接线P1和 P2与接地线GND电连接。
示例性的，第一导电部还可以包括如图15中所示的驱动线VLED，电源线PWR；或者，第一导电部还可以包括如图16中所示的驱动线VR和VGB、数据线DATA，纵向的电源线VCC-V。其中，图16中的电源线还包括位于第二导电层5中的横向电源线VCC-H，纵向的电源线VCC-V通过过孔VIA与横向电源线VCC-H电连接，横向电源线VCC-H与第一导电垫电连接。
具体的，在图15中，第一导电部还包括第一引线31和第二引线32，第二导电层还包括走线51，其中，用于安装驱动芯片的第一导电垫组W1先通过连接走线，例如位于第二导电层5中的连接走线51，与用于安装发光器件的第一导电垫组W1电连接，再通过连接走线51与驱动线VLED电连接；
在图16中，第一导电部还包括第一引线31和第二引线32，第二导电层还包括走线51，其中，用于安装驱动芯片的第一导电垫组W1先与用于安装发光器件的第一导电垫组W1电连接，再通过连接走线51与驱动线VR或VGB电连接，其中，图16中所示的阵列基板包括两种驱动线，发光颜色为红色的发光器件连接一种驱动线VR，发光颜色为绿色和蓝色的发光器件共用一种驱动线VGB。
在示例性的实施例中，对于如图15和图16中所示的第一导电垫，第一导电垫沿平行于衬底基板1的方向上到与其最近的第二导电层(例如走线51)之间具有一段距离。对于在第一导电垫上设置保护层(镍金)的产品，在设计和制备工艺允许的范围内，第一导电垫沿平行于衬底基板1的方向上到与其最近的第二导电层之间的距离越大越好。以避免在第一导电垫上形成保护层时，金属离子渗入第二导电层附近，对第二导电层的电性能造成影响。
在本申请的实施例中，连接线包括位于绑定区中的连接线P1和位于绑定区之外的连接线P2。其中，位于周边区除绑定区之外的区域Z中的连接线P2通过过孔(图7中未示意)直接与接地线GND电连接；位于绑定区的连接线P1通过屏蔽线CS与接地线GND电连接。
在图7中，以接地线GND沿竖直方向延伸为例进行绘制，此时，为例方便连接，将连接线P2设置在显示区AA的上侧，将连接线P2设置在显示区AA的下侧。在实际应用中，连接线P2可以设置在显示区AA的左侧，或者，还可以设置在显示区的右侧。无论接地线沿何方向设置，连接线P2设置在接地线GND的一端，并通过过孔与接地线GND电连接，屏蔽线CS覆盖连接线P2的部分区域，连接线P1设置在接地线GND的另一端附近，且连接线P1通过屏蔽线CS与接地线GND电连接。
在本申请的实施例中，连接线P1和P2均与屏蔽线CS电连接，且各连接线P1和P2均直接或间接的与接地线GND电连接，使得屏蔽线CS与接地线GND电连接。这样，一方面，通过设置屏蔽线CS，能够提高阵列基板的抗静电能力；另一方面，通过屏蔽线CS与接地线GND电连接，能够降低接地线GND的电阻，提高线路的信号传输能力。
相关技术中，采用第一导电层或第二导电层的部分区域作为屏蔽线，然而，本申请的实施例中，屏蔽线CS未设置在第一导电层3和第二导电层5中，且设置屏蔽线CS的材料为导电胶，而非金属材料，这样，避免了在周边区中设置第一导电层或第二导电层对切割工艺的影响；另外，对于材料为导电胶的屏蔽线CS，由于在切割工艺之后才制备屏蔽线CS，需要预留的切割边距也较小，且屏蔽线CS对切割工艺影响较小，能够显著减小阵列基板的周边区的尺寸，从而给显示区预留更多的设计空间，有利于制备窄边框的显示产品。
在本申请的一些实施例中，参考图7所示，周边区包括扇出区F，扇出区F位于绑定区(包括B1和B2)与显示区AA之间，扇出区F包括扇出走线FL；第三导电垫，例如BD1，通过扇出走线FL与第一导电部电连接。
在示例性的实施例中，第一导电部包括接地线GND，第三导电垫，例如BD1，通过扇出走线FL与接地线GND电连接。
在一些实施例中，第一导电部还可以包括如图15中所示的驱动线VLED，电源线PWR。一部分第三导电垫，例如BD1，通过扇出走线FL 与驱动线VLED电连接，另一部分第三导电垫，例如BD1，通过扇出走线FL与电源线PWR电连接。
或者，第一导电部还可以包括如图16中所示的驱动线VR和VGB、数据线DATA，纵向的电源线VCC-V。一部分第三导电垫，例如BD1，通过扇出走线FL与驱动线VR和VGB电连接，另一部分第三导电垫，例如BD1，通过扇出走线FL与数据线DATA电连接，又一部分第三导电垫，例如BD1，通过扇出走线FL与纵向的电源线VCC-V电连接。
在一些实施例中，第一导电部还可以包括一些Dummy走线。一部分第三导电垫，例如BD1，通过扇出走线FL与Dummy走线电连接。
需要说明的是，本申请的实施例中涉及到的“一部分第三导电垫，另一部分第三导电垫，又一部分第三导电垫”相关的描述，并不代表只包括这三部分第三导电垫，在一些实施例中，还可以包括第四部分第三导电垫，具体可以根据实际情况确定。另外，本申请的其它地方相关的描述的含义与此处类似，不再赘述。
在示例性的实施例中，扇出走线FL可以位于第一导电层3中；或者，扇出走线FL可以位于第二导电层5中；或者，一部分扇出走线FL位于第一导电层3，另一部分扇出走线FL位于第二导电层5。具体可以根据实际产品需求确定，这里不进行限定。
在本申请的一些实施例中，参考图7和图8所示，绑定区包括第一绑定子区B1和第二绑定子区B2，第一绑定子区B1位于第二绑定子区B2远离显示区AA的一侧；其中，各第二导电垫，例如BD2，位于第一绑定子区B1，各第三导电垫，例如BD1，位于第二绑定子区B2，第二导电垫和第三导电垫均包括绑定端子。
在示例性的实施例中，各第二导电垫沿同一方向，例如OA方向，依次排列，各第三导电垫沿同一方向，例如OA方向，依次排列。
在实际应用中，第二导电垫的排列方向还可以为除OA方向的其它方向，第三导电垫的排列方向还可以为除OA方向的其它方向，具体可以根据实际情况确定。另外，本申请中对于第二导电垫的排列方向和第三导电垫的排列方向是否相同不进行限定。
在本申请的实施例中，通过将各第二导电垫和各第三导电垫分两排分别设置在第一绑定子区B1和第二绑定子区B2中，使得第二绑定子区B2中的各第三导电垫与扇出走线FL电连接，扇出走线FL与接地线GND的一端电连接；使得第一绑定子区B1中的各第二导电垫依次通过连接线P1、屏蔽线CS与接地线GND的另一端电连接，这样，可以减少扇出走线FL的数量，增大了扇出区F中的设计空间，同时缩小了扇出区F的尺寸，能够很大程度上减小了周边区的尺寸，有利于窄边框产品的制备。
在一些实施例中，各第三导电垫中的一部分可以设置在各第二导电垫的左侧区域，各第三导电垫中的另一部分可以设置在各第二导电垫的右侧区域，以进一步减小了周边区的尺寸。
在本申请的一些实施例中，参考图10和图11所示，各第二导电垫沿同一方向，例如OA方向，依次排列，各第三导电垫沿同一方向例如OA方向，依次排列；沿第二导电垫的排列方向OA上，每相邻两个第二导电垫之间，例如BD2之间，具有第一间隙，沿第三导电垫的排列OA方向上，每相邻两个第三导电垫之间，例如BD1之间，具有第二间隙；第一间隙和第二间隙中填充的第一绝缘层4的子层数量相同，且第二间隙中填充的第一绝缘层4的子层数量大于第一绝缘层位于第二导电垫组W2背离衬底基板1的表面的部分的子层数量。
在示例性的实施例中，第一间隙中填充的第一绝缘层4中各子层沿垂直于衬底基板1所在平面方向上的厚度大约等于第二间隙中填充的第一绝缘层4中各子层沿垂直于衬底基板1所在平面方向上的厚度，其中，大约等于指的是受制备工艺波动影响，厚度在可允许的误差范围内波动。衬底基板所在平面的含义与前文类似，不再赘述。
在示例性的实施例中，第二导电垫组W2包括第二导电垫和第三导电垫，其中，第一绝缘层4位于第二导电垫背离衬底基板1的表面部分的子层数量等于第一绝缘层4位于第三导电垫背离衬底基板1一侧的部分的子层数量。
在示例性的实施例中，第一绝缘层4位于第二导电垫背离衬底基板 1的表面的部分的子层沿垂直于衬底基板1所在平面方向上的厚度大约等于第一绝缘层4位于第三导电垫背离衬底基板1一侧的部分的子层的厚度。
在本申请的实施例中，通过在第一间隙和第二间隙中设置数量较多或厚度较厚的第一绝缘层4的子层，一方面，使得第一绝缘层4能够填充第一间隙和第二间隙，避免存在的间隙在绑定工艺中对对位过程的影响，提高了绑定工艺的良率，降低绑定工艺难度；另一方面，在第二导电垫组W2背离衬底基板1的表面的部分设置较少或较薄的第一绝缘层4的子层，使得绑定区的第二导电垫组W2上的膜层厚度较薄，避免在与电路板或柔性电路板绑定过程中造成绑定区的膜层局部脱离或绑定不良的问题。
在本申请的一些实施例中，结合图13和图14所示，第一绝缘层4包括依次设置的第一无机子层41、第一有机子层42、第二有机子层43和第二无机子层44，第一无机子层41和第一导电层直接接触；
其中，图14为图10或图11中沿B1B2方向的截面图，在图14中，第一有机子层42在衬底基板1上的正投影与衬底基板1位于绑定区的部分互不交叠。
在示例性的实施例中，参考图13所示，第一有机子层42在衬底基板1上的正投影与衬底基板1位于显示区的部分存在交叠。
示例性的，参考图13所示，第一有机子层42背离衬底基板1的表面沿衬底基板1厚度的方向上到衬底基板1之间的距离h1小于或等于第一导电垫，例如焊盘H，背离衬底基板1的表面沿衬底基板1厚度的方向上到衬底基板1之间的距离h2。
可以理解，在实际产品中，阵列基板位于绑定区的部分不设置第一有机子层42，而在阵列基板位于显示区的部分设置第一有机子层42。
在本申请的实施例中，在如图13中的显示区中设置第一有机子层42，而在如图14所示的绑定区中未设置第一有机子层42，在阵列基板的制备过程中，由于有机材料通常具有流平性，通过设置第一有机子层42先填充显示区内存在的凹槽，使得基板的表面趋于平坦，在制备第 二有机子层43时，第二有机子层43的有机材料流平性更好，更容易流入绑定区中，以填充绑定区中存在的第一间隙L1和第二间隙L2。需要说明的是，上述填充并不一定填满。
在本申请的一些实施例中，结合图13和图14所示，第一有机子层42和第二无机子层44在衬底基板上的正投影与第二导电垫，例如BD2，在衬底基板1上的正投影互不交叠；第一有机子层42和第二无机子层44在衬底基板1上的正投影与第三导电垫，例如BD1，在衬底基板1上的正投影互不交叠。
在本申请的实施例中，在第二导电垫远离衬底基板1的表面上和第三导电垫远离衬底基板1的表面上均不设置第一有机子层42和第二无机子层44，以减薄第二导电垫和第三导电垫所在位置的膜层厚度，便于第二导电垫和第三导电垫分别与电路板中的输出端子进行绑定，降低绑定工艺难度的同时，避免在绑定过程中第二导电垫和第三导电垫所在位置的膜层发生脱离或部分脱落，改善绑定不良的问题。
在本申请的一些实施例中，参考图14所示，第一间隙L1内至少依次设置有第一无机子层41、第二有机子层43和第二无机子层44，第二间隙L2内至少依次设置有第一无机子层41、第二有机子层43和第二无机子层44。
在示例性的实施例中，第二无机子层44背离衬底基板1的表面沿衬底基板1厚度的方向上到衬底基板1之间的最小距离h3小于第二导电垫(或第三导电垫)背离衬底基板1的表面沿衬底基板1厚度的方向上到衬底基板1之间的距离h4。
在本申请的一些实施例中，结合图13和图14所示，阵列基板还包括第二绝缘层6，第二绝缘层6位于第二导电层5背离衬底基板1的一侧；
其中，第二绝缘层6填充第一间隙L1和第二间隙L2，且第二绝缘层6在衬底基板1上的正投影与至少部分第二导电垫组W2在衬底基板上的正投影互不交叠。
其中，第二绝缘层6包括第三无机子层61和第三有机子层62，第 三有机子层62位于第三无机子层61背离衬底基板1的一侧；
第一间隙L1和第二间隙L2内还依次设置有第三无机子层61和第三有机子层62，第三无机子层61位于间隙L1和L2内的部分与第二无机子层44位于间隙L1和L2内的部分直接接触。
在本申请的一些实施例中，第二绝缘层4在衬底基板1上的正投影与第二导电垫的部分区域，例如BD2的部分区域，在衬底基板1上的正投影交叠，且第二绝缘层4在衬底基板1上的正投影与第二导电垫的另一部分区域在衬底基板1上的正投影互不交叠；第二绝缘层4在衬底基板1上的正投影与第三导电垫，例如BD1，远离衬底基板1的表面在衬底基板上的正投影互不交叠。
在示例性的实施例中，参考图11和图12所示，第二绝缘层4可以覆盖图12中虚线框区域内的第二导电垫上的部分区域，且暴露出第二导电垫的剩余部分区域用于覆盖屏蔽线CS。这样，可以避免裸露在外的第二导电垫上的部分区域被氧化或腐蚀，对第二导电垫起到保护作用。
在示例性的实施例中，为了降低制备工艺难度，可以在图12中虚线框内均设置第二绝缘层，也就是说，第二绝缘层4可以覆盖各第二导电垫的部分区域，还可以延伸覆盖到相邻两个第二导电垫之间的区域。
在示例性的实施例中，参考图10所示，在第三导电垫，例如BD1，所在的区域内，不设置第二绝缘层6。
在本申请的一些实施例中，第三有机子层62位于间隙L1和L2的部分远离衬底基板1的表面沿衬底基板1厚度方向上到衬底基板1之间的距离h5小于或等于第二有机子层43位于第二导电垫组(包括第二导电垫和第三导电垫)上的部分远离衬底基板1的表面沿衬底基板1厚度方向上到衬底基板1之间的距离h6。
图14中以第三有机子层62位于间隙L1和L2的部分远离衬底基板1的表面沿衬底基板1厚度方向上到衬底基板1之间的距离h5等于第二有机子层43位于第二导电垫组(包括第二导电垫和第三导电垫)上的部分远离衬底基板1的表面沿衬底基板1厚度方向上到衬底基板1之间的距离h6为例进行绘制。
在本申请的实施例中，尽可能通过第一绝缘层4和第二绝缘层6将第一间隙L1和第二间隙L2填平，但不能使得间隙中的第三有机子层62凸出第二有机子层43位于第二导电垫组上的部分，这样，能提高绑定工艺中的对位过程的准确性，另外，也避免了间隙中填充的绝缘层过高导致的第二导电垫组与电路板绑定不良。
在本申请的一些实施例中，参考图12所示，第二绝缘层6覆盖连接线P2的部分区域，屏蔽线CS覆盖连接线P2的部分区域。
这里对于上述覆盖连接线的屏蔽线CS和覆盖连接线的第二绝缘层6是否存在交叠不进行限定。
在示例性的实施例中，第二绝缘层6在衬底基板1上的正投影外轮廓的部分位置与屏蔽线CS在衬底基板1上的正投影外轮廓的部分位置之间存在间隙，使得一部分连接线P2裸露在外。参考图12所示，此时，屏蔽线CS线宽d3与第二绝缘层6覆盖连接线P2的部分的宽度d4之和小于连接线P2的长度d5。
在示例性的实施例中，第二绝缘层6在衬底基板1上的正投影部分位置与屏蔽线CS在衬底基板1上的正投影的部分位置存在重叠。这样，第二绝缘层6覆盖连接线的一部分区域并与该区域直接接触，屏蔽线CS覆盖连接线的另一部分区域并与该区域直接接触，除此之外，屏蔽线CS还延伸至第二绝缘层6远离连接线的表面的部分区域，并与这部分第二绝缘层6直接接触。此时，屏蔽线CS线宽d3与第二绝缘层6覆盖连接线P2的部分的宽度d4之和大于连接线P2的长度d5。
在第二绝缘层6在衬底基板1上的正投影外轮廓的部分位置与屏蔽线CS在衬底基板1上的正投影外轮廓的部分位置刚好相切时，屏蔽线CS线宽d3与第二绝缘层6覆盖连接线P2的部分的宽度d4之和等于连接线P2的长度d5。
在示例性的实施例中，第二绝缘层6在衬底基板1上的正投影外轮廓的部分位置与屏蔽线CS在衬底基板1上的正投影外轮廓的部分位置大致相切。这样，可以避免裸露在外的第二导电垫上的部分区域被氧化或腐蚀，对第二导电垫起到保护作用。
大致相切指的是，第二绝缘层6在衬底基板1上的正投影外轮廓的部分位置与屏蔽线CS在衬底基板1上的正投影外轮廓的部分位置在误差允许范围内波动。
在本申请的一些实施例中，参考图12所示，位于周边区除绑定区之外的区域中的连接线P2的沿垂直于参考面方向OA上的尺寸d2小于或等于接地线GND沿垂直于参考面方向OA上的尺寸d6，与第二导电垫电连接的连接线P1沿垂直于参考面方向OA上的尺寸d2小于或等于第二导电垫沿垂直于参考面方向OA上的尺寸d1；连接线的延伸方向OB和衬底基板1的厚度方向OC分别与参考面平行。
这样，能够避免连接线覆盖在第二导电垫的侧面的区域(或覆盖接地线的侧面的区域)，造成爬坡，使得连接线部分区域出现裂纹或断裂从而提高了阵列基板的品质。
在本申请的一些实施例中，参考图5和图6所示，阵列基板还包括保护层M4，保护层M4覆盖第一导电垫，例如焊盘H，在开口K处暴露出的区域，保护层M4的材料包括导电材料。
这里对于一个第一导电垫组W1中包括的焊盘的数量不进行限定，示例性的，可以为2个、3个、4个、6个或8个，具体可以根据实际情况确定。
示例性的，保护层M4的材料包括镍和/或金。
在本申请的实施例中，在焊接过程中，焊接材料优先与保护层M4的材料发生反应生成金属层间化合物，以形成连接层M3起到连接作用，保护层M4对第一导电垫起到保护作用，其中，连接层M3中包括金属层间化合物。
本申请的实施例提供的阵列基板中还包括Dummy绑定电极(Dummy BD1)以及一些Dummy走线，当然，还包括图2A中诸如黑色矩阵层8、缓冲层2等其它的结构和部件，这里仅介绍与发明点相关的结构和部件，阵列基板中包括的其它结构和部件可以参考相关技术。
本申请的实施例提供了一种显示装置，包括发光器件以及如上的阵 列基板，发光器件与第一导电垫组电连接。
在示例性的实施例中，显示装置中还可以包括驱动芯片，用于向显示装置提供驱动信号。
示例性的，发光器件可以包括Mini LED发光器件或者Micro LED发光器件。其中，Mini LED的尺寸约为100-300μm，Micro LED的尺寸为100μm以下。
在示例性的实施例中，发光器件的截面尺寸(长、宽或者对角线或者直径等参数)在大约100μm到大约300μm之间；发光器件的厚度例如为100μm。“大约”包括但不限于以下情况：受制备工艺波动的影响，元器件的尺寸出现波动，需要说明的是，该尺寸波动在误差允许范围内。
在本申请的一些实施例中，显示装置还包括电路板，电路板与第二导电垫组电连接。
该电路板可以包括柔性电路板。
这里对于显示装置中包括的电路板的数量不进行限定，具体可以根据实际情况确定。
该显示装置可以用作背光装置，或者，该显示装置也可以直接用作显示，这里不进行限制。
在本申请的实施例中，由于该显示装置包括上述阵列基板，阵列基板的第一导电层3中通常设置接地线、驱动线等对电阻要求较高的信号线，第一导电层3在沿垂直于衬底基板1所在平面方向上的厚度大于或等于第二导电层5在沿垂直于衬底基板1所在平面方向上的厚度，将导电垫组设置在第一导电层3中，第一方面，如图6所示，大大降低了在阵列基板修复(Rework)过程中形成的连接层M3穿透第一导电垫的概率，改善了第一导电垫导通不良的问题，提高了阵列基板的修复良率。其中，连接层M3包括焊接材料与第一导电垫的材料在高温下生成的金属间化合物。第二方面，由于将第一导电层3的部分区域作为绑定区的第二导电垫和绑定区的第三导电垫，相较于相关技术中由两层导电层构成的绑定端子，本申请的实施例提供的第二导电垫和第三导电垫所在的区域的整体膜层厚度降低，从而改善了在绑定工艺过程中由于膜层较厚 大、膜层数量较多造成的局部膜层脱落的问题，降低了绑定的工艺难度，提高了阵列基板制备的显示装置的品质。
本申请对于显示装置的使用不做具体限制，其可以是电视机、笔记本电脑、平板电脑、可穿戴显示设备、手机、车载显示、导航、电子书、数码相框、广告灯箱等任何具有显示功能的产品或部件。
本申请的实施例提供了一种阵列基板的制备方法，应用于制备如前文的阵列基板，该方法包括：
S01、提供衬底基板；
S02、形成第一导电层，第一导电层包括多个导电垫组，导电垫组包括至少一个导电垫；
S03、在第一导电层上依次形成第一无机子薄膜、图案化的第一有机子层、图案化的第二有机子层和第二无机子薄膜；
S04、形成第二导电层；
S05、对第一无机子薄膜和第二无机子薄膜进行图案化处理，得到第一无机子层和第二无机子层；其中，第一绝缘层包括第一无机子层、第一有机子层、第二有机子层和第二无机子层，第一绝缘层具有多个开口，开口暴露出导电垫的至少部分区域。
需要说明的是，在本申请的实施例中，“薄膜”指的是在进行图案化之前形成的整面的膜层。
在本申请的实施例中，在制备第一绝缘层时，通过先制备出图案化的第一有机子层和图案化的第二有机子层，使得第二无机薄膜覆盖第一导电层，在形成第二导电层之后，再对第二无机薄膜进行图案化处理，以使得在形成第二导电层的过程中，第二无机薄膜对第一导电层中裸露的部分区域(例如导电垫中裸露的部分区域)起到保护作用，避免对第一导电层中裸露的部分区域造成腐蚀，提高了阵列基板的可靠性。
本申请的实施例提供的阵列基板中的其它结构的制备方法可以结合相关技术中的制备方法确定，这里不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不 局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (27)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    第一导电层，位于所述衬底基板的一侧，包括多个导电垫组，所述导电垫组包括至少一个导电垫；
    第二导电层，位于所述第一导电层背离所述衬底基板的一侧，所述导电垫组中各所述导电垫的至少部分区域在所述衬底基板上的正投影与所述第二导电层在所述衬底基板上的正投影互不交叠；
    其中，所述第一导电层在沿垂直于所述衬底基板所在平面方向上的厚度大于或等于所述第二导电层在沿垂直于所述衬底基板所在平面方向上的厚度。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括位于所述第一导电层和所述第二导电层之间的第一绝缘层，所述第一绝缘层具有多个开口，所述开口暴露出所述导电垫的至少部分区域；
    其中，所述导电垫由所述开口暴露出的部分区域在所述衬底基板上的正投影与所述第二导电层在所述衬底基板上的正投影互不交叠。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括显示区，所述导电垫组包括第一导电垫组，所述第一导电垫组位于所述显示区。
  4. 根据权利要求3所述的阵列基板，其中，所述第一导电垫组包括第一导电垫，所述第一导电垫至少在所述开口暴露出的区域在所述衬底基板上的正投影与所述第二导电层在所述衬底基板上的正投影互不交叠。
  5. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括显示区以及围绕所述显示区的周边区；所述导电垫组包括第二导电垫组，所述第二导电垫组位于所述周边区。
  6. 根据权利要求5所述的阵列基板，其中，所述第二导电垫组包括第二导电垫和第三导电垫；
    除所述开口暴露出的所述第二导电垫的区域外，所述第二导电垫的 其它区域在所述衬底基板上的正投影与所述第二导电层在所述衬底基板上的正投影部分交叠；
    所述第三导电垫在所述衬底基板上的正投影与所述第二导电层在所述衬底基板上的正投影互不交叠。
  7. 根据权利要求6所述的阵列基板，其中，所述第二导电层包括位于所述周边区的多条连接线，所述第二导电垫与所述连接线电连接，且所述第二导电垫在所述衬底基板上的正投影与所述连接线在所述衬底基板上的正投影部分交叠。
  8. 根据权利要求7所述的阵列基板，其中，所述阵列基板包括屏蔽线，所述周边区包括位于所述显示区一侧的绑定区；
    所述屏蔽线的主体结构位于所述周边区中除所述绑定区之外的区域，所述屏蔽线的两端延伸至所述绑定区；所述屏蔽线的两端分别通过所述连接线与所述第二导电垫电连接。
  9. 根据权利要求8所述的阵列基板，其中，所述屏蔽线覆盖各所述连接线的至少部分区域，且所述屏蔽线与各所述连接线直接接触。
  10. 根据权利要求8所述的阵列基板，其中，所述第一导电层包括第一导电部，所述第一导电部包括位于所述显示区的接地线；所述连接线与所述接地线电连接。
  11. 根据权利要求10所述的阵列基板，其中，位于所述周边区除所述绑定区之外的区域中的所述连接线通过过孔与所述接地线电连接；位于所述绑定区的所述连接线通过所述屏蔽线与所述接地线电连接。
  12. 根据权利要求10所述的阵列基板，其中，所述周边区包括扇出区，所述扇出区位于所述绑定区与所述显示区之间，所述扇出区包括扇出走线；所述第三导电垫通过所述扇出走线与所述第一导电部电连接。
  13. 根据权利要求8所述的阵列基板，其中，所述绑定区包括第一绑定子区和第二绑定子区，所述第一绑定子区位于所述第二绑定子区远离所述显示区的一侧；
    其中，各所述第二导电垫位于所述第一绑定子区，各所述第三导电垫位于所述第二绑定子区。
  14. 根据权利要求13所述的阵列基板，其中，各所述第二导电垫沿同一方向排列，各所述第三导电垫沿同一方向排列，沿所述第二导电垫的排列方向上，每相邻两个所述第二导电垫之间具有第一间隙，沿所述第三导电垫的排列方向上，每相邻两个所述第三导电垫之间具有第二间隙；
    所述第一间隙和所述第二间隙中填充的所述第一绝缘层的子层数量相同，且所述第二间隙中填充的所述第一绝缘层的子层数量大于所述第一绝缘层位于所述第二导电垫组背离所述衬底基板的表面的部分的子层数量。
  15. 根据权利要求14所述的阵列基板，其中，所述第一绝缘层包括依次设置的第一无机子层、第一有机子层、第二有机子层和第二无机子层，所述第一无机子层和所述第一导电层直接接触；
    其中，所述第一有机子层在所述衬底基板上的正投影与所述衬底基板位于所述绑定区的部分互不交叠。
  16. 根据权利要求15所述的阵列基板，其中，所述第一有机子层和所述第二无机子层在所述衬底基板上的正投影与所述第二导电垫在所述衬底基板上的正投影互不交叠；
    所述第一有机子层和所述第二无机子层在所述衬底基板上的正投影与所述第三导电垫在所述衬底基板上的正投影互不交叠。
  17. 根据权利要求16所述的阵列基板，其中，所述第一间隙内至少依次设置有所述第一无机子层、所述第二有机子层和所述第二无机子层，所述第二间隙内至少依次设置有所述第一无机子层、所述第二有机子层和所述第二无机子层。
  18. 根据权利要求17所述的阵列基板，其中，所述阵列基板还包括第二绝缘层，所述第二绝缘层位于所述第二导电层背离所述衬底基板的一侧；
    其中，所述第二绝缘层填充所述第一间隙和所述第二间隙，且所述第二绝缘层在所述衬底基板上的正投影与至少部分所述第二导电垫组在所述衬底基板上的正投影互不交叠。
  19. 根据权利要求18所述的阵列基板，其中，所述第二绝缘层包括第三无机子层和第三有机子层，所述第三有机子层位于所述第三无机子层背离所述衬底基板的一侧；
    所述第一间隙和所述第二间隙内还依次设置有所述第三无机子层和所述第三有机子层，所述第三无机子层位于间隙内的部分与所述第二无机子层位于所述间隙内的部分直接接触。
  20. 根据权利要求19所述的阵列基板，其中，所述第三有机子层位于所述间隙的部分远离所述衬底基板的表面沿所述衬底基板厚度方向上到所述衬底基板之间的距离小于或等于所述第二有机子层位于所述第二导电垫组上的部分远离所述衬底基板的表面沿所述衬底基板厚度方向上到所述衬底基板之间的距离。
  21. 根据权利要求18所述的阵列基板，其中，所述第二绝缘层覆盖所述连接线的部分区域，所述屏蔽线覆盖所述连接线的部分区域。
  22. 根据权利要求21所述的阵列基板，其中，所述第二绝缘层在所述衬底基板上的正投影外轮廓的部分位置与所述屏蔽线在所述衬底基板上的正投影外轮廓的部分位置大致相切。
  23. 根据权利要求18所述的阵列基板，其中，所述第二绝缘层在所述衬底基板上的正投影与所述第二导电垫的部分区域在所述衬底基板上的正投影交叠；
    所述第二绝缘层在所述衬底基板上的正投影与所述第三导电垫远离衬底基板的表面在所述衬底基板上的正投影互不交叠。
  24. 根据权利要求5所述的阵列基板，其中，所述阵列基板还包括保护层，所述保护层覆盖所述第一导电垫在所述开口处暴露出的区域，所述保护层的材料包括导电材料。
  25. 一种显示装置，其中，包括发光器件以及如权利要求1-24中任一项所述的阵列基板，所述发光器件与所述阵列基板的第一导电垫组电连接。
  26. 根据权利要求25所述的显示装置，其中，所述显示装置还包括电路板，所述电路板与所述阵列基板的第二导电垫组电连接。
  27. 一种阵列基板的制备方法，其中，应用于制备如权利要求1-24中任一项所述的阵列基板，所述方法包括：
    提供衬底基板；
    形成第一导电层，所述第一导电层包括多个导电垫组，所述导电垫组包括至少一个导电垫；
    在所述第一导电层上依次形成第一无机子薄膜、图案化的第一有机子层、图案化的第二有机子层和第二无机子薄膜；
    形成第二导电层；
    对所述第一无机子薄膜和所述第二无机子薄膜进行图案化处理，得到所述第一无机子层和所述第二无机子层；其中，第一绝缘层包括所述第一无机子层、所述第一有机子层、所述第二有机子层和所述第二无机子层，所述第一绝缘层具有多个开口，所述开口暴露出所述导电垫的至少部分区域。
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US6332782B1 (en) * 2000-06-19 2001-12-25 International Business Machines Corporation Spatial transformation interposer for electronic packaging
CN101685218A (zh) * 2008-09-24 2010-03-31 北京京东方光电科技有限公司 液晶显示面板阵列基板及其制造方法
CN102097390A (zh) * 2007-12-26 2011-06-15 友达光电股份有限公司 像素结构的制作方法

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Publication number Priority date Publication date Assignee Title
US6332782B1 (en) * 2000-06-19 2001-12-25 International Business Machines Corporation Spatial transformation interposer for electronic packaging
CN102097390A (zh) * 2007-12-26 2011-06-15 友达光电股份有限公司 像素结构的制作方法
CN101685218A (zh) * 2008-09-24 2010-03-31 北京京东方光电科技有限公司 液晶显示面板阵列基板及其制造方法

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